Acer 4330 Schematics
A
1 1
B
C
D
E
Compal Confidential
2 2
Qiao Hong Schematics Document
Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M
3 3
2008-07-07
REV: 1.0
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Cover Page
Cover Page
Cover Page
LA-4421P
LA-4421P
LA-4421P
E
0.2
0.2
1 40Friday, Augu st 08, 20 08
1 40Friday, Augu st 08, 20 08
1 40Friday, Augu st 08, 20 08
0.2
A
B
C
D
E
Compal Confidential
ZZZ2
ZZZ1
Model Name : KIZ00
File Name : LA-4421P
1 1
ZZZ1
PCB
PCB
DAZ@
DAZ@
ZZZ2
PCB
PCB
DAZ@
DAZ@
CRT Conn
Thermal Sensor
EMC1402
page 2
2 2
LCD Conn.
New Card
JMB385
page 23
SD/MMC/MS
CONN
3 3
Power ON/OFF
& LED CONN
page 26
DC IN
page 31
BATT IN
page 37
CHARGER
4 4
page 32
DC/DC Interface
3VALW/5VALW
1.5VS/0.9VS/
2.5VS
1.8V/VCCP
CPU_CORE
A
page 23
page 29
page 33
page 35
page 34
page 36
ZZZ
ZZZ
PCB
PCB
page 19
page 18
MINI Card x2
page 19
B
RGB
LVDS
PCI-Express
10/100 Ethernet
RTL8102EL
page 24
Transfermer
page 24
RJ45
page 24
Int.KBD
Diamondville SC
FCBGA8
437Pins
22x22mm
H_A#(3.. 31) H_D#(0.. 63)
400/533MHz
Calistoga GSE
FCBGA998
27x27mm
DMI
X2 mode
page 4,5
FSB
Memory BUS(DDRII)
1.8V DDRII 400/533
page 6,7,8,9,10
ICH7M
BGA652
31x31mm
page 15,16,17,18
SSD CONTROL
LPC BUS
ENE KBC
KB926
page 27
Touch Pad
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
SPI
page 25
SPI ROM
page 27
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
SM223AC
W/S 2G/4G/8G/16G
NAND Flash
page 25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
PATA
page 22
AMP & INT
Speaker
D
Clock Generator
CK505
page 12
DDRII-SO-DIMM
USB
HDA
Aralia Codec
ALC268-VB-GR
page 22
INT MIC HeadPhone &
page 23
page 23
Title
Title
Title
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
page 11
USB Port X1
USB Port X1
USB Port X1
BlueTooth
CMOS CAM
MIC Jack
page 23
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
LA-4421P
LA-4421P
LA-4421P
E
page 28
page 28
page 28
page19
page22
2 40Friday, Augu st 08, 20 08
2 40Friday, Augu st 08, 20 08
2 40Friday, Augu st 08, 20 08
0.1
0.1
0.1
A
1 1
Voltage Rails
DescriptionPower Plane
VIN
B+
+CPU_CORE
+VCCP
+1.5VS
+1.8V
+2.5VS
+3VALW
+3VS
+5VALW
2 2
+5VS
+VSB VSB always on power rail ON ON*
+RTCVCC RTC power
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
STATE
Full ON
S1(Power On Sus pend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
3 3
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
0.9V switched power rail for DDR terminator+0.9VS
VCCP switched power rail
1.5V switched power rail
1.8V power rail for DDR
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
SIGNAL
SLP_S3#
SLP_S4#
HIGH HIGH HIGH
HIGH
LOW
LOW LOW
LOWLOW
SLP_S5#
HIGHHIGHHIGH
HIGH
HIGH
BOARD ID Table(Page 25)
ID
0
1
2
3
BRD ID
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
Ra
NC
100K
100K
100K
Rb Vab
0
8.2K
18K
NC
0.25V
0.50V
3.3V
B
S5
S3S1
OFFON
OFFON
ON
OFF
ON ON*
OFF
ON ON*
OFF
ON
OFF
OFF
OFF
N/AN/AN/A
OFF
OFF
OFFOFFON
OFFOFFON
OFF
OFF
OFFON
ONON
ONON
LOW
OFF
OFF
OFF
N/A N/A N/A
ON
ON OFF
ON
ON
ON
ON
ON
+VALW
+V +VS Clock
ON
ON
ON
ON
ON
ON
ON
OFF
LOW
ON
OFF
C
External PCI Devices
DEVICE REQ/GNT #
IDSEL #
No PCI Device
EC SM Bus1 address
Device
Smart Battery
EEPROM(24C16/02)
Address
1010 000X b
D
EC SM Bus2 address
Device
EMC1402
PIRQ
Address
1001 100X b0001 011X b
E
ICH7M SM Bus address
Device
Clock Generator
0V
(SLG8SP556VTR)
DDR DIMMA
Address
1101 001Xb
1010 000Xb
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
LA-4421P
LA-4421P
LA-4421P
3 40Friday, Augu st 08, 20 08
3 40Friday, Augu st 08, 20 08
3 40Friday, Augu st 08, 20 08
E
0.2
0.2
0.2
H_ADSTB #0
T5
PADT5PAD
T7 P ADT7 PAD
H_INTR<16>
H_NMI<1 6>
H_SMI#<16 >
+VCCP
R34 1K _0402 _5%R34 1K _0402 _5%
R30 1K _0402 _5%R30 1K _0402 _5%
R31 1K _0402 _5%R31 1K _0402 _5%
R29 1K _0402 _5%R29 1K _0402 _5%
+VCCP
R28 1K_0 402_5 %R28 1K_0 402_5 %
R32 1K_0 402_5 %R32 1K_0 402_5 %
+VCCP
This sha ll plac e near CPU
R200 56_0 402_5 %
R200 56_0 402_5 %
R198 56_0 402_5 %
R198 56_0 402_5 %
R206 56_0 402_5 %R206 56_04 02_5 %
R199 56_0 402_5 %
R199 56_0 402_5 %
R213 56_0 402_5 %
R213 56_0 402_5 %
R218 56_0 402_5 %
R218 56_0 402_5 %
5
U5A
U5A
H_A#3
P21
A[3]#
H20
A[4]#
N20
A[5]#
R20
A[6]#
J19
A[7]#
N19
A[8]#
G20
A[9]#
M19
A[10]#
H21
A[11]#
L20
A[12]#
M20
A[13]#
K19
A[14]#
J20
A[15]#
L21
A[16]#
K20
ADSTB[0]#
D17
AP0
N21
REQ[0]#
J21
REQ[1]#
G19
REQ[2]#
P20
REQ[3]#
R19
REQ[4]#
C19
A[17]#
F19
A[18]#
E21
A[19]#
A16
A[20]#
D19
A[21]#
C14
A[22]#
C18
A[23]#
C20
A[24]#
E20
A[25]#
D20
A[26]#
B18
A[27]#
C15
A[28]#
B16
A[29]#
B17
A[30]#
C16
A[31]#
A17
A[32]#
B14
A[33]#
B15
A[34]#
A14
A[35]#
B19
ADSTB[1]#
M18
AP1
U18
A20M#
T16
FERR#
J4
IGNNE#
R16
STPCLK#
T15
LINT0
R15
LINT1
U17
SMI#
D6
NC1
G6
NC2
H6
NC3
K4
NC4
K5
NC5
M15
NC6
L16
NC7
AU8058 6GE025 512_ FCBGA437
AU8058 6GE025 512_ FCBGA437
H_A#32
H_A#33
H_A#34
H_A#35
H_A20M#
H_IGNN E#
ITP_TMS
ITP_TDI
PREQ#
ITP_TDO
ITP_TCK
ITP_TRST#
ADDR GROUP 1
ADDR GROUP 1
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_AP0
H_RE Q#0
H_RE Q#1
H_RE Q#2
H_RE Q#3
H_RE Q#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB #1
H_AP1
H_A20M#
H_FER R#
H_IGNN E# CLK_ CPU_B CLK#
H_STPC LK#
H_INTR
H_NMI
H_SMI#
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
5
GROUP
0
GROUP
0
CONTROL
CONTROL
PROCHOT#
XDP/ITP SIGNALS
XDP/ITP SIGNALS
THERM
THERM
THERMTRIP#
H CLK
H CLK
NC
NC
ADS#
BNR#
BPRI#
ADDR
ADDR
DEFER#
DRDY#
DBSY#
BR0#
IERR#
LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TRST#
BR1#
THRMDA
THRMDC
BCLK[0]
BCLK[1]
RSVD3
RSVD2
RSVD1
V19
Y19
U21
T21
T19
Y18
T20
F16
V16
INIT#
W20
D15
W18
Y17
U20
W19
AA17
HIT#
V20
K17
J18
H15
J15
K18
J16
M17
TCK
N16
TDI
M16
TDO
L17
TMS
K16
V15
G17
E4
E5
H17
V11
V12
C21
C1
A3
.
.
H_A#[3..16 ]<6>
D D
H_ADSTB #0<6 >
H_RE Q#[0..4]<6>
H_A#[17 ..31]<6>
H_ADSTB #1<6 >
C C
H_A20M#<16>
H_FER R#<16>
H_IGNN E#<16>
H_STPC LK#<16>
B B
A A
4
H_ADS#
H_BN R#
H_BPR I#
H_DE FER#
H_DR DY#
H_DB SY#
H_BR 0#
H_IERR #
H_INIT# _R
H_LOC K#
H_RE SET#
H_RS #0
H_RS #1
H_RS #2
H_TRD Y#
H_HIT#
H_HITM#
PREQ#
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
H_PR OCHOT#_ R
H_THE RMDA
H_THE RMDC
H_THE RMTRIP#
CLK_ CPU_B CLK
R202 22 _0402 _5%R 202 22_0 402_ 5%
+CPU_ GTLREF
C62
C62
0.1U_ 0402_ 16V4Z~D
0.1U_ 0402_ 16V4Z~D
Close to CPU pin
within 500mils.
Zo=55ohm
4
H_ADS# <6 >
H_BN R# <6 >
H_BPR I# < 6>
H_DE FER# <6>
H_DR DY# <6>
H_DB SY# <6 >
H_BR 0# <6>
R33 1K_04 02_5 %R33 1K_04 02_5 %
1 2
Close to CPU
H_LOC K# <6>
H_RE SET# <6>
H_TRD Y# <6 >
H_HIT# <6>
H_HITM# <6>
1 2
Close to CPU
H_THE RMTRIP# <6,16>
CLK_ CPU_B CLK <12>
CLK_ CPU_B CLK# <12>
+VCCP
12
R47
R47
1K_04 02_1 %
1K_04 02_1 %
12
1
R48
R48
2K_04 02_1 %
2K_04 02_1 %
2
+VCCP +VCCP
12
12
R201
R201
56_0 402_5 %
56_0 402_5 %
H_RS #[0..2] <6>
H_PR OCHOT# <36>
+CPU_ EXTBGREF
C342
C342
1U_0 402_6 .3V4Z~D
1U_0 402_6 .3V4Z~D
Close to CPU pin
within 500mils.
Zo=55ohm
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
R27
R27
330_ 0402_ 5%
330_ 0402_ 5%
+VCCP
1
2
Issued Date
Issued Date
Issued Date
H_INIT# <16>
12
R234
R234
1K_04 02_1 %
1K_04 02_1 %
12
R238
R238
2K_04 02_1 %
2K_04 02_1 %
3
H_D# [0..15]<6>
H_DS TBN#0<6>
H_DS TBP#0<6 >
H_DIN V#0<6>
H_D# [16..31]<6>
H_DS TBN#1<6>
H_DS TBP#1<6 >
+CPU_ GTLREF
+CPU_ EXTBGREF
R240 1K_04 02_5 %@R240 1K_04 02_5 %@
1 2
R239 1K_04 02_5 %@R239 1K_04 02_5 %@
1 2
+VCCP
H_DIN V#1<6>
CPU_ BSEL0<12>
CPU_ BSEL1<12>
CPU_ BSEL2<12>
12
R51
12
1
C65
C65
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
R51
1K_04 02_1 %
1K_04 02_1 %
R49
R49
2K_04 02_1 %
2K_04 02_1 %
Deciphered Date
Deciphered Date
Deciphered Date
+CPU_ CMREF
0.1U_ 0402_ 16V4Z~D
0.1U_ 0402_ 16V4Z~D
Close to CPU pin
within 500mils.
Zo=55ohm
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
3
2
U5B
U5B
H_D# 0
Y11
C351
C351
2
W10
Y12
AA14
AA11
W12
AA16
Y10
Y9
Y13
W15
AA13
Y16
W13
AA9
W9
Y14
Y15
W16
V9
AA5
Y8
W3
U1
W7
W6
Y7
AA6
Y3
W2
V3
U2
T3
AA8
V2
W4
Y4
Y5
Y6
R4
A7
U5
V5
T17
R6
M6
N15
N6
P17
T6
J6
H5
G5
AU8058 6GE025 512_ FCBGA437
AU8058 6GE025 512_ FCBGA437
+3VS
1
C352
C352
2
H_THE RMDA
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
H_THE RMDC
2200 P_040 2_50V7K
2200 P_040 2_50V7K
D[0]#
D[1]#
D[2]#
DATA GRP 0 DATA GRP 1
DATA GRP 0 DATA GRP 1
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
DATA GRP 2
DATA GRP 2
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBN[2]#
DSTBP[0]#
DSTBP[2]#
DINV[0]#
DP#0
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1
GTLREF
ACLKPH
DCLKPH
BINIT#
EDM
EXTBGREF
FORCEPR#
HFPLL
MCERR#
RSP#
BSEL[0]
BSEL[1]
BSEL[2]
DINV[2]#
DATA GRP 3
DATA GRP 3
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
MISC
MISC
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
CORE_DET
CMREF[1]
Layout note:
COMP0,2 connect with Zo=27.4o hm +/-15%, mak e
trace length sh orter than 0.5 "
COMP1,3 connect with Zo=55ohm +/-15%, make
trace length sh orter than0.5"
CPU THERMAL SENSOR
U17
U17
1
VDD
2
DP
3
DN
THERM#4GND
EMC140 2-1-ACZL- TR_MSOP8
EMC140 2-1-ACZL- TR_MSOP8
Address:100_1100
Title
Title
Title
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
H_D# 1
H_D# 2
H_D# 3
H_D# 4
H_D# 5
H_D# 6
H_D# 7
H_D# 8
H_D# 9
H_D# 10
H_D# 11
H_D# 12
H_D# 13
H_D# 14
H_D# 15
H_DS TBN#0
H_DS TBP#0
H_DIN V#0
H_DP #0
T10 PADT10 PAD
H_D# 16
H_D# 17
H_D# 18
H_D# 19
H_D# 20
H_D# 21
H_D# 22
H_D# 23
H_D# 24
H_D# 25
H_D# 26
H_D# 27
H_D# 28
H_D# 29
H_D# 30
H_D# 31
H_DS TBN#1 H_DST BN#3
H_DS TBP#1
H_DIN V#1
H_DP #1
T13 PADT13 PAD
ACLKPH
DCLK PH
CPU_ BSEL0
CPU_ BSEL1
CPU_ BSEL2
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
1 2
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DP#2
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DP#3
SLP#
Cus tom
Cus tom
Cus tom
H_D# 32
R3
H_D# 33
R2
H_D# 34
P1
H_D# 35
N1
H_D# 36
M2
H_D# 37
P2
H_D# 38
J3
H_D# 39
N3
H_D# 40
G3
H_D# 41
H2
H_D# 42
N2
H_D# 43
L2
H_D# 44
M3
H_D# 45
J2
H_D# 46
H1
H_D# 47
J1
H_DS TBN#2
K2
H_DS TBP#2
K3
H_DIN V#2
L1
H_DP #2
M4
C2
G2
F1
D3
B4
E1
A5
C3
A6
F2
C6
B6
B3
C4
C7
D2
E2
F3
C5
D4
T1
T2
F20
F21
R18
R17
U4
V17
N18
A13
B7
SMDATA
T15PAD T15PAD
H_D# 48
H_D# 49
H_D# 50
H_D# 51
H_D# 52
H_D# 53
H_D# 54
H_D# 55
H_D# 56
H_D# 57
H_D# 58
H_D# 59
H_D# 60
H_D# 61
H_D# 62
H_D# 63
H_DS TBP#3
H_DIN V#3
H_DP #3
T12PAD T12PAD
COMP0
R57 27.4_ 0402 _1%
R57 27.4_ 0402 _1%
1 2
COMP1
R58 54.9_ 0402 _1%
R58 54.9_ 0402 _1%
1 2
COMP2
R208 27.4_ 0402 _1%
R208 27.4_ 0402 _1%
COMP3
R209 54.9_ 0402 _1%
R209 54.9_ 0402 _1%
H_DP RSTP#
H_DP SLP#
H_DP WR#
H_PWR GOOD
H_CP USLP#
EC_SMB_ CK2
8
SMCLK
EC_SMB_ DA2
7
6
ALERT#
5
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Diamondville(1/2)
Diamondville(1/2)
Diamondville(1/2)
LA-4421P
LA-4421P
LA-4421P
1
H_D# [32..47] <6>
H_DS TBN#2 <6 >
H_DS TBP#2 <6 >
H_DIN V#2 <6>
H_D# [48..63] <6>
H_DS TBN#3 <6 >
H_DS TBP#3 <6 >
H_DIN V#3 <6>
12
12
H_DP RSTP# <1 6,36>
H_DP SLP# <1 6>
H_DP WR# <6 >
H_PWR GOOD <16>
H_CP USLP# < 6>
+CPU_ CMREF
R304
R304
12
10K_0 402_ 5%
10K_0 402_ 5%
1
EC_SMB_ CK2 <25>
EC_SMB_ DA2 <25>
+3VS
4 40Friday, Augu st 08, 20 08
4 40Friday, Augu st 08, 20 08
4 40Friday, Augu st 08, 20 08
0.2
0.2
0.2
5
4
3
2
1
U5C
V10
A10
A11
A12
B10
B11
B12
C10
C11
C12
D10
D11
D12
E10
E11
E12
F10
F11
F12
G10
G11
G12
H10
H11
H12
K10
K11
K12
L10
L11
L12
M10
M11
M12
N10
N11
N12
P10
P11
P12
R10
R11
R12
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C309
C309
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
C299
C299
2
J10
J11
J12
U5C
VCCF
A9
VCCQ1
B9
VCCQ2
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCPC64
VCCPC63
VCCP17
VCCPC62
VCCP18
VCCPC61
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCP25
VCCP26
VCCP27
VCCP28
VCCP29
VCCP30
VCCP31
VCCP32
VCCP33
VCCP34
VCCP35
VCCP36
VCCP37
VCCP38
VCCP39
VCCP40
VCCP41
VCCP42
VCCSENSE
VCCP43
VCCP44
VCCP45
VSSSENSE
AU80586GE025512_FCBGA437
AU80586GE025512_FCBGA437
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
C310
C310
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
1
C301
C301
C300
C300
2
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VCCA
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
1
C311
C311
2
1
2
C9
D9
E9
F8
F9
G8
G14
H8
H14
J8
J14
K8
K14
L8
L14
M8
M14
N8
N14
P8
P14
R8
R14
T8
T14
U8
U9
U10
U11
U12
U13
U14
F14
F13
E14
E13
D7
F15
D16
E18
G15
G16
E17
G18
C13
D13
PLACE IN CAVITY
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C312
C312
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
C302
C302
C46
C46
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
+1.5VS
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
VCCSENSE
VSSSENSE
C313
C313
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
C314
C314
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C304
C304
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
C307
C307
C295
C295
2
CPU_VID0 <36>
CPU_VID1 <36>
CPU_VID2 <36>
CPU_VID3 <36>
CPU_VID4 <36>
CPU_VID5 <36>
CPU_VID6 <36>
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
C320
C320
2
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
1
C303
C303
2
2
1
C337
C337
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
130mA
1
C321
C321
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C335
C335
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
U5D
U5D
A2
VSS1
A4
VSS2
A8
VSS4
A15
VSS5
A18
VSS6
A19
VSS7
A20
VSS8
B1
VSS9
B2
D D
C C
B B
A A
VSS10
B5
VSS11
B8
VSS12
B13
VSS13
B20
VSS14
B21
VSS15
C8
VSS16
C17
VSS17
D1
VSS18
D5
VSS19
D8
VSS20
D14
VSS21
D18
VSS22
D21
VSS23
E3
VSS24
E6
VSS25
E7
VSS26
E8
VSS27
E15
VSS28
E16
VSS29
E19
VSS30
F4
VSS31
F5
VSS32
F6
VSS33
F7
VSS34
F17
VSS35
F18
VSS36
G1
VSS37
G4
VSS38
G7
VSS39
G9
VSS41
G13
VSS42
G21
VSS45
H3
VSS46
H4
VSS48
H7
VSS49
H9
VSS51
H13
VSS52
H16
VSS53
H18
VSS54
H19
VSS55
J5
VSS56
J7
VSS57
J9
VSS58
J13
VSS59
J17
VSS60
K1
VSS61
K6
VSS62
K7
VSS63
K9
VSS64
K13
VSS65
K15
VSS66
K21
VSS67
L3
VSS68
L4
VSS69
L5
VSS70
L6
VSS71
L7
VSS72
L9
VSS73
L13
VSS74
L15
VSS75
L18
VSS76
L19
VSS77
M1
VSS78
M5
VSS79
M7
VSS80
M9
VSS81
M13
VSS82
M21
VSS83
N4
VSS84
AU80586GE025512_FCBGA437
AU80586GE025512_FCBGA437
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
N5
N7
N9
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20
+CPU_CORE
+VCCP
+CPU_CORE
C308
C308
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C298
C298
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
C341
C341
C57
C57
2
2
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
PLACE IN CAVITY
+1.5VS
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C322
C322
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
C328
C328
C47
C47
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
+VCCP
1
+
+
2
1
C338
C338
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C323
C323
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
C334
C334
2
+CPU_CORE
1
C324
C324
2
1
2
12
R221
R221
100_0402_1%
100_0402_1%
12
R220
R220
100_0402_1%
100_0402_1%
1
C326
C326
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
VCCSENSE <36>
VSSSENSE <36>
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C327
C327
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
Length match within 25 mils
The trace space 7 mils,
Zo=27.4ohm
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
C315
C315
C325
C325
2
2
+CPU_CORE
2 x 330uF(9mohm/2)
1
+
+
C51
C51
330U 2.5V Y
330U 2.5V Y
2
1
+
+
C331
C331
330U 2.5V Y
330U 2.5V Y
2
PLACE IN CORRIDOR AND CLOSE TO CPU
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHE ET OF ENGINEE RING DR AWING IS THE PR OPRIETARY PROP ERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS CONFIDEN TIAL
THIS SHE ET OF ENGINEE RING DR AWING IS THE PR OPRIETARY PROP ERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS CONFIDEN TIAL
THIS SHE ET OF ENGINEE RING DR AWING IS THE PR OPRIETARY PROP ERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS CONFIDEN TIAL
AND TRADE S ECRET IN FORMATION. THIS SHE ET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETEN T DIVISION OF R &D
AND TRADE S ECRET IN FORMATION. THIS SHE ET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETEN T DIVISION OF R &D
AND TRADE S ECRET IN FORMATION. THIS SHE ET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETEN T DIVISION OF R &D
DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. NE ITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. NE ITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. NE ITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF C OMPAL ELECTR ONICS, INC.
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF C OMPAL ELECTR ONICS, INC.
5
4
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF C OMPAL ELECTR ONICS, INC.
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
3
Com pal Secret D ata
Com pal Secret D ata
Com pal Secret D ata
Deciphered Date
Deciphered Date
Deciphered Date
Com pal El ectron ics, Inc.
Com pal El ectron ics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Com pal El ectron ics, Inc.
B
B
B
Diamondville(2/2)
Diamondville(2/2)
Diamondville(2/2)
LA-4421P
LA-4421P
LA-4421P
5 40Friday, August 08, 2008
5 40Friday, August 08, 2008
5 40Friday, August 08, 2008
1
0.2
0.2
0.2
5
4
3
2
1
H_D# [0..63]<4>
D D
C C
+VCCP
12
12
R6
R6
R175
R175
54.9_0402_1%
54.9_0402_1%
54.9_0402_1%
54.9_0402_1%
B B
+H_SW NG0
+H_SW NG1
12
12
R7
R7
R182
R182
24.9_0402_1%
24.9_0402_1%
24.9_0402_1%
24.9_0402_1%
H_D# 0
H_D# 1
H_D# 2
H_D# 3
H_D# 4
H_D# 5
H_D# 6
H_D# 7
H_D# 8
H_D# 9
H_D# 10
H_D# 11
H_D# 12
H_D# 13
H_D# 14
H_D# 15
H_D# 16
H_D# 17
H_D# 18
H_D# 19
H_D# 20
H_D# 21
H_D# 22
H_D# 23
H_D# 24
H_D# 25
H_D# 26
H_D# 27
H_D# 28
H_D# 29
H_D# 30
H_D# 31
H_D# 32
H_D# 33
H_D# 34
H_D# 35
H_D# 36
H_D# 37
H_D# 38
H_D# 39
H_D# 40
H_D# 41
H_D# 42
H_D# 43
H_D# 44
H_D# 45
H_D# 46
H_D# 47
H_D# 48
H_D# 49
H_D# 50
H_D# 51
H_D# 52
H_D# 53
H_D# 54
H_D# 55
H_D# 56
H_D# 57
H_D# 58
H_D# 59
H_D# 60
H_D# 61
H_D# 62
H_D# 63
H_XRCO MP
H_XSCOMP
H_YRCO MP
H_YSCOMP
U1A
U1A
C4
H_D#_0
F6
H_D#_1
H9
H_D#_2
H6
H_D#_3
F7
H_D#_4
E3
H_D#_5
C2
H_D#_6
C3
H_D#_7
K9
H_D#_8
F5
H_D#_9
J7
H_D#_10
K7
H_D#_11
H8
H_D#_12
E5
H_D#_13
K8
H_D#_14
J8
H_D#_15
J2
H_D#_16
J3
H_D#_17
N1
H_D#_18
M5
H_D#_19
K5
H_D#_20
J5
H_D#_21
H3
H_D#_22
J4
H_D#_23
N3
H_D#_24
M4
H_D#_25
M3
H_D#_26
N8
H_D#_27
N6
H_D#_28
K3
H_D#_29
N9
H_D#_30
M1
H_D#_31
V8
H_D#_32
V9
H_D#_33
R6
H_D#_34
T8
H_D#_35
R2
H_D#_36
N5
H_D#_37
N2
H_D#_38
R5
H_D#_39
U7
H_D#_40
R8
H_D#_41
T4
H_D#_42
T7
H_D#_43
R3
H_D#_44
T5
H_D#_45
V6
H_D#_46
V3
H_D#_47
W2
H_D#_48
W1
H_D#_49
V2
H_D#_50
W4
H_D#_51
W7
H_D#_52
W5
H_D#_53
V5
H_D#_54
AB4
H_D#_55
AB8
H_D#_56
W8
H_D#_57
AA9
H_D#_58
AA8
H_D#_59
AB1
H_D#_60
AB7
H_D#_61
AA2
H_D#_62
AB5
H_D#_63
A10
H_XRCOMP
A6
H_XSCOMP
C15
H_XSWING
J1
H_YRCOMP
K1
H_YSCOMP
H1
H_YSWING
H_ADSTB#_0
H_ADSTB#_1
H_BREQ0#
H_CPURST#
HOST
HOST
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DPWR#
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_SLPCPU#
Calis toga- GSE_FCB GA998
Calis toga- GSE_FCB GA998
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_ADS#
H_VREF0
H_BNR#
H_BPRI#
H_VREF1
HCLKN
HCLKP
H_DBSY#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_RS#_0
H_RS#_1
H_RS#_2
H_TRDY#
F8
D12
C13
A8
E13
E12
J12
B13
A13
G13
A12
D14
F14
J13
E17
H15
G15
G14
A15
B18
B15
E14
H13
C14
A17
E15
H17
D17
G17
F10
C12
H16
E2
B9
C7
G8
B10
E1
AA6
AA5
C10
C6
H5
J6
T9
U6
G7
E6
F3
M8
T1
AA3
F4
M7
T2
AB3
C8
B4
C5
G9
E9
G12
B8
F12
A5
B6
G10
E8
E10
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADS#
H_ADSTB #0
H_ADSTB #1
+H_VREF
H_BN R#
H_BPR I#
H_BR 0#
H_RE SET#
+H_VREF
CLK_ MCH_BC LK#
CLK_ MCH_BC LK
H_DB SY#
H_DE FER#
H_DIN V#0
H_DIN V#1
H_DIN V#2
H_DIN V#3
H_DP WR#
H_DR DY#
H_DS TBN#0
H_DS TBN#1
H_DS TBN#2
H_DS TBN#3
H_DS TBP#0
H_DS TBP#1
H_DS TBP#2
H_DS TBP#3
H_HIT#
H_HITM#
H_LOC K#
H_RE Q#0
H_RE Q#1
H_RE Q#2
H_RE Q#3
H_RE Q#4
H_RS #0
H_RS #1
H_RS #2
H_CP USLP#
H_TRD Y#
H_A#[3..31 ] <4>
H_ADS# <4>
H_ADSTB #0 <4 >
H_ADSTB #1 <4 >
H_BN R# <4 >
H_BPR I# <4>
H_BR 0# <4>
H_RE SET# <4>
CLK_ MCH_BC LK# <12 >
CLK_ MCH_BC LK <12>
H_DB SY# <4>
H_DE FER# <4>
H_DIN V#0 < 4>
H_DIN V#1 < 4>
H_DIN V#2 < 4>
H_DIN V#3 < 4>
H_DP WR# <4>
H_DR DY# <4>
H_DS TBN#[0..3] < 4>
H_DS TBP#[0..3] <4>
H_HIT# <4>
H_HITM# <4>
H_LOC K# <4>
H_RE Q#[0..4] <4>
H_RS #[0..2] <4 >
H_CP USLP# <4>
H_TRD Y# <4 >
+1.8V
+DIMM_VREF
DMI_TXN0<17>
DMI_TXN1<17>
DMI_TXP0<17 >
DMI_TXP1<17 >
DMI_RXN0<17>
DMI_RXN1<17>
DMI_RXP0<17>
DMI_RXP1<17>
M_CLK_ DDR0<11>
M_CLK_ DDR1<11>
M_CLK_ DDR# 0<11>
M_CLK_ DDR# 1<11>
DDR_ CKE0<11>
DDR_ CKE1<11>
DDR_ CS0#<11 >
DDR_ CS1#<11 >
M_ODT0< 11>
M_ODT1<11 >
R232 80.6_0 402_ 1%
R232 80.6_0 402_ 1%
1 2
1 2
1
Layout Note:
+DIMM_VREF trace
width and spacing
2
is 20/20.
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10uA
R228 80.6_0 402_ 1%
R228 80.6_0 402_ 1%
C53
C53
DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1
DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1
M_CLK_ DDR0
M_CLK_ DDR1
M_CLK_ DDR# 0
M_CLK_ DDR# 1
DDR_ CKE0
DDR_ CKE1
DDR_ CS0#
DDR_ CS1#
M_ODT0
M_ODT1
SMRCOMPN
SMRCOMPP
AF33
AM30
AG33
AN30
AN21
AN22
AF26
AF25
AG14
AF12
AK14
AH12
AF11
AE12
AF14
AN12
AN14
AA33
Y29
Y32
Y28
Y31
V28
V31
V29
V32
AG1
AJ1
AF1
AK1
AJ21
AJ14
AJ12
AE1
U1B
U1B
DMI_RXN_0
DMI_RXN_1
DMI_RXP_0
DMI_RXP_1
DMI_TXN_0
DMI_TXN_1
DMI_TXP_0
DMI_TXP_1
SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3
SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_OCDCOMP_0
SM_OCDCOMP_1
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMPN
SM_RCOMPP
SM_VREF_0
SM_VREF_1
DMI
DMI
RESERVED1
RESERVED2
RESERVED7
RESERVED8
RESERVED9
CFG/RSVD
CFG/RSVD
DDR2 MUXING
DDR2 MUXING
PM_ICHSYNC#
PM_BMBUSY#
PM_EXTTS#_0
PM
PM
PM_EXTTS#_1
THRMTRIP#
PWROK
D_REFCLKN
D_REFCLKP
CLK
CLK
D_REFSSCLKN
D_REFSSCLKP
CLKREQ#
Calis toga- GSE_FCB GA998
Calis toga- GSE_FCB GA998
MCH_C LKSEL0
C18
CFG_0
MCH_C LKSEL1
E18
CFG_1
MCH_C LKSEL2
G20
CFG_2
CFG3
G18
CFG_3
CFG5
J20
CFG_5
CFG6
J18
CFG_6
K32
K31
C17
F18
A3
E31
G21
PM_EXTTS#0
F26
PM_EXTTS#1
H26
J15
AB29
W27
RSTIN#
PLTRST_ R#
A27
A26
J33
H33
J22
Strap Pin Table
CFG5
1 2
R181 2.2K_0 402_ 5%R181 2.2K_0 402_ 5%
12
R203 0 _040 2_5%R203 0 _040 2_5%
H_THE RMTRIP#
ICH_PO K
1 2
R211 1 00_0 402_5 %
R211 1 00_0 402_5 %
Low = DMI x 2
High = DMI x 4
MCH_C LKSEL0 <1 2>
MCH_C LKSEL1 <1 2>
MCH_C LKSEL2 <1 2>
MCH_ICH _SYNC# <15 >
PM_BMBUSY# <17>
PM_EXTTS#0 <11 >
PM_DPR SLPVR <1 7,36>
H_THE RMTRIP# <4 ,16>
ICH_PO K <1 7,25>
PLTRST# <15 ,17,19,22 ,23,24>
CLK_ MCH_DR EFCLK# <12>
CLK_ MCH_DR EFCLK < 12>
MCH_SS CDREFC LK# <1 2>
MCH_SS CDREFC LK <12 >
MCH_C LKREQ# <12>
*
Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.
+VCCP
12
R176
A A
R176
100_0402_1%
100_0402_1%
+H_VREF
12
1
R174
R174
200_0402_1%
200_0402_1%
C243
C243
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
5
C50 be p laced < 100mils
from GMC H pin
+VCCP
12
R167
R167
221_0402_1%~D
221_0402_1%~D
12
1
R166
R166
2
100_0402_1%
100_0402_1%
+H_SW NG0
C240
C240
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4
+VCCP
R180
R180
R178
R178
12
+H_SW NG1
221_0402_1%~D
221_0402_1%~D
12
1
C251
C251
Security Classification
Security Classification
2
100_0402_1%
100_0402_1%
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
PM_EXTTS#0
1 2
R187 10K_ 0402 _5%R187 10K_ 0402 _5%
PM_EXTTS#1
1 2
R188 10K_ 0402 _5%
R188 10K_ 0402 _5%
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Calistoga(1/5)-GTL/DMI/DDR
Calistoga(1/5)-GTL/DMI/DDR
Calistoga(1/5)-GTL/DMI/DDR
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
Cus tom
Cus tom
Cus tom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-4421P
LA-4421P
LA-4421P
+3VS
@
@
0.2
0.2
6 40Friday, Augu st 08, 20 08
6 40Friday, Augu st 08, 20 08
6 40Friday, Augu st 08, 20 08
1
0.2
5
4
3
2
1
D D
C C
B B
DDR_A_BS0<11>
DDR_A_BS1<11>
DDR_A_BS2<11>
DDR_A_DM[0..7]<11>
DDR_A_DQS[0..7]<11>
DDR_A_DQS#[0..7]<11>
DDR_A_MA[0..13]< 11>
DDR_A_CAS#<11>
DDR_A_RAS#<11>
DDR_A_WE#<11>
T9 PA DT 9 PAD
T8 PA DT 8 PAD
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
SA_RCVENIN#
SA_RCVENOUT#
DDR_A_WE#
AK12
AH11
AG17
AB30
AF30
AK26
AC28
AK33
AC29
AK30
AM25
AM17
AM15
AH15
AK15
AN15
AF19
AN17
AG16
AG18
AK18
AN28
AM28
AH17
AH21
AE27
AG22
AF21
AM21
AE21
AE22
AE26
AE20
AL31
AL9
AG7
AK5
AH3
AJ30
AL25
AN9
AH8
AM2
AE3
AJ33
AN8
AJ8
AM3
AE2
AJ15
AJ18
AL17
AL18
AL14
AJ17
AJ20
AN20
AL21
AK21
AK22
AL22
AH22
AL20
U1C
U1C
SA_BS_0
SA_BS_1
SA_BS_2
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
SB_BS_0
SB_BS_1
SB_BS_2
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
DDR2 SYSTEM MEMORY
DDR2 SYSTEM MEMORY
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SB_CAS#
SB_RAS#
Calistoga-GSE_FCBGA998
Calistoga-GSE_FCBGA998
SB_WE#
AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5
AG19
AG21
AG20
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D0
AC31
DDR_A_D[0..63] <11>
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
3
Com pal Secret D ata
Com pal Secret D ata
Com pal Secret D ata
Decipher ed Date
Decipher ed Date
Decipher ed Date
Comp al El ectron ics, I nc.
Comp al El ectron ics, I nc.
Comp al El ectron ics, I nc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Calistoga(2/5)-DDR2
Calistoga(2/5)-DDR2
Calistoga(2/5)-DDR2
LA-4421P
LA-4421P
LA-4421P
1
0.2
0.2
7 40Friday, August 08, 2008
7 40Friday, August 08, 2008
7 40Friday, August 08, 2008
0.2
5
D D
GMCH_CRT_R
12
R10 150_0402_1%R10 150_0402_1%
R8 150_0402_1%R8 150_0402_1%
R9 150_0402_1%R9 150_0402_1%
GMCH_CRT_G
12
GMCH_CRT_B
12
Close to U4.H25
12
R183 255_0402_1%
R183 255_0402_1%
C C
+3VS
1 2
R192 10K_0402_5%R192 10K_0402_5%
1 2
B B
R191 10K_0402_5%R191 10K_0402_5%
LCTLA_CLK
LCTLB_DATA
R171 100K_0402_5%R171 100K_0402_5%
GMCH_ENBKL<25>
R184 1.5K_0402_1%
R184 1.5K_0402_1%
4
U1F
U1F
H27
SDVO_CTRLDAT A
J27
SDVO_CTRLCL K
CLK_MCH_3GPLL#<12>
CLK_MCH_3GPLL<12>
GMCH_CRT_CLK<14>
GMCH_CRT_DATA<14>
GMCH_CRT_B<14>
GMCH_CRT_G<14>
GMCH_CRT_R<14>
GMCH_CRT_VSYNC<14>
GMCH_CRT_HSYNC<14>
12
LVDS_SCL<13>
LVDS_SDA<13>
GMCH_ENVDD<13>
12
LVDS_ACLK#<13>
LVDS_ACLK<13>
LVDS_A0#<13>
LVDS_A1#<13>
LVDS_A2#<13>
LVDS_A0<13>
LVDS_A1<13>
LVDS_A2<13>
GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_R
CRT_IREF
LCTLA_CLK
LCTLB_DATA
LVDS_SCL
LVDS_SDA
L_IBG
LVDS_ACLK#
LVDS_ACLK
LVDS_A0#
LVDS_A1#
LVDS_A2#
LVDS_A0
LVDS_A1
LVDS_A2
AA26
Y26
H20
H22
A24
A23
E25
F25
C25
D25
F27
D27
H25
H30
G29
F28
E28
G28
H28
K30
K27
J29
J30
K29
D30
C30
A30
A29
G31
F32
D31
H31
G32
C31
F33
D33
F30
E33
D32
F29
G_CLKN
G_CLKP
CRT_DDC_CL K
CRT_DDC_DAT A
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_VSYNC
CRT_HSYNC
CRT_IREF
L_BKLTCT L
L_BKLTEN
L_CLKCTL A
L_CTLBDAT A
L_DDC_CLK
L_DDC_DATA
L_VDDEN
L_IBG
L_VBG
L_VREFH
L_VREFL
LA_CLKN
LA_CLKP
LB_CLKN
LB_CLKP
LA_DATAN_0
LA_DATAN_1
LA_DATAN_2
LA_DATAP_0
LA_DATAP_1
LA_DATAP_2
LB_DATAN_0
LB_DATAN_1
LB_DATAN_2
LB_DATAP_0
LB_DATAP_1
LB_DATAP_2
3
EXP_A_COMPI
EXP_A_ICOMPO
SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDST ALL#
MISC
MISC
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDST ALL
SDVO
SDVO
SDVO_RED#
SDVO_GREEN#
SDVO_BLUE#
SDVO_CLKN
SDVO_RED
SDVO_GREEN
SDVO_BLUE
SDVO_CLKP
TV_DACA
TV_DACB
TV_DACC
TV_IREF
TV_IRTNA
TV
TV
TV_IRTNB
LVDS VGA
LVDS VGA
TV_IRTNC
TV_DCONSEL0
TV_DCONSEL1
Calistoga-GSE_FCBGA998
Calistoga-GSE_FCBGA998
2
+1.5VS_PCIE
R190
R190
24.9_0402_1%
24.9_0402_1%
PEGCOMP
R28
M28
N30
R30
T29
M30
P30
T30
P28
N32
P32
T32
N28
M32
P33
R32
A21
C20
E20
G23
B21
C21
D21
G26
J26
1 2
+1.5VS
Disable TV
1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHE ET OF ENGINEE RING DR AWING IS THE PR OPRIETARY PROP ERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS CONFIDEN TIAL
THIS SHE ET OF ENGINEE RING DR AWING IS THE PR OPRIETARY PROP ERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS CONFIDEN TIAL
THIS SHE ET OF ENGINEE RING DR AWING IS THE PR OPRIETARY PROP ERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS CONFIDEN TIAL
AND TRADE S ECRET IN FORMATION. THIS SHE ET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETEN T DIVISION OF R &D
AND TRADE S ECRET IN FORMATION. THIS SHE ET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETEN T DIVISION OF R &D
AND TRADE S ECRET IN FORMATION. THIS SHE ET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETEN T DIVISION OF R &D
DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. NE ITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. NE ITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. NE ITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF C OMPAL ELECTR ONICS, INC.
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF C OMPAL ELECTR ONICS, INC.
5
4
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF C OMPAL ELECTR ONICS, INC.
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
3
Com pal Secret D ata
Com pal Secret D ata
Com pal Secret D ata
Deciphered Date
Deciphered Date
Deciphered Date
Com pal El ectron ics, Inc.
Com pal El ectron ics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Com pal El ectron ics, Inc.
Calistoga(3/5)-VGA/LVDS/TV
Calistoga(3/5)-VGA/LVDS/TV
Calistoga(3/5)-VGA/LVDS/TV
B
B
B
LA-4421P
LA-4421P
LA-4421P
1
0.2
0.2
8 40Friday, August 08, 2008
8 40Friday, August 08, 2008
8 40Friday, August 08, 2008
0.2
5
+VCCP
D D
C C
+VCCP
B B
A A
5
U1H
U1H
T25
VCC_NCTF1
R25
VCC_NCTF2
P25
VCC_NCTF3
N25
VCC_NCTF4
M25
VCC_NCTF5
P24
VCC_NCTF6
N24
VCC_NCTF7
M24
VCC_NCTF8
Y22
VCC_NCTF9
W22
VCC_NCTF10
V22
VCC_NCTF11
U22
VCC_NCTF12
T22
VCC_NCTF13
R22
VCC_NCTF14
P22
VCC_NCTF15
N22
VCC_NCTF16
M22
VCC_NCTF17
Y21
VCC_NCTF18
W21
VCC_NCTF19
V21
VCC_NCTF20
U21
VCC_NCTF21
T21
VCC_NCTF22
R21
VCC_NCTF23
P21
VCC_NCTF24
N21
VCC_NCTF25
M21
VCC_NCTF26
Y20
VCC_NCTF27
W20
VCC_NCTF28
V20
VCC_NCTF29
U20
VCC_NCTF30
T20
VCC_NCTF31
R20
VCC_NCTF32
P20
VCC_NCTF33
N20
VCC_NCTF34
M20
VCC_NCTF35
Y19
VCC_NCTF36
P19
VCC_NCTF37
N19
VCC_NCTF38
M19
VCC_NCTF39
Y18
VCC_NCTF40
P18
VCC_NCTF41
N18
VCC_NCTF42
NCTF
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
RSVD_3
RSVD_4
RSVD_5
RSVD_6
NCTF
M18
Y17
P17
N17
M17
Y16
P16
N16
M16
Y15
P15
N15
M15
Y14
W14
V14
U14
T14
R14
P14
N14
M14
T10
R10
P10
N10
L10
D1
M10
A18
AB10
AA10
4
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
CFG_19
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED24
RESERVED25
Calis toga- GSE_FCB GA998
Calis toga- GSE_FCB GA998
4
+1.5VS
AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1
K28
K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15
3
U1E
U1E
AH33
VSS_1
Y33
VSS_2
V33
VSS_3
R33
VSS_4
G33
VSS_5
AK32
VSS_6
AG32
VSS_7
AE32
VSS_8
AC32
VSS_9
AA32
VSS_10
U32
VSS_11
H32
VSS_12
E32
VSS_13
C32
VSS_14
AM31
VSS_15
AJ31
VSS_16
AA31
VSS_17
U31
VSS_18
T31
VSS_19
R31
VSS_20
P31
VSS_21
N31
VSS_22
M31
VSS_23
J31
VSS_24
F31
VSS_25
AL30
VSS_26
AG30
VSS_27
AE30
VSS_28
AC30
VSS_29
AA30
VSS_30
Y30
VSS_31
V30
VSS_32
U30
VSS_33
G30
VSS_34
E30
VSS_35
B30
VSS_36
AA29
VSS_37
U29
VSS_38
R29
VSS_39
P29
VSS_40
N29
VSS_41
M29
VSS_42
H29
VSS_43
E29
VSS_44
B29
VSS_45
AK28
VSS_46
AH28
VSS_47
AE28
VSS_48
AA28
VSS_49
U28
VSS_50
T28
VSS_51
J28
VSS_52
D28
VSS_53
AM27
VSS_54
AF27
VSS_55
AB27
VSS_56
AA27
VSS_57
Y27
VSS_58
U27
VSS_59
T27
VSS_60
R27
VSS_61
P27
VSS_62
N27
VSS_63
M27
VSS_64
G27
VSS_65
E27
VSS_66
C27
VSS_67
B27
VSS_68
AL26
VSS_69
AH26
VSS_70
W26
VSS_71
U26
VSS_72
AN25
VSS_73
AK25
VSS_74
AG25
VSS_75
AE25
VSS_76
J25
VSS_77
G25
VSS_78
A25
VSS_79
H23
VSS_80
F23
VSS_81
B23
VSS_82
AM22
VSS_83
AJ22
VSS_84
AF22
VSS_85
G22
VSS_86
E22
VSS_87
J21
VSS_88
H21
VSS_89
F21
VSS_90
AM20
VSS_91
AK20
VSS_92
AH20
VSS_93
AF20
VSS_94
D20
VSS_95
W19
VSS_96
R19
VSS_97
AM18
VSS_98
AH18
VSS_99
AF18
VSS_100
U18
VSS_101
H18
VSS_102
D18
VSS_103
AK17
VSS_104
V17
VSS_105
T17
VSS_106
F17
VSS_107
B17
VSS_108
AH16
VSS_109
U16
VSS_110
Calis toga- GSE_FCB GA998
Calis toga- GSE_FCB GA998
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
3
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS
VSS
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
Compal Secret Data
Compal Secret Data
Compal Secret Data
J16
AL15
AG15
W15
R15
F15
D15
AM14
AH14
AE14
H14
B14
F13
D13
AL12
AG12
H12
B12
AN11
AJ11
AE11
AM9
AJ9
AB9
W9
R9
M9
J9
F9
C9
A9
AL8
AG8
AE8
U8
AA7
V7
R7
N7
H7
E7
B7
AL6
AG6
AE6
AB6
W6
T6
M6
K6
AN5
AJ5
B5
AA4
V4
R4
N4
K4
H4
E4
AL3
AD3
W3
T3
B3
AK2
AH2
AF2
AB2
M2
K2
H2
F2
V1
R1
Deciphered Date
Deciphered Date
Deciphered Date
2
U1G
U1G
W33
NC1
AM33
NC2
AL33
NC3
C33
NC4
B33
NC5
AN32
NC6
A32
NC7
AN31
NC8
W28
NC9
V27
NC10
W29
NC11
J24
NC12
H24
NC13
W32
NC14
G24
NC15
F24
NC16
E24
NC17
D24
NC18
K33
NC19
A31
NC20
E21
NC21
C23
NC22
AN19
NC23
AM19
NC24
AL19
NC25
AK19
NC26
AJ19
NC27
AH19
NC28
AN3
NC29
Y9
NC30
J19
NC31
H19
NC32
G19
NC33
F19
NC34
E19
NC35
D19
NC36
C19
NC37
B19
NC38
A19
NC39
Y8
NC40
G16
NC41
F16
NC42
E16
NC43
D16
NC44
C16
NC45
B16
NC46
AN2
NC47
A16
NC48
Y7
NC49
AM4
NC50
AF4
NC51
AD4
NC52
AL4
NC53
AK4
NC54
W31
NC55
AJ4
NC56
AH4
NC57
AG4
NC58
AE4
NC59
AM1
NC60
Calis toga- GSE_FCB GA998
Calis toga- GSE_FCB GA998
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Calistoga(4/5)-PWR/GND
Calistoga(4/5)-PWR/GND
Calistoga(4/5)-PWR/GND
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
Cus tom
Cus tom
Cus tom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
NC
NC
RESERVED26
RESERVED27
RESERVED28
RESERVED29
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
RESERVED38
RESERVED39
RESERVED40
RESERVED41
RESERVED42
LA-4421P
LA-4421P
LA-4421P
1
W30
NC61
Y6
NC62
AL1
NC63
Y5
NC64
Y10
NC65
W10
NC66
W25
NC67
V24
NC68
U24
NC69
V10
NC70
U10
NC71
K18
NC72
Y25
Y24
AB22
AB21
AB19
AB16
AB14
AA12
W24
AA24
AB24
AB20
AB18
AB15
AB13
AB12
AB17
0.2
0.2
9 40Friday, Augu st 08, 20 08
9 40Friday, Augu st 08, 20 08
9 40Friday, Augu st 08, 20 08
0.2
2940mA
1
+
+
C37
C37
C41
C41
2
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
+VCCP
RB75 1V-40TE17 _SOD3 23-2
RB75 1V-40TE17 _SOD3 23-2
1 2
12
R168
R168
@
@
5
1
1
1
1
C39
C39
C261
C261
2
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
10U_0805_10V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
D15
@D15
@
+2.5VS
0.47U _0603 _16VY5V
0.47U _0603 _16VY5V
5
C265
C265
2
1
+
+
C40
C40
2
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
1
C266
C266
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1250mA
C25
C25
1 2
0.47U _0603 _16VY5V
0.47U _0603 _16VY5V
C22
C22
1 2
10mil
0.47U _0603 _16VY5V
0.47U _0603 _16VY5V
1
C281
C281
2
4.7U_0603_6.3V4Z~D
4.7U_0603_6.3V4Z~D
C283
C283
780mA
10mil
C276
C276
4.7U_0603_6.3V4Z~D
4.7U_0603_6.3V4Z~D
10mil
2
1
+1.5VS
C250
C250
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+VCCP
1
2
1
2
U4_A14
U4_A7
U4_AA1
U4_F1
10mil
2
C248
C248
0.47U _0402 _10V4Z~D
0.47U _0402 _10V4Z~D
1
+VCCP
D D
10_0 402_5 %
10_0 402_5 %
C C
B B
A A
4
U1D
U1D
T26
VCC0
R26
VCC1
P26
VCC2
N26
VCC3
M26
VCC4
V19
VCC5
U19
VCC6
T19
VCC7
W18
VCC8
V18
VCC9
T18
VCC10
R18
VCC11
W17
VCC12
U17
VCC13
R17
VCC14
W16
VCC15
V16
VCC16
T16
VCC17
R16
VCC18
V15
VCC19
U15
VCC20
T15
VCC21
AD33
VCCAUX1
AD32
VCCAUX2
AD31
VCCAUX3
AD30
VCCAUX4
AD29
VCCAUX5
AD28
VCCAUX6
AD27
VCCAUX7
AC27
VCCAUX8
AD26
VCCAUX9
AC26
VCCAUX10
AB26
VCCAUX11
AE19
VCCAUX12
AE18
VCCAUX13
AF17
VCCAUX14
AE17
VCCAUX15
AF16
VCCAUX16
AE16
VCCAUX17
AF15
VCCAUX18
AE15
VCCAUX19
J14
VCCAUX20
J10
VCCAUX21
H10
VCCAUX22
AE9
VCCAUX23
AD9
VCCAUX24
U9
VCCAUX25
AD8
VCCAUX26
AD7
VCCAUX27
AD6
VCCAUX28
A14
VTT0
D10
VTT1
P9
VTT2
L9
VTT3
D9
VTT4
P8
VTT5
L8
VTT6
D8
VTT7
P7
VTT8
L7
VTT9
D7
VTT10
A7
VTT11
P6
VTT12
L6
VTT13
G6
VTT14
D6
VTT15
U5
VTT16
P5
VTT17
L5
VTT18
G5
VTT19
D5
VTT20
Y4
VTT21
U4
VTT22
P4
VTT23
L4
VTT24
G4
VTT25
D4
VTT26
Y3
VTT27
U3
VTT28
P3
VTT29
L3
VTT30
G3
VTT31
D3
VTT32
Y2
VTT33
U2
VTT34
P2
VTT36
L2
VTT35
G2
VTT37
D2
VTT38
AA1
VTT39
F1
VTT40
VCCATVDACA0
VCCATVDACA1
VCCATVDACB0
VCCATVDACB1
VCCATVDACC0
VCCATVDACC1
VCCDTVDAC
VCCDQTVDAC
POWER
POWER
VCCDHMPLL1
VCCDHMPLL2
VCCTXLVDS0
VCCTXLVDS1
VCCACRTDAC0
VCCACRTDAC1
VSSACRTDAC
Calis toga- GSE_FCB GA998
Calis toga- GSE_FCB GA998
4
VCCATVBG
VSSATVBG
VCCDLVDS0
VCCDLVDS1
VCCDLVDS2
VCCAMPLL
VCCADPLLA
VCCADPLLB
VCCA3GPLL
VCCA3GBG
VSSA3GBG
VCCALVDS
VSSALVDS
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCAHPLL
VCC3G0
VCC3G1
VCCSYNC
VTT41
VTT42
VTT43
VTT44
VTT45
B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26
N33
M33
J23
C24
B24
B25
B31
B32
P1
L1
G1
U1
Y1
+1.5VS
400mA
2mA
10mA
144mA
+1.5VS_MPL L
+1.5VS_H PLL
+1.5VS_D PLLA
+1.5VS_D PLLB
+1.5VS
+2.5VS
+1.5VS_3 GPLL
+2.5VS
+2.5VS
+2.5VS_C RTDAC
Disable TV
20mA
40mA
U4_AB3 3
U4_AM32
10mil
C318
C318
10mil
10mil
10mil
C54
C54
1U_0603_10V6K~D
1U_0603_10V6K~D
150mA
60mA
400mA
+VCCP
10mil
1
2
1U_0603_10V6K~D
1U_0603_10V6K~D
1
C319
C319
1U_0 402_6 .3V4Z~D
1U_0 402_6 .3V4Z~D
2
3
+1.5VS
+3VS
1
1
C23
C23
C239
2
2
1
C239
10U_0805_10V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
C286
C286
0.1U_0402_16V4Z~D
2
1U_0603_10V6K~D
1U_0603_10V6K~D
C288
C288
+1.8V
533 MTS=1720mA
1
1
1
C293
C293
C330
C330
2
2
2
1U_0603_10V6K~D
1U_0603_10V6K~D
4.7U_0603_6.3V4Z~D
4.7U_0603_6.3V4Z~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
1
1
C24
C24
C235
2
2
C235
10U_0805_10V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
1
C329
C329
2
1
1U_0603_10V6K~D
1U_0603_10V6K~D
2
45mA
45mA
50mA
50mA
Route +2.5VS fr om GMCH pinN33 to
decoupling cap <200mil to the edge.
70mA
70mA
1
1
1
C244
C244
C242
C242
2
2
2
C241
C241
10U_0805_10V4Z~D
10U_0805_10V4Z~D
0.022U_0402_16V7K
0.022U_0402_16V7K
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
Route VSSACRTDAC gnd from GMCH to
decoup ling cap gro und lead an d then
connec t to the g nd plane.
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
3
C267
C267
R172
R172
12
+2.5VS
10_0 603_5 %
10_0 603_5 %
CRTDAC: Route FB
within 3" of Calistoga
+2.5VS
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+2.5VS
1
C245
C245
C256
C256
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+1.5VS_P CIE
1
C254
C254
C253
C253
2
1
10U_0805_10V4Z~D
10U_0805_10V4Z~D
2
2
PCI-E/MEM/PSB PLL decoupling
R210
R210
+1.5VS_MPL L
1
C48
C48
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
1
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
C277
C277
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
45mA Max.
R45
R45
0_06 03_5%
0_06 03_5%
1
C52
C52
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
L20
L20
1 2
FBM-L10-1 6080 8-301 -T_060 3
FBM-L10-1 6080 8-301 -T_060 3
330U_D2E_2.5VM
330U_D2E_2.5VM
1
C249
C249
C257
C257
+
+
2
0_08 05_5%
0_08 05_5%
1
+
+
C259
C259
2
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
+1.5VS_3 GPLL
1
C278
C278
2
10U_0805_10V4Z
10U_0805_10V4Z
12
R177
R177
12
Title
Title
Title
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
Cus tom
Cus tom
Cus tom
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
0_06 03_5%
0_06 03_5%
+1.5VS
+1.5VS +1.5VS
+1.5VS
+2.5VS
1
C260
C260
2
4.7U_0603_6.3V4Z~D
4.7U_0603_6.3V4Z~D
close pin C29/D 29
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Calistoga(5/5)-PWR/GND
Calistoga(5/5)-PWR/GND
Calistoga(5/5)-PWR/GND
1
+1.5VS
+1.5VS_H PLL
1
C43
C43
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+1.5VS_D PLLA+1.5VS_D PLLB
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C236
C236
1
2
1
C247
C247
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
LA-4421P
LA-4421P
LA-4421P
1
+1.5VS+1.5VS_3 GPLL
1
@
@
C287
C287
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
45mA Max.
R38
R38
0_06 03_5%
0_06 03_5%
1
C44
C44
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
40mA Max.40mA Max.
L2
L2
1 2
FBM-L10-1 6080 8-301 -T_060 3
FBM-L10-1 6080 8-301 -T_060 3
330U_D2E_2.5VM
330U_D2E_2.5VM
1
C13
C13
+
+
2
+2.5VS
1
C237
C237
2
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
close pin B31
10 40Friday, Augus t 08, 200 8
10 40Friday, Augus t 08, 200 8
10 40Friday, Augus t 08, 200 8
12
+1.5VS
1
C246
C246
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.2
0.2
0.2
5
DDR_ A_DQS#[0 ..7]<7>
DDR_ A_D[0..63]< 7>
DDR_ A_DM[0..7]<7>
DDR_ A_DQS[0..7]<7>
DDR_ A_MA[0..13]<7>
D D
+1.8V
2
2
C91
C91
1
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
+
+
@
@
C69
C69
C61
C61
2
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
C C
+0.9VS
1
1
1
C79
C79
C84
C84
C104
C104
2
2
B B
A A
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DDR_ A_MA0
DDR_ A_MA13
DDR_ CS0#
M_ODT0
DDR_ A_MA1
DDR_ A_MA3
DDR_ A_MA5
DDR_ A_CAS#
DDR_ A_WE#
DDR_ A_BS0
M_ODT1
DDR_ CS1#
DDR_ A_BS2
DDR_ CKE0
5
2
C90
C90
C89
C89
1
1
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
1
C68
C68
C88
C88
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
Layout Note:
Place one cap c lose to every 2 pullup
resistors termi nated to +0.9V S
1
1
C81
C81
C102
C102
C103
C103
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+0.9VS
RP1
RP1
1 8
2 7
3 6
4 5
56_0 804_8 P4R_5 %
56_0 804_8 P4R_5 %
RP2
RP2
1 8
2 7
3 6
4 5
56_0 804_8 P4R_5 %
56_0 804_8 P4R_5 %
RP3
RP3
1 8
2 7
3 6
4 5
56_0 804_8 P4R_5 %
56_0 804_8 P4R_5 %
R159
R159
1 2
56_0 402_5 %
56_0 402_5 %
R160
R160
1 2
56_0 402_5 %
56_0 402_5 %
2
C70
C70
1
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
C87
C87
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
C83
C83
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
RP5
RP5
56_0 804_8 P4R_5 %
56_0 804_8 P4R_5 %
RP6
RP6
56_0 804_8 P4R_5 %
56_0 804_8 P4R_5 %
RP4
RP4
56_0 804_8 P4R_5 %
56_0 804_8 P4R_5 %
C71
C71
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
18
27
36
45
18
27
36
45
18
27
36
45
2
1
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
C82
C82
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DDR_ A_RAS#
DDR_ A_MA4
DDR_ A_MA2
DDR_ A_BS1
DDR_ CKE1
DDR_ A_MA7
DDR_A_MA6
DDR_ A_MA11
DDR_ A_MA12
DDR_ A_MA9
DDR_ A_MA8
DDR_A_MA10
C101
C101
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4
Layout Note:
Place near JDIM 1
1
1
1
C78
C78
C99
C99
2
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4
1
1
C80
C80
C100
C100
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
Layout Note:
Place these resistor
closely DIMMA,all
trace length<750 mil
Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1.3"
3
+1.8V
12
R41
R41
1K_04 02_1 %
1K_04 02_1 %
1K_04 02_1 %
1K_04 02_1 %
12
R43
R43
+DIMM_VREF
20mils
1
C86
C86
0.1U_ 0402_ 16V4Z~D
0.1U_ 0402_ 16V4Z~D
2
+DIMM_VREF
Share +DIMM_VRE F for
1.DDRII VREF
2.GMCH SM_VREF_ 0
SM_VREF_ 1
1
C92
C92
2.2U_ 0603_ 6.3V6K~D
2.2U_ 0603_ 6.3V6K~D
2
+3VS
@
@
1
C360
C360
2
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+DIMM_VREF
DDR_ A_D0
DDR_ A_D1
DDR_ A_DQS#0
DDR_ A_DQS0
DDR_ A_D2
DDR_ A_D3
DDR_ A_D9
DDR_ A_D8
DDR_ A_DQS#1
DDR_ A_DQS1
DDR_ A_D10
DDR_ A_D11
DDR_ A_D16
DDR_ A_D17
DDR_ A_DQS#2
DDR_ A_DQS2
DDR_ A_D18
DDR_ A_D19
DDR_ A_D24
DDR_ A_D25
DDR_ A_DM3
DDR_ A_D26
DDR_ A_D27
DDR_ CKE0<6>
DDR_ A_BS2< 7>
DDR_ A_BS0< 7>
DDR_ A_WE#<7> DDR_ CS0# <6>
DDR_ A_CAS#<7>
DDR_ CS1#<6>
M_ODT1<6>
CLK_ SMBDATA<12>
CLK_ SMBCLK<12>
1
C361
C361
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
DDR_ CKE0
DDR_ A_BS2
DDR_ A_MA12
DDR_ A_MA9
DDR_A_MA8
DDR_ A_MA5
DDR_ A_MA3
DDR_ A_MA1
DDR_ A_MA10
DDR_ A_BS0
DDR_ A_WE#
DDR_ A_CAS#
DDR_ CS1#
M_ODT1
DDR_ A_D32
DDR_ A_D33
DDR_ A_DQS#4
DDR_ A_DQS4
DDR_ A_D34
DDR_ A_D35
DDR_ A_D40
DDR_ A_D41
DDR_ A_DM5
DDR_ A_D42
DDR_ A_D43
DDR_ A_D48
DDR_ A_D49
DDR_ A_DQS#6
DDR_ A_DQS6
DDR_ A_D50
DDR_ A_D51
DDR_ A_D56
DDR_ A_D57
DDR_ A_DM7
DDR_ A_D58
DDR_ A_D59
CLK_ SMBDATA
CLK_ SMBCLK
Compal Secret Data
Compal Secret Data
Compal Secret Data
+1.8V +1.8V
+3VS
Deciphered Date
Deciphered Date
Deciphered Date
2
JDIM1
JDIM1
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
FOX_AS0A426- N2SN-7 F~D
FOX_AS0A426- N2SN-7 F~D
ME@
ME@
DIMMA
2
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
NC/A15
NC/A14
RAS#
ODT0
NC/A13
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
2
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
CK0
CK0#
VSS
VSS
VSS
VSS
NC
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
S0#
VDD
VDD
NC
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
CK1
CK1#
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SAO
SA1
DDR_ A_D4
4
DDR_ A_D5
6
8
DDR_ A_DM0
10
12
DDR_ A_D6
14
DDR_ A_D7
16
18
DDR_ A_D12
20
DDR_ A_D13
22
24
DDR_ A_DM1
26
28
M_CLK_ DDR0
30
M_CLK_ DDR# 0
32
34
DDR_ A_D14
36
DDR_ A_D15
38
40
42
DDR_ A_D20
44
DDR_ A_D21
46
48
50
DDR_ A_DM2
52
54
DDR_ A_D22
56
DDR_ A_D23
58
60
DDR_ A_D28
62
DDR_ A_D29
64
66
DDR_ A_DQS#3
68
DDR_ A_DQS3
70
72
DDR_ A_D30
74
DDR_ A_D31
76
78
DDR_ CKE1
80
82
84
86
88
DDR_A_MA11
90
DDR_ A_MA7
92
DDR_A_MA6
94
96
DDR_ A_MA4
98
DDR_ A_MA2
100
DDR_ A_MA0
102
104
DDR_ A_BS1
106
DDR_ A_RAS#
108
DDR_ CS0#
110
112
M_ODT0
114
DDR_ A_MA13
116
118
120
122
DDR_ A_D36
124
DDR_ A_D37
126
128
DDR_ A_DM4
130
132
DDR_ A_D38
134
DDR_ A_D39
136
138
DDR_ A_D44
140
DDR_ A_D45
142
144
DDR_ A_DQS#5
146
DDR_ A_DQS5
148
150
DDR_ A_D46
152
DDR_ A_D47
154
156
DDR_ A_D52
158
DDR_ A_D53
160
162
M_CLK_ DDR1
164
M_CLK_ DDR# 1
166
168
DDR_ A_DM6
170
172
DDR_ A_D54
174
DDR_ A_D55
176
178
DDR_ A_D60
180
DDR_ A_D61
182
184
DDR_ A_DQS#7
186
DDR_ A_DQS7
188
190
DDR_ A_D62
192
DDR_ A_D63
194
196
R53 10 K_040 2_5%
R53 10 K_040 2_5%
198
200
1 2
R52 10 K_040 2_5% R52 10 K_040 2_5%
1 2
Title
Title
Title
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
Size Docum ent N umb er Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
M_CLK_ DDR0 <6 >
M_CLK_ DDR# 0 <6 >
R54
R54
1 2
0_04 02_5%
0_04 02_5%
DDR_ CKE1 <6>
DDR_ A_BS1 <7>
DDR_ A_RAS# <7>
M_ODT0 <6 >
M_CLK_ DDR1 <6 >
M_CLK_ DDR# 1 <6 >
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDRII-SODIMMA
DDRII-SODIMMA
DDRII-SODIMMA
LA-4421P
LA-4421P
LA-4421P
1
PM_EXTTS#0 <6>
0.2
0.2
11 40Friday, Augus t 08, 200 8
11 40Friday, Augus t 08, 200 8
11 40Friday, Augus t 08, 200 8
1
0.2
5
PCI
SRC
CPU
CLKSEL1
FSA
CLKSEL0
0
MHz
266
MHz
1000
MHz
33.30
DOT_96
MHz
MHz
14.318 96.0 48.0
FSC FSB REF
CLKSEL2
0 1000 133 33.31 14.318 96.0 48.0
0 1001 200 33.30 14.318 96.0 48.0
0 1001 166 33.31 14.318 96.0 48.0
D D
1 1000 333 33.30 14.318 96.0 48.0
1 1000 100 33.31 14.318 96.0 48.0
1 1001 400 33.30 14.318 96.0 48.0
1 1 1
+VCCP
R138
R138
2.2K_0402_5%
2.2K_0402_5%
FSA
C C
CPU_BSEL0<4>
CPU_BSEL1<4>
B B
CPU_BSEL2<4>
A A
R147
R147
0_0402_5%
0_0402_5%
1 2
R91
R91
0_0402_5%
0_0402_5%
R100
R100
10K_0402_5%
10K_0402_5%
FSC
R95
R95
0_0402_5%
0_0402_5%
12
@
@1 2
+VCCP
FSB
@
@
+VCCP
12
@
@1 2
C169 22P_0402_50V8JC169 22P_0402_50V8J
14.31818MHZ_16PF_DSX840GA
14.31818MHZ_16PF_DSX840GA
C162 22P_0402_50V8JC162 22P_0402_50V8J
Routing the trace at least 10mil
5
R140
R140
56_0402_5%
56_0402_5%
1 2
1 2
12
R141
R141
1K_0402_5%
1K_0402_5%
@
@
R81
R81
1K_0402_5%
1K_0402_5%
@
@
1 2
1 2
12
R82
R82
0_0402_5%
0_0402_5%
R97
R97
1K_0402_5%
1K_0402_5%
@
@
1 2
1 2
12
R98
R98
0_0402_5%
0_0402_5%
R142
R142
1K_0402_5%
1K_0402_5%
R86
R86
1K_0402_5%
1K_0402_5%
R99
R99
1K_0402_5%
1K_0402_5%
Reserved
MCH_CLKSEL0 <6>
MCH_CLKSEL1 <6>
MCH_CLKSEL2 <6>
12
Y2
Y2
For ITP _EN, 0 =SRC8/S RC8#; 1 = ITP/I TP#
For PCI4 _SEL, 0 = Pin2 4/25 : D OT96 / DOT96#
Pin2 8/29 : L CDCLK / LCDCLK #
For PCI2 _TME:0= Overclo cking of CPU an d SRC a llowed
(ICS onl y) 1= Overclo cking of CPU an d SRC N OT allo wed
CLK_XTAL_IN
CLK_XTAL_OUT
4
USB
MHz
1 = Pin2 4/25 : SRC_0 / SRC_0#
Pin2 8/29 : 27M/27M _SS
R129
R129
10K_0402_5%
10K_0402_5%
@
@
1 2
ITP_EN PCI4_SEL PCI2_TME
R132
R132
10K_0402_5%
10K_0402_5%
1 2
4
+3VS
+VCCP
CLK_ICH_48M<17>
CLK_ICH_14M<17>
VGATE<17,25,36>
H_STP_CPU#<17>
H_STP_PCI#<17>
CLK_PCI_LPC<25>
CLK_PCI_ICH<15>
+3VS+3VS +3VS
R119
R119
10K_0402_5%
10K_0402_5%
@
@
1 2
R117
R117
10K_0402_5%
10K_0402_5%
1 2
1
C181
C181
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
1
C198
C198
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
3
1
2
+3VM_CK505
1 2
R78 0_0805_5%R78 0_0805_5%
1 2
R131 0_0805_5%R131 0_0805_5%
1
C151
C151
10U_0805_10V4Z~D
10U_0805_10V4Z~D
2
+1.05VM_CK505
1
C163
C163
10U_0805_10V4Z~D
10U_0805_10V4Z~D
2
SA000020K00 (Silego : SLG8SP556VTR )
SA000020H10 (ICS : ICS9LPRS387AKLFT)
+3VM_CK505
U11
U11
55
VDD_SRC
6
VDD_REF
12
VDD_PCI
72
VDD_CPU
19
VDD_48
27
VDD_PLL3
FSA
FSB
FSC
VGATE
H_STP_CPU#
H_STP_PCI#
CLK_XTAL_IN
CLK_XTAL_OUT
PCI2_TME
PCI4_SEL
ITP_EN
66
VDD_CPU_IO
31
VDD_PLL3_IO
62
VDD_SRC_IO
52
VDD_SRC_IO
23
VDD_IO
38
VDD_SRC_IO
20
USB_0/FS_A
2
FS_B/TEST_MODE
7
REF_0/FS_C/TEST_
8
REF_1
1
CKPWRGD/PD#
11
NC
53
CPU_STOP#
54
PCI_STOP#
5
XTAL_IN
4
XTAL_OUT
13
PCI_1
14
PCI_2
15
PCI_3
16
PCI_4/SEL_LCDCL
17
PCIF_5/ITP_EN
18
VSS_PCI
3
VSS_REF
22
VSS_48
26
VSS_IO
69
VSS_CPU
30
VSS_PLL3
34
VSS_SRC
59
VSS_SRC
42
VSS_SRC
73
VSS
SLG8SP556VTR_QFN72_10X10
SLG8SP556VTR_QFN72_10X10
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEE T OF ENGINEERING DRA WING IS THE PROPRIE TARY PR OPERTY OF COMPA L ELECTRONICS , INC. AND CONTAI NS CONFIDENTIA L
THIS SHEE T OF ENGINEERING DRA WING IS THE PROPRIE TARY PR OPERTY OF COMPA L ELECTRONICS , INC. AND CONTAI NS CONFIDENTIA L
THIS SHEE T OF ENGINEERING DRA WING IS THE PROPRIE TARY PR OPERTY OF COMPA L ELECTRONICS , INC. AND CONTAI NS CONFIDENTIA L
AND TRADE S ECRET INFORMA TION. THIS SHEE T MAY NOT B E TRANSFER ED FROM THE CUS TODY OF THE COMPETEN T DIVIS ION OF R&D
AND TRADE S ECRET INFORMA TION. THIS SHEE T MAY NOT B E TRANSFER ED FROM THE CUS TODY OF THE COMPETEN T DIVIS ION OF R&D
AND TRADE S ECRET INFORMA TION. THIS SHEE T MAY NOT B E TRANSFER ED FROM THE CUS TODY OF THE COMPETEN T DIVIS ION OF R&D
DEPARTME NT EXCEP T AS AU THORIZED BY COMP AL ELE CTRONICS, INC. NE ITHER THIS SH EET NOR THE INFORMA TION IT CONTAINS
DEPARTME NT EXCEP T AS AU THORIZED BY COMP AL ELE CTRONICS, INC. NE ITHER THIS SH EET NOR THE INFORMA TION IT CONTAINS
DEPARTME NT EXCEP T AS AU THORIZED BY COMP AL ELE CTRONICS, INC. NE ITHER THIS SH EET NOR THE INFORMA TION IT CONTAINS
MAY BE US ED B Y O R DIS CLO SED TO ANY T HIRD PART Y WIT HOUT PR IOR WRIT TE N CO NSE NT O F CO MP AL ELE CT RONIC S, INC.
MAY BE US ED B Y O R DIS CLO SED TO ANY T HIRD PART Y WIT HOUT PR IOR WRIT TE N CO NSE NT O F CO MP AL ELE CT RONIC S, INC.
MAY BE US ED B Y O R DIS CLO SED TO ANY T HIRD PART Y WIT HOUT PR IOR WRIT TE N CO NSE NT O F CO MP AL ELE CT RONIC S, INC.
3
1 2
4.7P_0402_50VNPO
4.7P_0402_50VNPO
@
@
1 2
1 2
+1.05VM_CK505
1 2
1 2
C392
C392
1 2
1 2
R109
R109
10K_0402_5%
10K_0402_5%
@
@
R110
R110
10K_0402_5%
10K_0402_5%
R13733_0402_5%
R13733_0402_5%
R10133_0402_5%
R10133_0402_5%
R11533_0402_5% R11533_0402_5%
R12133_0402_5%
R12133_0402_5%
C175
C175
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
C152
C152
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
2
1
1
C197
C197
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
2
1
C153
C153
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
SDA
SCL
CPU_0
CPU_0#
CPU_1
CPU_1#
SRC_0/DOT_96
SRC_0#/DOT_96#
LCDCLK/27M
LCDCLK#/27M_SS
SRC_2
SRC_2#
SRC_3
SRC_3#
SRC_4
SRC_4#
SRC_6
SRC_6#
SRC_7
SRC_7#
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
SRC_9
SRC_9#
SRC_10
SRC_10#
SRC_11
SRC_11#
CLKREQ_3#
CLKREQ_4#
CLKREQ_6#
CLKREQ_7#
CLKREQ_9#
SLKREQ_10#
CLKREQ_11#
USB_1/CLKREQ_A#
2007/10/15 2008/10/15
2007/10/15 2008/10/15
2007/10/15 2008/10/15
C199
C199
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
C167
C167
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
CLK_SMBDATA
9
CLK_SMBCLK
10
CLK_CPU_BCLK
71
CLK_CPU_BCLK#
70
CLK_MCH_BCLK
68
CLK_MCH_BCLK#
67
CLK_MCH_DREFCLK
24
CLK_MCH_DREFCLK#
25
MCH_SSCDREFCLK
28
MCH_SSCDREFCLK#
29
CLK_MCH_3GPLL
32
CLK_MCH_3GPLL#
33
35
36
CLK_PCIE_CARD
39
CLK_PCIE_CARD#
40
CLK_PCIE_WLAN
57
CLK_PCIE_WLAN#
56
61
60
64
63
CLK_PCIE_LAN
44
CLK_PCIE_LAN#
45
CLK_PCIE_ICH
50
CLK_PCIE_ICH#
51
48
47
37
41
WLAN_CLKREQ#
58
65
CLKREQ_LAN#
43
49
46
MCH_CLKREQ#
21
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1
C155
C155
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
1
C189
C189
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
2
1
C154
C154
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
1
C200
C200
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
2.2K_0402_5%
2.2K_0402_5%
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
ICH_SMBDATA<17>
ICH_SMBCLK<17>
CLK_SMBDATA <11>
CLK_SMBCLK <11>
CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>
CLK_MCH_BCLK <6>
CLK_MCH_BCLK# <6>
CLK_MCH_DREFCLK <6>
CLK_MCH_DREFCLK# <6>
MCH_SSCDREFCLK <6>
MCH_SSCDREFCLK# <6>
CLK_MCH_3GPLL <8>
CLK_MCH_3GPLL# <8>
CLK_PCIE_CARD <23>
CLK_PCIE_CARD# <23>
CLK_PCIE_WLAN <19>
CLK_PCIE_WLAN# <19>
CLK_PCIE_LAN <24>
CLK_PCIE_LAN# <24>
CLK_PCIE_ICH <17>
CLK_PCIE_ICH# <17>
6 1
+3VS
354
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
SRC P ORT L IST
PORT
SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11
MCH_CLKREQ#
CLKREQ_LAN#
WLAN_CLKREQ#
REQ PORT LIST
REQ_3#
WLAN_CLKREQ# <19>
CLKREQ_LAN# <24>
MCH_CLKREQ# <6>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Clock Generator CK505
Clock Generator CK505
Clock Generator CK505
1
+3VS
R112
R112
Q10A
Q10A
2
Q10B
Q10B
DEVICE
MCH_DREFCLK
MCH_3GPLL
PCIE_CARDREADER
PCIE_WLAN
PCIE_LAN
PCIE_ICH
R139 10K_0402_5%R139 10K_0402_5%12
R111 10K_0402_5%R111 10K_0402_5%
12
R84 10K_0402_5%R84 10K_0402_5%
12
DEVICEPORT
PCIE_WLAN
PCIE_LAN
MCH_3GPLL
LA-4421P
LA-4421P
LA-4421P
12 40Friday, August 08, 2008
12 40Friday, August 08, 2008
12 40Friday, August 08, 2008
1
R108
R108
2.2K_0402_5%
2.2K_0402_5%
CLK_SMBDATA
CLK_SMBCLK
+3VS
0.2
0.2
0.2
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