Abit CX6E User Manual

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The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this manual.

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If you do not properly set the motherboard settings causing the motherboard to malfunction or fail, we cannot guarantee any responsibility.

CX6 Motherboard User’s Manual



Table of Contents

Chapter 1. Introduction of CX6 Features



Features of this Motherboard






Layout Diagram



The System Block Diagram


Chapter 2. Installing the Motherboard



Installing the Motherboard to the Chassis



Installation of the Pentium II/III CPU



Installing System Memory



Connectors, Headers and Switches


Chapter 3. Introduction of The BIOS


3-1.CPU Soft Menu™ II


3-2.Standard CMOS Features Setup Menu


3-3.Advanced BIOS Features Setup Menu


3-4.Advanced Chipset Features Setup Menu


3-5.Integrated Peripherals



Power Management Setup Menu



PnP/PCI Configurations



PC Health Status



Load Fail-SafeDefaults



Load Optimized Defaults


3-11.Set Password



Save & Exit Setup



Exit Without Saving



Rev. 1.00

Appendix A Intel INF Installation Utility for Windows® 98 SE Appendix B Installing the Audio Driver for Windows® 98 SE Appendix C Installing the Audio Drivers for the Windows® NT Appendix D BIOS Flashing User Instructions

Appendix E Installing the HighPoint XStore Pro Utility

Appendix F Hardware Monitoring Function (Installing the Winbond Hardware Doctor Utility)

Appendix G Installation Guide for Suspend to RAM Appendix H Troubleshooting (Need Assistance?) Appendix I How to Get Technical Support

Introduction of CX6 Features




Chapter 1. Introduction of CX6 Features

1-1.Featuresof this Motherboard

This motherboard is designed for the new generation of CPUs. It supports the Intel SLOT1 structure (Pentium II/III processor), up to 1GB of memory, super I/O, and Green PC functions. The motherboard provides high performance for server systems and meets the requirements for future multimedia desktop systems.

The CX6 uses the new generation Intel® 820 chipset (Camino) for more efficiency and high integration of the system. What are the main features of the Intel® Camino chipset? Its structure is shown in Figure1-2.

133 MHz System Bus

!The Intel® 820 platform supports the new 133 MHz system bus

"Up to 33% increased peak bandwidth over the Intel® 440BX platform.

AGP 4x Graphics

!Up to 1GB/Sec transfer rate

"Twice the peak bandwidth of AGP 2x of the 440BX AGPset

!Broad industry support for AGP 4x from all leading graphics IHVs

"NVIDIA, 3Dfx, S3, ATI, Intel, Matrox, etc.

RDRAM Memory

!Provides memory bandwidth to keep up with ever increasing application demands

"Faster processors, graphics, and I/O

!RDRAM delivers up to 3x the effective bandwidth of PC100 SDRAM

"1.6 GByte/sec for PC800 RDRAM

!RDRAM provides the required headroom for further application improvement

"Constant Computing

"More realistic environments

"Platform longevity and stability

The Intel® 820 chipset is a combination of three chips: the FW82820, FW82801 and FW82802. The FW82820 is called MCH chip (MemoryControllerHub), FW82801 is called ICH chip (I/OControllerHub), FW82802 is called FWH chip (FirmWareHub).

MCH (Memory Controller Hub)

The MCH provides the host interface, DRAM interface, I/O interface, and AGP interface in a Camino platform. Camino MCH is optimized for the Katmai or Coppermine processor. It supports a single channel of direct Rambus memory technology. Its AGP interface is fully compliant with AGP 2.0 specification. Communication to ICH is over a private interface or the hub interface (link). The Camino MCH contains the following functionality:

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Supports the Katmai and Coppermine processors at 100/133MHz for Slot 1

Supports an IOQ (In-OrderQueue) depth of 6

GTL+ host bus supporting 32-bithost addressing

Single Direct Rambus channel optimized for 300, 356 and 400 MHz operation

1GB DRAM supported with 256Mbit memory technology

AGP 2.0 interface with 1x/2x/4x data transfer and 2x/4x fast write capability

The hub interface (link) to ICH

Fully optimized data paths and buffering

Distributed arbitration for highly concurrent operation

ACPI 1.0 power management compliant

ICH (I/O Controller Hub)

The ICH is a highly integrated multifunctional component supporting the following functions and capabilities:

PCI Rev. 2.2 compliant with support for 33MHz PCI operations

Supports up to 6 Req/Gnt pairs (PCI Slots)

Integrated IDE controller with Ultra DMA/66 support

USB host interface with support for 2 USB ports

AC '97 2.1 compliant link for audio and telephony CODECs

Firmware Hub (FWH) interface support

FWH (FirmWare Hub)

The FWH component is part of several integrated Intel® chipsets. The FWH is key to enabling future security and manageability infrastructures for the PC platform. The device operates under the FWH interface/protocol. The hardware features of this device include aRandomNumberGenerator (RNG), fiveGeneralPurposeInputs (GPIs),register-basedblock locking, andhardware-basedlocking. An integrated combination of logic features andnon-volatilememory enables better protection for the storage/update of platform code/data, adds platform flexibility through additional GPIs and allows for quicker introduction of new security/manageability features into the current and future Intel® architecture platform. It's available in 8Mbit (82802AC), 4Mbit (82802AB), and 2Mbit (82802AA) densities. It uses the 32L PLCC or 40L TSOP industry standard packages.

AMR (Audio/Modem Riser)

The CX6 has one AMR slot onboard, called the Audio/ModemRiser(AMR) slot. The Audio/Modem Riser is an openindustry-standardspecification that defines a hardware


Introduction of CX6 Features




scalable OriginalEquipmentManufacturer (OEM) motherboard riser board and interface, which supports both audio and modem functions. The specification's main objective is to reduce the baseline implementation cost of audio and modem functionality. In accordance with PC user's demands forfeature-richPCs, combined with the industry's current trend towards lower cost PCs, all of theses functions are built into the motherboard. But motherboard integration of the modem subsystem has been problematic to date, in large part due to FCC and other international telecom certification processes that may delay the introduction of a motherboard. Resolving the homologation/certification issue for modems is one of the AMR specification's key objectives.

In the future, not only OEM motherboards will have an AMR design, the AMR card will appear in the market and you can make a choice in buying this kind of card according to your budget. But your motherboard must have an AMR slot to be able to plug an AMR card. The CX6 insures this expansibility for this issue.

Yamaha YMF752-Saudio chip

YMF752 is an AC’97 Audio CODEC LSI, which is fully compliant with the industry standard “Audio CODEC ’97” component specification (Revision 2.1).

YMF752 includes a SRC (Sampling Rate Converter) for support variable sampling rate, which can work the A/D and D/A converter at different rate. YMF752 has an AC-Linkserial interface, which can be used with digital controller LSI. Therefore, YMF752 is the best audio solution for both laptops and desktop PCs as well as AMR (Audio Modem Riser) and MDC (Mobile Daughter Card).

YMF752 also supports low power consumption while normal operating and allows for controlling the power down mode.

Direct Rambus Technology

During the past few years, computer main memory has become the speed bottleneck that has blocked improved system performance. This is true despite the fact that DRAM densities have been accelerating sharply from yesterday's 1Kbit per chip to today's 64Mbit devices. While that aspect of DRAM technology has advanced by a factor of 1,000 in the past 10 years, the time it takes to access main memory has improved by only a factor of five. The result is that memory bandwidth, the number of bytes per second that can be moved across memory I/O, has been hobbled. That sluggish performance improvement is now a severe drag on systems powered by microprocessors that have improved CPU performance 200 fold in the same timeframe.

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DRAM synchronization has set the stage for system designers to move from a 66MHz to a 100 MHz system bus, partially closing the speed gap between processor and memory. But even as engineering teams wrestle with this design challenge, microprocessors are advancing to speeds of 300MHz, 400MHz, and beyond.

Memory technologists are now developing new DRAM architectures that are expected to be fast enough to unleash the power of tomorrow's processors. These architectures add special registers to each DRAM pin and special controller functions to the DRAM array core. Currently, the most fully developed of these architectures is Direct Rambus DRAM (Direct RDRAM) which uses a special controller, layout, and bus to achieve high I/O bandwidth.

While other firms were employing techniques such as SRAM caches, parallel arrays of DRAMs, and expensive frame buffers to increase memory bandwidth, Rambus, Inc. took an entirely different tack. Rambus targeted a two-bytewide data path, 800MHz transfer rate, and a 95% protocol efficiency. The development resulted in a newchip-to-chipbus, termed the Direct Rambus Channel (DRC) which includes a controller and one or more Direct RDRAMs connected together via a common bus. Using a limited number ofhigh-speedsignals to carry all address, data, and control information, DRC links main memory to system devices that have a need to access memory, including microprocessors, DSPs, graphics processors, and ASICs. Low voltage swing signaling is used with conventional PCB technology to permit data transfer up to 800Mbits/s/pin, resulting in the 1.6GB/s peak bandwidth that will be required for Intel's projected 1999high-endsystems.

Table 1-1Direct Rambus Technology Features


800 MHz

Maximum Device Bandwidth

1.6 Gbytes/sec



Data Width

16 or 18 bits



Protocol Efficiency for 32-byteTransfers










STR (Suspend to RAM)

The CX6 supports the STR function. The STR function enables a PC to achieve the S3 state during idle periods, then quick “wake up” and retrieve the last “state” of the system before it went to sleep. When idle, STR-enabledsystems consume only a small fraction of the power used for full operation. Instead of shutting down the system to save power when not in use and then having to reboot later, users can let the STR function take over and not have to worry about using power to run all the electronics, fans and disks. When needed, a PC with STR function can restore all applications and features to an operational state within a few seconds.


Introduction of CX6 Features






Ultra DMA/66

The CX6 supports Ultra ATA/66 IDE devices. Ultra ATA/66 is the new standard for IDE devices. It enhances existing Ultra ATA/33 technology by increasing both performance and data integrity. This new high-speedinterface doubles the Ultra ATA/33 burst data transfer rate to 66.6 Mbytes/sec. The result is maximum disc performance using the current PCI local bus environment. You can connect either Ultra ATA/33 IDE devices or Ultra ATA/66 IDE devices to the IDE connectors on this motherboard.

PC Health

The CX6 has built-inhardware monitoring functions, that can monitor and protect your computer insuring a safe computing environment.

Sets You Free From the Y2K Threat

The potential threat of Year 2000 (Y2K) problems are making everyone very nervous. The Y2K issue applies to almost any device, firmware, or software that operates on or with year based dates. This problem is caused by a design flaw in the RealTimeClock (RTC) unit. The RTC only changes the last two digits of the year code, but not the century information. As a result, when it comes to 12:00 AM January 1, 2000 the RTC will switch from December 31 11:59 PM 1999 to 12:00 AM January 1 1900.

Y2K compliance deals with the date change over from 31 December 1999 to 1 January 2000, and with recording and reporting of all dates from the RTC including leap year dates. This motherboard is free from the Y2K problem because its BIOS are Y2K compliant.

Please Note

If the operating system or application software cannot handle Year 2000 dates, you will still be facing the Y2K threat because it is not a hardware problem that relates to the motherboard itself. According to Award BIOS, it is BIOS source code released after 31 May 1995 complies with all known Y2K issues; however, it may still fail the 2000.exe test. Award has modified its BIOS source code to accommodate the requirements of 2000.exe. Award BIOS source code issued later than 18 November 1996 passes the NTSL 2000.exe test program.

User’s Manual






1. CPU

# Supports Intel Pentium® III Coppermine with 128/256K

# Supports Intel Pentium® III Katmai

# Supports Intel Pentium III 450 ~ 800 MHz Processor cartridge.

# Supports Intel Pentium II 350 ~ 450 MHz Processor cartridge.

# Supports 100 and 133MHz CPU external clock speeds

2. Chipset

# Intel® 820 chipset (FW82820, FW82801 and FW82802AB)

# Supports Ultra DMA 33/66 IDE protocol

# Supports Advanced Configuration and Power Management Interface (ACPI)

# Supports AGP 1X/2X/4X (Sideband) 1.5V/3.3V device

3. Memory (System Memory)

# Two184-pinRIMM sockets support Direct Rambus Memory module

# Supports up to 1GB. (1GB uses 256Mbit technology)

# Supports PC600, PC700 and PC800 RDRAM

# Supports ECC

4. Yamaha YMF752-Saudio chip

YMF752 is an AC’97 Audio CODEC LSI, which is fully compliant with the industry standard “Audio CODEC ’97” component specification (Revision 2.1).

#AC’97 Revision 2.1 Compliant

#Exceeds PC’98/’99 Audio Performance Requirements

#Analog Inputs:

4 Stereo Inputs: LINE, CD, AUX

1 Monaural Inputs: PC BEEP Inputs

1 Independent Microphone Inputs

#PC BEEP can directly output to Line Out

#Internal +20dB amplifier circuitry for microphone

#Analog Outputs:

Stereo LINE Output with volume control

True LINE Level with volume control

Monaural Output with volume control

#Supports 3D Enhancement (Wide Stereo)

#Supports Variable Sampling Rate (48k/44.1k/22.05k/16k/11.025k/8kHz)

#The A/D and D/A converter can be worked at different sampling rate.