ZILOG Z90211, Z90212, Z90213, Z90218, Z90219 Datasheet
CP96TEL2400
P R E L I M I N A R Y
1
1
P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
Z90219/213/212/211/218
1
Z8
®
D
IGITAL
T
ELEVISION
C
ONTROLLERS
FEATURES
Z8-Based CMOS Microcontroller for Consumer
Television, Cable Box, and Satellite Receiver
Applications.
■
42-Pin SDIP Package
■
Z8
®
Microcontroller Core at 6 MHz
■
Mask ROM sizes Available in 8, 12 and 16 Kbytes
■
Eleven Pulse Width Modulators
■
On-Chip Infrared (IR) Capture Registers
■
Four Channel 3-bit Analog-to-Digital Converter
■
Twenty General Purpose I/O Pins
■
I
2
C Serial Communication Port)
On Screen Display (OSD) Section
■
Supports Displays up to 10 rows by 24 Columns with
256 Characters
■
Character Cell Resolution of 14 Pixels by 18 Scan lines
■
Variable Inter-row Spacing from 0-15 Horizontal Scan
Lines
■
Foreground and Background Colors Fully
Programmable by Character
GENERAL DESCRIPTION
The Z9021x Digital Television Controller (DTC) family is
Zilog’s latest and most powerful Z8-based DTC product offering. These parts feature larger system RAM and ROM
options, together with a host of new features including a
new color palette system, flexible inter-row spacing, higher
character cell resolution, background mesh effect, dedicated I.R. capture registers, on-chip Analog-to-Digital conversion, and a hardware Master mode I
2
C interface. The familiar Z8 core in combination with these advanced features
makes the Z9021x family an ideal choice for low to midrange televisions in both PAL and NTSC markets.
The Z9021x family consists of two basic device types;
Z9020x and Z9021x. The only difference between the two
types is the presence of a hardware I
2
C serial communication port and half-tone OSD circuitry on the Z9021x family.
Of course I
2
C communication is supported on the Z9020x
family in software with the dedication of any two I/O pins to
the task.
The Z9021x family takes full advantage of the Z8’s expanded register file space to offer greater flexibility in On
Screen Display creation.
Device
ROM
(KB)
RAM*
(Bytes)
I/O
Lines
Voltage
Range
Z90211 16 (OTP) 237 20 4.5V to 5.5V
Z90218 8 237 20 4.5V to 5.5V
Z90212 12 237 20 4.5V to 5.5V
Z90213 16 237 20 4.5V to 5.5V
Z90219 32 (ext.) 237 N/A 4.5V to 5.5V
Note: OTP and Z9021x products under development
Z90219/213/212/211
Z8
®
Digital Television Controllers Zilog
2
P R E L I M I N A R Y
CP96TEL2400
BLOCK DIAGRAM
Figure 1. Functional Block Diagram
8/12/16K Byte
Program ROM
Z8 CPU
Core
RESET
Oscillator
WDT
Counter
Timer
Counter
Timer
3-bit
ADC
IR
Counter
Port3
256 Byte
Register File
Port2
Port4
On Screen
Display
240 by 11-bit
Character RAM
9K by 7-bit
Character ROM
PWM 11
PWM 1
to
PWM 10
(14-bit)
(6-bit)
XTAL1
XTAL2
/RESET
ADC0
ADC1
ADC2
ADC3
IRIN
P30
P31
P34
P35
P21
P22
P23
P24
P25
P26
P27
P40
P41
P42
P43
P44
P45
P46
P47
P20
OSDX1
OSDX2
HSync
VSync
R
G
B
VBlank
PWM11
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
PWM10
& 10 by 8-bit
SCLK0
SDATA0
I
2
C
P1
P2
P3
P4
P5
P6
P7
Output
Port
Interface
SCLK1
SDATA1
HLFTN
Z9021x ONLY
Z9021x ONLY
Z90219/213/212/211
Zilog Z8
®
Digital Television Controllers
CP96TEL2400
P R E L I M I N A R Y
3
1
PIN IDENTIFICATION
PWM11/P7
PWM6/P6
PWM5/P5
PWM4/P4
PWM3/P3
PWM2/P2
PWM1/P1
P40
P34/ADC3
P35/ADC2
P41/ADC1
P31/ADC0
AGND
P42
P43
P30
P44/PWM7
P45/PWM8
P46/PWM9
P47/PWM10
P20/HLFTN
P27/SDATA1
P26/SCLK1
P25/SDATA0
P24/SCLK0
P23
P22
IRIN
P21
VCC
/RESET
XTAL2
XTAL1
GND
OSDX2
OSDX1
VSYNC
HSYNC
VBLANK
R
G
B
42
Z9021x
(T op View)
1
21 22
Loading...