ZILOG Z90202, Z90203, Z90209 Datasheet
FEATURES
ROM RAM* Speed Package
■ Part (KB) (Kbyte) (MHz) Type
Z90209 16 236 6 124-Pin PGA
Z90203 16 236 6 42-Pin SDIP
Z90202 8 236 6 42-Pin SDIP
*General-Purpose
■ 4.5V to 5.5V Operating Range
■ 0°C to +70°C Temperature Range
Z90209/203/202
Z90209/203/202
TELEVISION CONTROLLERS
■ On-Screen Display (OSD) Logic Circuits
■ One 14-Bit and One 108-Bit Pulse Width Modulator
(PWM) Circuits
■ 20 Input/Output Lines
■ Program Memory, Video RAM, and Register File
Address Spaces
■ Low-Power Consumption
GENERAL DESCRIPTION
The Z9020X Family of Digital Television Controllers are
cost-effective members of the Z8® single-chip
microcontroller family. The devices provides an ideal
performance and reliability solution for consumer and
industrial television applications.
The Z90209 is the ROMless In-Circuit Emulation (ICE )Chip
version of the Z90200 Digital Television Controller Family
used in emulators and development boards.
The device features an 8-bit internal data path controlled
by a Z8 microcontroller, On-Screen Display (OSD) logic
circuits, and Pulse Width Modulators (PWM). On-chip
peripherals include two register mapped I/O ports (Ports 2
and Port 3), interrupt control logic (one software, two
external and three internal interrupts) and a standby mode
recovery input port (Port 3, pin P30).
The OSD control circuits support ten rows by 24 columns
of characters. The character color is specified by character.
The OSD inter-row spacing is variable and can be
programmed from 0 to 15 horizontal scan lines. The OSD
is capable of displaying high resolution (14 x18 dot pattern)
characters.
A 14-bit PWM port provides enough voltage resolution for
a voltage synthesizer tuning system. Ten 8-bit PWM ports
are used for controlling audio signal levels to vary picture
levels.
■ Two On-Chip Counter/Timers
Three basic address spaces, The Program Memory, Video
RAM, and Register File, support a wide range of memory
configurations.
For applications demanding powerful I/O capabilities, the
Z9020X's dedicated input and output lines are grouped
into three ports, and are configurable under software
control to provide timing, status signals, parallel I/O and an
address/data bus for interfacing to external memory.
To unburden the program from coping with the real-time
problems such as counting/timing and data communication,
the Z9020X offers two on-chip counter/timers with a large
number of user selectable modes.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection Circuit Device
Power V
Ground GND V
CC
V
DD
SS
245
GENERAL DESCRIPTION (Continued)
Z90209/203/202
XTAL1
XTAL2
/RESET
ADC0
ADC1
ADC2
ADC3
IRIN
P30
P31
P34
P35
PWM11
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
PWM10
Oscillator
WDT
RESET
Counter
Timer
Counter
Timer
3-Bit
ADC
IR
Counter
IR
Counter
Port 3
PWM 11
(14-Bit)
PWM 1
to
PWM 10
(8-Bit)
16K Byte
Program ROM
Z8 CPU
Core
256 Byte
Register File
240 x 11-Bit
and
10 x 8-Bit
Character
RAM
9K x 7-Bit
Character
ROM
Port 2
Port 4
On-Screen
Display
P20
P21
P22
P23
P24
P25
P26
P27
P40
P41
P42
P43
P44
P45
P46
P47
OSDX1
OSDX2
HSYNC
VSYNC
R
G
B
VBLANK
246
Functional Block Diagram
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