ZILOG Z9011004PSC, Z9012004PSC, Z9013004PSC Datasheet
1
Z90110/120/130
CP95TEL1300
P R E L I M I N A R Y
CP95TEL1300 (10/95)
FEATURES
GENERAL DESCRIPTION
The Z901XX 40-pin Digital Television Controller is a costeffective member of the Z8® single-chip microcontroller
family. The device provides an ideal performance and
reliability solution for consumer and industrial television
applications.
The Z901XX offers mask-programmed ROM, which enables the Z8 microcontroller to be used in a high-volume
production application device embedded with a custom
program (customer-supplied program) and combines to
provide support for mid-range and low-end TV applications.
The device features an 8-bit internal data path controlled
by a Z8 microcontroller, On-Screen Display (OSD) logic
circuits, and Pulse Width Modulators (PWM). On-chip
peripherals include two register mapped I/O ports (Ports 2
and Port 3), interrupt control logic (one software, two
external and three internal interrupts) and a standby mode
recovery input port (Port 3, pin P30).
The OSD control circuits support six rows by 20 columns
of characters. The character color is specified by row. One
of the eight rows is assigned to show two kinds of colors for
bar type displays such as volume control. The OSD is
capable of displaying either low resolution (5x7 dot pattern)
or high resolution (11x15 dot pattern) characters.
A 14-bit PWM port provides enough voltage resolution for
a voltage synthesizer tuning system. Three 6-bit PWM
ports are used for controlling audio signal levels, and
Three 8-bit PWM ports used to vary picture levels.
Three basic address spaces, The Program Memory, Video
RAM, and Register File, support a wide range of memory
configurations.
For applications demanding powerful I/O capabilities, the
Z901XX's dedicated input and output lines are grouped
into three ports, and are configurable under software
control to provide timing, status signals, parallel I/O and an
address/data bus for interfacing to external memory.
To unburden the program from coping with the real-time
problems such as counting/timing and data communication,
the Z901XX offers two on-chip counter/timers with a large
number of user selectable modes.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection Circuit Device
Power V
CC
V
DD
Ground GND V
SS
PRELIMINARY
CUSTOMER PROCUREMENT SPECIFICATION
Z90110/120/130
40-PIN LOW-COST DIGIT AL
TELEVISION CONTROLLER
ROM RAM* Speed
n Part (KB) (Kbyte) (MHz)
Z90110 4 236 4
Z90120 6 236 4
Z90130 8 236 4
*General-Purpose
n 40-Pin DIP Package
n 4.5V to 5.5V Operating Range
n 0°C to +70°C Temperature Range
n Low-Power Consumption
n On-Screen Display (OSD) Logic Circuits
n One 14-Bit and Three 6-Bit Pulse Width Modulator
(PWM) Circuits
n 24 Input/Output Lines
n Program Memory, Video RAM, and Register File
Address Spaces
n Two On-Chip Counter/Timers
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Z90110/120/130
CP95TEL1300
P R E L I M I N A R Y
GENERAL DESCRIPTION (Continued)
Counter
Timer
Counter
Timer
6 KByte
Program ROM
RESET
Oscillator
WDT
Port 3/
Interrupt
Port 6
(Control)
Z8 CPU
Core
Port 2
256 Byte
Register File
Port 1
A8-15 AD0-7
PWM 1
14 -bit
PWM 6
to
PWM 8
6-bit
On Screen
Display
Port 0
120 Byte
Character RAM
3 KByte
Character ROM
P27
P26
P25
P24
P23
P22
P21
P20
PWM 6
PWM 7
PWM 8
OSCIN
OSCOU
T
HSYNC
VSYNC
VRED
VGREEN
VBLUE
VBLANK
XTAL1
XTAL2
/RESET
P30
P31
P34
P35
P36
P60
P61
P62
P63
P64
P65
AFCIN
PWM 1
PWM 9
to
PWM11
PWM 9
PWM 10
PWM 11
Functional Block Diagram
3
Z90110/120/130
CP95TEL1300
P R E L I M I N A R Y
PIN CONFIGURATION
40-Pin Mask-ROM Plastic DIP
/RESET
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P27
P26
P25
P24
P23
P22
P20
VBLANK
VBLUE
VGREEN
VRED
VSYNC
HSYNC
P21
PWM6
PWM7
PWM8
PWM9
PWM10
PWM11
Z90100
(LDTC)
1
2
9
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
PWM1
P35
P36
P34
P31
P30
XTAL1
XTAL2
P60
GND
P61
P62
VCC
P63
P64
P65
AFCIN
OSCIN
OSCOUT
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