ZILOG Z89331 Datasheet

FEATURES

PRELIMINARY

PRELIMINARY
CUSTOMER PROCUREMENT SPECIFICATION

Z89331

OTP DIGITAL
TELEVISION CONTROLLER

Z89331

CP95TEL1400

n Part ROM RAM* Speed

Number (KB) (Bytes) (MHz)

Z89331 24 640 12

*General-Purpose

n 42-Pin SDIP Package

n 4.75- to 5.25-Volt Operating Range
n 0°C to +70°C Temperature Range

n One-Time Programmable

GENERAL DESCRIPTION

The Z89331 One-Time Programmable (OTP) Digital
Television Controller is designed to provide complete
audio and video control of television receivers, video
recorders, and advanced on-screen display facilities. The
Z89331 features a Z89C00 RISC processor core that
controls on-board peripheral functions and registers using
the standard processor instruction set.

Character attributes can be controlled through two modes:
the on-screen display Character-Control Mode and the
Closed-Caption Mode. The Character-Control Mode
provides access to the full set of attribute controls, allowing
the modification of attributes on a character-by-character
basis. The insertion of control characters permits direction
of other character attributes. Closed-caption text can be
decoded directly from the composite video signal and
displayed on-screen with the assistance of the processor's
digital signal processing (DSP) capabilities.

The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of
display attributes that include underlining, italics, blinking,
eight foreground/background colors, character position
offset delay, and background transparency.

n Serial Interfacing I2C Port

n Fully Customized Character Set

n Character-Control and Closed-Caption Modes

n Keypad User Control

n TV Tuner Serial Interface

n Direct Video Signals

n Low-EMI Option

Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tunning adjustments, may be accessed
through the industry-standard I2C port.

User control can be monitored through the keypad scanning
port, or the 16-bit remote control capture register. Receiver
functions such as color and volume can be directly
controlled by eight 8-bit pulse width modulated ports.

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).

Power connections follow conventional descriptions below:

Connection Circuit Device

Power V

Ground GND V

CC

V

DD
SS

CP95TEL[phone]

1

PRELIMINARY

GENERAL DESCRIPTION (Continued)

Z89331

CP95TEL1400

Port 17
Port 00
Port 05
Port 04

Capture
IRIN

ADC

ADC0
ADC1
ADC2
ADC3
ADC4
ADC5

Port 0

Port 00
Port 01
Port 02

Port 03
Port 04
Port 05
Port 06
Port 07

Port 08
Port 09

Port 0A
Port 0B
Port 0C
Port 0D
Port 0E
Port 0F

PWM

PWM1
PWM2
PWM3
PWM4

PWM5
PWM6

PWM7
PWM8
PWM9
PWM10

Port1

Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16

Port 17
Port 18
Port 19

Note: Dotted pin functions
not available on 42-pin device.

I2C

RAM

640 x 16

Address

Data

Control
XTAL1

XTAL2
LPF
HSYNC
VSYNC
/Reset

CPU

Z89C00

Core

Register Addr/Data

ROM Addr

ROM Data

Functional Block Diagram

SCL
SCD

OSD

V1
V2
V3

BLANK

HALFBLNK

ROM

12K x 16
16K x 16
24K x 16

Port 01/11
Port 02/12

Port0F

2

PRELIMINARY

Z89331

CP95TEL1400

PWM10

PWM9
PWM5

PWM4

PWM3

PWM2
PWM1

Port 03

Port 04/ADC4
Port 05/ADC3

Port 00/ADC2
Port 17/ADC1

GND

Port 10/R<0>

Port 06/Counter

Port 18/G<0>
Port 13/G<1>
Port 14/B<0>

Port 15/B<1>

Port 16/SCLK

Port 0F/HalfBlnk

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

Z89331

42-Pin
Shrink

DIP

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

Port12/I2MSD
Port 11/12MSC
Port 02/I2SSD
Port 01/I2SSC
Port 09

Port 08/R<1>
IRIN
Port 07/CSync

VCC
/Reset
XTAL2
XTAL1
ANGND

LPF
CVI/ADC0
VSync

HSync
VBlank

V1
V2

V3

42-Pin Shrink DIP Pin Configuration

3