YMF724F (DS-1) is a high performance audio controller for the PCI Bus. DS-1 consists of two separated
functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block
allows Software Driver to handle maximum of 73 concurrent audio streams with the Bus Master DMA engine.
The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without
utilizing the CPU or causing system latency. By using the Software Driver from YAMAHA, PCI Audio
provides 64-voice XG wavetable synthesizer with Reverb and variation. It also supports DirectSound hardware
accelerator, Downloadable Sound (DLS) and DirectMusic accelerator.
Legacy Audio block supports OPL3, Sound Blaster Pro, MPU401 UART mode and Joystick function in order
to provide hardware compatibility for numerous PC games on real DOS without any software driver. To
achieve legacy DMAC compatibility on the PCI, DS-1 supports both PC/PCI and Distributed DMA protocols.
DS-1 also supports Serialized IRQ for legacy IRQ compatibility.
DS-1 supports the connection to YAMAHA YMF730 (AC-2) which provides high quality DAC, ADC and
analog mixing. In addition, it supports consumer IEC958, Audio Digital Interface (SPDIF) output, for highquality, external audio amplification.
FEATURES
• PCI 2.1 Compliant
• PC’97/PC’98 specification Compliant
• PCI Bus Power Management rev. 1.0 Compliant
(Support D0, D2 and D3 state)
• PCI Bus Master for PCI Audio
True Full Duplex Playback and Capture with
different Sampling Rate
Maximum 64-voice XG capital Wavetable
Synthesizer including GM compatibility
DirectSound Hardware Acceleration
DirectMusic Hardware Acceleration
Downloadable Sound (DLS) level-1
GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI),
and indicates GM system level 1 Compliant.
XG logo is a trademark of YAMAHA Corporation.
SONDIUS-XG logo is a trademark that Stanford University in the United States and
YAMAHA Corporation hold jointly.
Sensaura logo is a trad emark of Central Research Laboratories Limited.
1. GM system level 1
GM system level 1 is a world standard format about MIDI synthesizer which provides voice arrangements
and MIDI functions.
2. XG
XG is a format about MIDI synthesizer that is proposed by YAMAHA, and keeps the upper compatibility of
GM system level 1. The good points are the voice arrangements kept extensively, a large number of the
voices, modification of the voices, 3 kinds of effects, and so on.
3. SONDIUS-XG
Products bearing the SONDIUS-XG logo are licensed under patents of Stanford University and YAMAHA
Corporation as listed on <http://www.sondius-xg.com>. The SONDIUS-XG produces acoustic sound
outputs by running a virtual simulation of the actual acoustic instrument operation. Therefo re, it provides
much more real-world acoustic sound outputs fundamentally different fr om the Wavetable sound generator
that simply processes the recorded acoustic sound sources only. The SONDIUS-XG adds the technology
of virtual acoustic sound to the XG format.
4. Sensaura
Sensaura is a technology which provides 3D positional audio and moving effect by HRTF (Head Related
Transfer Function) with 2 speakers or headphone. This feature makes it possible to enjoy invariable and
unchangeable sound feelings in all-positional area covering as wide as 360 degrees.
PCICLKIPPCI Clock
RST#IPReset
AD[31:0]IOPtrAddress / Data
C/BE[3:0]#IOPtrCommand / Byte Enable
PARIOPtrParity
FRAME#IOPstrFrame
IRDY#IOPstrInitiator Ready
TRDY#IOPstrTarget Ready
STOP#IOPstrStop
IDSELIPID Select
DEVSEL#IOPstrDevice Select
REQA#OPPCI Request
GNTA#IPPCI Grant
PCREQ#OPtrPC/PCI Request
PCGNT#IPtrPC/PCI Grant
PERR#IOPstrParity Error
SERR#OPodSystem Error
INTA#OPodInterrupt signal output for PCI bus
SERIRQ#IOPtrSerialized IRQ.
2. YMF730(AC-2) Interface (6-pin)
nameI/OTypeSizefunction
CRST#OT6mAReset signal for AC-2
CMCLKOC-Master Clock of AC link (24.576MHz) and
AC3F2
CBCLKIT-AC-link: Bit Clock for AC-2 audio data
CSDOOT6mAAC-link: AC-2 Serial audio output data
CSDIIT-AC-link: AC-2 Serial audio input data
CSYNCOT6mAAC-link: Synchronized signal
September 21, 1998
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YMF724F
3. YMF727(AC3F2) Interface (9-pin)
nameI/Otypesizefunction
XRST#OC2mAReset for local device
ACS#OT3mAChip select for AC3F2
ASCLKOT6mAClock for Serial control data transfer of AC3F2
ACDOOT3mASerial control data output of AC3F2
ACDIITup-Serial control data input of AC3F2
ALRCKOT3mAL/R clock for Serial audio data of AC3F2
ABCLKOT6mABit clock for Serial audio data of AC3F2
ASDOOT3mASerial audio data output to AC3F2
ASDIITup-Mixed Serial audio data input of AC3F2
4. SPDIF Interface (1-pin)
nameI/OtypeSizefunction
DITOT3mADigital audio interface output (48kHz)
5. Legacy Device Interface (16-pin)
nameI/OtypeSizefunction
IRQ5OTtr12mAInterrupt5 of Legacy Audio
It is directly connected to the interrupt signal of
System I/O chip.
IRQ7OTtr12mAInterrupt7 of Legacy Audio
IRQ9OTtr12mAInterrupt9 of Legacy Audio
IRQ10OTtr12mAInterrupt10 of Legacy Audio
IRQ11OTtr12mAInterrupt11 of Legacy Audio.
GP[3:0]IA-Game Port
GP[7:4]ITup-Game Port
GREFIA-Reference for Game Port
RXDITup-MIDI Data Receive
TXDOT3mAMIDI Data Transfer
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September 21, 1998
YMF724F
6. Miscellaneous (15-pin)
nameI/OtypeSizefunction
ROMCSOT3 mAChip select for external EEPROM
ROMSK / VOLUP#IOTup3mA
ROMDO / VOLDW#IOTup3mA
ROMDI / TEST2 #ITup-
XI24IC-24.576 MHz Crystal
XO24OC2mA24.576 MHz Crystal
TEST[7:4,1:0]#ITup-Test pins (Do not connect externally)
TEST3#IOTup3mATest pin (Connect to ground)
LOOPF[1:0]---Capacitor of PLL
Note) Hardware volume and EEPROM interface can not be used at the same time. When both hardware
volume and EEPROM are not used, do not connect these pins externally.
Serial clock for external EEPROM
or Hardware Volume (Up)
Serial data output for external EEPROM
or Hardware Volume (Down)
Serial data input for external EEPROM or Test pin
(Do not connect externally when EEPROM is not.)
7. Power Supply (39-pin)
nameI/OtypeSizefunction
PVDD[5:0]---Power supply for PCI Bus Interface (+5.0)
PVSS[14:0]---Ground for PCI Bus Interface
LVDD---Power supply for PLL Filter (+3.3)
LVSS---Ground for PLL Filter
VDD3[3:0]---Power supply (+3.3V)
VDD5[3:0]---Power supply (+5.0V)
VSS[7:0]---Ground
TYPE
T : TTL A : AnalogPtr : Tri-State PCI
Ttr : Tri-State TTL C : CMOSPstr : Sustained Tri-Sate PCI
Tup : Pull up (Max. 300kohm) TTL P : PCIPod : Open Drain PCI
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September 21, 1998
YMF724F
BLOCK DIAGRAM
PC-PCI /
D-DMA /
S-IRQ
PCI Bus
Interface
Legacy Audio
SB Pro
OPL3
MPU401
Joystick
BUS Master
DMA Controller
Memory
Rate Converter
/ Mixer
PCI Audio
XG Synthesizer
Direct Sound Acc.
Wave In/Out
AC-2
Interface
SPDIF
(output)
AC3F2
Interface
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September 21, 1998
YMF724F
SYSTEM DIAGRAM
DirectX
Application
AC-3
Application
DLS
Appllication
Win16API
WaveOut
Device
MidiOut
Device
Device
WaveIn
VxD
DirectSound
Win32API
HAL
DirectSound
DRV for PCI Audio
Engine
XG/DLS
Soft
Effect
VxD for PCI Audio
PCI Audio
DS-1 Slot Manager (Up to 64-sound)
MMSystem
VM
DOS
MidiIn
Device
Device
MidiOut
DRV for Legacy
I/O Traps
I/O Traps
Msjstck.drv
YMF724F(DS-1)
VxD for Legacy
MPU401
OPL3SB Pro
Vjoyd.vxd
Joystick
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YMF724F
FUNCTION OVERVIEW
1. PCI INTERFACE
DS-1 supports the PCI bus interface and complies to PCI revision 2.1.
1111Memory Write and Invalidate (not support)
DS-1 does not assert DEVSEL# when accessed with commands that are indicated as (not supported) or
reserved.
1-1-2. Master Device Mode
C/BE[3:0]#Command
0110Memory Read
0111Memory Write
When DS-1 becomes a Master Device, it generates only memory write and read cycle commands.
September 21, 1998
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YMF724F
1-2. PCI Configuration Register
In addition to the Configuration Register defined by PCI Revision 2.1, DS-1 provides proprietary PCI
Configuration Registers in order to control legacy audio functio n, such as OPL3, So und Blaster Pro, MPU401
and Joystick. These additional registers are configured by BIOS or the configuration software from
YAMAHA Corporation.
The following shows the overview of the PCI Configuration Register.
Offsetb[31..24]b[23..16]b[15..8]b[7..0]
00-03hDevice IDVendor ID
04-07hStatusCommand
08-0BhBase Class CodeSub Class CodeProgramming IFRevision ID
0C-0FhReservedHeader TypeLatency TimerReserved
10-13hPCI Audio Memory Base Addres s
14-2BhReserved
2C-2FhSubsystem IDSubsystem Vendor ID
30-33hReserved
34-37hReservedCap Pointer
38-3BhReserved
3C-3FhMaximum LatencyMinimum GrantInterrupt Pi nInterrupt Line
40-43hExtended Legacy Audio ControlLegacy Audio Control
44-47hSubsystem ID WriteSubsystem Vendor ID Write
48-4BhDS-1 Power ControlDS-1 Control
4C-4FhReservedD-DMA Sl ave Configuration
50-53hPower Management CapabilitiesNext Item PointerCapability ID
54-57hReservedPower Management Control / Status
58-5BhReservedACPI Mode
5C-FFhReserved
Reserved registers are hardwired to “0”. All data written to these registers are discarded. The values
read from these registers are all zero.
DS-1 can be accessed by using any bus width, 8-bit, 16-bit or 32-bit.
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September 21, 1998
YMF724F
00 - 01h: Vendor ID
Read Only
Default: 1073h
Access Bus Width: 8, 16, 32-bit
b15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0
Vendor ID
b[15:0]........Vendor ID
This register contains the YAMAHA Vendor ID registered in Revision 2.1. This register is hardwired to
1073h.
02 - 03h: Device ID
Read Only
Default: 000Dh
Access Bus Width: 8, 16, 32-bit
b15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0
Device ID
b[15:0]........Device ID
This register contains the Device ID of DS-1. This register is hardwired to 000Dh.
This bit enables DS-1 to response to Memory Space Access.
“0”: DS-1 ignores Memory Space Access.(default)
“1”: DS-1 responds to Memory Space Access.
b2................BME: Bus Master Enable
This bit enables DS-1 to act as a master device on the PCI bus.
“0”: Do not set DS-1 to be the master device.(default)
“1”: Set DS-1 to be the master device.
b6................PER: Parity Error Response
This bit enables DS-1 responses to Parity Error.
“0”: DS-1 ignores all parity errors.
“1”: DS-1 performs error operation when DS-1 detects a parity error.
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September 21, 1998
YMF724F
b8................SER: SERR# Enable
This bit enables DS-1 to drive SERR#.
“0”: Do not drive SERR#.(default)
“1”: Drives SERR# when DS-1 detects an Address Parity Error on normal target cycle or a Data Parity
This bit indicates that DS-1 supports the capability register. This bit is read only. When 58-59h :
ACPI Mode register, ACPI bit is “0”, the bit is “1”. When ACPI bit is “1”, the bit is “0”.
b8................DPD: Data Parity Error Detected
This bit indicates that DS-1 detects a Data Parity Error during a PCI master cycle.
b[10:9] ........DEVT: DEVSEL Timing
This bit indicates that the decoding speed of DS-1 is Medium.
b11..............STA: Signaled Target Abort
This bit indicates that DS-1 terminates a transaction with Target Abort during a target cycle.
b12..............RTA: Received Target Abort
This bit indicates that a transaction is terminated with Target Abort while DS-1 is in the master memory
cycle.
b13..............RMA: Received Master Abort
This bit indicates that a transaction is terminated with Master Abort while DS-1 is in the master memory
cycle.
b14..............SSE: Signaled System Error
This bit indicates that DS-1 asserts SERR#.
b15..............DPE: Detected Parity Error
This bit indicates that DS-1 detects Address Parity Error or Data Parity Error during a transaction.
September 21, 1998
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YMF724F
08h: Revision ID
Read Only
Default: 03h
Access Bus Width: 8, 16, 32-bit
b7b6b5b4b3b2b1b0
Revision ID
b[7:0]..........Revision ID
This register conta i ns the revision number of DS-1. This register is har dwired to 03h.
09h: Programming Interface
Read Only
Default: 00h
Access Bus Width: 8, 16, 32-bit
b7b6b5b4b3b2b1b0
Programming Interf ace
b[7:0]..........Programming Interface
This register indicates the programming interface of DS-1. This register is hardwired to 00h.
0Ah: Sub-class Code
Read Only
Default: 01h
Access Bus Width: 8, 16, 32-bit
b7b6b5b4b3b2b1b0
Sub-class Code
b[7:0]..........Sub-class Code
This register indicates the sub-class of DS-1. This register is hardwired to 01h. DS-1 b elongs to the
Audio Sub-class.
0Bh: Base Class Code
Read Only
Default: 04h
Access Bus Width: 8, 16, 32-bit
b7b6b5b4b3b2b1b0
Base Class Code
b[7:0]..........Base Class Code
This register indicates the base class of DS-1. This register is hardwired to 04h. DS-1 belongs to the
Multimedia Base Class.
This register indicates the physical Memory Base address of the PCI Audio registers in DS-1. The base
address can be located anywhere in the 32-bit address space. Data in the DS-1 register is not
prefetchable.
DS-1 needs 32768-bytes of memory address space.
---------------
MBA (higher)
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YMF724F
2C-2Dh: Subsystem Vendor ID
Read Only
Default: 1073h
Access Bus Width: 8, 16, 32-bit
b15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0
Subsystem Vendor ID
b[15:0]........Subsystem Vendor ID
This register contains the Subsystem Vendor ID . In gene ral, this ID is used to distinguish adapters or
systems made by different IHVs using the same chip by the same vendor. This register is read only.
To write the IHV’s Vendor ID, use 44-45h (Subsystem Vendor ID Write Register). IHVs must change
this ID to their Vendor ID in the BIOS POST routine.
In case of the system such as Sound Card which BIOS can not control, this ID can be changed by
connecting EEPROM externally. Then, Subsystem Vendor ID Write Register is invalid.
In case EEPROM is not externally, the default value is the YAMAHA's Vendor ID, 1073h.
2E-2Fh: Subsystem ID
Read Only
Default: 000Dh
Access Bus Width: 8, 16, 32-bit
b15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0
Subsystem ID
b[15:0]........Subsystem ID
This register contains the Sub system ID. In general, this ID is used to distinguish adapters o r systems
made by different IHVs using the same chip by the same vendor. This register is read only. To write
the IHV's Device ID, use 46-47h (Subsystem ID Write Register). IHVs must change this ID to their ID
in the BIOS POST routine.
In case of the system such as Sound Card which BIOS can not control, this ID can be changed by
connecting EEPROM externally. Then, Subsystem ID Write Register is invalid.
In case EEPROM is not externally, the default value is the YAMAHA's Device ID, 000Dh.
34h: Capability Register Pointer
Read Only
Default: 50h
Access Bus Width: 8, 16, 32-bit
b7b6b5b4b3b2b1b0
Capability Register Pointer
b[7:0]..........Capability Register Pointer
This register indicates the offset address of the Capabilities register in the PCI Configuration register
when 58-59h: ACPI Mode register, ACPI bit is “0”. DS-1 provides PCI Bus Power Management
registers as the capabilities. The Power Management registers are mapped to 50h - 57h in the PCI
Configuration register, and this register indicates “50h”.
When ACPI bit is “1”, this register indicates “00h”.
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September 21, 1998
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