YAMAHA YMF721 Datasheet

YMF721

OPL4-ML2

FM + Wavetable Synthesizer LSI

OVERVIEW

YMF721 (OPL4-ML2) is a high quality and low cost Wavetable synthesizer LSI. YMF721 (OPL4-ML2) integrates an OPL3 (FM synthesizer), General MIDI processor and 1 Mbyte Wavetable sample ROM into one chip, and complies with General MIDI (GM) system level 1. Thus, it is best suited to multimedia applications, sound cards, MIDI synthesis modules and other sound applications. Since this LSI outputs stereophonic 16 bit digital signal (fs = 44.1 kHz), it can b e connected directly with YMF701B, 711 or 715 (OPL3-SA, SA2 or SA3) or with YAC516(DAC16-L). Operating voltage, 3.3 V, allows this LSI to be controlled with notebook personal computers. Power management functions (power d own and suspend/resume functions) of OPL4-ML2 contribute to low power consumption of personal computers into which this product is built-in.

FEATURES

• The Wavetable synthesizer of this LSI is able to generate up to 24 types of sounds simultaneously.

• Has an interface that makes this LSI compatible with MPU-401 UART mode.

• Has an OPL3 (FM synthesizer) for AdLib/Sound Blaster applications.

• Has a 1 Mbyte built-in Wavetable sample ROM.

• Complies with GM system Level 1. (Thus, it is compatible with DOS applications that support MPU-401.)

• MIDI signal can be transmitted either through seria l input or parallel input.

• FM synthesizer and Wavetable synthesizer of this LSI can generate their sound at the same time.

• FM synthesizer is register-compatible with OPL3.

• All registers are readable.

• Power management functions included power down and suspend/resume can be supported.

• Frequency of master clock signal is 33.8688 MHz.

• Pin compatible with YMF704C-S (100 pin SQPF)

• Voltage of power supply can be 5.0 V or 3.3 V.

• Silicone gate CMOS process

• 100-pin SQFP (YMF721-S).

GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI), and indicates GM system level 1 Compliant.

YAMAHA

CORPORATION

CATALOG No.:LSI-4MF721A20

YMF721 CATALOG

July 10, 1997

Jury 10, 1997

YMF721

/ /

PIN CONFIGURATION

YMF721-S

VDD

N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS

XOXI5V/3V

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26272829303132333435363738394041424344454647484950

ADB7

ADB6

VSS

ADB5

ADB4

ADB3

ADB2

ADB1

ADB0

AIRQ

RST

/IOW

/IOR

VSSA2A1A0/OPLCS

9998979695949392919089888786858483828180797877

VDD

/MPUCS

ARDY

ABDIR

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS VDD N.C. VSS

TEST2

RESETSEL TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0

DO3

DO2

DO1

LRO

WCO

DO0

BCO

CLKO

RXD

/PDOUT

FSP

VDD

T0T1T2T3T4T5T6

VSS

/TEST

/TEST3

/TESTB

/TESTA

100 pin SQFP Top View

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YMF721

)

PIN DESCRIPTION

ISA bus interface : 19 pins Pin name ADB7-0 8 I/O TTL 2mA Data bus A2-0 3 I TTL - Address bus /MPUCS 1 I TTL - MPU401 chip select /OPLCS 1 I TTL - FM/Wavetable/Command/Control chip select /IOW 1 I TTL - Write enable /IOR 1 I TTL - Read enable RST 1 I TTL - Initial clear input AIR ABDIR 1 O TTL 2mA Selection of data transfer direction

ARDY 1 OD TTL 12mA I/O channel ready/busy selection ("L" : Bus

MIDI interface : 2 pins Pin name RXD 1 I T TL - MIDI serial data input FSP 1 I TTL - Selection of MIDI serial/parallel transmission

ins I/O Type Size Function

1 O TTL 2mA Interrupt signal ("H" : Interrupt

(“L” : YMF721®Host)

ins I/O Type Size Function

(“H” : Parallel, “L” : Serial)

Serial audio interface : 8 pins Pin name CLKO 1 O CMOS 8mA Clock output (384fs = 16.9344MHz) BCO 1 O CMOS 2mA Bit clock output (48fs = 2.1168MHz) LRO 1 O CMOS 2mA L/R clock output (fs = 44.1kHz) WCO 1 O CMOS 2mA Word clock output (2fs = 88.2kHz) DO3 1 O CMOS 2mA Effect send output DO2 1 O CMOS 2mA MIX (FM + Wavetable) output DO1 1 O CMOS 2mA Wavetable output DO0 1 O CMOS 2mA FM output

ins I/O Type Size Function

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YMF721

)

Others : 39 pins Pin name 5V/3V 1 I CMOS - Selection of power suppl /RESETSEL 1 I+ TTL - RST signal polarity control pin

/PDOUT 1 O CMOS 2mA Power down control output XI 1 I CMOS 2mA Crystal oscillator connection or master clock input

XO 1 O CMOS 2mA Crystal oscillator connection pin N.C. 34 - - - To be open at normal use.

LSI test pins : 21 pins Pin name /TESTA 1 I+ TTL - To be open at normal use. /TESTB 1 I+ TTL - To be open at normal use. /TEST 1 I+ TTL - To be open at normal use. /TEST2 1 I+ TTL - To be open at normal use. /TEST3 1 I+ TTL - To be open at normal use. T7-0 8 O CMOS 2mA To be open at normal use. TD7-0 8 I/O CMOS 2mA To be open at normal use.

ins I/O Type Size Function

(When this pin is at "L", RST is active at "L".)

(33.8688 MHz)

ins I/O Type Size Function

Power supply, ground : 11 pins Pin name VDD 4 - - - Power supply (put on +5.0 V or +3.3V VSS 7 - - - Ground

Total : 100 pins

Note : I+ : Input pin with built-in pull-up resistor, OD : Open drain output pin

ins I/O Type Size Function

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YMF721

[

]

BLOCK DIAGRAM

/MPUCS

/RESETSEL

ADB[7-0

/OPLCS

/IOW

RXD

2-0

/IOR

RST

FSP

ABDIR

AIRQ

ARDY

5V/3V

ISA BUS

Interface

Decode

Logic

UART

Timing

Generator

Micro Processor

MIDI Interpreter

Command Interpreter

Control

(MPU/Command

/Control)

SRAM

32kbit

Synthesizer

Interface

(arbitration etc.)

ROM

256kbit

TD[7-0]

TEST Logic

Synthesizer

/TEST

/TEST2

/TEST3

/TESTA

T[7-0

/TESTB

VSS

VDD

Wave ROM

1M byte

Wavetable

DO3 DO1

Synthesizer

DO2

OPL3

FM Synthesizer

Timing Control

MIX(FM+Wave)

DO0

PDOUT CLKO BCO LRO WCO

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YMF721

FUNCTIONS

1. 1. Example of system configuration 1-1. System with MPU401 UART

This section describes two examples of systems that have an MPU401 UART in them. In these examples, YMF701B, 711 or 715 (OPL3-SA, SA2 or SA3) has a built-in MPU401 UART.

(1) ISA BUS Connect System

YMF7xx

(OPL3-SAx)

CLKO

SYNCS EXTEN

TXD

BCLK_ML LRCK_ML SIN_ML

OPLCS

MPUCS FSP RXD

BCO LRO DO2

ARDY

RST

A2-0

/IOW

/IOR

ADB7-0

YMF721

ABDIR

(OPL4-ML2)

LS245

IOCHRDY RESETDRV SA2-0

IOW IOR

SD7-0

Note : YMF721 (OPL4-ML2) has MPU401 UART in it. Thus, for the above case, TXD of YMF7xx (OPL3-SAx) is connected with RXD of YMF721 (OPL4-ML2) and MPU401 port (/MPUCS) of YMF721 (OPL4-ML2) is disabled so that YMF7xx(OPL3-SAx) sends MIDI data directly to YMF721 (OPL4-ML2). For the above case, FM synthesizer of YMF7xx (OPL3-SAx) is disabled and the one in YMF721 (OPL4ML2) is made active. (This c ontrol is made through /EXT EN pin of YMF7xx.) For the above system, the data bus that connects with YMF721(OPL4-ML2) gains access to FM-synthesizer/Command/Control port of YMF721(OPL4-ML2). (Chip select signal is outputted from /SYNCS pin of YMF7xx.) For the source of master clock to be inputted to XI pin of YMF721 (OPL4-ML2), it is recommended to use CLKO pin of YMF7xx (OPL3-SAx). For other methods, a crystal oscillator can be used by attaching it to XI and XO pins of YMF721 (OPL4-ML), or a clock of 33.8688 MHz supplied from the system can be used. When serial data outputs of YMF721 (OPL4-ML2), BCO, LRO and DO2 pins, are connected with external serial data interface (BCLK_ML, LRCK_ML, SIN_ML) of YMF7xx (OPL3-SAx), the serial data is converted to analog signal in YMF7xx (OPL3-SAx) and outputted as analog signal.

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YMF721

(2) No ISA BUS Connect System

OPLCS

MPUCS FSP RXD

PDOUT CLKO BCO LRO DO2

YMF721

YMF7xx

(OPL3-SAx)

Note :

TXD

LchAUX2L

RchAUX2R

Gain (+12dB)

PDIN MCLK BCLK LRCK SDATA

YAC516

ARDY

ADB7-0

ABDIR

(OPL4-ML2)

RST

A2-0

/IOW

/IOR

RESET

YMF721 (OPL4-ML2) has MPU401 UART in it. Thus, for the above case, TXD of YMF7xx (OPL3-SAx) is connected with RXD of YMF721 (OPL4-ML2) and MPU401 port (/MPUCS) of YMF721 (OPL4-ML2) is disabled so that YMF7xx(OPL3-SAx) sends MIDI data directly to YMF721 (OPL4-ML2). The above system does not connect YMF721 (OPL4-ML2) and ISA bus, which is an example of Wavetable upgrade solution represented b y the Wavetable daughter card . Input pins of the ISA bus interface should be pulled up externally. At this time, FM synthesizer/Command/Control ports are disabled, but the power down function is enabled by receiving System Exclusive Message on the MIDI data, except that Suspend/Resume function is disabled. As a source of master clock for YMF721 (OPL4-ML2), use a crystal oscillator by connecting it to XI and XO pins, or use the clock of 33.8688 MHz from the system. Connect BCO, LRO, DO2, /PDOUT and CLKO directly to YAC516 (DAC16-L) as shown to convert serial data output to analog signal. Then, it is recommended to input the converted analog signal to AUX2L and AUX2R of YMF7xx (OPL3-SAx) after amplifying the volume of source of YMF721 through the gain of +12 dB as shown for the purpose of equalizing the volumes of multiple sources.

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YMF721

1-2. System without MPU401 UART

This section describes an example of a system that does not have MPU401 UART in it. In this example, MPU401 UART of YMF721 (OPL4-ML2) is used. FM synthesizer of this LSI is compatible with applications that support AdLib/Sound Blaster, and Wavetable synthesizer is compatible with applications that support MPU401.

SA15-0

AEN

OPLCS

Address

Decoder

PDIN

LchLch out

RchRch out

Gain up

MCLK BCLK LRCK SDATA

YAC516

MPUCS FSP RXD

PDOUT CLKO BCO LRO DO2

ARDY

RESET

A2-0

/IOW

/IOR

ADB7-0

YMF721

ABDIR

(OPL4-ML2)

LS245

IOCHRDY RESETDRV SA2-0

IOW IOR

SD7-0

Note : For the above case, MPU401 port of YMF721 (OPL4-ML2) must be made active because the system does not have MPU401 UART in it. Addresses of standard ports through which reading or writing of registers of YMF721 (OPL4-ML2) is made are as follows.

1) /OPLCS : 388 - 38Fh (8byte)

2) /MPUCS : 330 - 331h (2byte) As a source of master clock for YMF721 (OPL4-ML2), use a crystal oscillator by connecting it to XI and XO pins, or use the clock of 33.8688 MHz from the system. Connect BCO, LRO, DO2, /PDOUT and CLKO directly to YAC516 (DAC16-L) as shown to convert serial data output to analog signal. Then, it is recommended to amplify the volume of source of YMF721 through the suitable gain as shown for the purpose of equalizing the volumes of multiple sources.

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YMF721

2. ISA bus interface

8 bit parallel I/O of YMF721 (OPL4-ML2) can be connected with ISA bus. The ISA bus interface allows transfer of commands between the each block of YMF721 (OPL4-ML2) and host.

Data Bus & Address Bus

ADB7-0 : ISA data bus A2-0 : ISA address bus /MPUCS : MPU401 chip select /OPLCS : FM/Wavetable/Command/Control chip select /IOW : ISA write enable /IOR : ISA read enable ABDIR : Data bus direction switching (“L” : YMF721 ® ISA) ARDY : I/O channel ready (“L” : busy)

Control of the data bus is made with /MPUCS, /OPLCS, /IOW and /IOR signals. The mode of control of the data bus varies as follows according to the combination of states of the signals. The direction of data transfer on the data bus is determined by ABDIR. In normal operatio n, the internal data bus of YMF721 (OPL4-ML2) connects the built-in processor and FM/Wavetable synthesizer blocks. Every time the ISA bus accesses the register for FM/Wavetable, an internal arbitration circuit causes the internal bus to connect ISA bus and FM/Wavetable synthesizer blocks. YMF721 (OPL4-ML2) uses I/O channel ready (ARDY pin) as the internal arbitration circuit. ARDY becomes "L" (busy) every time data bus accesses the register for FM/Wavetable.

/MPUCS

/OPLCS /IOW /IOR A2 A1 A0 MODE

LHHL LHLH LHHL LHLH HLHLLLLFM-synth. Status read H L L H L H/L L FM-synth. Address write HLLHL HLHLL H L H L H L L Wavetable-synth. Status read H L L H H L L Wavetable-synth. Address write H L L H H L H Wavetable-synth. Data write H L H L H L H Wavetable-synth. Data read HLHLHHLCommand response read HLLHHHLCommand write HLLHHHHControl write H L H L H H H Status read HLHH HH

´´´´´

´ ´ ´ ´

´´´

L L MPU401 Acknowledge (FEh) L L MPU401 MIDI Data write L H MPU401 Status read L H MPU401 Command write

´ ´

H FM-synth. Data write H FM-synth. Data read

No-active or UART mode No-active or UART mode

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YMF721

Notes: ´ : Don’t care When address has been written into FM block, the time required to wait until writing of address or data into Wavetable block is started is 0 (zero) nsec. When add ress has been written into Wavetable block, the time required to wait until writing of address or d ata into FM block is started is also 0 (zero) nsec. When FM block has been accessed, it is necessary to wait 860 nsec or more before the FM block can be accessed again.

Interrupt

AIRQ : Interrupt signal ("H" : Interrupt)

YMF721 (OPL4-ML2) is able to provide one interrupt signal. There are two types of sources of this interrupt signal as follows.

1) Two timer flags that are used for tempo counter of FM synthesizer

2) The flag that occurs when internal processor writes data into the Command response register The flags described in 2) is disabled as a default.

3. Serial audio interface

YMF721 (OPL4-ML2) can be connected directly with an external DAC such as YAC516 through BCO, LRO, WCO and DO3-0 pins.

BCO... Outputs bit clock. The frequency of this clock is 48 fs. (fs is the sampling

frequency that is equal to the frequency of clock outputted from LRO.) Typical duty factor of this signal is 50 %.

LRO... Specifies a channel for serial audio data. When LRO is "H", data is outputted

from left channel, or when "L", from right channel. Frequency of this clock is

44.1 kHz. Typical duty factor of this signal is 50 %. WCO... Frequency of this clock is 88.2 kHz. Typical duty factor of this signal is 50 %. DO3-0... These pins output serial audio data as follows.

DO3... Outputs data of Wavetable whose effect send level has been adjusted. DO2... Outputs data that is the mixture of those of FM and Wavetable. DO1... Outputs Wavetable data. DO0... Outputs FM data.

Format of the serial audio interface is as follows.

BCO

DO3-0

LRO

WCO

010123456789101115 14 13 12 0123456789101115 14 13 12

Left Channel Right Channel

Format of YMF721 (OPL4-ML2) serial audio interface

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YMF721

4. MIDI Interface

MIDI serial data can be inputted from RXD pin. It is necessary to input MIDI data complied with MIDI

1.0 detailed specification to RXD pin. The serial data is the rate of 31.25kbit/sec (+/-1%) and the unit of 10 bits. T he first bit is a start bit, the next 8 bits are data (LSB to MSB), and the 10th bit is a stop bit.

5. Power management functions

YMF721 (OPL4-ML2) has two types of power management functions as follows.

(1) Global power down mode (2) Suspend/Resume mode

5-1. Global power down mode

Generation of clock signal is disabled (stopped). Total power consumption of YMF721 (OPL4-ML2) is approximately 20uA (typ.). Writing "FDh" into command register or receiving System Exclusive MIDI Message makes in this mode. YMF721 (OPL4-ML2) outputs "L" from /PDOUT pin in this mode, which can be used as power down control signal for peripheral equipment. Set KON bit (FM synthesizer register) to "0" for all channels before going into this mode. Check that play back of MIDI data is stopped. /RESETSEL pin has a built-in pull up resistor. When this pin is at "L" in this mode, the power consumption is higher by approximately 30uA than the one when this pin is open or at "H".

5-1-1. ISA BUS Connect System

When "FDh" has been written into command register, the internal pr ocesso r goes into the glo bal p ower down mode after performing the following internal processes.

1) Disabling synthesizer's internal clock

2) Setting GBUSY bit of status register to "0". YMF721 (OPL4-ML2) requires over 30 msec to complete the above processes before going into the power down mode. Since generation of the clock has been disabled, recovery from the power down mode can not be made by using command. Thus, it is nec essary to use PDY and P DX bits of co ntrol registe r for the re cove ry. To resume normal ope ra tion thr o ugh the re co ver y sequence , waiting time of 5 0 to 100 msec is required before the oscillation of crystal stabilizes when internal oscillation is used, or 3 msec or more before the recovery of cloc k generated in the synthesizer. For the details of power down command, refer to 6-3. After the power down command, FDh, has been written, do not write any command before sending a recovery command to the control register to return to the normal mode.

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YMF721

Comma nd write “FDh” Control write PDY=1, PDX=0

(wait time ~100 msec)

Control write PDY=0, PDX=0

Synthesizer clock enable

Normal Operation

~30msec

Synthesizer clock disabl e

Status read GBUSY=0

all clock (X’tal)disable

Power down sequence when connected with ISA bus

~3msec

5-1-2. No ISA BUS Connect System

When YMF721 (OPL4-ML2) is not connected with ISA bus, power down operation can be controlled by sending Yamaha's original System Exclusive Message as the MIDI data. The System Exclusive Message includes the following three byte ID.

43h, 79h, 04h : Yamaha YMF721(OPL4-ML2) ID

The System Exclusive Message is as follows.

F0h, <Yamaha YMF721(OPL4-ML2) ID>, <Command>, <Data>, F7h

YMF721 (OPL4-ML2) supports the following commands and data.

Command Data Function

0Eh 6Dh Power Down Command 0Fh 6Bh

Internal Micro-processor Reset Command

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YMF721

(1) Power Down in

When YMF721 (OPL4-ML2) has received the System Exclusive Message shown above, it goes into the global power down mode after performing the processes as described in "5-1-1. ISA BUS Connect System".

(2) Power Down out

Since the clock generation has been disabled, YMF721 (OPL4-ML2) is not able to recover from the global power down mode by using the System Exclusive Message. Thus, the LSI needs to receive the "3byte MIDI data" as shown below to recover from the global power down mode. To resume normal oper ation through the recovery sequence , waiting time of 50 to 100 msec is required before the oscillation of crystal stabilizes when internal oscillation is used, o r 3 msec or more before the re covery of clock genera ted in the synthesizer.

System Exclusive : F0h, 43h, 79h, 04h,0Eh, 6Dh, F7h receiving MIDI F8h

(wait time ~100 msec)

~30msec

<Micro-processor Reset>

The internal microprocessor is reset by receiving the above System Exchange Message.

Synthesizer clock disabl e

all clock (X’tal)disable

~3msec

Power down sequence without ISA bus

receiving MIDI E0h

receiving MIDI F8h

Synthesizer clock enable

Normal Operation

5-2. Suspend/Resume mode

The state of internal processor is suspended by writing "E0h" into the co mmand register before turning off the power. When the power has been turned on, it can be resumed by resetting it, writing "E1h" into the command register and then writing data that has been read before suspended. On FM synthesizer block, check setting KON bit to "0" for all channels before reading out all register and turning off the power. Write register that has been read after turning on and resetting at the recovery sequence. For the details of suspend/resume, refer to 6-3.

Note : The system that includes YMF721 not connected with ISA bus can not support the suspend/resume function.

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