YAMAHA YGV627 Datasheet

YGV627

AVDP3E

Advanced Video Display processor 3 Enhanced

OUTLINE

■

YGV627 is a VDP (Video Display Processor) that realizes higher resolution, multi-color and high speed drawing by adopting a synchronous DRAM as the video memory, while maintaining the register compatibility with YGV617B that is used for controlling the high minuteness On Screen Display (OSD).

Since the device is capable of displaying bitmap images with various resolutions ranging from NTSC to SVGA on the monitors with any size of screen including wide screen, it can be used for controlling OSD for various display units. Also, it is capable of representation of varied images in accordance with the application because numerous number of colors can be selected such as the one in the range from 16 to 65536 RGB color display, or natural image display using YCbCr.

In addition, the existing system can be up-graded easily thanks to the basic features from YGV617B such as a high speed drawing function, character drawing function, synchronization with external video signal, digital video input / output function, and hardware cursor display function.

FEATURES

■■■■

YGV627 is capable of selecting two modes by using the setting of

For convenience, the case of using

pin with LOW level (enabled) is referred to as “expansion mode” in this

ENH

document. In the expansion mode, all the functions can be used.

The case of using

pin with HIGH level (disabled) is referred to as “compatibility mode”. In the compatibility

ENH

mode, the software compatibility with YGV617B is maintained, but the functions enhanced for YGV617B cannot be used. These modes should be used in accordance with the purpose of the application of this device.

ENH

pin.

[Display functions]

●

Three screen configuration including bitmap screen, sprite cursor screen and external input video screen (or single color border screen)

●

Monitor synchronization frequency, dot clock frequency, and display screen resolution can be specified optionally.

●

Display dot clock up to 40 MHz (Example of resolution: NTSC, PAL, VGA, SVGA, NTSC wide, and VGA wide)

●

Support with progressive scanning and interlaced scanning

●

Resolution of sprite cursor screen is 32 X 32 dots. (The sprite cursor can also be used as cross-hair line cursor.)

●

Smooth hardware scroll function

●

Upper / lower two division display on the bitmap screen (The two sections can be scrolled independently).

●

256 word X 16 bit CLUT is built-in (The number of display colors of 32768 colors or 65536 colors can be selected.)

●

Display colors: 16 palette color, 256 palette color, 32768 RGB color, 65536 RGB color, YCbCr422 (ITU601)

●

YCbCr (ITU601) -to-8 bit RGB decoder is built-in.

●

α blending function that mixes with external input screen or single color border screen. (64 intensity levels)

●

Dot clock gener ation with built-in PLL circ uit

●

Generates dot clock that synchronizes with HSYNC of external video signal.

●

Generates dot clock that synchronizes with external input clock. (such as sub-carrier clock)

YGV627 CATALOG

CATALOG No.: LSI-4GV627A2

2001.01

YGV627

[Drawing functions]

●

Commands Block transfer by word (CPU to VRAM, VRAM to CPU, VRAM to VRAM)

Font drawing, dot drawing and rectangular drawing.

●

Drawing attribute Sets drawing clip area, drawing offset or drawing page, and designates bit mask, color mask,

logical operation (NOT, AND, OR, EOR etc.), or direction of transfer.

[Operational clock]

●

System clock (clock for drawing system): up to 33 MHz

●

Dot clock (clock for display system): up to 40 MHz

[CPU interface]

●

16 bit or 8 bit asynchronous interface

●

Provided with a video memory space up to 8M bytes and internal register space of 128 bytes.

●

The video memory space and internal register space can be mapped indirectly with 16 byte registers.

●

Built-in data buffer for memory space access and built-in data FIFO for drawing commands

●

CPU interruption based on various conditions of display and drawing

●

DMA transfer of drawing command data can be made when connected with external DMA controller

[Video memory interface]

●

Connected memory: 16M bit SDRAM (512k words X 16 bits X 2 banks) 1 piece

or 64M bit SDRAM (1M words X 16 bits X 4 banks) 1 piece

●

SDRAM clock: up to 66 MHz (System clock multiplied by 2 or 4)

●

Built-in FIFO for display data improves the drawing access efficiency and realizes high speed drawing.

[Monitor interface]

●

Analog RGB output with built-in DAC (8 bits for RGB individually)

●

Digital video input / output (6 bits for RGB individually)

●

Equipped with sub-carrier clock output, dot clock output, sync signal output, YS and attribute output pins.

[Others]

●

Package: 176LQFP (YGV627-V)

●

CMOS, 3.3V single power supply

●

Operating temperature range: −40 to +85

Supplementary information:

For YGV627, Application Manual that details the specifications of the device and the evaluation board (MSY627DB01) are available in addition to this brochure. The evaluation board is equipped with an SDRAM of 8 MB as a video memory. A high performance system can be realized when it is used with Hitachi’s CPU board, Super H Solution Engine.

The device driver provided by Yamaha and attached to the evaluatio n board consists of the main body of the driver and API related layers, allowing the user to build it into the system easily according to the environment.

For the details of these products, inquire of the sales agents or our business offices.

For CPU board, inquire of: Hitachi ULSI Systems Co., Ltd.

Tel:+81-42-351-6600

YGV627

BLOCK DIAGRAM

■■■■

YGV627

CPU

Digital video input

YGV627 is connected to the external memory bus of CPU as an external I/O device. As a video memory, SDRAM of up to 64M bits can be connected to local memory bus of YGV627 to send bitmap image data stored in the video memory into monitor as RGB signal in accordance with display scan timing.

YGV627 stores image data from CPU to the video memory by accessing video memory directly through CPU interface or by accessing the video memory using internal drawing command that transfers the data by block.

YGV627 has a function that synthesizes external images with bitmap image of YGV627 on the screen by synchronizing the scan timing of YGV627 with display timing of external video signals.

CPU

Interface

Sync.

control

PLL

Drawing

command

Display

control

OSD screen

Screen

synthesis

Memory

control

DAC

Analog

RGB

Digital video output

(Also us ed as digit al video input pin)

SDRAM

16Mbit

TFT

Panel

PIN ASSIGNMENT

■

NCA4A3A2A1

CSREG

CSMEM

DACK

LWD

RESET

WR1 A0/

DMAP

WR0

AVDD1

SYSEL

SPLLFILT

SPLLRREF

SPLLVSSR

VSS

AVSS1

VDD

SYCKIN

SYCKOUT

DTCKIN

DTCKOUT

AVDD2

DPLLFILT

DPLLRREF

DPLLVSSR

AVSS2

AVSS3RGBIREF

AVDD3

TEST0

YGV627

DVOUT

ENH

TEST2

TEST1

VR64

A5 A6 A7 A8

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22

VSS VDD INT2

INT

WAIT

READY

DREQ

VSS

D10 D11 D12 D13 D14 D15

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

176

174

175

1 2 3 4 5 6 7 8 9

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89

NC VSS VSIN HSIN VDD AT YS FSC CSYNC VSYNC HSYNC BLANK VSS DV17 DV16 DV15 DV14 DV13 DV12 VDD DV11 DV10 DV9 DV8 VSS DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 DOTCLK VDD VSS VSS VDD VA4 VA3 VA5 VA2 VA6 NC

VDD

VSS

VDD

VD0

VD1

VD15

VD2

VD14

VD3

VD13

VSS

VD4

VD12

VD5

VD11

VDD

VD10

VD6

VD9

VD7

VSS

VD8

DQML

DQMH

CAS

RAS

BA0

BA1

VSS

VDD

SDCLK

VA9

VA11

VA8

VA10

VA0

VSS

VA7

VA1

TOP VIEW

YGV627

PIN FUNCTIONS

■

●●●●

D15

0 ( I/O: PULL UP

−−−−

This is a data bus for connecting with external processor. D15−D8 are not used when the CPU bus with 8 bit type (when low level is inputted to LWD). At this time, keep the D15−D8 open. These pins are provided with pull-up resistors respectively.

●●●●

A22−1 ( I

This is an address bus to be connected with external general purpose microcomputer. In the indirect access mode (high level inputted to In the direct access mode (low level inputted to

CSREG

YGV627 can be used as a YGV617B compatible device when A22 and A21 pins are fixed to low level. Unused pins must be set to low level or high level.

●●●●

CSREG

It is a chip select signal input to register space (I/O). When this chip select signal is active, the read / write pulses inputted are made valid so that the registers in the YGV627 are accessed.

The function of this pin is the same as that of

●●●●

CSMEM

This is a chip select signal input pin for video memor y port. T he read / write pulse inputted while this sig nal is active can be used to directly access the video memory controlled by YGV627.

It is possible not to use necessary to input high level to

●●●●

When chip select input is active, these pins control write access to YGV627.

D15−D8 are controlled by

When the CPU is 8 bit type,

)

space.

)

( I

)

( I

WR1, WR0 ( I

)

DMAP

CSMEM

)

pin), input to A22−A4 pins are ignored when accessing

DMAP

CSIO

because the video memory can also be accessed from registers. In such case, it is

CSMEM

WR1

pin.

, and D7−D0 by

functions as CPU address bit 0.

WR1

pin), input to A22−A8 pins are ignored when accessing

pin of YGV617B.

WR0

CSREG

space.

●●●●

RD ( I

When chip select input is active,

D15−D0 are in Output State in the period while both this signa l and chip select signals are active.

●●●●

READY

This is data ready signal output to CPU. The accessible. high impedance state, and when from

Some CPU must use

)

( O: PULL UP, 3-state output

READY

is a 3-state output. When

signal instead of this signal.

WAIT

A22-A1 CS

A0/WR1, WR0

D15-D0

¯¯¯¯¯¯

READY

signals is active and RD or

controls read access from YGV627.

)

READY

CSREG

Hi-Z Hi-Z

READY

signal is made low when the internal state of YGV627 is or

CSMEM

VALID

signal at write access

(hereafter called CS signals) is not active, it is

WR1, WR0

VALID

is not active, high level is outputted

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