YAMAHA YGV619 Datasheet

YGV619

AVDP6

Advanced Video Display Processor 6

Outline

■

YGV619 is a VDP (Video Display Processor) adopting OSD display control system which is best suited to the data broadcasting. The digital image interface of this device for connection with MPEG decoder has been improved. The use of this device allows screen composition that is suited to mobile information terminals, car navigation system, etc. Scan timing conforming to the display standard of digital TVs can be made.

Two built-in PLL circuits allows to realize superimposition of external image signal on original image signal, and to produce clock best suited to SDRAM that is adopted as external video memory.

Features

■

●

Display planes: External digital image is overlaid with OSD images composed of regions.

Up to four planes, which are individually composed of back drop plane (plane on which external images are inputted) + region, are available.

●

OSD image format:

8bit/dot palette mode, and 16 bit RGB or YCbCr format can be selected. YCbCr conforms to the conversion method of ITU601. Color palette (256 colors in 16777 k colors) can be specified by region.

●

Digital image input format:

· 18bitR6G6B6 (Max. dot clock frequency: 80 MHz)

· 16bitYCbCr422 (Max. dot clock frequency: 80 MHz)

· 8bitITU656 (Dot clock frequency 27 MHz)

●

Digital image output format:

· R6G6B6 + 2 bit AT

· 18bitYCbCr444 + 2 bit AT

· 16bitYCbCr422 + 2 bit AT

· 8bitITU656 + 2 bit AT + 6 bit

●

Max. OSD resolution: 960 dots × 1080 lines

(However, max. resolution of overlaid external image is 1920 ×1080 lines)

●

Applicable digital TV image format:

· 525i

· 525p

· 1125i

●

Video capture function:

· Draws external image input on the frame memory in real time.

· Can convert resolution.

· Provided with progressive scanning conversion

α blending coefficient

YGV619 CATALOG

CATALOG No.: LSI-4GV619A1

2001.01

YGV619

●

Priority of display planes

Regular priority: Plane D > Plane C > Plane B > Plane A > Back drop plane The priority can be changed by region.

●

α blending function (64 intensity level)

Blending weight can be set by dot.

●

Flicker cancel filter is built in.

Enabling / disabling flicker cancel function can be set by region.

●

8 bit DACs are built in for R, G and B individually. (Max. operating frequency: 80 MHz)

●

Two PLLs are built in. (1: Generates SDRAM clock and system clock 2: Generates dot clock)

●

Display monitor control

· Display resolution and scanning frequency can be set optionally. This function is compatible with progressive scanning and interlaced scanning modes. NTSC subcarrier output

●

SDRAM can be added externally as VRAM (SDRAM generation clock frequency: Max. 80 MHz.)

·16 bit bus

512k words × 16 bits × 2 banks × 1 pc. (capacity: 2M bytes) 1M words × 16 bits × 4 banks × 1 pc. (capacity: 8M bytes) 2M words × 16 bits × 2 banks × 1 pc. (capacity: 8M bytes)

·32 bit bus

512k words × 16 bits × 2 banks × 2 pcs. (capacity: 4M bytes) 512k words × 32 bits × 4 banks × 1 pc. (capacity: 8M bytes)

1M words × 16 bits × 4 banks × 2 pcs. (capacity: 16M bytes) 2M words × 16 bits × 2 banks × 2 pcs. (capacity: 16M bytes)

●

CPU interface

Compatible with 16/32 bit CPU. Various built-in tables can be mapped on CPU space. Compatible with little endian and big endian

●

Package: 240SQFP (YGV619-S)

●

Operating temperature range: -45 to +85°C

●

Power supply: 3.3V, single power supply

Supplementary information:

For YGV619, Application Manual that details the specifications of the device and the evaluation board (MSY619DB01) are available in addition to this brochure. The evaluation board is equipped with an SDRAM of 16 MB as a video memory. A high performance system can be realized when it is used with Hitachi’s CPU board, Super H Solution Engine.

The device driver provided by Yamaha and attached to the evaluation board consists of the main body of the driver and API related layers, allowing the user to build it into the system easily according to the environment.

For the details of these products, inquire of the sales agents or our business offices.

For CPU board, inquire of: Hitachi ULSI Systems Co., Ltd.

Tel:+81-42-351-6600

YGV619

Block Diagram

■

D31A23-2

CSRE

CSME

DRE

A1/WR

WR2-

WAI

READ

RESE

SYCKI

SYCKOU

CSYN HSYN

HSI

VSI

CPU

INTE RF AC E

CRT

CONTROLLER

DRAWING

PROCESSOR

UNIT

VIDEO

CAPTURE

CONTROLLER

SDRAM

INTE RF AC E

SDQ31-0 SA12-0 SBA1-0 SCS RAS CAS WE DQM3-0 SDCLK

DCKI

DCKOU

GCKI

DRI[5 :0 ]

DGI[5 :0 ]

DBI[5 :0 ]

PIXEL DATA

CONTROLLER

DAC

AT1-0 GCKOUT DRO[5:0] DGO[5:0] DBO[5:0]

R, G, B

AVDP6 performs parallel processing including operation of writing display data into video memory (SDRAM) connected on the local bus (drawing function) and operation of sequentially reading bit map image stored in the video memory in accordance with monitor scanning (display function).

Drawing function:

This function transfers bit map image data configured on the external memory of CPU to video memory. For the transfer of the data, a method that maps the video memory as external memory managed by CPU and performs the transfer as the transfer between external memories of CPU, or a method that uses internal drawing processor of AVDP6 to configure the display image on the video memory can be used.

Display function:

This function displays the bit map image stored in the video memory in accordance with the display parameters that are stored in the internal registers of AVDP6 and the video memory. Basically, AVDP6 automatically sends out display data and refreshes SDRAM once initial setting for internal registers are completed. When performing dynamic processing such as scroll, the processing that synchronizes with the scanning of AVDP6 can be performed easily by using internal flag polling of AVDP6 or interrupt function.

Pin Assignment

■

VDD

240

A23 A22 A21 A20 A19

VSS

A18

VDD

A17 A16 A15 A14 A13 A12 A11 A10

VSS

A8 A7 A6 A5

VDD

A4 A3 A2

VSS

VDD

VSS

INT

D31

VDD

D30 D29 D28 D27 D26 D25 D24

VSS

D23 D22 D21

VDD

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

616263646566676869707172737475767778798081828384858687888990919293949596979899

AVSS1 AVDD1

WR3 WR2 WR1

WR0

RESET

CSREG

CSMEM

LWD

LEND

SYCKS

DREQ

READY

WAIT

DCKOUT

DCKIN

238

239

VSS

237

TCK80

TCKS

235

236

VSIN

HSIN

233

234

GCKS

GCKIN

231

232

DBI0

230

VDD

229

DBI1

228

DBI2

227

DBI3

226

VSS

225

DBI4

224

DBI5

223

DGI0

DGI1

221

222

DGI2

DGI3

219

220

DGI4

DGI5

217

218

VDD

DRI0

215

216

DRI1

VSS

213

214

DRI2

DRI3

211

212

DRI5

DRI4

209

210

AVDD3

AVSS3

207

208

AVDD4

REXT

AVSS4

204

205

206

203

AVSS4

201

202

100

AVSS4

199

200

101

102

VSS

AVSS4

197

198

103

104

DBO1

DBO0

195

196

105

106

VDD

DBO2

193

194

107

108

DBO4

DBO3

191

192

109

110

YGV619

DGO1

DGO0

187

188

113

114

DGO3

DGO2

185

186

115

116

VSS

184

117

DGO4

DGO5

182

183

118

119

DRO0

181

180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121

120

VSS

190

111

DBO5

189

112

VDD DRO1 DRO2

VSS DRO3 DRO4 DRO5 GCKOUT

AT0

VSS

AT1 FSC BLANK HSYNC CSYNC

VDD SDQ24

VSS SDQ23 SDQ25 SDQ22 SDQ26 SDQ21

VSS SDQ27 SDQ20 SDQ28 SDQ19

VDD SDQ29

VSS SDQ18 SDQ30 SDQ17 SDQ31 SDQ16

VSS DQM3 DQM2 SA4 SA3

VDD SA5 SA2 SA7

VSS SA6 SA1 SA0 SA8 SA10 SA9 SA12

VDD SBA0

VSS SA11 SBA1 SCS RAS

D20

D19

D18

D17

D16

VSS

D15

D14

D13

D12

D11

VDD

D10

VSS

D3D1D4D2D0

VSS

SYCKIN

SYCKOUT

VDD

TEST1

TEST2

SDQ0

TEST0

VSS

SDQ1

SDQ15

SDQ2

SDQ14

SDQ13

VDD

SDQ3

VSS

SDQ4

SDQ12

SDQ5

SDQ11

SDQ10

VSS

SDQ6

SDQ9

SDQ7

SDQ8

VDD

DQM0

VSS

CAS

DQM1

AVSS2

SDCLK

AVDD2

D8D7D5

Top view

YGV619

Pin Functions

■

< CPU INTERFACE >

D31-0

CPU data bus. D31-16 pins are not used for 16 bit CPU (LWD=0). These pins are provided with a pull-up resistor.

Unused pins are to be open.

((((

I/O: Pull Up

))))

A23-8

((((

I: Pull Up

CPU address bus. When accessing

))))

A7-2

((((I))))

CSREG

space, signals inputted to A23-8 pins are ignored without regarding to the bus width of CPU. Internal registers are selected depending on the state of signals inputted to A7-2 for 32 bit CPU or A72 and

WR3

pin for 16 bit CPU. Systems that control AVDP6 only with

CSREG

do not use this address bus. However, A23-8 pins must be open because they are provided with pull-up resistor. All the addresses are valid when accessing

CSREG

CSMEM

((((I))))

space.

Chip select signal input to REG space. Internal registers of AVDP6 are accessed by a using write / read pulse that is

inputted when the chip select signal is active.

When this signal is low, inputs to A23-8 pins are ignored.

CSMEM

((((I))))

is made active when directly mapping the video memory connected to local bus of AVDP6 on the memory space of CPU. The video memory managed by AVDP6 is directly accessed using write / read pulse t hat is inputted with this chip select signal is active. The video memory can be accessed from REG space without using this pin, however, high level signal must be inputted to

LWD

(I: Pull Up)

CSMEM

in this case.

Selects a CPU data bus width. When high level signal is inputted to this pin, AVDP6 operates as CPU 32 bit device, or

when low level signal is inputted to this pi n, AVDP6 operates as CPU 16 bit device.

WR3

WR2-0

Controls write access to AVDP6 when chip select input signal is active.

D23-16,

controls D15-8, and

WR1

For 16 bit CPU,

WR3

((((I))))

controls D7-0.

WR0

function as A1 o f CPU a ddr ess.

control D31-24,

WR3

is not used, and thus must be open because the pin is

WR2

controls

provided with a pull-up resistor.

((((I))))

Controls read access to AVDP6 when chip select input signal is active. D31-0 pins are in output state while this signal and chip select signals are active. For 16 bit CPU, only D15-0 pins are in output state and D31-16 pins are in input states at all times.

WAIT

((((

O: Pull Up, 3-state output

Data wait signal output to CPU. When signal is asserted once for RD or This pin becomes high impedance state when

and

READY

((((

O: Pull Up, 3-state output

WR3

and

WR2-0

))))

pin or

CSMEM

signals, and then negated when AVDP6 becomes accessible.

WR3

CSREG

and

WR2-0

pin is not active, and outputs high level signal when CS pin is active

pins are not active. Use this pin or

))))

pin (hereafter called “CS pin”) is active, the

READY

depending on the type of CPU.

WAIT

Data ready signal output to CPU. When AVDP6 becomes accessible, this signal is asserted. This pin becomes high impedance state when

WR2-0

pins are not active. Use this pin or

((((O))))

INT

pin is not active, outputs high level signal when CS pin is active and RD or

depending on the type of CPU.

WAIT

WR3

Interrupt request signal output to CPU. This pin becomes active when internal state of AVDP6 coincides with the setting conditions of the registers, and is reset when internal registers of AVDP6 are accessed.

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