Xilinx Zynq-7000, ZC702 Getting Started Manual

Zynq-7000 All Programmable SoC:
ZC702 Evaluation Kit
and
Video and Imaging Kit
(Vivado Design Suite 2013.3)

Getting Started Guide

UG926 (v6.0) December 17, 2013

This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4

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© Copyright 2012–2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands
included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight,
Cortex, and PrimeCell are trademarks of ARM in the EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used
under license. HDMI, HDMI logo, and High-Definition Multimedia Interface are trademarks of HDMI Licensing LLC. All other trademarks are
the property of their respective owners.

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; IP cores may be subject to warranty and support

2 www.xilinx.com ZC702 and ZVIK Getting Started Guide

UG926 (v6.0) December 17, 2013

Revision History

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The following table shows the revision history for this document.

Date Version Revision

05/25/2012 1.0

05/29/2012 1.1

06/21/2012 1.2

09/18/2012 2.0

Initial Xilinx release.

Added Figure 4-3 and the text just before and after it.

Chapter 1, Introduction: Added a “Reference Designs and Demonstrations” group to

section ZC702 Evaluation Kit Contents, page 8. Changed cable from Digilent USB
JTAG to Digilent USB-to-JTAG. Added that the SD MMC card contains bootable
configuration files for the Base TRD demo design files and Linux applications
platform. Updated USB JTAG interface information and added details to the clock
sources list in section For reference design files, documents, and board source files,

go to the Zynq-7000 AP SoC Video and Imaging Kit documentation page., page 10.

Changed FMC1 and FMC2 connector types to LPC I/O expansion connectors. Added
tables of default settings to the section Default Jumper and Switch Settings, page 11.

Chapter 2, ZC702 Evaluation Kit Built-In Self-Test: Updated switch settings in the
Introduction, page 15. Added bring-up details through the chapter. Settings were

added to section Run the BIST Application, page 22.
Added Chapter 3, Getting Started with the Base Targeted Reference Design.
Added Chapter 4, Using the AMS101 Evaluation Card.
Additional references were added through the book and to Appendix A, Additional

Resources.

The ZC702 evaluation kit now includes a USB Micro-B to female A adapter. Added
information about the Zynq-7000 AP SoC Video and Imaging Kit (ZVIK) to the

Overview, page 7 and a new section Zynq-7000 AP SoC Video and Imaging Kit
Contents, page 10. Photos are updated in Figure 1-3: Feature Callout for the ZC702

Board and Figure 2-2: ZC702 with the UART and Power Cable Attached. The TRD

Demonstration Procedure, page 30 adds information on how to demo the video

application using an external video source supporting use of the ZVIK. Added

Tab l e 3- 1 and Ta bl e 3 -2 . Added support for 720p video resolution in the video demo

application in Running the Video Demonstration for 720p Video Resolution, page 38.

11/12/2012 2.1

01/24/2013 3.0

ZC702 and ZVIK Getting Started Guide www.xilinx.com 3

UG926 (v6.0) December 17, 2013

Updated for ISE® Design Suite v14.3. Document and web site references changed
throughout the book. In BIST Setup Requirements, page 15, “A power adapter and
power cable for the ZC702 board” was removed. In ZC702 Evaluation Board Setup,

page 16, step 1 changed. In Install the USB-UART Driver, page 18,step 1 and step 2

changed. An introduction was added to Chapter 3. In Base TRD Key Features, page 27,
“1 GB DDR3 running at 533 MHz” was removed. In Base TRD Hardware Setup

Requirements, page 28, zImage and ramdisk8M.image.gz became uImage and

uramdisk8M.image.gz. The USB stick (or key) is not included in the kit. Instead,
download files from the ZC702 Product Page at www.xilinx.com/zc702
the Docs & Designs tab. Standoffs and a new Figure 3-3 showing mounting hardware
details were added to TRD Demonstration Procedure, page 30. Figure 3-6 and

Figure 3-7 were replaced to illustrate the QT-based GUI and minimized GUI mode.

USB key was removed from Chapter 4. Next Steps became Chapter 5.

Updated for ISE Design Suite 14.5. Revised eighth bullet on page 28 to replace
sentence ending in “to exercise the portions of the demo ...” to be “use the frame
buffer console terminal that will come up, once user exit the demo.” Added third note
on page 29. Revised Figure 3-6, page 33 and Figure 3-7, page 34.

and click on

Date Version Revision

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02/12/2013 3.0.1

05/14/2013 4.0

08/12/13 5.0

Draft

10/21/13 6.0

Draft

Removed stray internal draft banner from the cover page, and from the first page in
each chapter and appendix.

Deleted “Key Features of the ZC702 Evaluation Board” section. The Base TRD Key

Features, page 27 were updated for the Programmable Logic (PL) to “One

Performance Monitor”. The required binaries in Base TRD Hardware Setup

Requirements, page 28 were updated to include “zynq-zc702-base-trd.dts“.

Port “P1” was labelled in Figure 3-2. Figure 3-6 and Figure 3-7 were replaced to
illustrate the QT-based GUI and minimized GUI mode. In Running the Video

Demonstration for 720p Video Resolution, page 38, the instructions were updated for

running QT based GUI in 720p mode and running the UART Menu based
Demonstration Application in 720p mode.

Updated document for Vivado Design Suite 2013.2. Added Command Line Application
block to Figure 3-1. Updated binaries under Base TRD Hardware Setup Requirements.
Updated commands under Running the Qt-Based GUI Application Demonstration,

Running the UART Menu-Based Demonstration Application, and Running the Video
Demonstration for 720p Video Resolution. Updated Figure 3-9 and Figure 4-1.

Updated Requirements to Get Started (modified steps 3 and 4 and deleted step 5).
Updated Evaluating AMS steps 2 and 3.

Updated document for Vivado Design Suite 2013.3. Updated Figure 3-6, Figure 3-7,
and Figure 3-9. Updated zynq> commands (changed sobel_qt to run_sobel.sh).

4 www.xilinx.com ZC702 and ZVIK Getting Started Guide

UG926 (v6.0) December 17, 2013

Table of Contents

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Chapter 1: Introduction

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

ZC702 Evaluation Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Zynq-7000 AP SoC Video and Imaging Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Key Features of the ZVIK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Default Jumper and Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 2: ZC702 Evaluation Kit Built-In Self-Test

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

BIST Setup Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Hardware BIST Board Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Hardware Bring-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Run the BIST Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chapter 3: Getting Started with the Base Targeted Reference Design

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Base TRD Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Base TRD Hardware Setup Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

TRD Demonstration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Running the Qt-Based GUI Application Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Running the UART Menu-Based Demonstration Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Running the Video Demonstration for 720p Video Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Chapter 4: Using the AMS101 Evaluation Card

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Requirements to Get Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Evaluating AMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Chapter 5: Next Steps

Next Steps for the Zynq-7000 AP SoC Video and Imaging Kit (ZVIK) . . . . . . . . . . . . . . . . . . . . . . . . 45

ZC702 and ZVIK Getting Started Guide www.xilinx.com 5

UG926 (v6.0) December 17, 2013

Appendix A: Additional Resources

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Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Appendix B: Warranty

6 www.xilinx.com ZC702 and ZVIK Getting Started Guide

UG926 (v6.0) December 17, 2013

Introduction

UG926_c1_01_060712

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Overview

The Zynq®-7000 All Programmable SoC (AP SoC) ZC702 evaluation kit shown in Figure 1-1
is based on the XC7Z020 CLG484-1 AP SoC. For additional information, see the Zynq-7000
AP SoC Product Table [Ref 1]. A built-in self-test (BIST) is provided for the ZC702 evaluation
kit. The BIST provides a convenient way to test many of the board's features on power-up.
The tutorials and reference designs available on the Zynq-7000 AP SoC ZC702 Evaluation Kit

documentation page can be used to further explore the capabilities of the ZC702 board and

the Zynq-7000 AP SoC.

TIP: For the most up-to-date information on the content provided with the ZC702 evaluation kit, see

the Zynq-7000 AP SoC ZC702 Evaluation Kit product page
Concepts, Tools, and Techniques (UG873) [Ref 2] shows the basic hardware and software flow using the
ZC702 board. The Zynq-7000 AP SoC documentation page is also helpful.

Chapter 1

. Zynq-7000 All Programmable SoC:

X-Ref Target - Figure 1-1

Figure 1-1: ZC702 Evaluation Kit

ZC702 and ZVIK Getting Started Guide www.xilinx.com 7

UG926 (v6.0) December 17, 2013

Chapter 1: Introduction

UG926_c1_02_110512

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The Zynq-7000 AP SoC Video and Imaging Kit (ZVIK) shown in Figure 1-2 is based on the
ZC702 evaluation kit and includes all of the components of the ZC702 kit with the
addition of components enabling HD video input from an High-Definition Multimedia
Interface (HDMI™) source or from the included HD image sensor. All of the information
presented in this guide related to the ZC702 evaluation kit applies to the ZVIK. For the
most current information on the content provided with the ZVIK, see the Zynq-7000 All

Programmable SoC Video and Imaging Kit product page.

X-Ref Target - Figure 1-2

Figure 1-2: Zynq-7000 AP SoC Video and Imaging Kit

This user guide also describes a Base Targeted Reference Design (TRD) based on Zynq-7000
AP SoC architecture. The Base TRD showcases various features and capabilities of the
Zynq Z-7020 AP SoC for the embedded domain in a single package.

TRDs are key components of the Xilinx Targeted Design Platform (TDP) strategy. TDPs from
Xilinx provide customers with basic scalable design platforms for the creation of
FPGA-based solutions in a wide variety of applications and industries.

Note:

as the ZC702 Evaluation Kit and the Zynq-7000 AP SoC Video and Imaging Kit is referred to as ZVIK.

In the remainder of this document, the Zynq-7000 AP SoC ZC702 evaluation kit is referred to

ZC702 Evaluation Kit Contents

The ZC702 evaluation kit includes the following items:

• ZC702 EK-Z7-ZC702-G evaluation board featuring the XC7Z020 CLG484-1

• Agile Mixed Signal (AMS) evaluation board

• Full Vivado design suite

8 www.xilinx.com ZC702 and ZVIK Getting Started Guide

UG926 (v6.0) December 17, 2013

Node-locked, device-locked to the Zynq-7000 XC7Z020 CLG484-1 device

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°

•Board design files

Schematics

°

Board layout files

°

Bill of materials

°

• Documentation

ZC702 Evaluation Kit and Video Imaging Kit Targeted Reference Design

°

Documentation Advisory

• Reference Designs and Demonstrations

BIST Utility and Demonstration

°

Targeted Reference Design (TRD), demonstrating a video processing pipeline.

°

ZC702 Evaluation Kit Contents

Note:

design, the user needs to register for an evaluation IP license for the Video IP.

AMS demonstration, providing an overview of the analog capabilities of the

°

The video demonstration contains the licensed IPs with no timeout. To recompile this

Zynq-7000 AP SoC devices.

• 12V AC adapter power supply

•Cables

RJ-45 Ethernet cable

°

HDMI cable

°

USB Type-A to USB Micro-B cable (Digilent USB-to-JTAG Programing Port)

°

USB Type-A to USB Mini-B cable (serial UART)

°

USB Micro-B to female A adapter (for connecting USB hub, keyboard, and mouse)

°

• Secure Digital Multimedia Card (SD MMC) (contains bootable configuration files for the
Base TRD demonstration design files and Linux platform applications)

The kit contains the software and reference designs, a demonstration, and documents to
help the user get started quickly.

ZC702 and ZVIK Getting Started Guide www.xilinx.com 9

UG926 (v6.0) December 17, 2013

For reference design files, documents, and board source files, go to the Zynq-7000 AP SoC

ZC702 Evaluation Kit documentation page.

Chapter 1: Introduction

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Zynq-7000 AP SoC Video and Imaging Kit Contents

The ZVIK contains all of the items included in the ZC702 evaluation kit plus the following
items. For more information on the HDMI input/output FMC module and ON Semiconductor
image sensor, refer to the Avnet product page [Ref 3].

• HDMI input/output FPGA mezzanine card (FMC) module

• ON Semiconductor VITA 2000 Color Image Sensor module

• Standard interchangeable

•Infrared (IR) cut filter

•Camera tripod

• Lens holder

•Cables

2

/3-inch 8 mm C-mount lens

Second HDMI cable

°

LCEDI image sensor cable

°

For reference design files, documents, and board source files, go to the Zynq-7000 AP

SoC Video and Imaging Kit documentation page.

Key Features of the ZVIK

Key features of the additional components of the Zynq-7000 AP SoC Video and Imaging kit
include:

•HDMI input/output FMC module

HDMI input

°

HDMI output

°

Video clock synthesizer

°

Interface for ON Semiconductor VITA image sensor module

°

• ON Semiconductor VITA 2000 color image sensor module

10 www.xilinx.com ZC702 and ZVIK Getting Started Guide

Supports up to WXGA resolution: 1920 (H) x 1200 (V) format

°

92 frames per second (fps) at full resolution

°

4.8 μ m x 4.8 μ m pixel size 2/3-inch optical format

°

Pipelined and triggered global shutter, rolling shutter

°

UG926 (v6.0) December 17, 2013

X-Ref Target - Figure 1-3

FMC1 LPC

Connector

Xilinx XADC

Header

UG926_c1_03_111913

FMC2 LPC

Connector

8 User LEDs

User 2-Pole DIP Switch

Zynq-7000 AP SoC

Power Management System
(Bottom and Top of Board)

FPGA PROG Pushbutton

I2C Real-time Clock (RTC)

DDR3 Component
Memory (1 GB)

RGMII Ethernet
PHY Oscillator,
25,000 MHz

Quad SPI Flash Memory (1 Gb)

SD Card Interface Connector

Configuration Mode Select Switch

System Clock, 200 MHz,

2.5V LVDS

I2C Bus Switch

Power On/Off Slide Switch

CAN Bus Transceiver

HDMI Controller,

HDMI Video Connector

USB JTAG

Module with Integrated

USB Micro-B Connector

I2C Programmable User

Clock 3.3V LVDS

User Pushbuttons

Active High

Ethernet Status

LEDs

USB-to-UART Bridge,

USB Mini-B Connector

2x6 Male Header

Pins I/O Driven from

I2C Expander U80

USB 2.0 ULPI

Transceiver,

USB Micro-B

Connector

10/100/1000 MHz

Ethernet PHY,

RJ45 with Magnetics

2x6 and 1x6

PMOD I/O Header

12V Power Connector

PMBus Connector
(Bottom of board)

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Default Jumper and Switch Settings

Random programmable region of interest (ROI) readout

°

Automatic exposure control (AEC)

°

2

• Standard interchangeable

/3-inch, 8 mm C-mount lens

Default Jumper and Switch Settings

Figure 1-3 calls out the major features on the ZC702 board. See the ZC702 Evaluation Board

for the Zynq-7000 XC7Z020 All Programmable SoC User Guide (UG850) [Ref 4] for more

detailed information about the ZC702 board.

Default factory settings of jumpers and switches on the ZC702 board are highlighted in

Figure 1-4. Default switch and jumper settings are listed in Tab le 1- 1 and Ta bl e 1- 2.

ZC702 and ZVIK Getting Started Guide www.xilinx.com 11

UG926 (v6.0) December 17, 2013

Figure 1-3: Feature Callout for the ZC702 Board

Chapter 1: Introduction

UG926_c1_04_021213

1

8

9

7

SW11

Down/Off

2

3

4

6 5

1

8

9

7

SW11

Down/Off

2

3

4

6 5

Send Feedback

X-Ref Target - Figure 1-4

12 www.xilinx.com ZC702 and ZVIK Getting Started Guide

Figure 1-4: Default Jumper and Switch Settings on the ZC702 Board

UG926 (v6.0) December 17, 2013

Table 1-1: Default Switch Settings

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Default Jumper and Switch Settings

Switch Position Setting

SW10
(JTAG chain input select two-position DIP switch)

SW12
(two-position DIP switch)

SW15
(two-position DIP switch)

SW16
(five-position DIP switch)

SW11
(power slide switch)

1Off

2On

1Off

2Off

1Off

2Off

1Right

2Right

3Right

4Right

5Right

Off

1Down

Figure 1-4

Callout

9

2

2

1

8

Default jumper positions are shown in Figure 1-4 and listed in Tabl e 1 - 2 .

Table 1-2: Default Jumper Settings

Jumper Function Default Position

HDR_1 X 2

J5 CFGBVS short to GND

J6 POR Master Reset

J7 USB 2.0 USB_VBUS_SEL

J8 XADC GND L3 Bypass

J9 XADC GND

J10 ARM HDR J41 pin 2 to VADJ

J11 UCD9248 U32 ADDR52 RESET_B

J12 FMC_VADJ_ON_B

J13 UCD9248 U33 ADDR53 RESET_B

J14 UCD9248 U34 ADDR54 RESET_B

J15 CAN BUS COMMON-MODE CANH HDR

J43 Ethernet PHY HDR

J44 USB 2.0 USB_RESET_B

J53 CAN BUS COMMON-MODE CANL HDR

OFF 4

OFF 1

ON 6

OFF 2

ON 2

OFF 7

OFF 4

ON 4

OFF 3

OFF 5

ON 7

ON 7

OFF 7

ON 7

Figure 1-4

Callout

ZC702 and ZVIK Getting Started Guide www.xilinx.com 13

UG926 (v6.0) December 17, 2013

J56 JTAG HDR J58 pin 2 3.3V SEL

J65 XADC_VCC5V0 = VCC5V0

OFF 9

ON 2

Chapter 1: Introduction

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Table 1-2: Default Jumper Settings (Cont’d)

Jumper Function Default Position

HDR_1 X 3

J27 PS_SRST_B

J28 PS_POR_B

J30 Ethernet PHY HDR

J31 Ethernet PHY HDR

J32 Ethernet PHY HDR

J33 USB 2.0 Mode

J34 USB 2.0 J1 ID SEL

J35 USB 2.0 J1 VBUS CAP SEL

J36 USB 2.0 J1 GND SEL

J37 XADC_VREP SEL

J38 XADC_VCC SEL

J70 XADC_VREF Source SEL

1-2 1

1-2 1

1-2 7

NONE 7

NONE 7

2-3 6

1-2 7

1-2 6

1-2 7

1-2 2

2-3 2

2-3 2

Figure 1-4

Callout

14 www.xilinx.com ZC702 and ZVIK Getting Started Guide

UG926 (v6.0) December 17, 2013

Chapter 2

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ZC702 Evaluation Kit Built-In Self-Test

Introduction

The BIST tests many of the features offered by the ZC702 evaluation kit. The test is stored in
the onboard nonvolatile Quad SPI flash memory and configures the AP SoC when mode
switch SW16 is set to where SW1, 2, 3, and 5 are switched to the right and SW4 is switched
to the left, indicating QSPI configuration. This exercise of running the BIST demonstration
should take approximately 10 to 15 minutes.

Note:

Zynq-7000 XC7Z020 All Programmable SoC User Guide (UG850) [Ref 4].

For a description of all the features on the ZC702 board, see ZC702 Evaluation Board for the

BIST Setup Requirements

These are the prerequisites for running the BIST demonstration.

• Hardware setup:

ZC702 evaluation board with XC7Z020 CLG484-1 part

°

USB Type-A to Mini-B cable (for UART)

°

AC power adapter (12 VDC)

°

• Windows software and driver setup:

Tera Term Pro [Ref 5] (or similar) terminal program (might already be installed)

°

USB-UART driver from Silicon Labs [Ref 6] (might already be installed)

°

ZC702 and ZVIK Getting Started Guide www.xilinx.com 15

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