XILINX XQ4000XL User Manual

0

R

DS029 (v1.3) June 25, 2000

02

XQ4000X Series Features

• Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer Listing)

• Ceramic and plastic packages

• Also available under the following standard microcircuit
drawings (SMD)

- XQ4013XL 5962-98513

- XQ4036XL 5962-98510

- XQ4062XL 5962-98511

- XQ4085XL 5962-99575

• For more information contact the Defense Supply
Center Columbus (DSCC)

http://www.dscc.dla.mis/v/va/smd/smdsrch.html

• Available in -3 speed

• System featured Field-Programmable Gate Arrays

- SelectRAM™ memory: on-chip ultra-fast RAM with

· synchronous write option

· dual-port RAM option

- Abundant flip-flops

- Flexible function generators

- Dedicated high-speed carry logic

- Wide edge decoders on each edge

- Hierarchy of interconnect lines

- Internal 3-state bus capability

- Eight global low-skew clock or signal distribution

networks

• System performance beyond 50 MHz

• Flexible array architec t u re

• Low power segmented routing architecture

• Systems-oriented features

- IEEE 1149.1-compatible boundary scan logic

support

- Individually programmable output slew rate

- Programmable input pull-up or pull-down resistors

- 12 mA sink current per XQ4000XL output

• Configured by loading binary file

- Unlimited reprogrammability

• Readback capability

- Program verification

- Internal node observability

QPRO XQ4000XL Series QML
High-Reliability FPGAs

Produc t S pecif i catio n

• Development system runs on most common computer
platforms

- Interfaces to popular design environments

- Fully automatic mapping , placement and ro uting

- Interactive design editor for design optimization

• Highest capacity—over 180,000 usable gates

• Additional routing over XQ4000E

- Almost twice the routing capacity for high-density

designs

• Buffered Interconnect for maximum speed

• New latch capability in configurable logic blocks

• Improved VersaRing™ I/O interconnect for better Fix ed

pinout flexibility

- Virtually unlimited number of clock signals

• Optional multiplexer or 2-input function generator on
device outputs

• 5V tolerant I/Os

• 0.35 µm SRAM process

Introduction

The QPRO™ XQ4000XL Series high-performance,
high-capacity Field Programmable Gate Arrays (FPGAs)
provide the benefits of custom CMOS VLSI, while avoiding
the initial cost, long development cycle, and inherent risk of
a conventional masked gate array.

The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com­bine architectural versatility, on-chip Select-RAM memor y
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated
soft-ware to achieve fully automated implementation of
complex, high-density, high-performance designs.

Refer to the complete Commercial XC 4000XL Se ries Field
Programmable Gate Arrays Data Sheet for more informa­tion on device architecture and timing, and the latest Xilinx
databook for package pinouts other than the CB228
(included in this data sheet). (Pinouts for XQ4000XL device
are identical to XC4000XL.)

© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS029 (v1.3) June 25, 2000 www.xilinx.com 1

Product Specification 1-800-255-7778

QPR O XQ4000X L Seri es QML High-Rel iabi l i ty FPGA s

Table 1: XQ4000XL Series High Reliability Field Progammable Gate Arrays

Max

Device

Logic

Cells

Logic
Gates

(No

RAM)

(1)

Max.
RAM

Bits (No

Logic)

Typical Gate

Range

(Logic and

(1)

RAM)

CLB

Matrix

Total

CLBs

Number

of

Flip-Flops

Max.
User

I/O Packages

XQ4013XL 2432 13,000 18,43 2 10,000-30,000 24x24 576 1,536 192 PG223, CB228,

PQ240, BG256

XQ4036XL 3078 36,000 4 1,472 22,000-65,000 36x36 1,296 3,168 288 PG411, CB228,

HQ240, BG352

XQ4062XL 5472 62,000 7 3,728 40,000-130,000 48x48 2, 304 5,376 384 PG475, CB228,

HQ240, BG432

XQ4085XL 7448 85,000 100,352 55,000-180,000 56x56 3,136 7,168 448 PG475, CB228,

HQ240, BG432

Notes:

1. Maximum val ues of typical gate range includes 20% to 30% of CLBs used as RAM.

R

2 www.xilinx.com DS029 (v1.3) June 25, 2000

1-800-255-7778 Product Specification

R

QPRO XQ4000XL Series QML High-Reliability FPGAs

XQ4000XL Switching Characteristics

Definition of Terms

In the following tables, some specifications may be designated as Advance or Preliminary. These ter ms are defined as
follows:

Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or

devicefamilies. Values are subject to change. Use as estimates, not for production.

Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.

Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this documen t are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions.

All specifications subject to change without notice.

Additio nal Specif icati ons

Except for pin-to-pin input and output parameters, the a.c.
parameter delay specifications included in this document
are derived from measuring internal test patterns. All speci­fications are representative of worst-case supply voltage
and junction temperature conditions. The parameters
included are common to popular designs and typical appli-

Absolute Maximum Ratings

(1)

cations. For design considerations requiring more detailed
timing information, se e the appropriate family AC supple­ments available on the Xilinx web site at:

http://www.xilinx.com/partinfo/databook.htm

.

Symbol Description Units

V

V
T
T

V

V

CCt
STG
SOL

T

CC

IN

TS

J

Supply voltage relative to GND –0.5 to 4.0 V
Input voltage relative to GND
Voltage applied to High-Z output

(2)

(2)

–0.5 to 5.5 V
–0.5 to 5.5 V

Longest supply voltage rise time from 1V to 3V 50 ms
Storage temperature (ambient) –65 to +150 °C
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
Junction temperature Ceramic package +150 °C

Plastic package +125 °C

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings onl y, and functional operat ion of the device at these or any other condition s beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affec t device reliab il ity.

2. Maximum DC over shoot or undershoot above V
achieve. During transitions, the device pins may undershoot to –2. 0 V or over shoot to VCC + 2.0V, pro vided this over- or undershoot
lasts less than 10 ns and with the forcing current being limited to 200 mA.

Recommended Operating Conditions

or below GND must be limited to either 0.5V or 10 mA, whichever is easier to

CC

(1)

Symbol Description Min Max Units

V

CC

V

V

T

Notes:

1. At junction temperatures abov e those listed as Operating Conditions, all delay param eters increase by 0.35% per °C.

2. Input and output measurement threshold is ~50% of V

Supply voltage relative to GND, TJ = –55°C to +125°CPlastic 3.0 3.6 V
Supply voltage relative to GND, T
High-level input voltage

IH

Low-level input vol tage 0 30% of V

IL

Input signal transition time - 250 ns

IN

(2)

= –55°C to +125°C Ceramic 3.0 3.6 V

C

CC

50% of V

.

CC

5.5 V

CC

V

DS029 (v1.3) June 25, 2000 www.xilinx.com 3

Product Specification 1-800-255-7778

QPR O XQ4000X L Series QML High-Reliability FPGAs

XQ4000XL DC Characteristics Over Recommended Operating Conditions

Symbol Description Min Max Units

R

V

OH

V

V

I

CCO

I

C

OL

DR

L

IN

High-level output voltage at IOH = –4 mA, VCC min (LVTTL) 2.4 - V
High-level output voltage at I
Low-lev el output voltage at IOL = 12 mA, VCC min (LVTTL)
Low-lev el output voltage at I

= –500 µA, (LVCMOS) 90% V

OH

(1)

= 1500 µA, (LVCMOS) - 10% V

OL

CC

-0.4V

Data retention supply voltage (below which configuration data may be lost) 2.5 - V
Quiescent FPGA supply current

(2)

-5mA
Input or output leakage current –10 +10 µA
Input capacitance (sample tested) BGA, PQ, HQ, packages - 10 pF

PGA packages - 16 pF

I

RPU

I

RPD

I

RLL

Notes:

1. With up to 64 pins simul taneously sinking 12 mA.

2. With no output current l oads, no active input or Longline pull- up resistors, all I/O pins in a High-Z state and floating.

Pad pull-up (when selected) at VIN = 0V (sample tested) 0.02 0.25 mA
Pad pull-down (when selected) at VIN = 3.6V (sample tested) 0.02 0.15 mA
Horizontal longline pull-up (when selected) at logic Low 0.3 2.0 mA

Power-On Power Supply Requirements

Xilinx FPGAs require a minimum rated power supply current
capacity to insure proper initialization, and the power supply
ramp-up time does affect the current required. A fast
ramp-up time requires more current than a slow ramp-up
time. The slowest ramp-up time is 50 ms. Current capacity
is not specified for a ramp-up time faster than 2 ms. The cur-

rent capacity varies linealy with ramp-up time, e.g., an
XQ4036XL with a ramp-up time of 25 ms would require a
capacity predicted by the po int on the straight line drawn
from 1A at 120 µs to 500 mA at 50 ms at the 25 ms time
mark. This point is approximately 750 mA

-V

CC

.

V

Ramp-up Time

Product Descrip t ion

Fast (120 µs) Slow (50 ms)

XQ4013 - 36XL Minimum required current supply 1A 500 mA
XC4062XL Minimum required curre nt supply 2A 500 mA
XC4085XL

Notes:

1. The XC4085XL fast r am p-up time is 5 ms.

2. Devices ar e guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may result in a
large r initialization current.

3. This specification applies to Commercial and Industrial grade products only.

4. Ramp-up Time is measured from 0V
on reset threshold voltage . After initialization and before configuration, I

(1)

Minimum required current supply 2A

to 3.6VDC. Peak current required lasts less than 3 ms, and occurs near the internal power

DC

max is less than 10 mA.

CC

(1)

500 mA

4 www.xilinx.com DS029 (v1.3) June 25, 2000

1-800-255-7778 Product Specification

R

XQ4000XL AC Switching Characteristic

QPRO XQ4000XL Series QML High-Reliability FPGAs

Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values where one global clock input
drives one vertical clock line in each acc essible column, and
where all accessible IOB and CLB flip-flops are c locked by
the global clock net.

When fewer vertical clock lines are connected, the clock dis-

driven from the same gl obal clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing str ucture, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature)

tribution is faster; when multiple clock lines per column are

Global Buffer Switching Characteristics

Symbol Description Device

T

GLS

Delay from pad through Global Low Skew buffer, to any
clo ck K

XQ4013XL 0.6 3.6 - ns
XQ4036XL 1.1 4.8 - ns
XQ4062XL 1.4 6.3 - ns
XQ4085XL 1.6 - 5.7 ns

Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock Characteristics

All

Min

-3 -1
UnitsMax Max

Symbol Description Device

T

GE

Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 1, 2, 5 and 6.

XQ4013XL 0.4 2.4 - ns
XQ4036XL 0.3 3.1 - ns
XQ4062XL 0.3 4.9 - ns
XQ4085XL 0.4 - 4.7 ns

Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock Characteristics

Symbol Description Device

T

GE

Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 3, 4, 7 and 8.

XQ4013XL 0.7 2.4 - ns
XQ4036XL 0.9 4.7 - ns
XQ4062XL 1.2 5.9 - ns
XQ4085XL 1.3 - 5.5 ns

All

Min

All

Min

-3 -1
UnitsMax Max

-3 -1
UnitsMax Max

DS029 (v1.3) June 25, 2000 www.xilinx.com 5

Product Specification 1-800-255-7778

QPR O XQ4000X L Series QML High-Reliability FPGAs

XQ4000XL CLB Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported

by the static timing analyzer (TRCE in the Xilinx Develop­ment System) an d back-ann otated to th e simu lation n etlist.
All timing parameters ass ume worst-case operating con di­tions (supply voltage and junction temperature). Values
apply to all XQ4000XL devices and expressed in nanos ec­onds unless otherwise noted.

CLB Switching Characteristics

Symbol Description

Combinatorial Delays

T

ILO

T

IHO

T

ITO

T

HH0O

T

HH1O

T

HH2O

T

CBYP

CLB Fast Carry Logic

T

OPCY

T

ASCY

T

INCY

T

SUM

T

BYP

T

NET

Sequential Delays

T

CKO

T

CKLO

Setup Time Before Clock K

T

ICK

T

IHCK

T

HH0CK

T

HH1CK

T

HH2CK

T

DICK

T

ECCK

T

RCK

T

CCK

T

CHCK

F/G inputs to X/Y outputs - 1.6 - 1.3 ns
F/G inputs vi a H ’ to X/Y outputs - 2.7 - 2.2 ns
F/G inputs via transparent latch to Q outputs - 2.9 - 2.2 ns
C inputs via SR/H0 via H to X/Y outputs - 2.5 - 2.0 ns
C inputs via H1 via H to X/Y outputs - 2.4 - 1.9 ns
C inputs via DIN/H2 via H to X/Y outputs - 2 .5 - 2.0 ns
C inputs via EC, DIN/H2 to YQ, XQ output (bypass) - 1.5 - 1.1 ns

Operand inputs (F1, F2, G1, G4) to C
Add/subtract input (F3) to C

OUT

Initialization inputs (F1, F3) to C

OUT

OUT

CIN through function generators to X/Y outputs - 2.8 - 2.4 ns
C

to C

IN

Carry net delay, C

, bypass function generators - 0.26 - 0.20 ns

OUT

to C

OUT

IN

Clock K to flip-flop outputs Q - 2.1 - 1.6 ns
Clock K to latch outputs Q - 2.1 - 1.6 ns

F/G inputs 1.1 - 0.9 - ns
F/G in puts via H 2.2 - 1.7 - ns
C inputs via H0 through H 2.0 - 1.6 - ns
C inputs via H1 through H 1.9 - 1.4 - ns
C inputs via H2 through H 2.0 - 1.6 - ns
C inputs via D

IN

C inputs via EC 1.0 - 0.8 - ns
C inputs via S/R, going Low (inactive) 0.6 - 0.5 - ns
CIN input via F/G 2.3 - 1.9 - ns
CIN input via F/G and H 3.4 - 2.7 - ns

R

-3 -1
UnitsMin Max Min Max

-2.7-2.0ns

-3.3-2.5ns

-2.0-1.5ns

- 0.32 - 0.25 ns

0.9 - 0.7 - ns

6 www.xilinx.com DS029 (v1.3) June 25, 2000

1-800-255-7778 Product Specification

R

CLB Switching Characteristics (Continued)

Symbol Description

Hold Time After Clock K

T

CKI

T

CKIH

T

CKHH0

T

CKHH1

T

CKHH2

T

CKDI

T

CKEC

T

CKR

Clock

T

CH

T

CL

Set/Reset Direct

T

RPW

T

RIO

Global Set/Reset

T

MRW

T

MRQ

F

TOG

F/G inputs 0 - 0 - ns
F/G inputs vi a H 0 - 0 - ns
C inputs via SR/H0 through H 0 - 0 - ns
C inputs via H1 through H 0 - 0 - ns
C inputs via DIN/H2 through H 0 - 0 - ns
C inputs via DIN/H2 0 - 0 - ns
C inputs via EC 0 - 0 - ns
C inputs via SR, going Low (inactive) 0 - 0 - ns

Clock High time 3.0 - 2.5 - ns
Clock Low time 3.0 - 2.5 - ns

Width (High) 3.0 - 2.5 - ns
Delay from C inputs via S/R, going High to Q - 3.7 - 2.8 ns

Minimum GSR pulse width - 19.8 - 15.0 ns
Delay from GSR input to any Q See page 17 for T
Toggle frequency (MHz) (for export control) - 166 - 200 MHz

QPRO XQ4000XL Series QML High-Reliability FPGAs

-3 -1
UnitsMin M ax Min Max

values per device.

RRI

DS029 (v1.3) June 25, 2000 www.xilinx.com 7

Product Specification 1-800-255-7778