XILINX XQ4000E, XQ4000EX User Manual

查询XQ4000ESERIES供应商

0

R

DS021 (v2.2) June 25, 2000

02

Product Features

• Certified to MIL-PRF-38535, appendix A QML
(Qualified Manufacturers Listing)

• Also available under the fol lo wing Standard Microcircuit
Drawings (SMD)

- XC4005E 5962-97522

- XC4010E 5962-97523

- XC4013E 5962-97524

- XC4025E 5962-97525

- XC4028EX 5962-98509

• For more information contact the Defense Supply
Center Columbus (DSCC)

http://www.dscc.dla.mis/v/va/smd/smdsrch.html

• System featured Field-Programmable Gate Arrays

TM

- Select-RAM

· Synchronous write option

· Dual-port RAM option

- Abundant flip-flops

- Flexible function generators

- Dedicated high-speed carry logic

- Wide edge decoders on each edge

- Hierarchy of interconnect lines

- Internal 3-state bus capability

- Eight global low-skew clock or signal distribution

networks

• System Performance beyond 60 MHz

• Flexible Array Archit ec tur e

• Low Power Segmented Routing Architecture

• Systems-Oriented Features

- IEEE 1149.1-compatible boundary scan logic

support

- Individually programmable output slew rate

- Programmable input pull-up or pull-down resistors

- 12 mA sink current per XQ4000E/EX output

memory: on-chip ultra-fast RAM with

QPRO XQ4000E/EX
QML High-Reliability FPGAs

Produc t S pecif i catio n

• Configured by Loading Binary Fi le

- Unlimited reprogrammability

• Readback Capability

- Program verification

- Inter nal node observability

• Backward Compatible with XC4000 Devices

• Development System runs on most common computer

platforms

- Interfaces to popular design environments

- Fully automatic mapping , placement and ro uting

- Interactive design editor for design optimization

• Available Speed Grades:

- XQ4000E -3 for plastic packages only

- -4 for ceramic packages only

- XQ4028EX -4 for all packages

More Information

For more information refer to Xilinx XC4000E and XC4000X
series Field Programmable Gate A rrays product specifica­tion. This data sheet contains pinout tables for XQ4010E
only. Refer to Xilinx web site for pinout tables for other
devices. (Pinouts for XQ4000E/EX are identical to
XC4000E/EX.)
(http://www.xilinx.com/partinfo/databook.htm

)

© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS021 (v2.2) June 25, 2000 www.xilinx.com 1

Product Specification 1-800-255-7778

QPRO XQ4000E/EX QML High-Reliability FPGAs

Table 1: XQ4000E/EX Field Prog r ammable Gate Arra y s

R

Device

Max.
Logic
Gates

(No RAM)

Max.

RAM Bits

(No

Logic)

Typical

Gate Range

(Logic and

(1)

RAM)

CLB

Matrix

Total

CLBs

Number

of

Flip-Flops

Max.

Decode

Inputs

per Side

Max.
User

I/O Packages

XQ4005E 5,000 6,272 3,000 - 9,000 14 x 14 196 616 42 112 PG156,

CB164

XQ4010E 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 60 160 PG191,

CB196,

HQ208

XQ4013E 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 72 192 PG223,

CB228,

HQ240

XQ4025E 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 96 256 PG299,

CB228

XQ4028EX 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 96 256 PG299,

CB228,
HQ240,

BG352

Notes:

1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.

XQ4000E Switching Characteristics

XQ4000E Absolute Maximum Ratings

(1)

Symbol Description Units

V

T
T

V

V

STG
SOL

T

CC

IN

TS

J

Supply voltage relative to GND –0.5 to +7.0 V
Input voltage relative to GND
Voltage applied to High-Z output

(2)

(2)

–0.5 to VCC + 0.5 V
–0.5 to VCC + 0.5 V

Storage temperature (ambient) –65 to +150 °C
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
Junction temperature Ceramic package +150 °C

Plastic package +125 °C

Notes:

1. Stresses beyond t hose listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings onl y, and functional operat ion of the device at these or any other condition s beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affec t device reliab il ity.

2. Maximum DC excursion a bove V
transitions, the device pins may undershoot to –2.0V or overshoot to V
10 ns and with the forcing current being limited to 200 mA.

or below Ground must be limit ed to ei ther 0.5V or 10 mA, whi chever is easier to achiev e. During

CC

+ 2.0V, provided this over or undershoot lasts less than

CC

2 www.xilinx.com DS021 (v2.2) June 25, 2000

1-800-255-7778 Product Specification

R

QPRO XQ4000E/EX QML High-Reliability FPGAs

XQ4000E Recommended Operating Conditions

(1,2)

Symbol Description Min Max Units

V

CC

V

IH

Supply voltage relative to GND, TJ = –55°C to +125°CPlastic 4.5 5.5 V
Supply voltage relative to GND, T
High-Level Input Voltage TTL inputs 2.0 V

= –55°C to +125°C Ceramic 4.5 5.5 V

C

CC

CMOS inputs 70% 100% V

V

IL

Low-Level Input Voltage TTL inputs 0 0.8 V

CMOS inputs 0 20% V

T

IN

Notes:

1. At junction temperatures above those listed as Operating Condi tions, all delay parameter s increase by 0.35% per °C.

2. Input and output measurement thr eshold are 1.5V for TTL and 2.5V for CMOS.

Input signal transition time - 250 ns

XQ4000E DC Characteristics Over Recommended Operating Conditions

Symbol Description Min Max Units

V

OH

V

OL

I

CCO

I

L

C

IN

I

RIN

I

RLL

Notes:

1. With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.

2. With no output cu rrent loads , no a ctiv e in put or Longli ne pul l-up resist or s, a ll pa c kage pi ns a t V
with the dev elopment system Tie opti on.

3. Characterized Only.

High-level output voltage @ IOH = –4.0 mA, VCC min TTL outputs 2.4 - V
High-level output voltage @ I
Low-lev el output voltage @ IOL = 12.0 mA, VCC min

= –1.0 mA, VCC min CMOS outputs VCC – 0.5 - V

OH

(1)

TTL outputs - 0.4 V
CMOS outputs - 0.4 V

Quiescent FPGA supply current

(2)

-50mA
Input or output leakage current –10 +10 µA
Input capacitance (sample tested) - 16 pF

(3)

(3)

–0.02 –0.25 mA

0.2 2.5 mA

or GND, and the FPGA configured

CC

Pad pull-up (when selected) at VIN = 0V (sample tested)
Horizontal longline pull-up (when selected) at logic Low

V

CC

CC

DS021 (v2.2) June 25, 2000 www.xilinx.com 3

Product Specification 1-800-255-7778

QPRO XQ4000E/EX QML High-Reliability FPGAs

XQ4000E Switching Characteristic Guidelines

R

Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values where one global clock input
drives one vertical clock line in each acc essible column, and
where all accessible IOB and CLB flip-flops are c locked by
the global clock net.

When fewer vertical clock lines are connected, the clock dis­tribution is faster; when multiple clock lines per column are
driven from the same global c lock, the delay is longer. For

data, reflecting the actual routing str ucture, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).

Note: -3 Speed Grade only applies to XQ4010E and
XQ4013E Plastic Package options only. -4 Speed Grade
applies to all XQ devices and is only available in
Ceramic Packages only.

more specific, more precise, and worst-case guaranteed

XQ4000E Global Buffer Switching Characteristics

Symbol Description Device

T

PG

T

SG

From pad through primary buffer, to any clock K XQ4005E - 7.0 ns

XQ4010E 6.3 11.0 ns
XQ4013E 6.8 11.5 ns
XQ4025E - 12.5 ns

From pad through secondary buffer, to any clock K XQ4005E - 7.5 ns

XQ4010E 6.8 11.5 ns

-3

(1)

-4

(2)

UnitsMax Max

Notes:

1. For plastic package options only.

2. For ceramic package options only.

XQ4013E 7.3 12.0 ns
XQ4025E - 13.0 ns

4 www.xilinx.com DS021 (v2.2) June 25, 2000

1-800-255-7778 Product Specification

R

QPRO XQ4000E/EX QML High-Reliability FPGAs

XQ4000E Horizontal Longline Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static timing analyzer (TRCE i n the X ilinx Develop­ment System) and back-annotat ed to t he simulation net list.

These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup­ply voltage and junction tempe rature). Values apply to all
XQ4000E devices unless otherwise noted.

The following guidelines reflect worst-case values over the
recommended operating conditions.

-3 -4

Symbol Description Device

TBUF Driving a Horizontal Longline (LL):

T

IO1

I going High or Low to LL going High or Low, while T is Low.
Buffer is constantly active.

(1)

XQ4005E - 5.0 ns
XQ4010E 6.4 8.0 ns
XQ4013E 7.2 9.0 ns
XQ4025E - 11.0 ns

T

IO2

I going Low to LL going from resistive pull-up High to active Low.
TBUF configured as open-drain.

(1)

XQ4005E - 6.0 ns
XQ4010E 6.9 10.5 ns
XQ4013E 7.7 11.0 ns
XQ4025E - 12.0 ns

T

ON

T going Low to LL going from resistive pull-up or floating High to
active Low. TBUF configured as open-drain or active buf fer with
I=Low.

(1)

XQ4005E - 7.0 ns
XQ4010E 7.3 8.5 ns
XQ4013E 7.5 8.7 ns
XQ4025E - 11.0 ns

T

OFF

T going High to TBUF going inactive, not driving LL. XQ4005E - 1.8 ns

XQ4010E 1.5 1.8 ns
XQ4013E 1.5 1.8 ns
XQ4025E - 1.8 ns

UnitsMax Max

T

PUS

T going High to LL going from Low to High, pulled up by a single
resistor.

(1)

XQ4005E - 23.0 ns
XQ4010E 22.0 29.0 ns
XQ4013E 26.0 32.0 ns
XQ4025E - 42.0 ns

T

PUF

T going High to LL going from Low to High, pulled up by two
resistors.

(1)

XQ4005E - 10.0 ns
XQ4010E 11.0 13.5 ns
XQ4013E 13.0 15.0 ns
XQ4025E - 18.0 ns

Notes:

1. These values include a minimum load. Use the stati c ti m ing analyzer to determine the del ay for each destination.

DS021 (v2.2) June 25, 2000 www.xilinx.com 5

Product Specification 1-800-255-7778

QPRO XQ4000E/EX QML High-Reliability FPGAs

XQ4000E Wide Decoder Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static timing analyzer (TRCE i n the X ilinx Develop­ment System) and back-annotat ed to t he simulation net list.

Symbol Description

(1,2)

These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup­ply voltage and junction tempe rature). Values apply to all
XQ4000E devices unless otherwise noted.

The following guidelines reflect worst-case values over the
recommended operating conditions.

Device

R

-3 -4
UnitsMax Max

T

WAF

Full length, both pull-ups, inputs from IOB I-pins XQ4005E - 9.5 ns

XQ4010E 9.0 15.0 ns
XQ4013E 11.0 16.0 ns
XQ4025E - 18.0 ns

T

WAFL

Full length, both pull-ups, inputs from internal logic XQ4005E - 12.5 ns

XQ4010E 11.0 18.0 ns
XQ4013E 13.0 19.0 ns
XQ4025E - 21.0 ns

T

WAO

Half length, one pull-up, inputs from IOB I-pins XQ4005E - 10.5 ns

XQ4010E 10.0 16.0 ns
XQ4013E 12.0 17.0 ns
XQ4025E - 19.0 ns

T

WAOL

Half length, one pull-up, inputs from internal logic XQ4005E - 12.5 ns

XQ4010E 12.0 18.0 ns
XQ4013E 14.0 19.0 ns
XQ4025E - 21.0 ns

Notes:

1. These delays are specified from the decoder input to the decoder output.

2. Fewer than t he specified numbe r of pull-up resist ors can be used, if desired. Using fewer pull-ups reduces powe r consumption but
increases delays. Use the static timing analyzer to determine delays if few er pull-ups are used.

6 www.xilinx.com DS021 (v2.2) June 25, 2000

1-800-255-7778 Product Specification

R

XQ4000E CLB Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static ti ming analyzer (TR CE in the Xilinx Develop­ment System) and back-annotated to the simulation netlist.

These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup­ply voltage and junction tempe rature). Values apply to all
XQ4000E devices unless otherwise noted.

QPRO XQ4000E/EX QML High-Reliability FPGAs

-3 -4

Symbol Description

Combinatorial Delays

T

T

T

HH0O

T

HH1O

T

HH2O

ILO

IHO

F/G inputs to X/Y outputs - 2.01 - 2.7 ns
F/G inputs via H to X/Y outputs - 4.3 - 4.7 ns
C inputs via SR through H to X/Y outputs - 3.3 - 4.1 ns
C inputs via H to X/Y outputs - 3.6 - 3.7 ns
C inputs via DIN through H to X/Y outputs - 3.6 - 4.5 ns

CLB Fast Carry Logic

T

OPCY

T

ASCY

T

INCY

T

SUM

T

BYP

Operand inputs (F1, F2, G1, G4) to C
Add/Subtract input (F3) to C
Initialization inputs (F1, F3) to C
CIN through function generators to X/Y outputs - 3.3 - 3.8 ns
C

IN

to C

, bypass function generators - 0.7 - 1.0 ns

OUT

Sequential Delays

T

CKO

Clock K to outputs Q - 2.8 - 3.7 ns

Setup Time before Clock K

T

ICK

T

IHCK

T

HH0CK

T

HH1CK

T

HH2CK

T

DICK

T

ECCK

T

RCK

T

CCK

T

CHCK

F/G inputs 3.0 - 4.0 - ns
F/G in puts via H 4.6 - 6.1 - ns
C inputs via H0 through H 3.6 - 4.5 - ns
C inputs via H1 through H 4.1 - 5.0 - ns
C inputs via H2 through H 3.8 - 4.8 - ns
C inputs via D

IN

C inputs via EC 3.0 - 4.0 - ns
C inputs via S/R, going Low (inactive) 4.0 - 4.2 - ns
CIN input via F/G 2.1 - 2.5 - ns
CIN input via F/G and H 3.5 - 4.2 - ns

OUT

OUT

OUT

UnitsMin Max Min Max

-2.6-3.2ns

-4.4-5.5ns

-1.7-1.7ns

2.4 - 3.0 - ns

DS021 (v2.2) June 25, 2000 www.xilinx.com 7

Product Specification 1-800-255-7778

QPRO XQ4000E/EX QML High-Reliability FPGAs

XQ4000E CLB Switching Characteristic Guidelines (continued)

R

Symbol

Description

Hold Time after Clock K

T

CKI

T

CKIH

T

CKHH0

T

CKHH1

T

CKHH2

T

CKDI

T

CKEC

T

CKR

F/G inputs 0 - 0 - n s
F/G inputs vi a H 0 - 0 - n s
C inputs via H0 through H 0 - 0 - ns
C inputs via H1 through H 0 - 0 - ns
C inputs via H2 through H 0 - 0 - ns
C inputs via DIN/H2 0 - 0 - ns
C inputs via EC 0 - 0 - ns
C inputs via SR, going Low (inactive) 0 - 0 - ns

Clock

T

CH

T

CL

Clock High time 4.0 - 4 .5 - ns
Clock Low time 4.0 - 4.5 - ns

Set/Reset Direct

T

RPW

T

RIO

Master Set/Reset

T

MRW

T

MRQ

T

MRK

F

TOG

Notes:

1. Timing is based on the XC4005E. For other devices see the static timing analyzer.

2. Export Control Max. flip-flop toggle rate.

Width (High) 4.0 - 5.5 - ns
Delay from C inputs via S/R, going High to Q - 4.0 - 6.5 ns

(1)

Width (High or Low) 11.5 - 13.0 - ns
Delay from Global Set/Reset net to Q - 18.7 - 23.0 ns
Global Set/Reset inactive to first active clock K edge - 18.7 - 23.0 ns
Toggle Frequency

(2)

- 125 - 111 MHz

-3 -4
UnitsMin Max Min Max

8 www.xilinx.com DS021 (v2.2) June 25, 2000

1-800-255-7778 Product Specification

R

QPRO XQ4000E/EX QML High-Reliability FPGAs

XQ4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported

by the static timing analyzer (TRCE in the Xilinx Develop­ment System) an d back-ann otated to th e simu lation n etlist.
All timing parameters ass ume worst-case operating con di­tions (supply voltage and junction temperature). Values
apply to all XQ4000E/EX devices unless otherwise noted.

Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics

-3 -4

Symbol Write Operation Description Size

T

WCS

T

WCTS

T

WPS

T

WPTS

T

ASS

T

ASTS

T

AHS

T

AHTS

T

DSS

T

DSTS

T

DHS

T

DHTS

T

WSS

T

WSTS

T

WHS

T

WHTS

T

WOS

T

WOTS

Notes:

1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.

2. Applicable Read timin g speci fications are identi cal to Level-Sensitiv e Read timing.

Address write cycle time (clock K period) 16x2 14.4 - 15.0 - ns

32x1 14.4 - 15.0 - ns

Clock K pulse width (active edge) 16x2 7.2 1 ms 7.5 1 ms ns

32x1 7.2 1 ms 7 .5 1 ms ns

Address setup time before clock K 16x2 2.4 - 2.8 - ns

32x1 2. 4 - 2 .8 - ns

Address hold time after clock K 16x2 0 - 0 - ns

32x1 0 - 0 - ns

DIN setup time before clock K 16x2 3.2 - 3.5 - ns

32x1 1. 9 - 2 .5 - ns

D

hold time after clock K 16x 2 0 - 0 - ns

IN

32x1 0 - 0 - ns

WE setup time before clock K 16x2 2. 0 - 2.2 - ns

32x1 2. 0 - 2 .2 - ns

WE hold time after clock K 16x2 0 - 0 - ns

32x1 0 - 0 - ns

Data valid after clock K 16x2 8.8 - - 10.3 ns

32x1 10.3 - - 11.6 ns

UnitsMin Max Min Max

Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics

-3 -4

Symbol Write Operation Description Size

T

WCDS

T

WPDS

T

ASDS

T

AHDS

T

DSDS

T

DHDS

T

WSDS

T

WHDS

T

WODS

Notes:

1. Applicable Read timin g speci fications are identi cal to Level-Sensitiv e Read timing.

DS021 (v2.2) June 25, 2000 www.xilinx.com 9
Product Specification 1-800-255-7778

Address write cycle time (clock K period) 16x1 14.4 15.0 n s
Clock K pulse width (active edge) 16x1 7.2 1 ms 7.5 1 ms ns
Address setup time before clock K 16x1 2.5 - 2.8 - ns
Address hold time after clock K 16x1 0 - 0 - ns
DIN setup time before clock K 16x1 2. 5 - 2.2 - ns
DIN hold time after clock K 16x1 0 - 0 - ns
WE setup time before clock K 16x1 1.8 - 2.2 - ns
WE hold time after clock K 16x1 0 - 0.3 - ns
Data valid after clock K 16x1 - 7.8 - 10.0 ns

(1)

UnitsMin Max Min Max

QPRO XQ4000E/EX QML High-Reliability FPGAs

XQ4000E CLB RAM Synchronous (Edge-Triggered) Write Timing Waveform

T

WPS

WCLK (K)

R

T

WSS

T

WHS

WE

T

DSS

T

DHS

DATA IN

T

ASS

T

AHS

ADDRESS

T

ILO

DATA OUT

T

ILO

T

WOS

OLD NEW

DS021_01_060100

XQ4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveform

T

WPDS

WCLK (K)

WE

DATA IN

ADDRESS

DATA OUT

T

WSS

T

DSDS

T

ASDS

T

ILO

T

WODS

OLD NEW

T

WHS

T

DHDS

T

AHDS

DS021_02_060100

T

ILO

10 www.xilinx.com DS021 (v2.2) June 25, 2000

1-800-255-7778 Product Specification

R

QPRO XQ4000E/EX QML High-Reliability FPGAs

XQ4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported

by the static timing analyzer (TRCE in the Xilinx Develop­ment System) an d back-ann otated to th e simu lation n etlist.
All timing parameters ass ume worst-case operating con di­tions (supply voltage and junction temperature). Values
apply to all XQ4000E devices unless otherwise noted.

-3 -4

Symbol Single Port RAM Size

Write Operation

T

T

T

T

T

T

T

T

T

T

T

T

WC

WCT

WP

WPT

AS

AST

AH

AHT

DS

DST

DH

DHT

Address write cycle time 16x2 8.0 - 8.0 - ns

32x1 8. 0 - 8 .0 - ns

Write Enable pulse width (High) 16x2 4.0 - 4.0 - ns

32x1 4. 0 - 4 .0 - ns

Address setup time before WE 16x2 2.0 - 2.0 - ns

32x1 2. 0 - 2 .0 - ns

Address hold time after end of WE 16x2 2.0 - 2.5 - ns

32x1 2. 0 - 2 .0 - ns

DIN setup time before end of WE 16x2 2. 2 - 4.0 - ns

32x1 2. 2 - 5 .0 - ns

DIN hold time after end of WE 16x2 2.0 - 2.0 - ns

32x1 2. 0 - 2 .0 - ns

Read Operation

T

T

T

T

RC

RCT

ILO
IHO

Address read cycle time 16x2 3.1 - 4.5 - ns

32x1 5. 5 - 6 .5 - ns

Data valid after address change (no Write Enable) 16x2 - 1.8 - 2.7 ns

32x1 - 3.2 - 4.7 ns

Read Operation, Clocking Data into Flip-Flop

T

T

IHCK

ICK

Address setup time before clock K 16x2 3.0 - 4.0 - ns

32x1 4. 6 - 6 .1 - ns

Read During Write

UnitsMin Max Min Max

T

T

T

T

WO

WOT

DO

DOT

Data valid after WE goes active (DIN stable before WE) 16x2 - 6.0 - 10.0 ns

32x1 - 7.3 - 12.0 ns

Data valid after DIN (DIN changes during WE) 16x2 - 6.6 - 9.0 ns

32x1 - 7.6 - 11.0 ns

Read During Write, Clocking Data into Flip-Flop

T

WCK

T

WCKT

T

DCK

T

DOCK

Notes:

1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.

DS021 (v2.2) June 25, 2000 www.xilinx.com 11
Product Specification 1-800-255-7778

WE setup time before clock K 16x2 6. 0 - 8.0 - ns

32x1 6. 8 - 9 .6 - ns

Data setup time before clock K 16x2 5.2 - 7.0 - ns

32x1 6. 2 - 8 .0 - ns