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DS021 (v2.2) June 25, 2000
02
Product Features
• Certified to MIL-PRF-38535, appendix A QML
(Qualified Manufacturers Listing)
• Also available under the fol lo wing Standard Microcircuit
Drawings (SMD)
- XC4005E 5962-97522
- XC4010E 5962-97523
- XC4013E 5962-97524
- XC4025E 5962-97525
- XC4028EX 5962-98509
• For more information contact the Defense Supply
Center Columbus (DSCC)
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
• System featured Field-Programmable Gate Arrays
TM
- Select-RAM
· Synchronous write option
· Dual-port RAM option
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
• System Performance beyond 60 MHz
• Flexible Array Archit ec tur e
• Low Power Segmented Routing Architecture
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XQ4000E/EX output
memory: on-chip ultra-fast RAM with
QPRO XQ4000E/EX
QML High-Reliability FPGAs
Produc t S pecif i catio n
• Configured by Loading Binary Fi le
- Unlimited reprogrammability
• Readback Capability
- Program verification
- Inter nal node observability
• Backward Compatible with XC4000 Devices
• Development System runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping , placement and ro uting
- Interactive design editor for design optimization
• Available Speed Grades:
- XQ4000E -3 for plastic packages only
- -4 for ceramic packages only
- XQ4028EX -4 for all packages
More Information
For more information refer to Xilinx XC4000E and XC4000X
series Field Programmable Gate A rrays product specification. This data sheet contains pinout tables for XQ4010E
only. Refer to Xilinx web site for pinout tables for other
devices. (Pinouts for XQ4000E/EX are identical to
XC4000E/EX.)
(http://www.xilinx.com/partinfo/databook.htm
)
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS021 (v2.2) June 25, 2000 www.xilinx.com 1
Product Specification 1-800-255-7778
QPRO XQ4000E/EX QML High-Reliability FPGAs
Table 1: XQ4000E/EX Field Prog r ammable Gate Arra y s
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Device
Max.
Logic
Gates
(No RAM)
Max.
RAM Bits
(No
Logic)
Typical
Gate Range
(Logic and
(1)
RAM)
CLB
Matrix
Total
CLBs
Number
of
Flip-Flops
Max.
Decode
Inputs
per Side
Max.
User
I/O Packages
XQ4005E 5,000 6,272 3,000 - 9,000 14 x 14 196 616 42 112 PG156,
CB164
XQ4010E 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 60 160 PG191,
CB196,
HQ208
XQ4013E 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 72 192 PG223,
CB228,
HQ240
XQ4025E 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 96 256 PG299,
CB228
XQ4028EX 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 96 256 PG299,
CB228,
HQ240,
BG352
Notes:
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
XQ4000E Switching Characteristics
XQ4000E Absolute Maximum Ratings
(1)
Symbol Description Units
V
T
T
V
V
STG
SOL
T
CC
IN
TS
J
Supply voltage relative to GND –0.5 to +7.0 V
Input voltage relative to GND
Voltage applied to High-Z output
(2)
(2)
–0.5 to VCC + 0.5 V
–0.5 to VCC + 0.5 V
Storage temperature (ambient) –65 to +150 °C
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
Junction temperature Ceramic package +150 °C
Plastic package +125 °C
Notes:
1. Stresses beyond t hose listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings onl y, and functional operat ion of the device at these or any other condition s beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affec t device reliab il ity.
2. Maximum DC excursion a bove V
transitions, the device pins may undershoot to –2.0V or overshoot to V
10 ns and with the forcing current being limited to 200 mA.
or below Ground must be limit ed to ei ther 0.5V or 10 mA, whi chever is easier to achiev e. During
CC
+ 2.0V, provided this over or undershoot lasts less than
CC
2 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
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QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E Recommended Operating Conditions
(1,2)
Symbol Description Min Max Units
V
CC
V
IH
Supply voltage relative to GND, TJ = –55°C to +125°CPlastic 4.5 5.5 V
Supply voltage relative to GND, T
High-Level Input Voltage TTL inputs 2.0 V
= –55°C to +125°C Ceramic 4.5 5.5 V
C
CC
CMOS inputs 70% 100% V
V
IL
Low-Level Input Voltage TTL inputs 0 0.8 V
CMOS inputs 0 20% V
T
IN
Notes:
1. At junction temperatures above those listed as Operating Condi tions, all delay parameter s increase by 0.35% per °C.
2. Input and output measurement thr eshold are 1.5V for TTL and 2.5V for CMOS.
Input signal transition time - 250 ns
XQ4000E DC Characteristics Over Recommended Operating Conditions
Symbol Description Min Max Units
V
OH
V
OL
I
CCO
I
L
C
IN
I
RIN
I
RLL
Notes:
1. With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
2. With no output cu rrent loads , no a ctiv e in put or Longli ne pul l-up resist or s, a ll pa c kage pi ns a t V
with the dev elopment system Tie opti on.
3. Characterized Only.
High-level output voltage @ IOH = –4.0 mA, VCC min TTL outputs 2.4 - V
High-level output voltage @ I
Low-lev el output voltage @ IOL = 12.0 mA, VCC min
= –1.0 mA, VCC min CMOS outputs VCC – 0.5 - V
OH
(1)
TTL outputs - 0.4 V
CMOS outputs - 0.4 V
Quiescent FPGA supply current
(2)
-50mA
Input or output leakage current –10 +10 µA
Input capacitance (sample tested) - 16 pF
(3)
(3)
–0.02 –0.25 mA
0.2 2.5 mA
or GND, and the FPGA configured
CC
Pad pull-up (when selected) at VIN = 0V (sample tested)
Horizontal longline pull-up (when selected) at logic Low
V
CC
CC
DS021 (v2.2) June 25, 2000 www.xilinx.com 3
Product Specification 1-800-255-7778
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E Switching Characteristic Guidelines
R
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values where one global clock input
drives one vertical clock line in each acc essible column, and
where all accessible IOB and CLB flip-flops are c locked by
the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are
driven from the same global c lock, the delay is longer. For
data, reflecting the actual routing str ucture, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
Note: -3 Speed Grade only applies to XQ4010E and
XQ4013E Plastic Package options only. -4 Speed Grade
applies to all XQ devices and is only available in
Ceramic Packages only.
more specific, more precise, and worst-case guaranteed
XQ4000E Global Buffer Switching Characteristics
Symbol Description Device
T
PG
T
SG
From pad through primary buffer, to any clock K XQ4005E - 7.0 ns
XQ4010E 6.3 11.0 ns
XQ4013E 6.8 11.5 ns
XQ4025E - 12.5 ns
From pad through secondary buffer, to any clock K XQ4005E - 7.5 ns
XQ4010E 6.8 11.5 ns
-3
(1)
-4
(2)
UnitsMax Max
Notes:
1. For plastic package options only.
2. For ceramic package options only.
XQ4013E 7.3 12.0 ns
XQ4025E - 13.0 ns
4 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
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QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static timing analyzer (TRCE i n the X ilinx Development System) and back-annotat ed to t he simulation net list.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (supply voltage and junction tempe rature). Values apply to all
XQ4000E devices unless otherwise noted.
The following guidelines reflect worst-case values over the
recommended operating conditions.
-3 -4
Symbol Description Device
TBUF Driving a Horizontal Longline (LL):
T
IO1
I going High or Low to LL going High or Low, while T is Low.
Buffer is constantly active.
(1)
XQ4005E - 5.0 ns
XQ4010E 6.4 8.0 ns
XQ4013E 7.2 9.0 ns
XQ4025E - 11.0 ns
T
IO2
I going Low to LL going from resistive pull-up High to active Low.
TBUF configured as open-drain.
(1)
XQ4005E - 6.0 ns
XQ4010E 6.9 10.5 ns
XQ4013E 7.7 11.0 ns
XQ4025E - 12.0 ns
T
ON
T going Low to LL going from resistive pull-up or floating High to
active Low. TBUF configured as open-drain or active buf fer with
I=Low.
(1)
XQ4005E - 7.0 ns
XQ4010E 7.3 8.5 ns
XQ4013E 7.5 8.7 ns
XQ4025E - 11.0 ns
T
OFF
T going High to TBUF going inactive, not driving LL. XQ4005E - 1.8 ns
XQ4010E 1.5 1.8 ns
XQ4013E 1.5 1.8 ns
XQ4025E - 1.8 ns
UnitsMax Max
T
PUS
T going High to LL going from Low to High, pulled up by a single
resistor.
(1)
XQ4005E - 23.0 ns
XQ4010E 22.0 29.0 ns
XQ4013E 26.0 32.0 ns
XQ4025E - 42.0 ns
T
PUF
T going High to LL going from Low to High, pulled up by two
resistors.
(1)
XQ4005E - 10.0 ns
XQ4010E 11.0 13.5 ns
XQ4013E 13.0 15.0 ns
XQ4025E - 18.0 ns
Notes:
1. These values include a minimum load. Use the stati c ti m ing analyzer to determine the del ay for each destination.
DS021 (v2.2) June 25, 2000 www.xilinx.com 5
Product Specification 1-800-255-7778
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static timing analyzer (TRCE i n the X ilinx Development System) and back-annotat ed to t he simulation net list.
Symbol Description
(1,2)
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (supply voltage and junction tempe rature). Values apply to all
XQ4000E devices unless otherwise noted.
The following guidelines reflect worst-case values over the
recommended operating conditions.
Device
R
-3 -4
UnitsMax Max
T
WAF
Full length, both pull-ups, inputs from IOB I-pins XQ4005E - 9.5 ns
XQ4010E 9.0 15.0 ns
XQ4013E 11.0 16.0 ns
XQ4025E - 18.0 ns
T
WAFL
Full length, both pull-ups, inputs from internal logic XQ4005E - 12.5 ns
XQ4010E 11.0 18.0 ns
XQ4013E 13.0 19.0 ns
XQ4025E - 21.0 ns
T
WAO
Half length, one pull-up, inputs from IOB I-pins XQ4005E - 10.5 ns
XQ4010E 10.0 16.0 ns
XQ4013E 12.0 17.0 ns
XQ4025E - 19.0 ns
T
WAOL
Half length, one pull-up, inputs from internal logic XQ4005E - 12.5 ns
XQ4010E 12.0 18.0 ns
XQ4013E 14.0 19.0 ns
XQ4025E - 21.0 ns
Notes:
1. These delays are specified from the decoder input to the decoder output.
2. Fewer than t he specified numbe r of pull-up resist ors can be used, if desired. Using fewer pull-ups reduces powe r consumption but
increases delays. Use the static timing analyzer to determine delays if few er pull-ups are used.
6 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
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XQ4000E CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static ti ming analyzer (TR CE in the Xilinx Development System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (supply voltage and junction tempe rature). Values apply to all
XQ4000E devices unless otherwise noted.
QPRO XQ4000E/EX QML High-Reliability FPGAs
-3 -4
Symbol Description
Combinatorial Delays
T
T
T
HH0O
T
HH1O
T
HH2O
ILO
IHO
F/G inputs to X/Y outputs - 2.01 - 2.7 ns
F/G inputs via H to X/Y outputs - 4.3 - 4.7 ns
C inputs via SR through H to X/Y outputs - 3.3 - 4.1 ns
C inputs via H to X/Y outputs - 3.6 - 3.7 ns
C inputs via DIN through H to X/Y outputs - 3.6 - 4.5 ns
CLB Fast Carry Logic
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
Operand inputs (F1, F2, G1, G4) to C
Add/Subtract input (F3) to C
Initialization inputs (F1, F3) to C
CIN through function generators to X/Y outputs - 3.3 - 3.8 ns
C
IN
to C
, bypass function generators - 0.7 - 1.0 ns
OUT
Sequential Delays
T
CKO
Clock K to outputs Q - 2.8 - 3.7 ns
Setup Time before Clock K
T
ICK
T
IHCK
T
HH0CK
T
HH1CK
T
HH2CK
T
DICK
T
ECCK
T
RCK
T
CCK
T
CHCK
F/G inputs 3.0 - 4.0 - ns
F/G in puts via H 4.6 - 6.1 - ns
C inputs via H0 through H 3.6 - 4.5 - ns
C inputs via H1 through H 4.1 - 5.0 - ns
C inputs via H2 through H 3.8 - 4.8 - ns
C inputs via D
IN
C inputs via EC 3.0 - 4.0 - ns
C inputs via S/R, going Low (inactive) 4.0 - 4.2 - ns
CIN input via F/G 2.1 - 2.5 - ns
CIN input via F/G and H 3.5 - 4.2 - ns
OUT
OUT
OUT
UnitsMin Max Min Max
-2.6-3.2ns
-4.4-5.5ns
-1.7-1.7ns
2.4 - 3.0 - ns
DS021 (v2.2) June 25, 2000 www.xilinx.com 7
Product Specification 1-800-255-7778
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E CLB Switching Characteristic Guidelines (continued)
R
Symbol
Description
Hold Time after Clock K
T
CKI
T
CKIH
T
CKHH0
T
CKHH1
T
CKHH2
T
CKDI
T
CKEC
T
CKR
F/G inputs 0 - 0 - n s
F/G inputs vi a H 0 - 0 - n s
C inputs via H0 through H 0 - 0 - ns
C inputs via H1 through H 0 - 0 - ns
C inputs via H2 through H 0 - 0 - ns
C inputs via DIN/H2 0 - 0 - ns
C inputs via EC 0 - 0 - ns
C inputs via SR, going Low (inactive) 0 - 0 - ns
Clock
T
CH
T
CL
Clock High time 4.0 - 4 .5 - ns
Clock Low time 4.0 - 4.5 - ns
Set/Reset Direct
T
RPW
T
RIO
Master Set/Reset
T
MRW
T
MRQ
T
MRK
F
TOG
Notes:
1. Timing is based on the XC4005E. For other devices see the static timing analyzer.
2. Export Control Max. flip-flop toggle rate.
Width (High) 4.0 - 5.5 - ns
Delay from C inputs via S/R, going High to Q - 4.0 - 6.5 ns
(1)
Width (High or Low) 11.5 - 13.0 - ns
Delay from Global Set/Reset net to Q - 18.7 - 23.0 ns
Global Set/Reset inactive to first active clock K edge - 18.7 - 23.0 ns
Toggle Frequency
(2)
- 125 - 111 MHz
-3 -4
UnitsMin Max Min Max
8 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static timing analyzer (TRCE in the Xilinx Development System) an d back-ann otated to th e simu lation n etlist.
All timing parameters ass ume worst-case operating con ditions (supply voltage and junction temperature). Values
apply to all XQ4000E/EX devices unless otherwise noted.
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-3 -4
Symbol Write Operation Description Size
T
WCS
T
WCTS
T
WPS
T
WPTS
T
ASS
T
ASTS
T
AHS
T
AHTS
T
DSS
T
DSTS
T
DHS
T
DHTS
T
WSS
T
WSTS
T
WHS
T
WHTS
T
WOS
T
WOTS
Notes:
1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
2. Applicable Read timin g speci fications are identi cal to Level-Sensitiv e Read timing.
Address write cycle time (clock K period) 16x2 14.4 - 15.0 - ns
32x1 14.4 - 15.0 - ns
Clock K pulse width (active edge) 16x2 7.2 1 ms 7.5 1 ms ns
32x1 7.2 1 ms 7 .5 1 ms ns
Address setup time before clock K 16x2 2.4 - 2.8 - ns
32x1 2. 4 - 2 .8 - ns
Address hold time after clock K 16x2 0 - 0 - ns
32x1 0 - 0 - ns
DIN setup time before clock K 16x2 3.2 - 3.5 - ns
32x1 1. 9 - 2 .5 - ns
D
hold time after clock K 16x 2 0 - 0 - ns
IN
32x1 0 - 0 - ns
WE setup time before clock K 16x2 2. 0 - 2.2 - ns
32x1 2. 0 - 2 .2 - ns
WE hold time after clock K 16x2 0 - 0 - ns
32x1 0 - 0 - ns
Data valid after clock K 16x2 8.8 - - 10.3 ns
32x1 10.3 - - 11.6 ns
UnitsMin Max Min Max
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-3 -4
Symbol Write Operation Description Size
T
WCDS
T
WPDS
T
ASDS
T
AHDS
T
DSDS
T
DHDS
T
WSDS
T
WHDS
T
WODS
Notes:
1. Applicable Read timin g speci fications are identi cal to Level-Sensitiv e Read timing.
DS021 (v2.2) June 25, 2000 www.xilinx.com 9
Product Specification 1-800-255-7778
Address write cycle time (clock K period) 16x1 14.4 15.0 n s
Clock K pulse width (active edge) 16x1 7.2 1 ms 7.5 1 ms ns
Address setup time before clock K 16x1 2.5 - 2.8 - ns
Address hold time after clock K 16x1 0 - 0 - ns
DIN setup time before clock K 16x1 2. 5 - 2.2 - ns
DIN hold time after clock K 16x1 0 - 0 - ns
WE setup time before clock K 16x1 1.8 - 2.2 - ns
WE hold time after clock K 16x1 0 - 0.3 - ns
Data valid after clock K 16x1 - 7.8 - 10.0 ns
(1)
UnitsMin Max Min Max
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E CLB RAM Synchronous (Edge-Triggered) Write Timing Waveform
T
WPS
WCLK (K)
R
T
WSS
T
WHS
WE
T
DSS
T
DHS
DATA IN
T
ASS
T
AHS
ADDRESS
T
ILO
DATA OUT
T
ILO
T
WOS
OLD NEW
DS021_01_060100
XQ4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveform
T
WPDS
WCLK (K)
WE
DATA IN
ADDRESS
DATA OUT
T
WSS
T
DSDS
T
ASDS
T
ILO
T
WODS
OLD NEW
T
WHS
T
DHDS
T
AHDS
DS021_02_060100
T
ILO
10 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static timing analyzer (TRCE in the Xilinx Development System) an d back-ann otated to th e simu lation n etlist.
All timing parameters ass ume worst-case operating con ditions (supply voltage and junction temperature). Values
apply to all XQ4000E devices unless otherwise noted.
-3 -4
Symbol Single Port RAM Size
Write Operation
T
T
T
T
T
T
T
T
T
T
T
T
WC
WCT
WP
WPT
AS
AST
AH
AHT
DS
DST
DH
DHT
Address write cycle time 16x2 8.0 - 8.0 - ns
32x1 8. 0 - 8 .0 - ns
Write Enable pulse width (High) 16x2 4.0 - 4.0 - ns
32x1 4. 0 - 4 .0 - ns
Address setup time before WE 16x2 2.0 - 2.0 - ns
32x1 2. 0 - 2 .0 - ns
Address hold time after end of WE 16x2 2.0 - 2.5 - ns
32x1 2. 0 - 2 .0 - ns
DIN setup time before end of WE 16x2 2. 2 - 4.0 - ns
32x1 2. 2 - 5 .0 - ns
DIN hold time after end of WE 16x2 2.0 - 2.0 - ns
32x1 2. 0 - 2 .0 - ns
Read Operation
T
T
T
T
RC
RCT
ILO
IHO
Address read cycle time 16x2 3.1 - 4.5 - ns
32x1 5. 5 - 6 .5 - ns
Data valid after address change (no Write Enable) 16x2 - 1.8 - 2.7 ns
32x1 - 3.2 - 4.7 ns
Read Operation, Clocking Data into Flip-Flop
T
T
IHCK
ICK
Address setup time before clock K 16x2 3.0 - 4.0 - ns
32x1 4. 6 - 6 .1 - ns
Read During Write
UnitsMin Max Min Max
T
T
T
T
WO
WOT
DO
DOT
Data valid after WE goes active (DIN stable before WE) 16x2 - 6.0 - 10.0 ns
32x1 - 7.3 - 12.0 ns
Data valid after DIN (DIN changes during WE) 16x2 - 6.6 - 9.0 ns
32x1 - 7.6 - 11.0 ns
Read During Write, Clocking Data into Flip-Flop
T
WCK
T
WCKT
T
DCK
T
DOCK
Notes:
1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
DS021 (v2.2) June 25, 2000 www.xilinx.com 11
Product Specification 1-800-255-7778
WE setup time before clock K 16x2 6. 0 - 8.0 - ns
32x1 6. 8 - 9 .6 - ns
Data setup time before clock K 16x2 5.2 - 7.0 - ns
32x1 6. 2 - 8 .0 - ns
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E CLB Level-Sensitive RAM Timing Characteristics
R
WRITE
ADDRESS
T
AS
WE
DATA IN
READ WITHOUT WRITE
T
X,Y OUTPUTS
VALID
READ, CLOCKING DATA INTO FLIP-FLOP
CLOCK
XQ,YQ OUTPUTS
READ DURING WRITE
WRITE ENABLE
ILO
T
WC
T
WP
T
DS
REQUIRED
VALID
T
ICK
T
CH
T
CKO
T
WP
T
AH
T
DH
VALID (NEW)VALID (OLD)
(stable during WE)
DATA IN
T
WO
X,Y OUTPUTS
DATA IN
(changing during WE)
X,Y OUTPUTS
VALID
OLD NEW
T
WO
VALID
(PREVIOUS)
VALID
(OLD)
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
WRITE ENABLE
T
WCK
DATA IN
CLOCK
XQ,YQ OUTPUTS
T
DCK
T
DH
VALID
T
DO
VALID
(NEW)
T
WP
T
CKO
DS021_03_060100
12 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and inter nal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and nor mal
clock loading. For more specific, more precise, and
Symbol Description D evice -3 -4 Units
T
ICKOF
Global clock to output (fast) using OFF XQ4005E - 14.0 ns
(Max)
T
T
ICKO
PG
Global Clock-to-Output Delay
Global clock to output (slew-limited) using OFF XQ4005E - 18.0 ns
OFF
DS021_04_060100
(Max)
T
PG
Global Clock-to-Output Delay
OFF
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values apply to all XQ4000E devices
unless otherwise noted.
XQ4010E 10.9 16.0 ns
XQ4013E 11.0 16.5 ns
XQ4025E - 17.0 ns
XQ4010E 14.9 20.0 ns
XQ4013E 15.0 20.5 ns
XQ4025E - 21.0 ns
T
PSUF
(Min)
T
PHF
(Min)
T
PSU
(Min)
T
PH
(Min)
DS021_04_060100
Input setup time, using IFF (no delay) XQ4005E - 2.0 ns
XQ4010E 0.2 1.0 ns
XQ4013E 0 0.5 ns
XQ4025E - 0 ns
Input
Setup
and Hold
Time
D
T
PG
IFF
DS021_05_060100
Input hold time, using IFF (no delay) XQ4005E - 4.6 ns
XQ4010E 5.5 6.0 ns
XQ4013E 6.5 7.0 ns
XQ4025E - 8.0 ns
Input
Setup
and Hold
Time
D
T
PG
IFF
DS021_05_060100
Input setup time, using IFF (with delay) XQ4005E - 8.5 ns
XQ4010E 7.0 8.5 ns
XQ4013E 7.0 8.5 ns
XQ4025E - 9.5 ns
Input
Setup
and Hold
Time
D
T
PG
IFF
DS021_05_060100
Input hold time, using IFF (with delay) XQ4005E - 0 ns
XQ4010E 0 0 ns
XQ4013E 0 0 ns
XQ4025E - 0 ns
Input
Setup
and Hold
Time
D
T
PG
IFF
DS021_05_060100
Notes:
1. OFF = Output Flip-Flop
2. IFF = Input Flip-Flop or Latch
DS021 (v2.2) June 25, 2000 www.xilinx.com 13
Product Specification 1-800-255-7778
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and inter nal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and nor mal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values apply to all XQ4000E devices
unless otherwise noted.
R
-3 -4
Symbol Description Device
Propagation Delays (TTL Inputs)
T
T
T
PID
PLI
PDLI
Pad to I1, I2 All devices - 2. 5 - 3.0 ns
Pad to I1, I2 via transparent input latch, no delay A ll devices - 3.6 - 4.8 ns
Pad to I1, I2 via transparent FCL and input latch,
with delay
(1)
XQ4005E - - - 10.8 ns
XQ4010E - 10.8 - 11.0 ns
UnitsMin Max Min Max
XQ4013E - 11.2 - 11.4 ns
XQ4025E - - - 13.8 ns
Propagation Delays (CMOS Inputs)
T
PIDC
T
PLIC
T
PDLIC
Pad to I1, I2 All devices - 4. 1 - 5.5 ns
Pad to I1, I2 via transparent input latch, no delay A ll devices - 8.8 - 6.8 ns
Pad to I1, I2 via transparent FCL and input latch,
with delay
(1)
XQ4005E - - - 16.5 ns
XQ4010E - 14.0 - 17.5 ns
XQ4013E - 14.4 - 18.0 ns
XQ4025E - - - 20.8 ns
Propagation Delays (TTL Inputs)
T
IKRI
T
IKLI
Hold Times
T
IKPI
T
IKPID
T
IKEC
T
IKECD
Notes:
1. Input pad setup and hold ti mes are speci fie d with re spec t to the int ernal cloc k (I K). F or set up and ho ld times with respect to the clock
input pin, see the pin- to-pin parameters in the Guaranteed Inpu t and Output Par am eters table.
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resi stor , or configured as a driven output, or can be driven from an external source.
Clock (IK) to I1, I2 (flip-flop) All devices - 2.8 - 5.6 ns
Clock (IK) to I1, I2 (latch enable, active Low) All devices - 4.0 - 6.2 ns
(2)
Pad to clock (IK), no delay All devices 0 - 0 - ns
Pad to clock (I K), with delay All devices 0 - 0 - ns
Clock enable (EC) to clock (K), no delay All devices 1.5 - 1.5 - ns
Clock enable (EC) to clock (K), with delay All devi ces 0 - 0 - ns
14 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E IOB Input Switching Characteristic Guidelines (continued)
-3 -4
Symbol Description Device
Setup Times (TTL Inputs)
T
PICK
T
PICKD
Pad to clock (IK), no delay All devices 2.6 - 4.0 - ns
Pad to clock (IK), with delay XQ4005E - - 10.9 - ns
(1,2)
XQ4010E 9.8 - 11.3 - ns
XQ4013E 10.2 - 11.8 - ns
XQ4025E - - 14.0 - ns
Setup Times (CMOS Inputs)
T
PICKC
T
PICKDC
Pad to clock (IK), no delay All devices 3.3 - 6.0 - ns
Pad to clock (IK), with delay XQ4005E - - 12.0 - ns
(1,2)
XQ4010E 10.5 - 13.0 - ns
XQ4013E 10.9 - 13.5 - ns
XQ4025E - - 16.0 - ns
(TTL or CMOS)
T
ECIK
T
ECIKD
Clock enable (EC) to clock (IK), no delay All devices 2.5 - 3.5 - ns
Clock enable (EC) to clock (IK), with delay XQ4005E - - 10.4 - ns
XQ4010E 9.7 - 10.7 - ns
XQ4013E 10.1 - 11.1 - ns
UnitsMinMaxMinMax
XQ4025E - - 14.0 - ns
Global Set/Reset
T
RRI
T
MRW
T
MRI
Notes:
1. Input pad setup and hold times ar e sp ecified with r esp ect to the i nternal cloc k (IK). Fo r setup an d hol d ti mes with respe ct to the cl ock
input pin, see the pin- to-pin parameters in the Guaranteed Inpu t and Output Par am eters table.
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resi stor , or configured as a driven output, or can be driven from an external source.
3. Timing is based on the XC4005E. For other devices see the XACT timing calculator.
(3)
Delay from GSR net through Q to I1, I2 All devices - 7.8 - 12.0 ns
GSR width All devices 11.5 - 13.0 - ns
GSR inactive to first active clock (IK) edge All devices 11.5 - 13.0 - ns
DS021 (v2.2) June 25, 2000 www.xilinx.com 15
Product Specification 1-800-255-7778
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static ti ming analyzer (TR CE in the Xilinx Develop-
Symbol Descri ption
Propagation Delays (TTL Output Levels)
T
OKPOF
T
OKPOS
T
OPF
T
OPS
T
TSHZ
T
TSONF
T
TSONS
Clock (OK) to pad, fast - 6.5 - 7.5 ns
Clock (OK) to pad, slew-rate limited - 9.5 - 11.5 ns
Output (O) to pad, fast - 5.5 - 8.0 ns
Output (O) to pad, slew-rate limited - 8.6 - 12.0 ns
3-state to pad High-Z, slew-rate independent - 4.2 - 10 .0 ns
3-state to pad active and valid, fast - 8.1 - 10.0 ns
3-state to pad active and valid, slew-rate limited - 11.1 - 13.7 ns
Propagation Delays (CMOS Output Levels)
T
OKPOFC
T
OKPOSC
T
OPFC
T
OPSC
T
TSHZC
T
TSONFC
T
TSONSC
Clock (OK) to pad, fast - 7.8 - 9.5 ns
Clock (OK) to pad, slew-rate limited - 11. 6 - 13.5 ns
Output (O) to pad, fast - 9.7 - 10 .0 ns
Output (O) to pad, slew-rate limited - 13.4 - 14.0 ns
3-state to pad High-Z, slew-rate independent - 4.3 - 5.2 ns
3-state to pad active and valid, fast - 7.6 - 9.1 ns
3-state to pad active and valid, slew-rate limited - 11.4 - 13.1 ns
Setup and Hold Times
T
OOK
T
OKO
T
ECOK
T
OKEC
Output (O) to clock (OK) setup time 4. 6 - 5.0 - ns
Output (O) to clock (OK) hold time 0 - 0 - ns
Clock enable (EC) to clock (OK) setup 3.5 - 4.8 - ns
Clock enable (EC) to clock (OK) hold 1.2 - 1.2 - ns
Clock
T
CH
T
CL
Global Set/Reset
T
RRO
T
MRW
T
MRO
Notes:
1. Output timing is measured at pin thr eshold, with 50 pF external capaciti ve loads (incl. test fixture). Sle w-rate limited output rise/fall
times are appr o ximat ely t wo times lon ger th an f ast o utput rise/f al l ti mes. F or t he e ff ect of c apacit iv e l oads on g r ound bounce, se e the
“Additional XC4000 Data” section on the Xilinx web site, www.xilinx.com/partinfo/databook.htm
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resi stor , or configured as a driven output, or can be driven from an external source.
3. Timing is based on the XC4005E. For other devices see the XACT timing calculator.
Clock High 4.0 - 4.5 - ns
Clock Low 4.0 - 4.5 - ns
(3)
Delay from GSR net to pad - 11. 8 - 15.0 ns
GSR width 11.5 - 13.0 - ns
GSR inactive to first active clock (OK) edge 11.5 - 13.0 - ns
ment System) an d back-ann otated to th e simu lation n etlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values
apply to all XQ4000E devices unless otherwise noted.
-3 -4
UnitsMin Max Min Max
.
R
16 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are not
measured directly . They are derived from benchmark timing
patterns that are taken at device introduction, prior to any
process improvements. For more detailed, more precise,
and more up-to-date information, us e the values provided
These values can be printed in tabular format by running
LCA2XNF-S.
The following guidelines reflect worst-case values over the
recommended operating conditions. They are expressed in
units of nanoseconds and apply to all XC4000E devices
unless otherwise noted.
by the XACT timing calculator and used in the simulator.
-3 -4
UnitsSymbol Description Min Max Min Max
Setup Times
T
TDITCK
T
TMSTCK
Input (TDI) to clock (TCK) 30.0 30.0 ns
Input (TMS) to clock (TCK) 15.0 15.0 ns
Hold Times
T
TCKTDI
T
TCKTMS
Input (TDI) to clock (TCK) 0 0 ns
Input (TMS) to clock (TCK) 0 0 ns
Propagation Delay
T
TCKPO
Clock (TCK) to pad (TDO) 30.0 30.0 ns
Clock
T
TCKH
T
TCKL
F
MAX
Notes:
1. Input setup and hold times and clock-to-pad times are specified with respect to external signal pins.
2. Output timing is measured at pin thr eshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall
times are appr o ximat ely t wo times lon ger th an f ast o utput rise/f al l ti mes. F or t he e ff ect of c apacit iv e l oads on gr ound bounce, s ee the
“Additional XC4000 Data” secti on of the Programmab le Logic Data Book.
3. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resi stor , or configured as a driven output, or can be driven from an external source.
Clock (TCK) High 5.0 5.0 ns
Clock (TCK) Low 5.0 5.0 ns
Frequency 15.0 15.0 MHz
DS021 (v2.2) June 25, 2000 www.xilinx.com 17
Product Specification 1-800-255-7778
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX Swit chin g Chara cter ist ics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These ter ms are defined as
follows:
Advance: Initial estimates based on simulation and/or extrapolation from other spe ed grades, devices, or device families.
Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary character ization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the A.C. parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions.
All specifications subject to change without notice.
R
XQ4028EX Absolute Maximum Ratings
(1)
Symbol Description Units
V
V
T
T
V
V
CCt
STG
SOL
T
CC
IN
TS
J
Supply voltage relative to GND –0.5 to +7.0 V
Input voltage relative to GND
Voltage applied to High-Z output
(2)
(2)
–0.5 to VCC + 0.5 V
–0.5 to VCC + 0.5 V
Longest supply voltage rise time from 1V to 4V 50 ms
Storage temperature (ambient) –65 to +150 °C
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
Junction temperature Ceramic package +150 °C
Plastic package +125 °C
Notes:
1. Stresses beyond t hose listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings onl y, and functional operat ion of the device at these or any other condition s beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affec t device reliab il ity.
2. Maximum DC excursion above V
Maximum total com bined current on all dedicated inputs and Tri-state outputs must not exceed 200 mA. During transitions, the
device pins may undershoot to –2 .0V or ove rshoot toV
forcing current being limited to 200 mA.
or below Ground must be limited to either 0.5V or 10 mA, whic hever is easier to achieve.
CC
+2.0V, provided this over or undershoot lasts less than 10 ns and with the
CC
18 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX Recommended Operating Conditions
(1)
Symbol Descr iptiont Min Max Units
V
CC
V
IH
Supply voltage relative to GND, TJ = –55°C to +125°CPlastic 4.5 5.5 V
Supply voltage relative to GND, T
High-level input voltage
(2)
= –55°C to +125°C Ceramic 4.5 5.5 V
C
TTL inputs 2.0 V
CC
CMOS inputs 70% 100% V
V
Low-level input vol tage TTL inputs 0 0.8 V
IL
CMOS inputs 0 20% V
T
IN
Notes:
1. At junction temperatures above those listed as Operating Condi tions, all delay parameter s increase by 0.35% per °C.
2. Input and output measurement thr eshold are 1.5V for TTL and 2.5V for CMOS.
Input signal transition time - 250 ns
XQ4028EX DC Characteristics Over Recommended Operating Conditions
Symbol Description Min Max Units
V
OH
V
OL
High-level output voltage at IOH = –4 mA, VCC min TTL outputs 2.4 - V
High-level output voltage at I
Low-lev el output voltage at IOL = 12 mA, VCC min
= –1 mA CMOS outputs VCC – 0. 5 - V
OH
(1)
TTL outputs - 0.4 V
CMOS outputs - 0.4 V
V
CC
CC
V
I
CCO
C
DR
I
L
IN
Data retention supply voltage (below which configuration data may be lost) 3.0 - V
Quiescent FPGA supply current
(2)
Input or output leakage current –10 10 µA
Input capacitance (sample tested) Plastic packages - 10 V
Ceramic packages - 16 V
I
RPU
I
RPD
I
RLL
Notes:
1. With up to 64 pins simultaneously sinking 12 mA.
2. With no output current loads , no active input or Longl ine pull-up resi stors, all pac kage pins at V
Pad pull-up (when selected) at VIN = 0V (sample tested) 0.02 0.25 mA
Pad pull-down (when selected) at VIN = 5.5V (sample tested) 0.02 0.25 mA
Horizontal longline pull-up (when selected) at logic Low
(3)
-25mA
0.3 2.0 m A
or GND.
CC
DS021 (v2.2) June 25, 2000 www.xilinx.com 19
Product Specification 1-800-255-7778
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028E X Switchin g Chara ct erist ic Gu id elin es
R
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values where one global clock input
drives one vertical clock line in each acc essible column, and
where all accessible IOB and CLB flip-flops are c locked by
the global clock net.
When fewer vertical clock lines are connected, the clock dis-
driven from the same gl obal clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing str ucture, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature)
tribution is faster; when multiple clock lines per column are
Global Buffer Switching Characteristics.
Symbol Description
T
T
GLS
GE
From pad through Global Low Skew buffer, to any clock K 9.2 ns
From pad through Global Early buffer, to any clock K in same quadrant 5.7 ns
XQ4028EX Horizontal Longline Switching Characteristic Guidelines
Symbol Description
TBUF Driving a Horizontal Longline
T
IO1
I going High or Low to horizontal longline going High or Low, while T is Low. Buffer is
constan t ly active.
-4
UnitsMax
-4
UnitsMax
13.7 ns
T
ON
T going Low to horizontal longline going from resistive pull-up or floating High to active Low.
14.7 ns
TBUF configured as open-drain or active buffer with I = Low.
TBUF Driving Half a Horizontal Long line
T
HIO1
I going High or Low to half of a horizontal longline going High or Low, while T is Low. Buffer
6.3 ns
is constantly active.
T
HON
T going Low to half of a horizontal longline going from resistive pull-up or floating High to
7.2 ns
active Low. TBUF configured as open-drain or active buffer with I = Low.
Notes:
1. These values include a minimum load of one output, spaced as far as possible from the activated pull-up( s). Use the static timing
analyzer to det ermine t he delay f or each destination.
20 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
XQ4028EX CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation n etlist.
All timing parameters ass ume worst-case operating con ditions (supply voltage and junction temperature). Values
apply to all XQ4000EX devices unless otherwise noted.
CLB Switching Characteristics
Symbol
Combinatorial Delays
T
T
T
T
HH0O
T
HH1O
T
HH2O
T
CBYP
ILO
IHO
ITO
F/G inputs to X/Y outputs - 2.2 ns
F/G inputs v ia H ’ to X/Y outputs - 3.8 ns
F/G inputs via transparent latch to Q outputs - 3.2 ns
C inputs via SR/H0 via H to X/Y outputs - 3.6 ns
C inputs via H1 via H to X/Y outputs - 3.0 ns
C inputs via DIN/H2 via H to X/Y outputs - 3.6 ns
C inputs via EC, DIN/H2 to YQ, XQ output (bypass) - 2.0 ns
CLB Fast Carry Logic
T
OPCY
T
ASCY
T
T
T
T
INCY
SUM
BYP
NET
Operand inputs (F1, F2, G1, G4) to C
Add/Subtract input (F3) to C
Initializa t ion inputs ( F1, F3 ) to C
CIN through function generators to X/Y outputs - 3.0 ns
C
IN
Carry net selay, C
Sequential Delays
to C
, bypass function generators - 0.60 ns
OUT
OUT
Description
OUT
to C
IN
OUT
OUT
QPRO XQ4000E/EX QML High-Reliability FPGAs
-4
UnitsMin Max
-2.5ns
-4.1ns
-1.9ns
-0.18ns
T
T
CKLO
CKO
Clock K to flip-flop outputs Q - 2.2 ns
Clock K to latch outputs Q - 2.2 ns
Setup Time before Clock K
T
ICK
T
IHCK
T
HH0CK
T
HH1CK
T
HH2CK
T
DICK
T
ECCK
T
RCK
T
CCK
T
CHCK
F/G inputs 1.3 - ns
F/G inputs v i a H 3.0 - ns
C inputs via H0 through H 2.8 - ns
C inputs via H1 through H 2.2 - ns
C inputs via H2 through H 2.8 - ns
C inputs via DIN 1.2 - ns
C inputs via EC 1.2 - ns
C inputs via S/R, going Low (inactive) 0.8 - ns
CIN input via F/G 2.2 - ns
CIN input via F/G and H 3.9 - ns
Hold Time after Clock K
T
CKI
DS021 (v2.2) June 25, 2000 www.xilinx.com 21
Product Specification 1-800-255-7778
F/G inputs 0 - ns
QPRO XQ4000E/EX QML High-Reliability FPGAs
CLB Switching Characteristics (Continued)
Symbol
Description
R
-4
UnitsMin Max
T
CKIH
T
CKHH0
T
CKHH1
T
CKHH2
T
CKDI
T
CKEC
T
CKR
Clock
T
CH
T
CL
Set/Reset Direct
T
RPW
T
RIO
Global Set/Reset
T
MRW
T
MRQ
F
TOG
F/G inputs v ia H 0 - ns
C inputs via SR/H0 through H 0 - ns
C inputs via H1 through H 0 - ns
C inputs via DIN/H2 through H 0 - ns
C inputs via DIN/H2 0 - ns
C inputs via EC 0 - ns
C inputs via SR, going Low (inactive) 0 - ns
Clock High time 3.5 - ns
Clock Low time 3.5 - ns
Width (High) 3.5 - ns
Delay from C inputs via S/R, going High to Q - 4. 5 ns
Minimum GSR pulse width - 13.0 ns
Delay from GSR input to any Q - 22.8
Toggle frequency (MHz) (for export control) - 143 MHz
22 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
Symbol Single Port RAM Size
Write Operation
T
WCS
T
WCTS
T
WPS
T
WPTS
T
ASS
T
ASTS
T
AHS
T
AHTS
T
DSS
T
DSTS
T
DHS
T
DHTS
T
WSS
T
WSTS
T
WHS
T
WHTS
T
WOS
T
WOTS
Notes:
1. Applicable Read timin g speci fications are identi cal to Level-Sensitiv e Read timing.
Address write cycle time (clock K period) 16x2 11.0 - ns
Clock K pulse width (active edge) 16x2 5.5 - ns
Address setup time before clock K 16x2 2.7 - ns
Address hold time after clock K 16x2 0 - ns
DIN setup time before clock K 16x2 2.4 - ns
DIN hold time after clock K 16x2 0 - ns
WE setup time before clock K 16x2 2.3 - ns
WE hold time after clock K 16x2 0 - ns
Data valid after clock K 16x2 - 8.2 ns
by the static timing analyzer (TRCE in the Xilinx Development System) an d back-ann otated to th e simu lation n etlist.
All timing parameters ass ume worst-case operating con ditions (supply voltage and junction temperature). Values
apply to all XQ4000EX devices unless otherwise noted.
-4
32x1 11.0 - ns
32x1 5.5 - ns
32x1 2.6 - ns
32x1 0 - ns
32x1 2.9 - ns
32x1 0 - ns
32x1 2.1 - ns
32x1 0 - ns
32x1 - 10.1 ns
UnitsMin Max
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-4
Symbol Dual Port RAM Size
Write Operation
T
WCDS
T
WPDS
T
ASDS
T
AHDS
T
DSDS
T
DHDS
T
WSDS
T
WHDS
T
WODS
Notes:
1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
2. Applicable Read timin g speci fications are identi cal to Level-Sensitiv e Read timing.
DS021 (v2.2) June 25, 2000 www.xilinx.com 23
Product Specification 1-800-255-7778
Address write cycle time (clock K period) 16x1 11.0 ns
Clock K pulse width (active edge) 16x1 5.5 - ns
Address setu p time bef ore cloc k K 16x1 3.1 - ns
Address hold time after clock K 16x1 0 - ns
DIN setup time before cloc k K 16x1 2.9 - ns
DIN hold time after clock K 16x1 0 - ns
WE setup time before clock K 16x1 2.1 - ns
WE hold time after clock K 16x1 0 - ns
Data valid after clock K 16x1 - 9.4 ns
(1)
UnitsMin Max
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Timing Waveform
T
WPS
WCLK (K)
R
T
WSS
T
WHS
WE
T
DSS
T
DHS
DATA IN
T
ASS
T
AHS
ADDRESS
T
ILO
DATA OUT
T
ILO
T
WOS
OLD NEW
DS021_01_060100
XQ4028EX CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveform
T
WPDS
WCLK (K)
WE
DATA IN
ADDRESS
DATA OUT
T
WSS
T
DSDS
T
ASDS
T
ILO
T
WODS
OLD NEW
T
WHS
T
DHDS
T
AHDS
DS021_02_060100
T
ILO
24 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static timing analyzer (TRCE in the Xilinx Development System) an d back-ann otated to th e simu lation n etlist.
All timing parameters ass ume worst-case operating con ditions (supply voltage and junction temperature). Values
apply to all XQ4000EX devices unless otherwise noted.
-4
Symbol Single Port RAM Size
Write Operation
T
T
T
T
T
T
T
T
T
T
T
T
WC
WCT
WP
WPT
AS
AST
AH
AHT
DS
DST
DH
DHT
Address write cycle time 16x2 10.6 - ns
Write Enable pulse width (High) 16x2 5.3 - ns
Address setup time before WE 16x2 2.8 - ns
Address hold time after end of WE 16x2 1.7 - ns
DIN setup time before end of WE 16x2 1.1 - ns
DIN hold time after end of WE 16x2 6.6 - ns
Read Operation
T
T
T
T
RCT
ILO
IHO
RC
Address read cycle time 16x2 4.5 - ns
Data valid after address change (no Write Enable) 16x2 - 2.2 ns
Read Operation, Clocking Data into Flip-Flop
T
T
ICK
IHCK
Address setup time before clock K 16x2 1.5 - ns
Read During Write
UnitsMin Max
32x1 10.6 - ns
32x1 5.3 - ns
32x1 2.8 - ns
32x1 1.7 - ns
32x1 1.1 - ns
32x1 6.6 - ns
32x1 6.5 - ns
32x1 - 3.8 ns
32x1 3.2 - ns
T
T
T
T
WO
WOT
DO
DOT
Data valid after WE goes active (DIN stable before WE) 16x2 - 6.5 ns
32x1 - 7.4 ns
Data valid after DIN (DIN changes during WE) 16x2 - 7.7 ns
32x1 - 8.2 ns
Read During Write, Clocking Data into Flip-Flop
T
WCK
T
WCKT
T
DCK
T
DOCK
Notes:
1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
DS021 (v2.2) June 25, 2000 www.xilinx.com 25
Product Specification 1-800-255-7778
WE setup time before clock K 16x2 7.1 - ns
32x1 9.2 - ns
Data setup time befo r e clock K 16x2 5.9 - ns
32x1 8.4 - ns
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX CLB Level-Sensitive RAM Timing Waveforms
R
WRITE
ADDRESS
T
AS
WE
DATA IN
READ WITHOUT WRITE
T
X,Y OUTPUTS
VALID
READ, CLOCKING DATA INTO FLIP-FLOP
CLOCK
XQ,YQ OUTPUTS
READ DURING WRITE
WRITE ENABLE
ILO
T
WC
T
WP
T
DS
REQUIRED
VALID
T
ICK
T
CH
T
CKO
T
WP
T
AH
T
DH
VALID (NEW)VALID (OLD)
(stable during WE)
DATA IN
T
WO
X,Y OUTPUTS
DATA IN
(changing during WE)
X,Y OUTPUTS
VALID
OLD NEW
T
WO
VALID
(PREVIOUS)
VALID
(OLD)
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
WRITE ENABLE
T
WCK
DATA IN
CLOCK
XQ,YQ OUTPUTS
T
DCK
T
DH
VALID
T
DO
VALID
(NEW)
T
WP
T
CKO
DS021_03_060100
Figure 1:
26 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and inter nal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and nor mal
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values apply to all XQ4000EX
devices unless otherwise noted.
clock loading. For more specific, more precise, and
XQ4028EX Output Flip-Flop, Clock to Out
Symbol
T
ICKOF
T
ICKEOF
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked b y the global clock net .
2. Output timing is measured at TTL threshold with 50 pF external capacitive load.
3. OFF = Output Flip-Flop
Global low skew clock to output using OFF
Global early clock to output using OFF
XQ4028EX Output Mux, Clock to Out
Symbol
T
PFPF
T
PEFPF
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked b y the global clock net .
2. Output timing is measured at ~50% V
3. OMUX = Output MUX
Global low skew clock to TTL output (fast) using OMUX
Global early clock to TTL output (fast) using OMUXF
threshold with 50 pF external capacitive load. For different loads, see graph below.
CC
(1,2)
Description
(3)
(1,2)
Description
-4
UnitsMax
(3)
3)
(3)
16.6 ns
13.1 ns
-4
UnitsMax
15.9 ns
12.4 ns
XQ4028EX Output Level and Slew Rate Adjustments
The following table must be used to adjust output parameters and output switching characteristics.
-4
Symbol Description
T
TTLOF
T
TTLO
T
CMOSOF
T
CMOSO
DS021 (v2.2) June 25, 2000 www.xilinx.com 27
Product Specification 1-800-255-7778
For TTL output FAST add 0 ns
For TTL output SLOW add 2.9 ns
For CMOS FAST output add 1.0 ns
For CMOS SLOW output add 3.6 ns
UnitsMax
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX Pin-to-Pin Input Parameter Guidelines
R
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and inter nal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and nor mal
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values apply to all XQ4000EX
devices unless otherwise noted
clock loading. For more specific, more precise, and
XQ4028EX Global Low Skew Clock, Setup and Hold
Symbol Description
T
PSD
T
PHD
Notes:
1. IFF = Flip-Flop or Latch
Input setup time, using Global Low Skew clock and IFF (full delay) 8.0 ns
Input hold time, using Global Low Skew clock and IFF (full delay) 0 ns
XQ4028EX Global Early Clock, Setup and Hold for IFF
Symbol Description
T
PSEP
T
PHEP
Notes:
1. IFF = Flip-Flop or Latch
2. Setup parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.6 ns for BUFGE #s 1, 2, 5 and 6.
Input setup time, using Global Early clock and IFF (full delay) 6.5 n s
Input hold time, using Global Early clock and IFF (full delay) 0 ns
-4
-4
(2)
UnitsMin
UnitsMin
XQ4028EX Global Early Clock, Setup and Hold for FCL
-4
Symbol Description
T
PFSEP
T
PFHEP
Notes:
1. FCL = Fast Capture Latch
2. For CMOS input levels, see the XQ4028EX Input Threshold Adjustments.
3. Setup time is measured with the f as test r oute and th e lightest load. Use the stat ic ti ming analy zer to determine the setup tim e under
given design conditions.
4. Hold time is measured using the f arthest di stance an d a ref er ence load of one cloc k pin per two IOBs. Use the stat ic tim ing analyzer
to determine the setup and hold tim es under given design conditions.
5. Setup parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.2 ns for BUFGE #s 1, 2, 5 and 6.
Input setup time, using Global Early clock and FCL (partial delay) 3.4 ns
Input hold time, using Global Early clock and FCL (partial delay) 0 ns
(2)
UnitsMin
XQ4028EX Input Threshold Adjustments
The following table must be used to adjust input parameters and input switching characteristics.
-4
Symbol Description
T
T
CMOSI
TTLI
For TTL input add 0 ns
For CMOS input add 0.3 ns
UnitsMax
28 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static ti ming analyzer (TR CE in the Xilinx Develop-
ment System) an d back-ann otated to th e simu lation n etlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (supply voltage and junction tempe rature). Values apply to all
XQ4000EX devices unless otherwise noted.
-4
Symbol Description
UnitsMin
Clocks
T
OKIK
Delay from FCL enable (OK) active to IFF clock (IK) active edge 3.2 ns
Propagation Delays
T
T
T
T
T
T
PPFLI
PID
PLI
PPLI
PDLI
PFLI
Pad to I1, I2 2.2 ns
Pad to I1, I2 via transparent input latch, no delay 3.8 ns
Pad to I1, I2 via transparent input latch, partial delay 13.3 ns
Pad to I1, I2 via transparent input latch, full delay 18. 2 ns
Pad to I1, I2 via transparent FCL and input latch, no delay 5.3 ns
Pad to I1, I2 via transparent FCL and input latch, partial delay 13.6 ns
Propagation Delays (TTL Inputs)
T
T
T
IKRI
IKLI
OKLI
Clock (IK) to I1, I2 (flip-flop) 3.0 ns
Clock (IK) to I1, I2 (latch enable, active Low) 3.2 ns
FCL enable (OK) active edge to I1, I2 (via transparent standard input latch) 6.2 ns
Global Set/Reset
T
MRW
T
RRI
Notes:
1. FCL = Fast Capture Latch, IFF = Input Flip-Flop or Latch
2. For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 28.
3. For setup and hold times with respect to the clock inp ut pin, see the Global Low Sk ew Clock and Glob al Early Clock Setup and Hold
tables on page 28.
Minimum GSR pulse width 13.0 ns
Delay from GSR input to any Q 22.8 ns
DS021 (v2.2) June 25, 2000 www.xilinx.com 29
Product Specification 1-800-255-7778
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX IOB Input Switching Characteristic Guidelines (Continued)
R
-4
UnitsMin
Symbol
Description
Setup Times
T
PICK
T
PICKP
T
PICKD
T
PICKF
T
PICKFP
T
POCK
T
POCKP
Pad to Clock (IK), no delay 2.5 ns
Pad to Clock (IK), partial delay 10.8 ns
Pad to Clock (IK), full delay 15.7 ns
Pad to Clock (IK), via transparent Fast Capture Latch, no delay 3.9 ns
Pad to Clock (IK), via transparent Fast Capture Latch, partial delay 12.3 ns
Pad to Fast Capture Latch Enable (OK), no delay 0.8 ns
Pad to Fast Capture Latch Enable (OK), partial delay 9.1 ns
Setup Times (TTL or CMOS Inputs)
T
ECIK
Clock Enable (EC) to Clock (IK) 0.3 ns
Hold Times
T
IKPI
T
IKPIP
T
IKPID
T
IKPIF
T
IKFPIP
T
IKFPID
T
IKEC
T
IKECP
T
IKECD
T
OKPI
T
OKPIP
Notes:
1. For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 28.
2. For setup and hold times wi th respe ct to th e cloc k input pin, see the Globa l Lo w Ske w Cloc k and Globa l Early Clo ck Setu p and Hold
tables on page 28.
Pad to Clock (IK), no delay 0 ns
Pad to Clock (IK), partial delay 0 ns
Pad to Clock (IK), full delay 0 ns
Pad to Clock (IK) via transparent Fast Capture Latch, no delay 0 ns
Pad to Clock (IK) via transparent Fast Capture Latch, partial delay 0 ns
Pad to Clock (IK) via transparent Fast Capture Latch, full delay 0 ns
Clock Enable (EC) to Clock (IK), no delay 0 ns
Clock Enable (EC) to Clock (IK), partial delay 0 ns
Clock Enable (EC) to Clock (IK), full delay 0 ns
Pad to Fast Capture Latch Enable (OK), no delay 0 ns
Pad to Fast Capture Latch Enable (OK), partial delay 0 n s
30 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
FXQ4028EX IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuri ng i nter n al t est patter ns. Listed below
are representative values. For mo re specific, more precise,
and worst-case guaranteed data, use t he values reported
by the static ti ming analyzer (TR CE in the Xilinx Develop-
ment System) an d back-ann otated to th e simu lation n etlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values
apply to all XQ4000EX devices unless otherwise noted.
-4
Symbol Description
Propagation Delays (TTL Output Levels)
T
OKPOF
T
OPF
T
TSHZ
T
TSONF
T
OKFPF
T
CEFPF
T
OFPF
Clock (OK) to pad, fast - 7.4 ns
Output (O) to pad, fast - 6.2 ns
3-state to pad High-Z, slew-rate independent - 4.9 ns
3-state to pad active and valid, fast - 6.2 ns
Output MUX select (OK) to pad - 6.7 ns
Fast path output MUX input (EC) to pad - 6.2
Slowest path output MUX input (EC) to pad - 7.3
Setup and Hold Times
T
OOK
T
OKO
T
ECOK
T
OKEC
Output (O) to clock (OK) setup time 0.6 - ns
Output (O) to clock (OK) hold time 0 - ns
Clock enable (EC) to clock (OK) setup 0 - ns
Clock enable (EC) to clock (OK) hold 0 - ns
Clocks
T
CH
T
CL
Clock High 3.5 - ns
Clock Low 3.5 - ns
Global Set/Reset
T
MRW
T
RRI
Notes:
1. Output timing is measured at TTL threshold, with 35 pF external capacitive loads.
2. For CMOS output levels, see the "XQ4028EX Output Level and Slew Rate Adjustments" on page 27.
Minimum GSR pulse width 13.0 - ns
Delay from GSR input to any pad 30.2 - ns
UnitsMin Max
DS021 (v2.2) June 25, 2000 www.xilinx.com 31
Product Specification 1-800-255-7778
QPRO XQ4000E/EX QML High-Reliability FPGAs
R
CB191/196 Package for XQ4010E
Bound
Pin Description PG191 CB196
GND D4 P1 -
PGCK1_(A16*I/0) C3 P2 122
I/O_(A17) C4 P3 125
I/0 B 3 P4 128
--P5
(1)
I/O C5 P6 131
I/O_(TDI) A2 P7 134
I/O_(TCK) B4 P8 137
I/O C6 P9 140
I/O A3 P10 143
I/O B5 P11 146
I/O B6 P12 149
GND C7 P13 -
I/O A4 P14 152
I/O A5 P15 155
I/O_(TMS) B7 P16 158
I/O A6 P17 161
I/O C8 P18 164
I/O A7 P19 167
I/O B8 P20 170
I/O A8 P21 173
I/O B9 P22 176
I/O C9 P23 179
GND D9 P24 VCC D10 P25 -
I/O C10 P26 182
I/O B10 P27 185
I/O A9 P28 -
I/O A10 P29 191
I/O A11 P30 194
I/O C11 P31 197
I/O B11 P32 200
I/O A12 P33 203
Notes:
1. Indicates unconnected package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
Scan
Bound
Pin Description PG191 CB196
Scan
I/O B12 P34 206
I/O A13 P35 209
GND C12 P36 -
I/O B13 P37 212
I/O A14 P38 215
-
I/O A15 P39 218
I/O C13 P40 221
I/O B14 P41 224
I/O A16 P42 227
I/O B15 P43 230
I/O C14 P44 233
I/O A17 P45 236
SCGK2_(I/O) B16 P46 239
M1 C15 P47 242
GND D15 P48 -
M0 A18 P49 245
(2)
VCC D16 P50 -
M2 C16 P51 246
(2)
PGCK2_(I/O) B17 P52 247
I/O_(HDC) E16 P53 250
--P54
(1)
-
I/O C17 P55 253
I/0 D17 P56 256
I/O B18 P57 259
I/O_(LDC) E17 P58 262
I/O F16 P59 265
I/O C18 P60 268
I/O D18 P61 271
I/O F17 P62 274
GND G16 P63 -
I/O E18 P64 277
I/O F18 P65 280
I/O G17 P66 283
I/O G18 P67 286
Notes:
1. Indicates unconnec ted package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
32 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
Bound
Pin Description PG191 CB196
Scan
I/O H16 P68 286
I/O H17 P69 291
I/O H18 P70 295
I/O J18 P71 298
I/O J17 P72 301
I/O_(/ERR_/INIT) J16 P73 304
VCC J15 P74 GND K15 P75 -
I/O K16 P76 307
I/O K17 P77 310
I/O K18 P78 313
I/O L18 P79 316
I/O L17 P80 319
I/O L16 P81 322
I/O M18 P82 325
I/O M17 P83 328
Bound
Pin Description PG191 CB196
PGCK3_(I/O) U16 P102 370
--P103
(1)
I/O T14 P104 376
I/O U15 P105 376
I/O_(D6) V17 P106 379
I/O V16 P107 382
I/O T13 P108 385
I/O U14 P109 388
I/O V15 P110 391
I/O V14 P111 394
GND T12 P112 -
I/O U13 P113 397
I/O V13 P114 400
I/O_(D5) U12 P115 403
I/O_(/CSO) V12 P116 406
I/O T11 P117 409
Scan
-
I/O N18 P84 331
I/O P18 P85 334
GND M16 P86 -
I/O N17 P87 337
I/O R18 P88 340
I/O T18 P89 343
I/O P17 P90 349
I/O N16 P91 349
I/O T17 P92 352
I/O R17 P93 355
I/O P16 P94 358
I/O U18 P95 361
SGCK3_(I/O) T16 P96 364
GND R16 P97 -
DONE U17 P98 -
VCC R15 P99 -
/PROG V18 P100 -
I/O_(D7) T15 P101 367
Notes:
1. Indicates unconnected package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
I/O U11 P118 412
I/O V11 P119 415
I/O V1 P120 418
I/O_(D4) U10 P121 421
I/O T10 P122 424
VCC R10 P123 GND R9 P124 -
I/O_(D3) T9 P125 427
I/O_(/RS) U9 P126 430
I/O V9 P127 433
I/O V8 P128 436
I/O U8 P129 439
I/O T8 P130 442
I/O_(D2) V7 P131 445
I/O U7 P132 448
I/O V6 P133 451
I/O U6 P134 454
GND T7 P135 -
Notes:
1. Indicates unconnec ted package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
DS021 (v2.2) June 25, 2000 www.xilinx.com 33
Product Specification 1-800-255-7778
QPRO XQ4000E/EX QML High-Reliability FPGAs
R
Bound
Pin Description PG191 CB196
Scan
I/O V5 P136 457
I/O V4 P137 460
I/O U5 P138 463
I/O T6 T139 446
I/O_(D1) V3 P140 469
I/O_(RCLK-/BUSY/RDY) V2 P14 1 472
I/O U4 P142 475
I/O T5 P143 478
I/O_(D0*_DIN) U3 P144 481
SGCK4_(DOUT*_I/O) T4 P 145 484
CCLK V1 P146 -
VCC R4 P14 7 TDO U2 P148 GND R3 P149 -
I/O_(A0*_WS) T3 P150 2
PGCK4_(I/O*_A1) U1 P15 1 5
- - P152
(1)
-
Pin Description PG191 CB196
I/O K1 P169 53
I/O_(A6) K2 P170 56
I/O_(A7) K3 P171 59
GND K4 P172 -
VCC J4 P173 I/O_(A8) J3 P174 62
I/O_(A9) J2 P175 65
I/O J1 P176 68
I/O H1 P177 71
I/O H2 P178 74
I/O H3 P179 77
I/O_(A10) G1 P180 80
I/O_(A11) G2 P181 83
I/O F1 P182 86
I/O E1 P183 89
GND G3 P184 -
I/O F2 P185 92
Bound
Scan
I/O P3 P153 8
I/O R2 P154 11
I/O_(CS1*_A2) T2 P155 14
I/O_(A3) N3 P156 17
I/O P2 P157 20
I/O T1 P158 23
I/O R1 P159 26
I/O N2 P160 29
GND M3 P 161 -
I/O P1 P162 32
I/O N1 P163 35
I/O_(A4) M2 P164 38
I/O_(A5) M1 P165 41
I/O L3 P166 44
I/O L2 P167 47
I/O L1 P168 50
Notes:
1. Indicates unconnected package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
I/O D1 P186 96
I/O C1 P187 98
I/O E2 P188 101
I/O_(A12) F3 P 189 104
I/O_(A13 D2 P 190 107
--P192
(1)
I/O E3 P193 113
I/O_(A14) C2 P194 116
SGCK1(A15*I/O) B2 P195 119
VCC D 3 P196 -
Notes:
1. Indicates unconnec ted package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
Additional XQ4010E Package Pins
CB196
No Connect Pins
P5 P54 P103 P152
P192 - - -
-
34 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
R
Ordering Information
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ 4010E -4 PG 191 M
MIL-PRF-38535
(QML) Processing
M = Cera mic (TC = –55°C to +125°C)
N = Plastic (T
= –55°C to +125°C)
J
Device Type
Temp erature Range
XQ4005E
Number of Pins
XQ4010E
XQ4013E
XQ4025E
XQ4028EX
Speed Grade
-3
-4
Package Type
CB = Top Brazed Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
HQ = Plastic Quad Flat Pack
BG = Plastic Ball Grid Array
Revision History
The following table shows the revision history for this document
Date Version Des cri ption
05/19/98 2.1 Updates.
06/25/00 2.2 Updated timing specifications to match with commercial data sheet. Updated format.
DS021 (v2.2) June 25, 2000 www.xilinx.com 35
Product Specification 1-800-255-7778
QPRO XQ4000E/EX QML High-Reliability FPGAs
R
36 www.xilinx.com DS021 (v2.2) June 25, 2000
1-800-255-7778 Product Specification
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