XILINX XCR5128 Product Specification
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APPLICATION NOTE
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XCR5128: 128 Macrocell CPLD
DS041 (v1.4) January 19, 2001
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Features
• Industry's first TotalCMOS™ PLD - both CMOS design
and process technologies
• Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
• IEEE 1149.1-compliant, JTAG Testing Capability
- Four pin JTAG interface (TCK, TMS, TDI, TDO)
- IEEE 1149.1 TAP Controller
- JTAG commands include: Bypass, Sample/Preload,
Extest, Usercode, Idcode, HighZ
• 5V, In- System Programmable (ISP) using the JTAG
interface
- On-chip supervoltage generation
- ISP commands include: Enable, Erase, Program,
Verify
- Supported by multiple ISP programming platforms
• High speed pin-to-pin delays of 7.5 ns
• Ultra-low static power of less than 100 µA
• 100% routable with 100% utilization while all pins and
all macrocells are fixed
• Deterministic timing model that is extremely simple to
use
• Four clocks available
• Programmable clock polarity at every macrocell
• Support for asynchronous clocking
• Innovative XPLA™ architecture combines high speed
with extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
•PCI compliant
2
• Advanced 0.5µ E
• Security bit prevents unauthorized access
• Design entry and verification using industry standard
and Xilinx CAE tools
• Reprogrammable using industry standard device
programmers
• Innovative Control Term structure provides either sum
terms or product terms in each logic block for:
- Programmable 3-state buffer
- Asynchronous macrocell register preset/reset
• Programmable global 3-state pin facilitates "bed of
nails" testing without using logic resources
• Available in PLCC, VQFP, and PQFP packages
• Available in both Commercial and Industrial grades
CMOS process
Product Specification
Description
The XCR5128 CPLD (Complex Programmable Logic
Device) is the third in a family of CoolRunner
Xilinx. These devices combine high speed and zero power
in a 128 macrocell CPLD. With the FZP design technique,
the XCR5128 offers true pin-to-pin speeds of 7.5 ns, while
simultaneously delivering power that is less than 100 µA at
standby without the need for ‘turbo bits' or other power
down schemes. By replacing conventional sense amplifier
methods for implementing product ter ms (a technique that
has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is
also substantially lower than any competing CPLD. These
devices are the first TotalCMOS PLDs, as they use both a
CMOS process technology and the patented full CMOS
FZP design technique. For 3V applications, Xilinx also
offers the high-speed XCR3128 CPLD that offers these f eatures in a full 3V implementation.
The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combines the best features of both PLA
and PAL type structures to deliver high speed a nd flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 7.5 ns PA L path with five
dedicated product terms per output. This PAL path is joined
by an additional PLA structure that de ploys a pool of 32
product terms to a fully programmable OR array that can
allocate the PLA product ter ms to any output in the logic
block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic
is allocated from the PLA array to an output is only 2 ns,
regardless of the number of PLA product terms used, which
results in worst case t
other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and
shared across multiple outputs via the OR array, effectively
increasing design density.
The XCR5128 CPLDs are supported by industry standard
CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor , Synopsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry . Design v erification uses industry standard simulators for functional
and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting
's of only 9.5 ns from any pin to any
PD
®
CPLDs from
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XCR5128: 128 Macrocell CP LD
uses a Xilinx developed tool, XPLA Professional (available
on the Xilinx web site).
The XCR5128 CPLD is electrically reprogrammable using
industry standard device programmers from vendors such
as Data I/O, BP Microsystems, SMS, and others. The
XCR5128 also includes an industry-standard, IEEE
1149.1, JTAG interface through which in-system program-
ming (ISP) and reprogramming of the device is supported.
XPLA Architecture
Figure 1 shows a high level block diagram of a 128 macro-
cell device implementing the XPLA architecture. The XPLA
MC1
I/O
MC2
MC16
LOGIC
BLOCK
36
16
16
architecture consists of logic bl ock s that ar e interconnected
by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic bloc k als o provides 32 ZIA feedback paths
from the macrocells and I/O pins.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.
MC1
36
16
16
LOGIC
BLOCK
MC2
MC16
I/O
I/O
I/O
I/O
MC1
MC2
MC16
MC1
MC2
MC16
MC1
MC2
MC16
LOGIC
BLOCK
LOGIC
BLOCK
LOGIC
BLOCK
MC1
36
16
16
ZIA
36
16
16
36
16
16
36
16
16
36
16
16
36
16
16
LOGIC
BLOCK
LOGIC
BLOCK
LOGIC
BLOCK
MC2
MC16
MC1
MC2
MC16
MC1
MC2
MC16
I/O
I/O
I/O
SP00464
Figure 1: Xilinx XPLA CPLD Architecture
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XCR5128: 128 Macrocell CPLD
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Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic
block contains control terms, a PAL array, a PLA array, and
16 macrocells. the six control terms can individually be configured as either SUM or PRODUCT terms, and are used to
control the preset/reset and output enables of the 16 macrocells’ flip-flops. The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array
consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased
product term density.
Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin t
of the XCR5128 device
PD
through the PAL array is 7.5 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using one or all 32 PLA product terms is just 2 ns. So
the total pin-to-pin t
for the XCR5128 using six to 37
PD
product terms is 9.5 ns (7.5 ns for the PAL + 2 ns for the
PLA)
.
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36 ZIA INPUTS
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XCR5128: 128 Macrocell CP LD
CONTROL
PAL
ARRAY
6
5
TO 16 MACROCELLS
PLA
ARRAY
(32)
SP00435A
Figure 2: Xilinx XPLA Logic Block Architecture
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XCR5128: 128 Macrocell CPLD
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Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in
the CoolRunner family. The macrocell consists of a flip-flop
that can be configured as either a D- or T- type. A D-type
flip-flop is generally more useful for implementing state
machines and data buffering. A T-typ e flip-flop is generally
more useful in implementing counters. All CoolRunner family members provide both synchronous and asynchronous
clocking and provide the ability to clock off either the falling
or rising edges of these clocks. These devices are
designed such that the skew between the rising and falling
edges of a clock are minimized for clocking integrity. There
are four clocks available on the XCR5128 device. Clock 0
(CLK0) is designated as the "synchronous" clock and must
be driven by an external source. Clock 1 (CLK1), Clock 2
(CLK2), and Clock 3 (CLK3) can either be used as a synchronous clock (driven by an external source) or as an
asynchronous clock (driven by a macrocell equation). The
timing for asynchronous clocks is different in that the t
time is extended by the amount of time that it takes for the
signal to propagate through the array and reach the clock
network, and the t
time is reduced.
SU
Two of the control terms (CT0 and CT1) are used to control
the Preset/Reset of the macrocell’s flip-flop. The Preset/Reset feature for each macrocell can also be disabled.
Note that the Power-on Reset leaves all macrocells in the
"zero" state when power is properly applied. The other four
CO
control terms (CT2-CT5) can be used to control the Output
Enable of the macrocell’s output buffers. The reason there
are as many control terms dedicated for the Output Enable
of the macrocell is to insure that all CoolRunner devices are
PCI compliant. The macrocell’s output buffers can also be
always enabled or disabled. All CoolRunner devices also
provide a Global 3-State (GTS) pin, which, when enabled
and pulled Low, will 3-state all the outputs of the device.
This pin is provided to support "In-Circuit Testing" or
"Bed-of-Nails Testing".
There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path
before the output buffer is the macrocell feedback path,
while the ZIA feedback path after the output buffer is the I/O
pin ZIA path. When the macrocell is used as an output, the
output buffer is enabled, and the macrocell feedback path
can be used to feedback the logic implemented in the macrocell. When the I/O pin is used as an input, the output
buffer will be 3-stated and the input signal will be fed into
the ZIA via the I/O feedback path, and the logic implemented in the buried macrocell can be fed back to the ZIA
via the macrocell feedback path. It should be noted that
unused inputs or I/Os should be properly terminated (see
the section on T erminations in this data sheet and the application note: Terminating Unused I/O Pins in xilinx XPLA1
and XPLA2 CPLDs).
PAL
PLA
CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
Figure 3: XCR5128 Macrocell Architecture
D/T Q
INIT
(P or R)
TO ZIA
CT0
CT1
GND
GTS
CT2
CT3
CT4
CT5
V
GND
GND
CC
SP00457
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XCR5128: 128 Macrocell CP LD
Simple Timing Model
Figure 4 shows the CoolRunner Timing Model. The C ool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including t
tures, the user may be able to fit the design into the CPLD,
but is not sure whether system timing requirements can be
met until after the design has been fit into the device . This is
because the timing models of competing architectures are
very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model.
, tSU, and tCO. In other competing architec-
PD
t
PD_PAL
t
PD_PLA
REGISTERED
t
= PAL ONLY
SU_PAL
= PAL + PLA
t
SU_PLA
= COMBINATORIAL PAL ONLY
= COMBINATORIAL PAL + PLA
TotalCMOS De sign Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CP LD, both in process technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 5 and Table 1 showing the I
Frequency of Xilinx’ XCR5128 TotalCMOS CPLD (data
taken w/eight up/down, loadable 16 bit counters at 5V,
25°C.
OUTPUT PININPUT PIN
REGISTERED
t
DQ
CO
OUTPUT PININPUT PIN
CC
vs.
GLOBAL CLOCK PIN
Figure 4: CoolRunner Timing Model
SP00441
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