XILINX XCR3256XL User Manual

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DS013 (v1.2) May 3, 2000

Features

• 7.5 ns pin-to-pin logic delays

• System frequencies up to 140 MHz

• 256 macrocells with 6,000 usable gates

• Available in small footprint packages

- 144-pin TQFP (116 user I/O pins)

- 208-pin PQFP (160 user I/O)

- 280-ball CS BGA (160 user I/O)

• Optimized for 3.3V systems

- Ultra low power operation

- 5V tolerant I/O pins with 3.3V core supply

- Advanced 0.35 micron five metal layer re­programmable process

- FZP™ CMOS desig n tech nol ogy

• Advanced system features

- In-system programming

- Input registers

- Predictable timing model

- Up to 23 clocks available per logic block

- Excellent pin retention during design changes

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

- Four global clocks

- Eight product term control terms per logic block

• Fast ISP programming times

• Port Enable pin for additional I/O

• 2.7V to 3.6V industrial grade voltage range

• Programmable slew rate control per output

• Security bit prevents unauthorized access

• Refer to XPLA3 family data sheet (DS012) for
architecture description

014

XCR3256XL 256 Macrocell CPLD

Preliminary Product Specification

Description

The XCR3256XL is a 3.3V , 256 macrocell CPLD targeted at
power sensitive designs that require leading edge program­mable logic solutions. A total of 16 logic blocks provide
6,000 usable gates. Pin-to-pin propagation delays are

7.5 ns with a maximum system frequency of 140 MHz.

TotalCMOS™ Design Technique for
Fast Zero Power

Xilinx offers a TotalCMOS CPLD, both in process technol­ogy and design technique. Xilinx employs a cascade of
CMOS gates to impl ement its sum of products ins tead of
the traditional sense amp approach. This CMOS gate
implementation all ows Xilinx to offer CPLDs that are both
high performance and low power, breaking the paradigm
that to have low power, you must have low performance.
Refer to Figure 1 and Table 1 showing the I
quency of our XCR3256XL TotalCMOS CPLD (data taken
with 16 up/down, loadable 16-bit counters at 3.3V, 25

CC

vs. Fre-

°

C).

© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at

http://www.xilinx.com/legal.htm

DS013 (v1.2) May 3, 2000 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778

. All other trademarks and registered trademarks are the property of their respective owners.

All specifications are subject to change without notice.

XCR3256XL 256 Macrocell CPLD

140

120

100

80

60

40

Typical ICC (mA)

20

0

0 20 40 60 80 100 120 140 160

Figure 1: XCR3256XL Typical ICC vs. Frequency at VCC = 3.3V, 25°C

R

Frequency (MHz)

Table 1: Typi cal I

vs. Frequency at VCC = 3.3V, 25°C

CC

Frequency (MHz) 0 1 10 20 40 60 80 100 120 140

Typical I

DC Electrical Characteristics Over Recommended Operating Conditions

(mA) 0.02 0.91 8.87 17.7 34.8 51.5 68 84.2 100.1 116.6

CC

(1)

Symbol Parameter Test Conditions Min. Max. Unit

V

OH

V

OL

I

IL

I

IH

I

CCSB

I

CC

Output High voltage for 3.3V outputs IOH = –8 mA 2.4 - V
Output Low voltage for 3.3V outputs IOL = 8 mA - 0.4 V
Input leakage current VIN = GND or V
I/O High-Z leakage current VIN = GND or V

CC
CC

–10 10
–10 10

Standby current VCC = 3.6V - 100
Dynamic current

(2,3)

f = 1 MHz - 2 mA
f = 50 MHz - 60 mA

C

IN

C

CLK

C

I/O

Notes:

1. See XPLA3 family data sheet (DS012) for recommended operating conditions.

2. See Table 1, Figure1 for typ ical values.

3. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and
unloaded. Inputs are tied to V

4. Typical values not tested.

Input pin capacitance
Clock input capacitance
I/O pin capacitance

(4)

(4)

(4)

or ground. This parameter guaranteed by design and characterization, not testing.

CC

f = 1 MHz - 8 pF
f = 1 MHz 5 12 pF
f = 1 MHz - 10 pF

m

A

m

A

m

A

2 www.xilinx.com DS013 (v1.2) May 3, 2000

1-800-255-7778 Prelimin ary Pr odu ct Specifi cati on

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XCR3256XL 256 Macrocell CPLD

AC Electrical Characteristics Over Recommended Operating Conditions

-7 -10 -12

(1,2)

Symbol Parameter

T

PD1

T

PD2

T

CO

T

SUF

T

SU

T

H

T

WLH

T

PLH

T

R

T

L

f

SYSTEM

T

CONFIG

T

POE

T

POD

T

PCO

T

PAO

Notes:

1. Specifications measured with one output switching.

2. See XPLA3 Family Data Sheet (DS012) for recommended operating conditions.

3. See Figure 4 for derating.

4. Typical current draw during configuration is 10 mA at 3.6V.

5. Output C

Propagation delay time (single p-term) - 7.0 - 9.0 - 10.8 ns
Propagation delay time (OR array)

(3)

- 7.5 - 10.0 - 12.0 ns
Clock to output (global synchronous pin clock) - 4.5 - 5.8 - 6.9 ns
Setup time fast 2.0 - 2.5 - 3.0 - ns
Setup time 4.8 - 6.5 - 7.9 - ns
Hold time 0-0-0-ns
Global clock pulse width (High or Low) 3.0 - 4.0 - 5.0 - ns
P-term clock pulse width (High or Low) 4.5 - 6.0 - 7.5 - ns
Input rise time - 20 - 20 - 20 ns
Input fall time - 20 - 20 - 20 ns
Maximum system frequency - 140 - 105 - 88 MHz
Configuration time

(4)

-40-40-40ms
P-term OE to output enabled - 9.0 - 11.0 - 13.0 ns
P-term OE to output disabled

(5)

- 9.0 - 11.0 - 13.0 ns
P-term clock to output - 8.0 - 10.3 - 12.4 ns
P-term set/reset to output valid - 9.0 - 11.0 - 13.0 ns

= 5 pF.

L

Unit Min. Max. Min. Max. Min. Max.

DS013 (v1.2) May 3, 2000 www.xilinx.com 3

Preliminary Product Specification 1-800-255-7778