XILINX XCR3064XL-10CS48I, XCR3064XL-10CS48C, XCR3064XL-10CP56I, XCR3064XL-10CP56C, XCR3064XL-7VQ44I Datasheet
...
DS017 (v1.6) January 8, 2002 www.xilinx.com 1
Product Specification 1-800-255-7778
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• Lowest power 64 macrocell CPLD
• 6.0 ns pin-to-pin logic delays
• System frequencies up to 145 MHz
• 64 macrocells with 1,500 usable gates
• Available in small footprint packages
- 44-pin PLCC (36 user I/O pins)
- 44-pin VQFP (36 user I/O pins)
- 48-ball CS BGA (40 user I/O pins)
- 56-ball CP BGA (48 user I/O pins)
- 100-pin VQFP (68 user I/O pins)
• Optimized for 3.3V systems
- Ultra-low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
• Advanced syste m features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control term s per function block
• Fast ISP programming times
• Port Enable pin for dual function of JTAG ISP pins
• 2.7V to 3.6V supply voltage at industrial temperature
range
• Programmable slew rate control per macrocell
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012
) for
architecture description
Description
The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at
power sensitive designs that require leading edge programmable logic solutions. A total of four function blocks provide
1,500 usable gates. Pin-to-pin propagation delays are
6.0 ns with a maximum system frequency of 145 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing the I
CC
vs. Frequency of our
XCR3064XL TotalCMOS CPLD (data taken with four
resetable up/down, 16-bit counters at 3.3V, 25°C).
0
XCR3064XL 64 Macrocell CPLD
DS017 (v1.6) January 8, 2002
014
Produc t S pecif i c ation
R
Figure 1: ICC vs. Frequency at VCC = 3.3V, 25°C
0.0
5.0
10.
0
15.
0
20.
0
25.
0
30.0
35.0
020406080100120140
Frequency (MHz
)
DS017_01_10240
1
pical I
(
mA
)
Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C)
Frequency (MHz) 0 1 5 10 20 40 60 80 100 120 140
Typical I
CC
(mA) 0 0.2 1.0 2.0 3.9 7.6 11.3 14.8 18.5 22.1 25.6
XCR3064XL 64 Macrocell CPLD
2 www.xilinx.com DS017 (v1.6) Janu ary 8, 2002
1-800-255-7778 Product Specification
R
DC Electrical Char acteristics Over Reco mmended Operating Conditions
(1)
Symbol Parameter Test Conditions Min. Max. Unit
V
OH
(2)
Output High voltage IOH = –8 mA 2.4 - V
V
OL
Output Low voltage for 3.3V outputs IOL = 8 mA - 0.4 V
I
IL
Input leakage current VIN = GND or V
CC
–10 10 µA
I
IH
I/O High-Z leakage current VIN = GND or V
CC
–10 10 µA
I
CCSB
Standby current VCC = 3.6V - 100 µA
I
CC
Dynamic current
(3,4)
f = 1 MHz - 0.5 mA
f = 50 MHz - 15 mA
C
IN
Input pin capacitance
(5)
f = 1 MHz - 8 pF
C
CLK
Clock input capacitance
(5)
f = 1 MHz - 12 pF
C
I/O
I/O pin capacitance
(5)
f = 1 MHz - 10 pF
Notes:
1. See XPLA3 family data sheet (
DS012) for recommended operating conditions.
2. See Figure 2 for output drive characteristics of the XPLA3 family.
3. See Table 1, Figure 1 for typical values.
4. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and
unloaded. Inputs are tied to V
CC
or ground. This parameter guaranteed by design and characterization, not testing.
5. Typical values, not tested.
Figure 2: Typical I/V Curve for the XPLA3 Family
0
0
1
0
2
0
30
4
0
50
60
7
0
80
90
1
00
0.51.52.5.54.5
Volt
s
L
3.3V
)
H
3.3V
)
H
2.7V
)
DS012_10_04190
1
XCR3064XL 64 Macrocell CPLD
DS017 (v1.6) January 8, 2002 www.xilinx.com 3
Product Specification 1-800-255-7778
R
AC Electrical Characteristics Over Recommended Operating Conditions
(1,2)
Symbol Parameter
-6 -7 -10
Unit Min. Max. Min. Max. Min. M ax.
T
PD1
Propagation delay time (single p-term) - 5.5 - 7.0 - 9.1 ns
T
PD2
Propagation delay time (OR array)
(3)
- 6.0 - 7.5 - 10.0 ns
T
CO
Clock to output (global synchronous pin clock) - 4.0 - 5.0 - 6.5 ns
T
SUF
Setup time (fast input register) 2.5 - 2.5 - 3.0 - ns
T
SU1
(4)
Setup time (single p-term) 3.5 - 4.3 - 5.4 - ns
T
SU2
Setup time (OR array) 4.0 - 4.8 - 6.3 - ns
T
H
(4)
Hold time 0-0-0-ns
T
WLH
(4)
Global Clock pulse width (High or Low) 2.5 - 3.0 - 4.0 - ns
Tt
PLH
(4)
P-term clock pulse width 4 .0 - 5.0 - 6.0 - ns
T
R
(4)
Inpu t r ise ti me - 20 - 20 - 20 ns
T
L
(4)
Input fall time - 20 - 20 - 20 ns
f
SYSTEM
(4)
Maximum system frequency - 145 - 119 - 95 MHz
T
CONFIG
(4)
Configuration time
(5)
-60-60-60µs
T
INIT
(4)
ISP initialization time - 60 - 60 - 60 µs
T
POE
(4)
P-term OE to output enabled - 7.5 - 9.3 - 11.2 ns
T
POD
(4)
P-term OE to output disabled
(6)
- 7.5 - 9.3 - 11.2 ns
T
PCO
(4)
P-term clock to output - 6.5 - 8.3 - 10.7 ns
T
PAO
(4)
P-term set/reset to output valid - 8.0 - 9.3 - 11.2 ns
Notes:
1. Specification s mea sured with one output s wit ching.
2. See XPLA3 family data sheet (
DS012) for recommended operating conditions.
3. See Figure 4 for derating.
4. These parameters guaranteed by design and/or characterization, not testing.
5. Typical current draw during configur ation is 6 mA at 3.6V.
6. Output C
L
= 5 pF.
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