XILINX XC9572XV-5PC44C, XC9572XV-5CS48C, XC9572XV-4VQ44C, XC9572XV-4TQ100C, XC9572XV-4PC44C Datasheet

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Advance Product Specification 1-800-255-7778

© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Features

• 72 macrocells with 1,600 usable gates

• Available in small footprint packages

- 44-pin PLCC (34 user I/O pins)

- 44-pin VQFP (34 user I/O pins)

- 48-pin CSP (38 user I/O pins)

- 100-pin TQFP (72-user I/O pins)

• Optimized for high-perfo rmance 2.5V systems

- Low power operation

- Multi-voltage operation

• Advanced system features

- In-system programmable

- Two separate output banks

- Superior pin-locking and routability with
FastCONNECT II™ switch matrix

- Extra wide 54-input Function Blocks

- Up to 90 product-terms per macrocell with
individual product-term allocation

- Local clock inversion with three global and one
product-term clocks

- Individual output enable per output pin

- Input hysteresis on all user and boundary-scan pin
inputs

- Bus-hold ciruitry on all user pin inputs

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

• Fast concurrent programming

• Slew rate control on individual outputs

• Enhanced data security features

• Excellent quality and reliability

- Endurance exceeding 10,000 program/erase
cycles

- 20 year data retention

- ESD protection exceeding 2,000V

Description

The XC9572XV is a 2.5V CPLD targeted for high-perfor­mance, low-voltage applications in leading-edge communi­cations and computing systems. It is comprised of four
54V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 4 ns.

Power Estimation

Power dissipation in CPLDs can vary substantially depend­ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In ad di­tion, unused product-terms and macrocells are automati­cally deactivated by the software to further conserve power.

For a general estimate of I

CC

, the following equation may be

used:
I

CC

(mA) =

MC

HP

(0.36) + MCLP(0.23) + MC(0.005 mA/MHz) f

Where:

MC

HP

= Macrocells in high-performance (default) mode

MC

LP

= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)

This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I

CC

value varies
with the design application and should be verified during
normal system operation.

Figure 1 shows the above estimation in a graphical form.

0

XC9572XV High-performance
CPLD

DS052 (v2.2) August 27, 2001

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Advance Product Specification

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Figure 1: Typical ICC vs. Frequency for XC9572XV

Clock Frequency (MHz)

Typical I

CC

(mA)

0100200

DS052_01_012501

30

50

Lo

wPower

15050

10

70

90

High Performance

XC9572XV High-performance CPLD

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Figure 2: X C9572XV Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

In-System Programming Controller

JTAG

Controller

I/O

Blocks

Function

Block 1

Macrocells

1 to 18

Macrocells

1 to 18

Macrocells

1 to 18

Macrocells

1 to 18

JTAG Port

3

54

I/O/GTS

I/O/GSR

I/O/GCK

I/O

I/O

I/O

I/O

2

1

I/O

I/O

I/O

I/O

3

DS052_02_041200

1

Function

Block 2

54

Function

Block 3

54

Function

Block 4

54

18

18

18

18

FastCONNECT II Switch Matrix

XC9572XV High-performance CPLD

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Absolute Maximum Ratings

Recommended Operation Conditions

Quality and Reliability Characteristics

Symbol Description Value Units

V

CC

Supply voltage relative to GND –0.5 to 2.7 V

V

CCIO

Supply voltage for output drivers –0.5 to 3.6 V

V

IN

Input voltage relative to GND

(1)

–0.5 to 3.6 V

V

TS

Voltage applied to 3-state output

(1)

–0.5 to 3.6 V

T

STG

Storage temperature (ambient) –65 to +150

o

C

T

SOL

Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260

o

C

T

J

Junction temperature +150

o

C

Notes:

1. Maximum DC unders hoot bel ow GND must be l imit ed to ei ther 0. 5V or 10 mA , whi chever is easi er to a chie v e . During tr a nsitions , the
device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other cond itions beyond those listed under Oper ating Conditions
is not implied. Exposure to Absolute Maximum Ratings condition s for ext ended periods of time may affect device reliability.

Symbol Parameter Min Max Units

V

CCINT

Supply voltage for internal logic
and input buffers

Commercial TA = 0oC to +70oC2.372.62 V
Industrial T

A

= –40oC to +85oC2.372.62

V

CCIO

Supply voltage for output drivers for 3.3V operation 3.13 3.46 V
Supply voltage for output drivers for 2.5V operation 2.37 2.62 V
Supply voltage for output drivers for 1.8V operation 1.71 1.89 V

V

IL

Low-level input volt ag e 0 0.8 V

V

IH

High-level input voltage 1.7 3.6 V

V

O

Output voltage 0 V

CCIO

V

Symbol Parameter Min Max Units

T

DR

Data retention 20 - Years

N

PE

Program/Erase cycles (endurance) 10,000 - Cycles

V

ESD

Electrostatic Discharge (ESD) 2,000 - Volts

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DC Characteristics (Over Recommended Operating Conditions)

AC Characteristics

Symbol Parameter Test Conditions Min Max Units

V

OH

Output high voltage for 3.3V outputs IOH = –4.0 mA 2.4 - V
Output high voltage for 2.5V outputs I

OH

= –1.0 mA 2. 0 - V

Output high voltage for 1.8V outputs I

OH

= –100 µA 90% V

CCIO

-V

V

OL

Output low voltage for 3.3V outputs IOL = 8.0 mA - 0.4 V
Output low voltage for 2.5V outputs I

OL

= 1.0 mA - 0.4 V

Output low voltage for 1.8V outputs I

OL

= 100 µA-0.4V

I

IL

Input leakage low current VCC = 2.62V

V

CCIO

= 3.6V

V

IN

= GND or 3.6V

-10µA

I

IH

Input leakagehigh current VCC = 2.62V

V

CCIO

= 3.6V

V

IN

= GND or 3.6V

-10µA

C

IN

I/O capacitance VIN = GND

f = 1.0 MHz

-10pF

I

CC

Operating Supply Current
(low power mode, active)

VI = GND, No load
f = 1.0 MHz

14 mA

Symbol Parameter

XC9572XV-4 XC9572XV-5 XC9572XV-7

UnitsMin Max Min Max Min Max

T

PD

I/O to output valid - 4.0 - 5.0 - 7 .5 ns

T

SU

I/O setup time before GCK 2.8 - 3.5 - 4.8 - ns

T

H

I/O hold time after GCK 0 - 0 - 0 - ns

T

CO

GCK to outpu t valid - 2.8 - 3.5 - 4.5 ns

f

SYSTEM

Multiple FB internal operating
frequency

- 250.0 - 222.2 - 125.0 MHz

T

PSU

I/O setup time before p-term clock
input

0.8 - 1.0 - 1.6 - ns

T

PH

I/O hold time after p-term clock input 2.0 - 2.5 - 3.2 - ns

T

PCO

P-term clock output valid - 4.8 - 6.0 - 7 .7 ns

T

OE

GTS to o u tput vali d - 3.2 - 4.0 - 5.0 ns

T

OD

GTS to output disable - 3.2 - 4.0 - 5 .0 ns

T

POE

Product term OE to output enabled - 5.6 - 7.0 - 9.5 ns

T

POD

Product term OE to output disabled - 5.6 - 7.0 - 9.5 ns

T

AO

GSR to output valid - 7.9 - 10.0 - 12.0 ns

T

PAO

P-term S/R to output valid - 8.5 - 10. 7 - 12.6 ns

T

WLH

GCK pulse width (High or Low) 2.0 - 2.2 - 4.0 - ns

T

PLH

P-term clock pulse width (High or Low) 5.0 - 5.0 - 6.5 - ns

Advance Information Prelim inary Information

Notes:

1.

Please c on t ac t X ilin x for up-to-date infor mation on ad vanc e specificat ions.

XC9572XV High-performance CPLD

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Internal Timing Parameters

Figure 3: AC Load Circuit

R

1

V

TEST

C

L

R

2

Device Output

Output Type V

TEST

3.3V

2.5V

1.8V

R

1

320Ω
250Ω

10KΩ

R

2

360Ω
660Ω

14KΩ

C

L

35 pF
35 pF
35 pF

DS051_03_0601000

V

CCIO

3.3V

2.5V

1.8V

Symbol Parameter

XC9572XV-4 XC9572XV-5 XC9572XV-7

UnitsMin Max Min Max Min Max

Buffer Delays

T

IN

Input buffer delay - 1.6 - 2.0 - 2.3 ns

T

GCK

GCK buffer delay - 1.0 - 1.2 - 1.5 ns

T

GSR

GSR buffer delay - 1.6 - 2.0 - 3.1 ns

T

GTS

GTS buffer delay - 3.2 - 4.0 - 5.0 ns

T

OUT

Output buffer delay - 1.6 - 2.1 - 2.5 ns

T

EN

Output buffer enable/disable delay - 0 - 0 - 0 ns

Product Term Control Delays

T

PTCK

Product term clock delay - 1.4 - 1.7 - 2.4 ns

T

PTSR

Product term set/reset delay - 0.6 - 0.7 - 1.4 ns

T

PTTS

Product term 3-state delay - 4.0 - 5.0 - 7.2 ns

Internal Register and Combinatorial Delays

T

PDI

Combinatorial logic propagation delay - 0.2 - 0.2 - 1.3 ns

T

SUI

Register setup time 1.6 - 2.0 - 2.6 - ns

T

HI

Register hold time 1.2 - 1.5 - 2.2 - ns

T

ECSU

Register clock enable setup time 1.6 - 2.0 - 2.6 - ns

T

ECHO

Register clock enable hold time 1.2 - 1.5 - 2.2 - ns

T

COI

Register clock to output valid time - 0. 2 - 0.2 - 0. 5 ns

T

AOI

Register async. S/R to output delay - 4.7 - 5. 9 - 6.4 ns

T

RAI

Register async. S/R recover before clock 4.0 5.0 7.5 ns

T

LOGI

Internal logic delay - 0.6 - 0.7 - 1.4 ns

T

LOGILP

Internal low power logic delay - 5.6 - 5.7 - 6.4 ns

Feedback Delays

T

F

FastCONNECT II™ feedback delay - 1.6 - 1.6 - 3.5 ns

Time Adders

T

PTA

Incremental product term allocator delay - 0.6 - 0.7 - 0.8 ns

T

PTA2

Adjacent macrocell p-term allocator delay - 0.2 - 0.3 - 0. 3 ns

T

SLEW

Slew-rate limited delay - 3.0 - 3.0 - 4.0 ns

Advance Information Preliminary Information

Notes:

1.

Please c on t ac t X ilin x for up-to-date infor mation on ad vanc e specificat ions.

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XC9572XV I/O Pins

Function

Block

Macro-

cell

PC44 VQ44 CS48 TQ100

BScan

Order

Function

Block

Macro-

cell

PC44 VQ44 CS48 TQ100

BScan

Order

1 1 - - - 16 213 3 1 - - - 41 105
1 2 139D7 13 210 3 2 11 5 B5 32 102
1 3 --D4 18 207 3 3 --C4 49 99
1 4 --- 20 204 3 4 ---5096
1 5 240D6 14 201 3 5 12 6 A4 35 93
1 6 341C7 15 198 3 6 ---5390
1 7 --- 25 195 3 7 ---5487
1 8 442C6 17 192 3 8 13 7 B4 37 84
1 9 5

(1)

43

(1)

B7

(1)

22

(1)

189 3 9 14 8 A3 42 81
1 10 --- 28 186 3 10 --D3 60 78
1 11 6

(1)

44

(1)

B6

(1)

23

(1)

183 3 11 18 12 B2 52 75
1 12 --- 33 180 3 12 ---6172
1 13 --- 36 177 3 13 ---6369
1 14 7

(1)

1

(1)

A7

(1)

27

(1)

174 3 14 19 13 B1 55 66
1 15 82A6 29 171 3 15 20 14 C2 56 63
1 16 --- 39 168 3 16 24 18 D2 64 60
1 17 93C5 30 165 3 17 22 16 C3 58 57
1 18 - - - 40 162 3 18 - - - 59 54
2 1 - - - 87 159 4 1---6551
2 2 35 29 F4 94 156 4 22519E16748
2 3 - - - 91 153 4 3---7145
2 4 - - - 93 150 4 4---7242
2 5 36 30 G5 95 147 4 52620E26839
2 6 37 31 F5 96 144 4 6--E47636
2 7 ---3

(2)

141 4 7---7733
2 8 38 32 G6 97 138 4 8 2721F1 70 30
2 939

(1)

33

(1)

G7

(1)

99

(1)

135 4 9---6627
2 10 - - - 1 132 4 10 - - - 81 24
2 11 40

(1)

34

(1)

F6

(1)

4

(1)

129 4 11 28 22 G1 74 21
2 12 - - - 6 126 4 12 - - - 82 18
2 13 - - - 8 123 4 13 - - - 85 15
2 14 42

(3)

36

(3)

E6

(3)

9

(3)

120 4 14 29 23 F2 78 12
2 15 43 37 E7 11 117 4 15 33 27 E3 89 9
2 16 - - - 10 114 4 16 - - - 86 6
2 17 44 38 E5 12 111 4 17 34 28 G4 90 3
2 18 - - - 92 108 4 18 - - - 79 0

Notes:

1. Global contro l pi n.

2. GTS1 for TQ100

3. GTS1 for PC44, CS48, VQ44

XC9572XV High-performance CPLD

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XC9572XV Global, JTAG and Power Pins

Pin Type PC44 VQ44 CS48 TQ100

I/O/GCK1 5 43 B7 22
I/O/GCK2 6 44 B6 23
I/O/GCK3 7 1 A7 27

I/O/GTS1 42 36 E6 3
I/O/GTS2 40 34 F6 4

I/O/GSR 39 33 G7 99

TCK 17 11 A1 48

TDI 15 9 B3 45
TDO 30 24 G2 83
TMS 16 10 A2 47

V

CCINT

2.5V 21, 41 15, 35 C1, F7 5, 57, 98

V

CCIO

1.8/2.5V/3.3V 32 26 G3 26, 38, 51, 88
GND 10, 23, 31 4, 17, 25 A5, D1, F3 21, 31, 44, 62, 69, 75,

84, 100

No Connects - - - 2, 7, 19, 24, 34, 43,

46, 73, 80

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Ordering Information

Component Availability

Revision History

Pins 44 44 48 100

Type Plastic PLCC Plastic VQFP Plastic CSP Pl astic TQFP

Code PC44 VQ44 CS48 TQ100

XC9572XV -7 C, I C, I C, I C, I

-5 C C C C

-4 (C) (C) - (C)

Notes:

1. C = Commercial (T

A

= 0oC to +70oC); I = Industrial (TA = –40oC to +85oC).

2. ( ) Parenthesis indicate future planned products. Please contact Xilinx for up-to-date information.

Date Revision No. Description

02/01/00 1.1 Initial Xilinx release. Advance information specification.
01/29/01 2.0 Added -4 performance specification and VQ44 pagkage. Deleted VQ64 package.

Updated I

CC

vs. Frequency Figure 1.

05/15/01 2.1 Updated I

CC

formula, Recommended Operation Conditions, -4 and -5 AC

Characteristics and Internal Timing Parameters

08/27/01 2.2 Changed V

CCIO

3.3V from 3.13 to 3.0 (min), 3.46 to 3.60 (max); DC characteristics: IIL

- added "low" current, I

IH

- changed to "Input leakage high current"; Internal Timing: -5

T

AOI

from 6.5 to 5.9.

XC9572XV -7 TQ 100 C

Example:

Temperature Range
Number of Pins
Package Type

Device Type
Speed Grade

Device Ordering Options

Speed Package Temperature

-7 7.5 ns pin-to-pi n delay PC44 44-pin Plastic Lead Chi p Carrier (PLCC) C = Commercial T

A

= 0°C to +70°C

-5 5 ns pin-to-pin del ay VQ44 44-pin Very Thin Quad Flat P ack (VQFP) I = Industrial T

A

= –40°C to +85 °C

-4 4 ns pin-to-pin del ay CS48 48-ball Chip Scale Package (CSP)

TQ100 100-pin Thin Quad Flat Pack (TQFP)