XILINX XC9572XL Product Specification

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DS057 (v1.1) August 28, 2000

Features

• 5 ns pin- t o-pin log ic delays

• System frequency up to 178 MHz

• 72 macrocells with 1,600 usable gates

• Available in small footprint packages

- 44-pin PLCC (34 user I/O pins)

- 44-pin VQFP (34 user I/O pins)

- 48-pin CSP (38 user I/O pins)

- 64-pin VQFP (52 user I/O pins)

- 100-pin TQFP (72 user I/O pins)

• Optimized for hi gh-performance 3.3V systems

- Low power operation

- 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V
signals

- 3.3V or 2.5V output capabilit y

- Advanced 0.35 micron feature size CMOS
FastFLASH™ technology

• Advanced system features

- In-system programmable

- Superior pin-locking and routability with
FastCONNECT II™ switch matrix

- Extra wide 54-input Function Blocks

- Up to 90 product-term s per macroc ell with
individual product-term allocation

- Local clock inversion with three global and one
product-term clocks

- Individual output enable per output pin

- Input hysteresis on all user and boundary-scan pin
inputs

- Bus-hold circuitry on all user pin inputs

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

• Fast concurrent programming

• Slew rate control on individual outputs

• Enhanced data security features

• Excellent quality and reliability

- Endurance exceeding 10,000 program/erase
cycles

- 20 year data retention

- ESD protection exceeding 2,000V

• Pin-compatible with 5V-core XC9572 device in the
44-pin PLCC package and the 100-pin TQFP package

05

XC9572XL High Performance
CPLD

Preliminary Product Specification

cations and computing systems. It is comprised of four
54V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 5 ns. See Figure 2 for architecture
overview.

Power Estimation

Power dissipation in CPLDs can vary substantially depend­ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In ad di­tion, unused product-terms and macrocells are automati­cally deactivated by the software to further conserve power.

For a general estimate of I
used:

I

(mA) = MCHP(0.5) + MCLP(0.3) + MC(0.0045 mA/MHz) f

CC

Where:

= Macrocells in high-performance (default) mode

MC

HP

= Macrocells in low-power mode

MC

LP

MC = Total number of macrocells used
f = Clock frequency (MHz)

This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
with the design application and should be verified during
normal system operation.

Figure 1 shows the above estimation in a graphical form.

100

80

60

(mA)

CC

Typical I

High Performance

40

Low Power

20

, the following equation may be

CC

value varies

CC

178 MHz

104 MHz

Description

The XC9572XL is a 3.3V CPLD targeted for high-perfor­mance, low-voltage applications in leading-edge communi-

© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS057 (v1.1) August 28, 2000 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778

Figure 1: Typi cal ICC vs. Frequency for XC9572XL

0 100 200

50 150

Clock Frequency (MHz)

DS057_01_08150

XC9572XL High Performance CPLD

R

JTAG Port

I/O/GCK

I/O/GSR

I/O/GTS

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

3

1

JTAG

Controller

In-System Programming Controller

54

18

Function

Block 1

Macrocells

1 to 18

54

18

Function

Block 2

Macrocells

I/O

1 to 18

Blocks

54

18

Function

Block 3

Macrocells

FastCONNECT II Switch Matrix

1 to 18

3

1

18

2

54

Function

Block 4

Macrocells

1 to 18

Figure 2: XC9572XL Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

DS057_02_082800

2 www.xilinx.com DS057 (v1.1) August 28, 2000

1-800-255-7778 Preliminary Product Specification

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XC9572XL High Performance CPLD

Absolute Maximum Ratings

Symbol Description Value Units

V

CC

V

IN

V

TS

T

STG

T

SOL

T

J

Notes:

1. Maximum DC under shoot bel ow GND mus t be l imite d to ei ther 0 .5V or 10 mA, whiche ve r i s easi er to achie v e . During t ransi t ions , the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings onl y, and functional operat ion of the device at these or any other condition s beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliab ility.

Supply voltage relative to GND –0.5 to 4.0 V
Input voltage relative to GND
Voltage applied to 3-state output
Storage temperature (ambient) –65 to +150
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260
Junction temperature +150

(1)

(1)

–0.5 to 5.5 V
–0.5 to 5.5 V

o
o
o

C
C
C

Recommended Operation Conditions

Symbol Parameter Min Max Units

V

CCINT

V

CCIO

V

V

V

Supply voltage for internal logic
and input buffers

Supply voltage for output drivers fo r 3.3V operation 3.0 3.6 V
Supply voltage for output drivers fo r 2.5V operation 2.3 2.7 V

IL

IH

O

Low-level input voltage 0 0.80 V
High-level input voltage 2.0 5.5 V
Output voltage 0 V

Comme r c ial TA = 0oC to 70oC3.0 3.6 V
Industrial T

= –40oC to +85oC3.0 3.6 V

A

CCIO

V

Quality and Reliability Characteristics

Symbol Parameter Min Max Units

Data Retention 20 - Years
Program/Erase Cycles (Endurance) 10,000 - Cycles
Electrostatic Discharge (ESD) 2,000 - Volts

V

T
N

ESD

DR

PE

DC Characteristic Over Recommended Operating Conditions

Symbol Parameter Test Conditions Min Max Units

V

OH

V

OL

I

IL

I

IH

C

IN

I

CC

Output high voltage for 3.3V outputs IOH = –4.0 mA 2.4 V
Output high voltage for 2.5V outputs I

= –500 µA90% V

OH

CCIO

Output low voltage for 3.3V outputs IOL = 8.0 mA - 0.4 V
Output low voltage for 2.5V outputs I
Input leakage current VCC = Max

I/O high- Z leakage c urre nt VCC = Max

I/O capacitance VIN = GND

= 500 µA-0.4V

OL

-±10µA

V

= GND or V

IN

CC

-±10µA

V

= GND or V

IN

CC

-10pF

f = 1.0 MHz

Operating supply current
(low power mode, active)

VI = GND, No load
f = 1.0 MHz

20 (Typical) mA

V

DS057 (v1.1) August 28, 2000 www.xilinx.com 3

Preliminary Product Specification 1-800-255-7778

XC9572XL High Performance CPLD

AC Characteristics

XC9572XL-5 XC9572XL-7 XC9572XL-10

Symbol Parameter

T

PD

T

SU

T

H

T

CO

f

SYSTEM

T

PSU

T

PH

T

PCO

T

OE

T

OD

T

POE

T

POD

T

AO

T

PAO

T

WLH

T

PLH

Notes:

1. Please contact Xili nx for up-to-date information on advance specific ati ons.

I/O to output valid - 5.0 - 7.5 - 10.0 ns
I/O setup time before GCK 3.7 - 4.8 - 6.5 - ns
I/O hold time after GCK 0.0 - 0.0 - 0.0 - ns
GCK to output valid - 3.5 - 4.5 - 5.8 ns
Multiple FB internal operating frequency - 178.6 - 125.0 - 100.0 MHz
I/O setup time before p-term clock input 1.7 - 1.6 - 2.1 - ns
I/O hold time after p-term clock input 2.0 - 3.2 - 4.4 - ns
P-term clock output valid - 5.5 - 7.7 - 10.2 ns
GTS to output valid - 4.0 - 5.0 - 7.0 ns
GTS to output disable - 4.0 - 5.0 - 7.0 ns
Product term OE to output enabled - 7.0 - 9.5 - 11.0 ns
Product term OE to output disabled - 7.0 - 9.5 - 11.0 ns
GSR to output valid - 10.0 - 12.0 - 14.5 ns
P-term S/R to output valid - 10.5 - 12 .6 - 15.3 ns
GCK pulse width (High or Low) 2.8 - 4.0 - 4.5 - ns
P-term clock pulse width (High or Low) 5.0 - 6.5 - 7.0 - ns

(1)

Advance Preliminary

Max

(1)

Min Max Min Max

R

UnitsMin

Device Output

V

TEST

R

1

R

2

C

L

Output Type V

V

CCIO

3.3V

2.5V

TEST

3.3V

2.5V

R

1

320 Ω

250 Ω

R

2

360 Ω

660 Ω

C

L

35 pF

35 pF

DS058_03_081500

Figure 3: AC Load Circuit

4 www.xilinx.com DS057 (v1.1) August 28, 2000

1-800-255-7778 Preliminary Product Specification

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Internal Timing Parameters

XC9572XL-5 XC9572XL-7 XC9572XL-10
Symbol Parameter
Buffer Delays

Input buffer delay - 1.5 - 2.3 - 3.5 ns

IN

GCK buffer delay - 1.1 - 1.5 - 1.8 ns
GSR buffer delay - 2.0 - 3.1 - 4.5 ns
GTS buffer delay - 4.0 - 5.0 - 7.0 ns
Output buffer delay - 2.0 - 2.5 - 3.0 ns
Output buffer enable/disable

T
T
T
T

T

T

GCK
GSR
GTS
OUT

EN

delay

Product Term Control Delays

T
T

T

PTCK
PTSR
PTTS

Product term clock delay - 1.6 - 2.4 - 2.7 ns
Prod u c t te rm set/re set del ay - 1.0 - 1.4 - 1.8 ns
Product term 3-state delay - 5.5 - 7.2 - 7.5 ns

Internal Register and Combinatorial Delays

T

PDI

T

SUI

T

T

ECSU

T

ECHO

T

COI

T

AOI

T

RAI

T

LOGI

T

LOGILP

Combinatorial logic propagation delay - 0.5 - 1.3 - 1.7 ns
Register setup time 2.3 - 2.6 - 3.0 - ns
Register hold time 1.4 - 2.2 - 3.5 - ns

HI

Register clock enable setup time 2.3 - 2.6 - 3. 0 - ns
Register clock enable hold time 1.4 - 2.2 - 3. 5 - ns
Register clock to output valid time - 0.4 - 0.5 - 1.0 ns
Register async. S/R to output delay - 6.0 - 6.4 - 7.0 ns
Register async. S/R recover before clock 5.0 7.5 10.0 ns
Internal logic delay - 1.0 - 1.4 - 1.8 ns
Internal low power logic delay - 5.0 - 6.4 - 7.3 ns

Feedback Delays

T

FastCONNECT II feedback delay - 1.9 - 3.5 - 4.2 ns

F

Time Adders

T

PTA

T

SLEW

Notes:

1.

Please c on t ac t X ilin x for up- t o- da te informati o n o n a dvan c e specificat ions.

Incremental product term allocator delay - 0.7 - 0.8 - 1.0 ns
Slew-rate limited delay - 3.0 - 4.0 - 4.5 ns

(1)

Max

- 0.0 - 0.0 - 0.0 ns

Advance Preliminary

XC9572XL High Performance CPLD

(1)

MinMaxMinMax

UnitsMin

DS057 (v1.1) August 28, 2000 www.xilinx.com 5

Preliminary Product Specification 1-800-255-7778

XC9572XL High Performance CPLD

XC9572XL I/O Pins

R

Func-

tion

Block

Macro-

cell PC44 VQ44 CS48 VQ64 TQ100

BScan

Order

Func

-tion

Block

Macro-

cell PC44 VQ44 CS48 VQ64 TQ100

BScan

Order

1 1 ----16213 3 1 ----41105
1 2 1 39 D7 8 13 210 3 2 11 5 B5 22 32 102
1 3 - - D4 12 18 207 3 3 - - C4 31 49 99
1 4 - - - 13 20 204 3 4 - - - 32 50 96
1 5 2 40 D6 9 14 201 3 5 12 6 A4 24 35 93
1 6 3 41 C7 10 15 198 3 6 - - - 34 53 90
1 7 ----25195 3 7 ----5487
18442C6111719238137B4253784
195

(1)

43

(1)

B7

(1)

15

(1)

22

(1)

189 3 9 14 8 A3 27 42 81
1 10 - - - 18 28 186 3 10 - - D3 39 60 78
1116

(1)

44

(1)

B6

(1)

16

(1)

23

(1)

183 3 11 1812B23352 75
1 12 - - - 23 33 180 3 12 - - - 40 61 72
1 13----36177 3 13----6369
1147

(1)

(1)

1

A7

(1)

17

(1)

27

(1)

174 3 14 1913B13555 66
11582A61929171 3152014C2365663
1 16----39168 3 162418D2426460
1 17 9 3 C52030165 3 17 2216C33858 57
1 18----40162 3 18----5954
2 1 ----87159 4 1 ----6551
2 2 35 29 F4 60 94 156 4 2 25 19 E1 43 67 48
2 3 - - - 58 91 153 4 3 - - - 46 71 45
2 4 - - - 59 93 150 4 4 - - - 47 72 42
2 5 36 30 G5 61 95 147 4 5 26 20 E2 44 68 39
2 6 37 31 F5 62 96 144 4 6 - - E4 49 76 36
2 7 ----3

(2)

141 4 7 ----7733
2 8 38 32 G6 63 97 138 4 8 27 21 F1 45 70 30
2939

(1)

33

(1)

G7

(1)

64

(1)

99

(1)

135 4 9 ----6627
2 10 - - - 1 1 132 4 10 - - - 51 81 24
21140

(1)

34

(1)

(1)2(1)

F6

(1)

4

129 4 11 2822G14874 21
2 12 - - - 4 6 126 4 12 - - - 52 82 18
2 13----8123 4 13----8515
21442

(3)

36

(3)

(3)5(3)

E6

(3)

9

120 4 14 2923F25078 12
2 15 4337E7 6 11117 4 15 3327E35689 9
2 16----10114 4 16----866
2 17 44 38 E5 7 12 111 4 17 34 28 G4 57 90 3
2 18----92108 4 18----790

Notes:

1. Global contro l pi n.

2. GTS1 for TQ100 .

3. GTS1 for PC44, VQ44, CS48, and VQ64.

6 www.xilinx.com DS057 (v1.1) August 28, 2000

1-800-255-7778 Preliminary Product Specification

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XC9572XL High Performance CPLD

XC9572XL Global, JTAG and Power Pins

Pin Type PC 44 VQ44 CS48 VQ 64 TQ100

I/O/GCK1 5 43 B7 15 22
I/O/GCK2 6 44 B6 16 23
I/O/GCK3 7 1 A7 17 27

I/O/GTS1 42 36 E6 5 3
I/O/GTS2 40 34 F6 2 4

I/O/GSR 39 33 G7 64 99

TCK 1711A13048

TDI 15 9 B3 28 45
TDO 3024G25383
TMS 1610A22947

3.3V 21, 41 15, 35 C1, F7 3, 37 5, 57, 98

V

CCINT

2.5V/3.3V 32 26 G3 26, 55 26, 38, 51, 88

V

CCIO

GND 10, 23, 31 4, 17, 25 A5, D1, F3 14, 21, 41, 54 21, 31, 44, 62,

69, 75, 84, 100

No Connects----2, 7, 19, 24, 34,

43, 4 6 , 7 3 , 8 0

DS057 (v1.1) August 28, 2000 www.xilinx.com 7

Preliminary Product Specification 1-800-255-7778

XC9572XL High Performance CPLD

Ordering Information

R

Example:

Device Type
Speed Grade

XC9572XL -7 TQ 100 C

Tempera ture Range
Number of Pins
Package Type

Device Ordering Options

Speed Package Temperature

-10 10 ns pin-to-pin delay PC44 44-p in Plas tic Lea d Chip Carrier (PLCC) C = Commercial T

-7 7.5 ns pin-to-pin delay VQ44 44-pin Quad Flat Pack (VQFP) I = Industrial T

-5 5 ns pin-to-pin del ay CS48 48-pin Chip Scale Package
VQ64 64-pin Quad Flat P ack (VQFP)

TQ100 100-pin Thin Quad Flat Pac k (TQFP)

Component Availability

Pins 44 44 48 64 100

Plastic

Type

PLCC

Code PC44 VQ44 CS48 VQ64 TQ100

XC9572XL

-10 C, I C, I - C, I C, I

-7 C, I C, I C C, I C, I

-5 (C) (C) - (C) (C)

Notes:

1. C = Commercial (T

2. ( ) Parenthesis indicate future products. Please contact Xilinx for up-to-date information.

= 0oC to +70oC); I = Industrial (TA = –40oC to +85oC)

A

Plastic

VQFP

Plastic

CSP

Plastic

VQFP

= 0°C to + 70°C

A

= –40°C to + 85°C

A

Plastic

TQFP

Revision History

The following table shows the revision history for this document.

Date Version Revision

09/28 /98 1.0 I nitial Xilinx r ele as e .
08/28/00 1.1 A dded VQ44 package.

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1-800-255-7778 Preliminary Product Specification