XILINX XC95288XV Product Specification

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R

DS050 (v2.2) August 27, 2001

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Features

• 288 macrocells with 6,400 usable gates

• Available in small footprint packages

- 144-pin TQFP (117 user I/O pins)

- 208-pin PQFP (168 user I/O pins)

- 280-pin CSP (192 user I/O pins)

- 256-pin FBGA (192 user I/O pins)

• Optimized for high-perfo rmance 2.5V systems

- Low power operation

- Multi-voltage operation

• Advanced syste m features

- In-system programmable

- Four separate output banks

- Superior pin-locking and routability with
FastCONNECT II™ switch matrix

- Extra wide 54-input Function Blocks

- Up to 90 product-terms per macrocell with
individual product-term allocation

- Local clock inversion with three global and one
product-term clocks

- Individual output enable per output pin

- Input hysteresis on all user and boundary-scan pin
inputs

- Bus-hold ciruitry on all user pin inputs

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

• Fast concurrent programming

• Slew rate control on individual outputs

• Enhanced data security features

• Excellent quality and reliability

- Endurance exceeding 10,000 program/erase
cycles

- 20 year data retention

- ESD protection exceeding 2,000V

Description

The XC95288XV is a 2.5V CPLD targeted for high-perfor­mance, low-voltage applications in leading-edge communi­cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 5 ns.

XC95288XV High-Performance
CPLD

Advance Product Specification

Power Estimation

Power dissipation in CPLDs can vary substantially depend­ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In ad di­tion, unused product-terms and macrocells are automati­cally deactivated by the software to further conserve power.

For a general estimate of I
used:

(mA ) =

I

CC

(0.36) + MCLP(0.23) + MC(0.005 mA/MHz) f

MC

HP

Where:
MC

= Macrocells in high-performance (default) mode

HP

= Macrocells in low-power mode

MC

LP

MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions

using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
with the design application and should be verified during
normal system operation.

Figure 1 shows the above estimation in a graphical form.

450

400

350

300

(mA)

250

CC

200

Typical I

150

100

50

0

e

gh P

i

H

Low Powe

50 150

, the following equation may be

CC

value varies

CC

nce

a

form

r

120 MHz

r

100 200 250

Clock Frequency (MHz)

200 MHz

DS050_01_012501

Figure 1: Typical I

© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS050 (v2.2) August 27, 2001 www.xilinx.com 1

Advance Product Specificati on 1-800-255-7778

vs. Frequency for XC95288XV

CC

XC95288XV High-Performance CPLD

R

JTAG Port

I/O/GCK
I/O/GSR

I/O/GTS

I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O

3

1

JTAG

Controller

In-System Programming Controller

54

18

Function

Block 1

Macrocells

1 to 18

54

18

Function

Block 2

Macrocells

I/O

1 to 18

Blocks

54

18

Function

Block 3

Macrocells

FastCONNECT II Switch Matrix

1 to 18

3
1

18

4

54

Function

Block 4

Macrocells

1 to 18

54

18

Function
Block 16

Macrocells

1 to 18

DS055_02_101300

Figure 2: XC9528 8X V Architecture

(Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.)

2 www.xilinx.com DS050 (v2.2) August 27, 2001

1-800-255-7778 Advance Product Specification

R

XC95288XV High-Performance CPLD

Absolute Maximum Ratings

Symbol Description Value Units

V

CC

V

CCIO

V

IN

V

TS

T

STG

T

SOL

T

J

Notes:

1. Maximum DC unders hoot bel ow GND must be l imit ed to ei ther 0. 5V or 10 m A, whi chever is easi er to a chie v e . Durin g tra nsitions , the
device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings onl y, and functional operation of t he device at these or any other condit ions beyond those list ed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliab ility.

Supply voltage relative to GND –0.5 to 2.7 V
Supply voltage for output drivers –0.5 to 3.6 V
Input voltage relative to GND
Voltage applied to 3-state output
Storage temperature (ambient) –65 to +150
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260
Junction temperature +150

(1)

(1)

–0.5 to 3.6 V
–0.5 to 3.6 V

o
o
o

C
C
C

Recommended Operation Conditions

Symbol Parameter Min Max Units

V

CCINT

V

CCIO

Supply voltage for internal logic
and input buffers

Supply voltage for output drivers for 3.3V operation 3.13 3.46 V
Supply voltage for output drivers for 2.5V operation 2.37 2.62 V

Commercial TA = 0oC to +70oC2.372.62 V
Industrial T

= –40oC to +85oC2.372.62

A

Supply voltage for output drivers for 1.8V operation 1.71 1.89 V

V

IL

V

IH

V

O

Low-level input volt ag e 0 0.8 V
High-level input voltage 1.7 3.6 V
Output voltage 0 V

CCIO

Quality and Reliability Characteristics

Symbol Parameter Min Max Units

V

T
N

ESD

DR

PE

Data retention 20 - Years
Program/Erase cycles (endurance) 10,000 - Cycles
Electrostatic Discharge (ESD) 2,000 - Volts

V

DS050 (v2.2) August 27, 2001 www.xilinx.com 3

Advance Product Specificati on 1-800-255-7778

XC95288XV High-Performance CPLD

DC Characteristics Over Recommended Operating Conditions

Symbol Parameter Test Conditions Min Max Units

R

V

OH

Output high voltage for 3.3V outputs IOH = –4.0 mA 2.4 - V
Output high voltage for 2.5V outputs I
Output high voltage for 1.8V outputs I

V

OL

Output low voltage for 3.3V outputs IOL = 8.0 mA - 0.4 V
Output low voltage for 2.5V outputs I
Output low voltage for 1.8V outputs I
Input leakagelow current VCC = 2.62V

Input leakage high current VCC = 2.62V

I/O capacitance VIN = GND

Operating Supply Current

C

I

I

I

CC

IL

IH

IN

(low power mode, active)

AC Characteristics

XC95288XV-5 XC95288XV-7 XC95288XV-10

Symbol Parameter

T

PD

T

SU

T

T

CO

f

SYSTEM

T

PSU

T

PH

T

PCO

T

OE

T

OD

T

POE

T

POD

T

AO

T

PAO

T

WLH

T

PLH

Notes:

1.

Please c on t ac t X ilin x for up- t o- da te informati o n o n a dvan c e specificat ions.

I/O to output valid - 5.0 - 7.5 - 10 ns
I/O setup time before GCK 3.5 - 4.8 - 6.5 - ns
I/O hold time after GCK 0 - 0 - 0 - ns

H

GCK to output valid - 3.5 - 4.5 - 5.8 ns
Multiple FB internal operating

- 222.2 - 125.0 - 100.0 MHz

frequency
I/O setup time before p-term clock

1.0 - 1.6 - 2.1 - ns

input
I/O hold time after p-term clock input 2.5 - 3.2 - 4.4 - ns
P-term clock output valid - 6.0 - 7.7 - 10.2 ns
GTS to output valid - 4.0 - 5 .0 - 7.0 ns
GTS to output disable - 4.0 - 5 .0 - 7.0 ns
Product term OE to output enabled - 7.0 - 9.5 - 11.0 ns
Product term OE to output disabled - 7.0 - 9.5 - 11.0 ns
GSR to output valid - 10.0 - 12.0 - 14.5 ns
P-term S/R to output valid - 10.7 - 12.6 - 15.3 ns
GCK pulse width (High or Low) 2.2 - 4.0 - 5.0 - ns
P-term clock pulse width (High or Low) 5.0 - 6.5 - 7.0 - ns

Advance Information Preliminary Information

= –1.0 mA 2.0 - V

OH

= –100 µA90%

OH

= 1.0 mA - 0.4 V

OL

= 100 µA-0.4V

OL

V

CCIO

-V

-10µA

V

= 3.6V

CCIO

V

= GND or 3.6V

IN

-10µA

V

= 3.6V

CCIO

V

= GND or 3.6V

IN

-10pF

f = 1.0 MHz
VI = GND, No load

59 mA

f = 1.0 MHz

UnitsMin Max Min Max Min Max

4 www.xilinx.com DS050 (v2.2) August 27, 2001

1-800-255-7778 Advance Product Specification