XICOR X1205V8I, X1205V8, X1205S8I, X1205S8 Datasheet

Preliminary Information

New Features

Repetitive Alarms &

Temperature Compensation

Real Time Clock/Calendar

FEATURES

• Real Time Clock/Calendar
—Tracks time in Hours, Minutes, and Seconds
—Day of the Week, Day, Month, and Year

• 2 Polled Alarms (Non-volatile)
—Settable on the Second, Minute, Hour, Day of

the Week, Day, or Month

—Repeat Mode (periodic interrupts)

• Oscillator Compensation on chip
—Internal feedback resistor and compensation

capacitors
—64 position Digitally Controlled Trim Capacitor
—6 digital frequency adjustment settings to

±30ppm

• Battery Switch or Super Cap Input

• 2-Wire™ Interface interoperable with I2C*
—400kHz data transfer rate

• Low Power CMOS
—1.25µA Operating Current (Typical)

• Small Package Options
—8-Lead SOIC and 8-Lead TSSOP

APPLICATIONS

• Utility Meters

• HVAC Equipment

• Audio / Video Components

• Set Top Box / Television

X1205

• Modems

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

• Pagers / PDA

• POS Equipment

• Test Meters / Fixtures

• Office Automation (Copiers, Fax)

• Home Appliances

• Computer Products

• Other Industrial / Medical / Automotive

DESCRIPTION

The X1205 device is a Real Time Clock with clock/
calendar, two polled alarms, oscillator compensation,
and battery backup switch.

The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.

The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, and Seconds. The
Calendar has separate registers for Date, Month, Year
and Day-of-week. The calendar is correct through
2099, with automatic leap year correction.

2-Wire

™

RTC

BLOCK DIAGRAM

32.768kHz

SCL

SDA

*I2C is a Trademark of Philips.

REV 1.0.9 8/29/02

Serial
Interface
Decoder

IRQ

OSC

Compensation

X1

X2

Oscillator

Frequency

Divider

1Hz

PRELIMINARY

Control

Decode

Logic

8

Control

Registers

(EEPROM)

Interrupt Enable

www.xicor.com

Status

Registers

(SRAM)

Alarm

Timer

Calendar

Logic

Alarm

Alarm

Characteristics subject to change without notice.

Keeping

Registers

(SRAM)

Compare

Alarm Regs

(EEPROM)

Mask

Time

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.

X1205 – Preliminary Information

DESCRIPTION (continued)

The powerful Dual Alarms can be set to any Clock/
Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide
a hardware interrupt (IRQ Pin). There is a repeat
mode for the alarms allowing a periodic interrupt.

The device offers a backup power input pin. This
V

pin allows the device to be backed up by battery

BACK

or SuperCap. The entire X1205 device is fully
operational from 2.7 to 5.5 volts and the clock/calendar
portion of the X1205 device remains fully operational
down to 1.8 volts (Standby Mode).

PIN DESCRIPTIONS

X1205

8-Pin SOIC

1

X1

2

X2

IRQ

V

NC = No internal connection

SS

3

4

8

7

6

5

V

CC

V

BACK

SCL

SDA

V

BACK

V

CC

X1
X2

8-Pin TSSOP

1

8

2

7

3

6

4

5

SCL

SDA
V

SS

IRQ

Serial Clock (SCL)

The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs. The input buffer is always active (not gated).

An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pull­down. The circuit is designed for 400kHz 2-wire inter-

PRELIMINARY

face speeds.

V

BACK

This input provides a backup supply voltage to the
device. V
event the V

supplies power to the device in the

BACK

supply fails. This pin can be connected

CC

to a battery, a Supercap or tied to ground if not used.

Interrupt Output – IRQ

This is an interrupt signal output. This signal notifies a
host processor that an alarm has occurred and
requests action. It is an open drain active low output.

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X1, X2

The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external

32.768kHz quartz crystal is used with the X1205 to
supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit.
Plenty of ground plane around the device and short
traces to X1 and X2 are highly recommended. See
Application section for more recommendations.

Figure 1. Recommended Crystal connection

X1
X2

POWER CONTROL OPERATION

The power control circuit accepts a V

and a V

CC

BACK

input. The power control circuit powers the clock from
V

when V

BACK

power the device from V

CC

< V

- 0.2V. It will switch back to

BACK

CC

when V

exceeds V

CC

BACK

Figure 2. Power Control

V

V

CC

BACK

Off

Voltage

On

In

REAL TIME CLOCK OPERATION

The Real Time Clock (RTC) uses an external

32.768kHz quartz crystal to maintain an accurate inter­nal representation of second, minute, hour, day, date,
month, and year. The RTC has leap-year correction.
The clock also corrects for months having fewer than
31 days and has a bit that controls 24 hour or AM/PM
format. When the X1205 powers up after the loss of
both V

CC

and V

, the clock will not operate until at

BACK

least one byte is written to the clock register.

Reading the Real Time Clock

The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change during

Characteristics subject to change without notice.

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X1205 – Preliminary Information

the course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a separate
latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a
read are unaffected by the read operation.

Writing to the Real Time Clock

The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the next “one second clock cycle” after
the stop bit is written. The RTC continues to update
the time while an RTC register write is in progress and
the RTC continues to run during any nonvolatile write
sequences. A single byte may be written to the RTC
without affecting the other bytes.

Accuracy of the Real Time Clock

The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC perfor­mance will also be dependent upon temperature. The
frequency deviation of the crystal is a function of the
turnover temperature of the crystal from the crystal’s
nominal frequency. For example, a >20ppm frequency
deviation translates into an accuracy of >1 minute per
month. These parameters are available from the
crystal manufacturer. Xicor’s RTC family provides on­chip crystal compensation networks to adjust load­capacitance to tune oscillator frequency from +116
ppm to –37 ppm when using a 12.5 pF load crystal.
For more detail information see the Application
section.

CLOCK/CONTROL REGISTERS (CCR)

The Control/Clock Registers are located in an area
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.

PRELIMINARY

CCR access

The contents of the CCR can be modified by perform­ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)

The CCR is divided into 5 sections. These are:

1. Alarm 0 (8 bytes; non-volatile)

2. Alarm 1 (8 bytes; non-volatile)

3. Control (4 bytes; non-volatile)

4. Real Time Clock (8 bytes; volatile)

5. Status (1 byte; volatile)

Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec­tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.

It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.

The state of the CCR can be read by performing a ran­dom read at any address in the CCR at any time. This
returns the contents of that register location. Addi­tional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
change the time being read. A sequential read of the
CCR will not result in the output of data from the mem­ory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.

ALARM REGISTERS

There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:

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Characteristics subject to change without notice.

3 of 22

X1205 – Preliminary Information

– Setting the Enable Month Bit (EMOn*) bit in combi-

nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.

*n = 0 for Alarm 0: N = 1 for Alarm 1

When there is a match, an alarm flag is set. The occur­rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.

The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.

Table 1. Clock/Control Memory Map

Addr. Type

003F Status SR BAT AL1 AL0 0 0 RWEL WEL RTCF 01h

0037 RTC (SRAM) Y2K 0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 20h

0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6 00h

0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h

0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 00h

0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 00h

0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 00h

0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h

0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h

0013 Control

(NONVOLATILE)

0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h

0011 INT IM AL1E AL0E 0 0 X X X 00h

0010 0 0 0 000000 00h

000F Alarm1

(NONVOLATILE)

000E DWA1 EDW1 0 0 0 0 DY2 DY1 DY0 0-6 00h

000D YRA1 Unused – Default = RTC Year value – Future expansion

000C MOA1 EMO1 0 0 A1G20 A1G13 A1G12 A1G11 A1G10 1-12 00h

000B DTA1 EDT1 0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1-31 00h

000A HRA1 EHR1 0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0-23 00h

0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h

0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h

0007 Alarm0

(NONVOLATILE)

0006 DWA0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h

0005 YRA0 Unused – Default = RTC Year value – Future expansion

0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h

0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h

0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h

0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h

0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h

Reg

Name

DTR 0 0 0 0 0 DTR2 DTR1 DTR0 00h

Y2K1 0 0 A1Y2K21 A1Y2K20 A1Y2K13 0 0 A1Y2K10 20h

76543210

PRELIMINARY

Y2K0 0 0 A0Y2K21 A0Y2K20 A0Y2K13 0 0 A0Y2K10 19/20 20h

– The user can set the X1205 to alarm every Wednes-

day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00AM
Wednesday.

– A daily alarm for 9:30PM results when the EHRn*

and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30PM.

*n = 0 for Alarm 0: N = 1 for Alarm 1

Bit

Range

Default

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Characteristics subject to change without notice.

4 of 22

X1205 – Preliminary Information

REAL TIME CLOCK REGISTERS

Clock/Calendar Registers (SC, MN, HR, DT, MO, YR)

These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is
1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.

Date of the Week Register (DW)

This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
default value is defined as ‘0’.

24 Hour Time

If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12­hour format and H21 bit functions as an AM/PM indi­cator with a ‘1’ representing PM. The clock defaults to
standard time with H21=0.

Leap Years

Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1205 does not correct for
the leap year in the year 2100.

STATUS REGISTER (SR)

The Status Register is located in the CCR memory
map at address 003Fh. This is a volatile register only
and is used to control the WEL and RWEL write
enable latches, read two power status and two alarm
bits. This register is separate from both the array and
the Clock/Control Registers (CCR).

PRELIMINARY

Table 2. Status Register (SR)

Addr 7 6 5 4 3 2 1 0

003Fh BAT AL1 AL0 0 0 RWEL WEL RTCF

Default 0 0 0 0 0 0 0 1

BAT: Battery Supply—Volatile

This bit set to “1” indicates that the device is operating

BACK

, not V

from V
reset by hardware (X1205 internally). Once the device
begins operating from V
“0”.

. It is a read-only bit and is set/

CC

, the device sets this bit to

CC

AL1, AL0: Alarm bits—Volatile

These bits announce if either alarm 0 or alarm 1 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read opera­tion is complete.

RWEL: Register Write Enable Latch—Volatile

This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both
the RWEL and WEL bits to be set in a specific
sequence.

WEL: Write Enable Latch—Volatile

The WEL bit controls the access to the CCR and
memory array during a write operation. This bit is a
volatile latch that powers up in the LOW (disabled)
state. While the WEL bit is LOW, writes to the CCR or
any array address will be ignored (no acknowledge will
be issued after the Data Byte). The WEL bit is set by
writing a “1” to the WEL bit and zeroes to the other bits
of the Status Register. Once set, WEL remains set
until either reset to 0 (by writing a “0” to the WEL bit
and zeroes to the other bits of the Status Register) or
until the part powers up again. Writes to WEL bit do
not cause a nonvolatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.

RTCF: Real Time Clock Fail Bit—Volatile

This bit is set to a ‘1’ after a total power failure. This is
a read only bit that is set by hardware (X1205 inter­nally) when the device powers up after having lost all
power to the device. The bit is set regardless of
whether V
one of the supplies does not result in setting the RTCF
bit. The first valid write to the RTC after a complete
power failure (writing one byte is sufficient) resets the
RTCF bit to ‘0’.

Unused Bits:

This device does not use bits 3 or 4 in the SR, but
must have a zero in these bit positions. The Data Byte
output during a SR read will contain zeros in these bit
locations.

CC

or V

is applied first. The loss of only

BACK

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Characteristics subject to change without notice.

5 of 22

X1205 – Preliminary Information

INTERRUPT CONTROL REGISTER (INT)

Interrupt Control and Status Bits (IM, AL1E, AL0E)

There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output (IRQ). The interrupts are enabled when either the
AL1E and AL0E bits are set to “1”, respectively.

Two volatile bits (AL1 and AL0), associated with the two
alarms respectively, indicate if an alarm has happened.
These bits are set on an alarm condition regardless of
whether the IRQ interrupt is enabled. The AL1 and AL0
bits in the status register are reset by the falling edge of
the eighth clock of a read of the register containing the
bits.

Pulse Interrupt Mode

The pulsed interrupt mode allows for repetitive or
recurring alarm functionality. Hence an repetitive or
recurring alarm can be set for every n
minute, or n
the week. The pulsed interrupt mode can be consid­ered a repetitive interrupt mode, with the repetition
rate set by the time setting fo the alarm.

The Pulse Interrupt Mode is enabled when the IM bit is
set.

IM Bit Interrupt / Alarm Frequency

0 Single Time Event Set By Alarm

1 Repetitive / Recurring Time Event Set By Alarm

The Alarm IRQ output will output a single pulse of
short duration (approximately 10-40ms) once the
alarm condition is met. If the interrupt mode bit (IM bit)
is set, then this pulse will be periodic.

ON-CHIP OSCILLATOR COMPENSATION

Digital Trimming Register (DTR) — DTR2, DTR1
and DTR0 (Non-Volatile)

The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.

DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.

th

hour, or n

th

date, or for the same day of

PRELIMINARY

th

second, or n

DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.

A range from -30ppm to +30ppm can be represented
by using three bits above.

Table 3. Digital Trimming Registers

DTR Register

0 0 0 0 (default)

0 1 0 +10

0 0 1 +20

0 1 1 +30

100 0

1 1 0 -10

1 0 1 -20

th

1 1 1 -30

Analog Trimming Register (ATR) (Non-volatile)

Six analog trimming Bits from ATR5 to ATR0 are pro-
vided to adjust the on-chip loading capacitance range.
The on-chip load capacitance ranges from 3.25pF to

18.75pF. Each bit has a different weight for capaci­tance adjustment. In addition, using a Citizen CFS-206
crystal with different ATR bit combinations provides an
estimated ppm range from +116ppm to -37ppm to the
nominal frequency compensation. The combination of
digital and analog trimming can give up to +146ppm
adjustment.

The on-chip capacitance can be calculated as follows:

C

= [(ATR value, decimal) x 0.25pF] + 11.0pF

AT R

Note that the ATR values are in two’s complement,
with ATR(000000) = 11.0pF, so the entire range runs
from 3.25pF to 18.75pF in 0.25pF steps.

The values calculated above are typical, and total load
capacitance seen by the crystal will include approxi­mately 2pF of package and board capacitance in addi­tion to the ATR value.

See Application section and Xicor’s Application Note
AN154 for more information.

Estimated frequency

PPMDTR2 DTR1 DTR0

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Characteristics subject to change without notice.

6 of 22

X1205 – Preliminary Information

WRITING TO THE CLOCK/CONTROL REGISTERS

Changing any of the nonvolatile bits of the clock/con­trol register requires the following steps:

– Write a 02h to the Status Register to set the Write

Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre­ceeded by a start and ended with a stop).

– Write a 06h to the Status Register to set both the

Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).

– Write one to 8 bytes to the Clock/Control Registers

with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
nonvolatile register values so these initiate a non­volatile write cycle and will take up to 10ms to com­plete. Writes to undefined areas have no effect. The
RWEL bit is reset by the completion of a nonvolatile
write cycle, so the sequence must be repeated to
again initiate another change to the CCR contents.
If the sequence is not completed for any reason
(by sending an incorrect number of bits or sending a
start instead of a stop, for example) the RWEL bit is
not reset and the device remains in an active mode.

– Writing all zeros to the status register resets both the

WEL and RWEL bits.

– A read operation occurring between any of the previ-

ous operations will not interrupt the register write
operation.

SERIAL COMMUNICATION

Interface Conventions

The device supports a bidirectional bus oriented proto­col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam­ily operate as slaves in all applications.

PRELIMINARY

Clock and Data

Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 3.

Start Condition

All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 4.

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the Standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus. See
Figure 4.

Acknowledge

Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans­mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 5.

The device will respond with an acknowledge after rec­ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:

– The Slave Address Byte when the Device Identifier

and/or Select bits are incorrect

– All Data Bytes of a write when the WEL in the Write

Protect Register is LOW

– The 2nd Data Byte of a Status Register Write

Operation (only 1 data byte is allowed)

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Characteristics subject to change without notice. 7 of 22