Note:Ensure that there are no unintentional external pull-ups on the following GPIOs
and these GPIOs are NOT logic high unintentionally before SDX55M comes out of reset
GPIO_24, GPIO_54, GPIO_58, GPIO_59 and GPIO_75
U1601-3
GND1
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97
GND98
GND99
GND100
AF24
AF26
AF28
AG15
AG5
AG7
AH10
AH14
AH18
AH20
AH8
AJ1
AJ17
AJ37
AK10
AK14
AK2
AK32
AK36
AK4
AK8
C3
C35
D10
D14
D18
D22
D26
D30
D34
D4
D6
E11
E13
E15
E17
E19
E21
E23
E25
E27
E29
E31
E33
E35
E37
E7
E9
F10
F16
A1
GND1
A11
GND2
A15
GND3
A19
GND4
A23
GND5
A27
GND6
A3
GND7
A31
GND8
A35
GND9
A37
GND10
A7
GND11
AA11
GND12
AA13
GND13
AA15
GND14
AA17
GND15
AA21
GND16
AA23
GND17
AA25
GND18
AA31
GND19
AA5
GND20
AA9
GND21
AB18
GND22
AB20
GND23
AB26
GND24
AB28
GND25
AB30
GND26
AB36
GND27
AB4
GND28
AB6
GND29
AD10
GND30
AD12
GND31
AD14
GND32
AD16
GND33
AD28
GND34
AD30
GND35
AD36
GND36
AD8
GND37
AE1
GND38
AE11
GND39
AE17
GND40
AE19
GND41
AE21
GND42
AE23
GND43
AE27
GND44
AE5
GND45
AE9
GND46
AF16
GND47
AF18
GND48
AF20
GND49
AF22
GND50
SDX55M
U1601-4
GND2
F22
GND101
F24
GND102
F26
GND103
F28
GND104
F30
GND105
F34
GND106
F8
GND107
G29
GND108
G31
GND109
G33
GND110
G35
GND111
H30
GND112
H32
GND113
H34
GND114
J13
GND115
J15
GND116
J17
GND117
J19
GND118
J21
GND119
J23
GND120
J25
GND121
J27
GND122
J29
GND123
J33
GND124
J35
GND125
J37
GND126
K10
GND127
K12
GND128
K14
GND129
K20
GND130
K22
GND131
K24
GND132
K26
GND133
K28
GND134
K30
GND135
K32
GND136
K34
GND137
K8
GND138
L1
GND139
L33
GND140
L35
GND141
M30
GND142
M32
GND143
M34
GND144
N11
GND145
N13
GND146
N15
GND147
N17
GND148
N19
GND149
N21
GND150
N23
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160
GND161
GND162
GND163
GND164
GND165
GND166
GND167
GND168
GND169
GND170
GND171
GND172
GND173
GND174
GND175
GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188
GND189
GND190
GND191
GND192
GND193
GND194
GND195
GND196
GND197
GND198
GND199
N25
N27
N33
N35
N9
P10
P12
P14
P16
P18
P20
P22
P24
P26
P30
R33
R35
T30
T32
T34
U1
U11
U13
U15
U17
U19
U25
U27
U33
U35
U9
V10
V12
V14
V16
V18
V20
V22
V24
V26
V28
V32
V34
V8
W33
W35
W37
Y30
SDX55M
SDX55M
Title
Title
Title
J11 MAIN
J11 MAIN
J11 MAIN
Size Document Number
Size Document Number
Size Document Number
Reserved(for 5G-sub 6G)
A2
Reserved(for 5G-sub 6G)
A2
Reserved(for 5G-sub 6G)
A2
Monday, December 23, 2019
Date:Sheet
Monday, December 23, 2019
Date:Sheet
Monday, December 23, 2019
5
4
3
2
Date:Sheet
1
5
W1701
2
VREG_S7E_MX_0P752_SENSE_P<19>
DD
CC
VREG_S5E_CX_0P752_SENSE_P<19>
BB
AA
o
112
SHORT
VREG_S7E_MX_0P752
VREG_S5E_CX_0P752
5
U1601-8
AB10
12
C1703
12
1uF
+/-20%
DC 6.3V
0201
1
C1785
22uF
13
2
4
C1704
NM
0402
W1702
2
o
2
1
SHORT
2389.1mA
2490mA
12
C1705
NM
0402
1
C1706
22uF
2
VREG_S3E_0P824
3
4
21.4mA
AB22
AB24
AD24
AE25
W13
W15
W19
W21
AA29
AB12
AB14
AB16
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AC25
AC27
AC29
AC9
AD18
AD20
AD22
AD26
W29
AB8
G23
G25
G27
H10
H8
K16
K18
L25
L27
M8
P28
P8
R19
R21
T14
T16
T28
T8
U21
U23
F32
VDDMX_1_1
VDDMX_1_2
VDDMX_1_3
VDDMX_1_4
VDDMX_1_5
VDDMX_1_6
VDDMX_1_7
VDDMX_1_8
VDDMX_1_9
VDDMX_1_10
VDDMX_1_11
VDDMX_1_12
VDDMX_1_13
VDDMX_1_14
VDDMX_1_15
VDDMX_1_16
VDDMX_1_17
VDDMX_1_18
VDDMX_1_19
VDDMX_1_20
VDDMX_1_21
VDDMX_1_22
VDDMX_1_23
VDDMX_1_24
VDDMX_1_25
VDDMX_1_26
VDDMX_1_27
VDDMX_1_28
VDDMX_1_29
VDDMX_1_30
VDDCX_1_1
VDDCX_1_2
VDDCX_1_3
VDDCX_1_4
VDDCX_1_5
VDDCX_1_6
VDDCX_1_7
VDDCX_1_8
VDDCX_1_9
VDDCX_1_10
VDDCX_1_11
VDDCX_1_12
VDDCX_1_13
VDDCX_1_14
VDDCX_1_15
VDDCX_1_16
VDDCX_1_17
VDDCX_1_18
VDDCX_1_19
VDDCX_1_20
VDD_ILDO_NAV
SDX55M
PWR1
VDD_MODEM_1
VDD_MODEM_2
VDD_MODEM_3
VDD_MODEM_4
VDD_MODEM_5
VDD_MODEM_6
VDD_MODEM_7
VDD_MODEM_8
VDD_MODEM_9
VDD_MODEM_10
VDD_MODEM_11
VDD_MODEM_12
VDD_MODEM_13
VDD_MODEM_14
VDD_MODEM_15
VDD_MODEM_16
VDD_MODEM_17
VDD_MODEM_18
VDD_MODEM_19
VDD_MODEM_20
VDD_MODEM_21
VDD_MODEM_22
VDD_MODEM_23
VDD_MODEM_24
VDD_MODEM_25
VDD_MODEM_26
VDD_MODEM_27
VDD_MODEM_28
VDD_MODEM_29
VDD_MODEM_30
VDD_MODEM_31
VDD_MODEM_32
VDD_MODEM_33
VDD_MODEM_34
VDD_MODEM_35
VDD_MODEM_36
VDD_MODEM_37
VDD_MODEM_38
VDD_MODEM_39
VDD_MODEM_40
VDD_MODEM_41
VDD_MODEM_42
VDD_MODEM_43
VDD_MODEM_44
VDD_MODEM_45
VDD_MODEM_46
VDD_MODEM_47
VDD_MODEM_48
VDD_MODEM_49
VDD_MODEM_50
VDD_MODEM_51
VDD_MODEM_52
VDD_MODEM_53
VDD_MODEM_54
VDD_MODEM_55
VDD_MODEM_56
VDD_MODEM_57
VDD_MODEM_58
VDD_MODEM_59
VDD_MODEM_60
VDD_MODEM_61
VDD_MODEM_62
VDD_MODEM_63
VDD_MODEM_64
VDD_MODEM_65
VDD_MODEM_66
VDD_MODEM_67
4
VREG_S1E_S6E_MODEM_0P752
C1735
22uF
13
C1736
22uF
2
4
13
2
4
12
RT1700
100K
±1%
0201
C1737
22uF
1
2
4
AA19
7800.9mA
AA27
G21
H12
H14
H16
H18
H20
H22
H24
H26
H28
J11
J9
L11
L13
L15
L17
L19
L21
L23
L9
M10
M12
M14
M16
M18
M20
M22
M24
M26
M28
R11
R13
R15
R17
R23
R25
R27
R9
T10
T12
T18
T20
T22
T24
T26
W11
W17
W23
W25
W27
W5
W9
Y10
Y12
Y14
Y16
Y18
Y20
Y22
Y24
Y26
Y28
Y4
Y6
Y8
4
3
VREG_L6E_RCM_1P8
o
MDM_SKIN_THERM <43>
3
VREG_S7E_MX_0P752
VREG_L14E_0P6
C1744
12
12
1uF
±20%
6.3V
0201
12
3
W1707
112
SHORT
W1708
112
SHORT
C1746
C1745
12
1uF
1uF
±20%
±20%
6.3V
6.3V
0201
0201
VREG_L1E_RCM_1P2VREG_L6E_RCM_1P8
C1751
C1752
1
1uF
1uF
±20%
±20%
6.3V
6.3V
2
0201
0201
2
2
12
12
VREG_IO_1P8
VREG_L4E_RCM_0P875
C1757
12
1uF
±20%
6.3V
0201
o
VREG_S1E_S6E_SENSE_P <19>
o
VREG_S1E_S6E_SENSE_M <19>
C1710
1uF
±20%
6.3V
0201
187.4mA
C1739
12
1uF
±20%
6.3V
0201
270.7mA
C1742
12
1uF
±20%
6.3V
0201
12
VREG_L11E_UIM1_1P8VREG_L13E_UIM2_1P8
C1711
12
1uF
±20%
6.3V
0201
VREG_L4E_RCM_0P875VREG_L1E_RCM_1P2
C1762
12
1uF
±20%
6.3V
0201
C1738
1uF
±20%
6.3V
0201
C1741
1uF
±20%
6.3V
0201
1
2
0.1mA
0mA
C1750
1uF
±20%
6.3V
0201
47.9mA
17.5mA
24.7mA
10mA
10mA
0mA
10mA
U1601-9
L29
VDDA_DDRSS1
N29
VDDA_DDRSS2
R29
VDDA_DDRSS3
U29
VDDA_DDRSS4
V30
VDDA_DDRSS_CC
J31
VDDIO_DDRSS1
L31
VDDIO_DDRSS2
N31
VDDIO_DDRSS3
U31
VDDIO_DDRSS4
R31
VDDIO_DDRSS_CK
AG1
VDDPX_0
AE37
VDDPX_3_1
AH2
VDDPX_3_2
AK22
VDDPX_3_3
AK34
VDDPX_3_4
B36
VDDPX_3_5
C1
VDDPX_3_6
R1
VDDPX_3_7
V2
VDDPX_4
W1
VDDPX_5
AF6
VDDPX_11
J1
VDDPX_12
AJ33
VDDPX_71
AG37
VDDPX_72
AJ21
VDDPX_73
AH4
VDDPX_74
AF14
VDDA_USB_SS_0P9
P32
VDDA_DDRSS_HV
W31
VDDA_DDRSS_PLL_HV
AF12
VDD_USB_HS_DVDD
SDX55M
2
PWR2
VDDA_QLINK0_LV_CK
VDDA_QLINK1_LV_CK_1
VDDA_QLINK1_LV_CK_2
2
VDDA_USB_HS_1P8
VDDA_USB_HS_3P3
VDDA_USB_SS_1P2
VDDA_PCIE_1P2
VDDA_PCIE_0P9_1
VDDA_PCIE_0P9_2
VDDA_QREF_0P9_1
VDDPX_VBIAS_UIM
VDDA_QLINK0_LV_1
VDDA_QLINK0_LV_2
VDDA_QLINK1_LV_1
VDDA_QLINK1_LV_2
VDDA_QREF_0P9_2
VDDA_QLINK0_HV
VDDA_QLINK1_HV
VDDA_QREF_1P8
VDD_QFPROM
VDD1_1
VDD1_2
VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VREG_L5E_RCM_1P7 VREG_L10E_3P1 VREG_L1E_RCM_1P2
AE13
0.5mA
AG13
0.2mA
AE15
15mA
AF8
15mA
AF10
50.4mA
AG11
G9
V6
3mA
F18
480mA
F12
F14
F20
G17
G11
G15
AC7
G19
6mA
G13
AE7
1mA
AE29
94.5mA
AC37
C1773
12
1uF
±20%
G37
6.3V
0201
AA37
290mA
C37
K36
C1778
1
L37
1uF
±20%
R37
6.3V
2
0201
U37
D36
98mA
C1782
12
F36
1uF
±20%
H36
6.3V
0201
M36
T36
V36
Y36
C1764
C1763
12
12
1uF
1uF
±20%
±20%
6.3V
6.3V
0201
0201
C1769
C1768
12
1
1uF
2.2uF
±20%
+/-10%
6.3V
DC 10V
2
0201
0402
C1774
1
1uF
±20%
6.3V
2
0201
C1779
C1780
12
12
1uF
1uF
±20%
±20%
6.3V
6.3V
0201
0201
C1784
C1783
12
12
1uF
1uF
±20%
±20%
6.3V
6.3V
0201
0201
Title
Title
Title
Size Document Number
Size Document Number
Size Document Number
Date:Sheet
Date:Sheet
Date:Sheet
C1770
12
1uF
±20%
6.3V
0201
C1776
12
1uF
±20%
6.3V
0201
J11 MAIN
J11 MAIN
J11 MAIN
Reserved(for MM Wave)
A2
Reserved(for MM Wave)
A2
Reserved(for MM Wave)
A2
Monday, December 23, 2019
Monday, December 23, 2019
Monday, December 23, 2019
1
VREG_L1E_RCM_1P2 VREG_L4E_RCM_0P875
C1766
12
1uF
±20%
6.3V
0201
C1777
12
1uF
±20%
6.3V
0201
VREF_SDX
VREG_L5E_RCM_1P7VREG_L1E_RCM_1P2
VREG_L2E_1P13
VREG_L14E_0P6
1
VREG_L4E_RCM_0P875
VREG_L6E_RCM_1P8
5
DD
U1801-1
GND
VREG_L1E_RCM_1P2
1194.1mA
9
26
8
132
16
143
142
140
139
115
40
31
7
39
5
6
141
C1814
1
4.7uF
+/-20%
10V
2
0402
57
TEST_EN_VPP
47
CMN_GND0
56
CMN_GND1
64
CMN_GND2
65
CMN_GND3
73
CMN_GND4
81
CMN_GND5
82
CMN_GND6
90
CMN_GND7
30
NC1
125
NC2
122
NC3
PMX55
VREG_L2E_1P13
323.7mA
C1815
12
4.7uF
+/-20%
10V
0402
VREG_L3E_RCM_0P8
1282.3mA
VREG_L4E_RCM_0P875
C1816
1
1
4.7uF
+/-20%
10V
2
2
0402
1070.6mA
VREG_L5E_RCM_1P7
C1817
4.7uF
+/-20%
10V
0402
U1801-2
2
84
83
74
92
67
58
100
101
75
66
U1801-3
VDD_L1_L2_0
VDD_L1_L2_1
VDD_L3_L9
VDD_L4_L12_0
VDD_L4_L12_1
VDD_L5_L6
VDD_L7_L8_0
VDD_L7_L8_1
VDD_L10_L11_L13
VDD_L14
VDD_L15
VDD_L16
VREG_L14_S
PMX55
5
GPIO_01
GPIO_02
GPIO_03
GPIO_04
GPIO_05
GPIO_06
GPIO_07
GPIO_08
GPIO_10
GPIO_11
PMX55
GPIO
LREG
VREG_L1_0
VREG_L1_1
VREG_L2
VREG_L3
VREG_L4
VREG_L5
VREG_L6
VREG_L7
VREG_L8
VREG_L9
VREG_L10
VREG_L11
VREG_L12
VREG_L13
VREG_L14
VREG_L15
VREG_L16
R1813 NM 0201
1
BB_HP_EN<48>
CC
BB
S7E is for L14 input and
SDX_MX/SDX_VDDA_EBI0
C3219 is reserved
AA
o
1517.8mA
1565.4mA
1656.7mA
727.3mA
1177mA
140.4mA
C1843
1
±20%
10V
1uF
2
0201
400mA
414.8mA
W1800
1
SHORT
o
17
25
124
15
24
134
123
131
48
14
23
133
22
2
2
1
SLEEP_CLK<32,43,75>
VREG_S2E_1P224
VREG_S3E_0P824
VREG_S2E_1P224
VREG_S4E_1P904
VREG_S3E_0P824
VREG_BOB
VREG_S7E_MX_0P752
368.7mA
VREG_S2E_1P224
C1842
1
4.7uF
+/-20%
10V
meet ESL/DCR requirements
2
0402
VREG_S4E_1P904
VREG_L14E_0P6VREG_L16E_RCM_1P8
PMx55 LDO capacitor table
N1200(L1,L2,L3,L4,L7,L8,L9,L12,L14,L15)4.7uF min .22uF max
N1200(L14)2*10uF or 1*22uF min.44uF max
MVP150(L10,L11,L13)0.47uF min. 5uF max
LVP600(L5,L6,L16) 4.7uF min .23.5uF max
Pseudo capless allows users to place the LDO output capacitor physically/electrically far from the LDO output, near the load. The routing ESL/ESR between the PMIC pin and the remote Cout should meet the capless LDO spec.
All PMOS LDOs are considered pseudo-capless, unless it has internal PMIC load. If an internal PMIC load, the output cap must be placed close to the PMIC.
Required capacitance for each LDO type can be found in App Note: 80-VT310-125
4
VREG_IO_1P8VREG_L6E_RCM_1P8
o
PMIC_SPMI_CLK<17,19,32,43,48,53,74>
o
PMIC_SPMI_DATA<17,19,32,43,48,53,74>
R1803 NM 0201
o
AUTO_ON_N<43,55>
o
SDX_PS_HOLD<17>
o
PA_THERM1<8>
o
PA_THERM2<8>
WIFI_SKIN_THERM<75>
GND_XO_ADC
Use dedicated route with thin trace to XTAL Therm GND and PMIC pin
Locate GND via close as possible to PMIC pin
Option for Embedded_shorting_bar to ensure no accidental other connection to GND
o
o
AMNIENT_THERM<19>
o
PMK_XO_THERM<19>
o
GND_XO_ADC<19>
Y1800 GND
12
R1807 3.65K ±1% 0201
1
For PON decode
C1801
1
1nF
+/-10%
50V
2
0201
VPH_PWR
727.3mA
VREG_L6E_RCM_1P8
269.6mA
VREG_L8E_RCM_0P8
824.56mA
C1818
C1819
1
1
4.7uF
100nF
+/-20%
+/-10%
10V
6.3V
2
2
0402
0201
4
C1821
1
4.7uF
+/-20%
10V
2
0402
VREG_L10E_3P1
0.2mA
12
C1823
NM
0201
2
1
VPH_PWR
VREG_L11E_UIM1_1P8
VPH_PWR
2
1
2
VPH_PWR
0201
C1832
1uF
10V
±20%
Share S4E input
power routes
with S2E cap
70.1mA
These VPH power pins
are low current:
about 2mA max @
U1801-4
106
VPH_PWR1
41
VPH_PWR2
91
VIO_IN
33
VDD_AP_IO
118
SPMI_CLK
109
SPMI_DATA
97
CBL_PWR_N
114
KPD_PWR_N
80
RESIN_N
72
PON_1
113
PS_HOLD
50
VBUS_DET
107
NC
2
EXT_ECM1
29
EXT_ECM2
55
AMUX1
46
AMUX2
54
AMUX3
38
AMUX4
37
AMUX5
71
XO_THERM
63
GND_XOADC
W1801
1
SHORT
2
0201
2
C1831
1uF
10V
1
±20%
VREG_L13E_UIM2_1P8
PMX55
VREF_RGMII_GPIO_09
U1801-6
59
VDD_S2_0
68
VDD_S2_1
43
GND_S2_1
42
GND_S2_0
144
VDD_S3_0
145
VDD_S3_1
127
GND_S3_1
119
GND_S3_0
76
VDD_S4_0
77
VDD_S4_1
85
VDD_S4_2
111
GND_S4_1
110
GND_S4_0
PMX55
70.1mA
VREG_L14E_0P6
12
MISC
PON_RESET_N
SREG_2
368.7mA
VREG_L15E_1P2
C1827
22uF
+/-20%
6.3V
0402
SLEEP_CLK
VIO_OUT
FAULT_N
DVDD_BYP
AVDD_BYP
REF_BYP
REF_GND
VREF_MDM
VFB_S2
VSW_S2_0
VSW_S2_1
VFB_S3
VSW_S3_0
VSW_S3_1
VFB_S4
VSW_S4_0
VSW_S4_1
VSW_S4_2
400mA
C1828
1
4.7uF
+/-20%
10V
2
0402
3
3
117
99
130
105
116
108
32
49
98
89
414.8mA
1
C1829
NM
0201
2
12
PMX_AVDD_BYP
34
51
60
126
128
136
135
93
94
102
VREG_IO_1P8
o
SDX_SLEEP_CLK <17>
o
R1808 0R±5%0201
o
C1803 1uF 0201
2
1
6.3V ±20%
C1804 1uF 0201
1
6.3V ±20%
AVDD_BYP
Use dedicated GND via
C1805
12
at quiet area close to PMIC
100nF
+/-10%
REF_BYP
6.3V
Use dedicated route
0201
and GND via close as possible to PMIC pin
VREF_RGMII is 0.85 V, low current
VREF_RGMII can be optionally configured as GPIO_09
VREF_MDM is 1.25 V, low current
VREF_SDX
C1802
12
±20%
6.3V
1uF
0201
SDX_RESIN_N <17>
PM_FAULT_N <43,48,53>
2
1
2
o
AMNIENT_THERM <19>
RT1801
100K
±1%
0201
VREG_S2E_1P224
3574.6mA
L1806 470nH ±20% 0805
12
C1834
1
10uF
±20%
6.3V
2
0402
VREG_S3E_0P824
3588.3mA
L1807 470nH ±20% 0805
12
C1835
1
10uF
±20%
6.3V
2
0402
VREG_S4E_1P904
1492.8mA
L1808 1uH ±20%
2
1
0805
1
C1836
12
22uF
C1837
+/-20%
NM
6.3V
0402
0402
2
PMK_XO_THERM<19>
GND_XO_ADC<19>
Note:
Place XO as close to PMK8002 as possible, away from heat source in
all directions (including Z-direction for stacked PCB).
Route XTAL_IN and XTAL_OUT traces on surface layer only with length <10mm.
No trace shall be present in at-least two immediate layers below XTAL.
Refer to 80-VP447-10 for XO Layout App Note.
2
U1801-5
SREG_1
137
VDD_S1_0
138
0201
2
C1806
Share S7E input
power routes
with S5E cap
PMIC_SPMI_DATA<17,19,32,43,48,53,74>
PMIC_SPMI_CLK<17,19,32,43,48,53,74>
PM_DVDD_BYP<43>
3
HOT2
4
SENSOR
2
GND
2
1uF
10V
1
±20%
0201
C1810
1uF
10V
1 2
±20%
0201
2
C1811
1uF
10V
1
±20%
VPH_PWR
C1809
C1807
12
12
10uF
10uF
+/-20%
+/-20%
10V
10V
0402
0402
VPH_PWR
VPH_PWR
C1808
1
10uF
±20%
6.3V
2
0402
C1812
1
10uF
±20%
6.3V
2
0402
o
o
VDD_S1_1
121
GND_S1_1
112
GND_S1_0
78
VDD_S6_0
87
VDD_S6_1
104
GND_S6_1
103
GND_S6_0
61
VDD_S8_0
69
VDD_S8_1
36
GND_S8_1
35
GND_S8_0
1
VDD_S5_0
10
VDD_S5_1
28
GND_S5_1
27
GND_S5_0
3
VDD_S7_0
11
VDD_S7_1
21
GND_S7_1
13
GND_S7_0
PMX55
o
o
o
VREG_IO_1P8
Y1800
HOT1
38.4MHz
Dedicated trace from REF_BYP to cap.
Dedicated trace from REF_GND to cap.
Dedicated via to main ground plane right under PMIC pin (REF_GND)
or as close to the pin as possible.
Do NOT add via at cap.
REF_BYP and REF_GND should be
routed away from noisy traces
12
12
1
VFB_S1
RMT_GND_S1
VSW_S1_0
VSW_S1_1
VFB_S6
RMT_GND_S6
VSW_S6_0
VSW_S6_1
VFB_S8
RMT_GND_S8
VSW_S8_0
VSW_S8_1
VFB_S5
VSW_S5_0
VSW_S5_1
VFB_S7
VSW_S7_0
VSW_S7_1
C1830
100nF
+/-10%
6.3V
0201
C1838
100nF
+/-10%
6.3V
0201
13
14
5
6
3
2
PMK8002
70
96
120
129
62
88
86
95
53
79
44
52
45
18
19
20
4
12
SPMI_DATA
SPMI_CLK
DVDD_BYP
VDD_IO
XTAL_OUT
XTAL_IN
L1802 470nH ±20% 0805
1
L1803 470nH ±20% 0805
12
L1809_NM 470nH ±20% 0805
1
o
VREG_S5E_CX_0P752_SENSE_P <18>
L1804 1uH ±20% 0805
1
o
VREG_S7E_MX_0P752_SENSE_P <18>
L1805 470nH ±20% 0805
12
S7E is for VDD_MX/VDDA_EBI/L14E_INPUT, STAR-ROUTE is NEEDED.
Pay attention to the S7E bulk cap placement and the star-routing.