Xiaomi Redmi 9a Schematics
5
D D
C C
B B
4
3
2
1
A A
Title
Title
Title
Amman
Amman
Amman
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Contents
Contents
Contents
V1.0
V1.0
V1.0
1 38Wednesday, April 0 1, 2020
1 38Wednesday, April 0 1, 2020
1 38Wednesday, April 0 1, 2020
1
5
Note: 22-3
D D
Set cap. close to PMIC
SH201
SHORT / 4MIL
C C
VSYS
R / 330 / K / 0201 / 1%
R / 39 / K / 0 201 / 1%
1 2
C203
C / 1 / uF / 10 V
2 1
VSYS
VBUS
VBAT
12
R207
BATON[16]
12
R208
VBUS
R / 7.5 / K / 0201 / 1% R210 R / 0 / ohm / 020 1
VCDT rating: 1.268V
B B
Note 22-1:
A A
Note 22-2:
Note 22-3:
Note 22-4:
Please refer to MT6765_MT6357 Co-Clock Design Notice for co-layout guide
1. Please Connect P1 and R1 ball first and then to GND
2. Please Connect P2 and N2 ball first and then to GND
3. Please connect DCXO GND to main GND by independent L1-2 GND via.;
DO NOT connect it through L1 GND
Let floating if disable HOMEKEY function
Please follow MT6765_MT6357 Co-Clock Design Notice for Layout guide of VAUX18,
then R210 can use 0 ohm to replace BEAD.
5
PWRKEY[3,24]
HOMEKEY[24]
SYSRSTB[10,26]
WATCHDOG[10]
SRCLKENA0[10]
SRCLKENA1[10,31]
EXT_PMIC_EN1[14]
EXT_PMIC_EN2[14]
TP201
PWRAP_SPI0_ CSN[10]
PWRAP_SPI0_ CK[10]
PWRAP_SPI0_ MO[10]
PWRAP_SPI0_ MI[10]
C204
C / 100 / nF / 10V
R209
2 1
C210
C / 1 / uF / 25 V
2 1
C / 100 / nF / 10V
Set resistor and cap. close to PMIC
C213
2 1
1
C205
D201
1 2
R202
R / 200 / K / 0201 / 1%
2 1
NC
CHD_DM[10]
CHD_DP[10]
LED_R
LED_G
21
CS_P[16]
CS_N[16]
4
UVLO_VTH
BATON
VCDT
CHRLDO
Differential
4
Differential
U201C
U / MT6357CRV/A
Control I/F RTC
R4
PWRKEY
N4
FCHR_ENB
R5
RESETB
T8
WDTRSTB_IN
N3
UVLO_VTH
N7
SRCLKEN_IN0
N8
SRCLKEN_IN1
M5
EXT_PMIC_EN1
N5
EXT_PMIC_EN2
M6
EXT_PMIC_PG
R8
SPI_CSN
M8
SPI_CLK
M7
SPI_MOSI
M9
SPI_MISO
P5
PMU_TESTMODE
P9
FSOURCE
Charger I/F
N9
VSYSSNS
M13
BATSNS
N13
ISENSE
R13
BATON
T11
VCDT
R11
CHRLDO
P13
VDRV
M10
CHG_DM
M11
CHG_DP
N12
PCHR_LED
Gauge
T10
CS_P
R10
CS_N
ISINK
L12
ISINK1
MT6357
DCXO
AUXADC
VRTC28
RTC32K_1V8_0
RTC32K_1V8_1
RTC32K_2V8
AVSS22_XO
AVSS22_XOBUF0
AVSS22_XOBUF1
AVSS22_XO_ISO0
AVSS22_XO_ISO1
XO_SOC
XO_CEL
XO_WCN
XO_NFC
XO_EXT
XTAL1
XTAL2
AVDD18_AUXADC
AVSS18_AUXADC
AUXADC_VIN
3
3
Set cap. close to chip
R12
D_GND
P14
R15
P11
AVSS22_XO
M2
AVSS22_XOBUF
P1
R1
AVSS22_XO_ISO
N2
P2
XO_SOC
R3
XO_CEL
T1
XO_WCN
P3
XO_NFC
R2
T2
M1
XTAL1
N1
XTAL2
R7
P7
T7
2
R222 R / 1.5 / K / 0201
C201
C / 100 / nF / 6.3V
2 1
3mil trace width
3mil trace width
C220 C / 10 / uF/04 02
RTC32K_CK [10]
Note: 22-2
SH205
2
1
SH206
1 2
SH207
1 2
1 2
R203 R / 0 / ohm / 020 1
1 2
R204 R / 0 / ohm / 020 1
C211
C / 1 / uF / 6.3 V
2 1
C212
C / 100 / nF / 6.3V
2 1
D_GND
D_GND
D_GND
C206
C / NC / 0201
2 1
C207
C / NC / 0201
2 1
1 2
C208
C / 5 / pF / NC
2 1
Note: 22-4
VAUX18_PMU
SH204
SHORT / 4MIL
1 2
C209
C / NC / 0201
2 1
Set cap. close to PMIC
AVSS18_AUXADC
AUXADC_VIN
AVDD18_AUXADC
3mil trace width
3mil trace width
3mil trace width
R211
R / 100 / K / 0201 / 1%
1 2
1%
XTAL1
3mil trace width
AVSS18_AUXADC
3mil trace width
4
Note: 22-1
Route AVDD18_AUXADC, AUXADC_VIN, and AVSS18_AUXADC with 3mils width traces and well GND shielding
Title
Title
Title
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Date: Sheet of
Date: Sheet of
2
Date: Sheet of
X201
TMS / OZ260300 01
RT1
XT11RT2
Amman
Amman
Amman
3
XT2
2
1
PMIC_CLK_BB [11]
PMIC_CLK_RF [31]
PMIC_CLK_W CN [37]
PMIC_CLK_NFC
XTAL2
3mil trace width
POWER_MT6357 _IF
POWER_MT6357 _IF
POWER_MT6357 _IF
1
V1.0
V1.0
V1.0
2 38Wednesday, April 01, 2020
2 38Wednesday, April 01, 2020
2 38Wednesday, April 01, 2020
5
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4
3
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1
Switching Charger Power Path
PG
Open drain active low power good indicator. Connect to the pull up rail
through 10-kΩ resistor. LOW indicates a
good input source if the input voltage is between UVLO and ACOV, above SLEEP
mode threshold, and current
limit is above 30 mA.
Power source selection input
CHG_PSEL[10]
C C
B B
input current limit by pulling H=500mA L=2.4A
CHG_PG[10]
VIO18_PMU
CHG_STAT[10]
SCL5[10]
SDA5[10]
CHG_INT[10]
ETA6953:address: D6H BQ25601:address: 6BH
VIO18_PMU
VBUS
R302 R / 10K/ 0201
R / NC / 0201
R / NC / 0201
R / 10 / K / 0201
R / 10 / K / 0201
R306
R304
R307
R305
D_GND
R309
GPIO_CHG_EN_0[10]
C301
21
C / 1 / uF / 25V /0603
24
VBUS
1
VAC
2
PSEL
3
PG
4
STAT
5
SCL
6
SDA
INT7NC18CE9NC210TS11QON
R / 10 / K / 0201
D_GND
D_GND
C303
21
C / 10/ uF / 16V /0603
23
PMID
CE=0 charge enabled
CE=1 charge disabled
1 2
R / 10 / K / 0201 / 5%
U301
R301
21
C / 4.7/ uF / 0402 /1 0V
22
REGN
ETA6953
C309
C / 47nF / 0201 / 25 V
2 1
21
BST
VLDO
Charge enable pin
C304
PL301
PL / 1 / uH / 2520
C308
C312
2 1
GND
SW219SW1
GND2
GND1
SYS2
SYS1
BAT2
BAT1
12
R315
R310
R / 10 / K / 0201 / 5%
25
18
17
16
15
14
13
1 2
2 1
C / 10 / uF / 10V
C / 10 / uF / 10V
D_GND
C307
C / 10 / uF / 6.3V
2 1
D_GND
R / NC / 0201
C320
2 1
D_GND
REGN [3]
20
1 2
VSYS
1
FV301
1
2
ESD56201D05
2
D_GND
VBAT
PWRKEY [2,24]
NC
REGN [3]
1 2
A A
Title
Title
Title
Amman
Amman
Amman
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
04_POWER_LCMBIAS_BL_FLASH
04_POWER_LCMBIAS_BL_FLASH
04_POWER_LCMBIAS_BL_FLASH
D
D
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Date: Sheet of
Date: Sheet of
Date: Sheet of
<Variant Name>
<Variant Name>
5
4
<Variant Name>
Title
Title
Title
11_POWER_SubPMIC-General
11_POWER_SubPMIC-General
11_POWER_SubPMIC-General
Size
Size
Size
D
D
D
MTK Confidential
MTK Confidential
MTK Confidential
Date: Sheet of
Date: Sheet of
Date: Sheet
3
of
3 35Wednesday, April 01, 2020
3 35Wednesday, April 01, 2020
3 35Wednesday, April 01, 2020
2
1
V1.0
V1.0
V1.0
3 38Wednesday, April 01, 2020
3 38Wednesday, April 01, 2020
3 38Wednesday, April 01, 2020
5
4
3
2
1
Flash LED Driver
PL401 PL / 1.0 / uH / 2016
PL402
PL / 10 / uH
1 2
C2
IN
EN
GND
B2
C / 330 /nF
C417
C / 10 / uF / 16V
VIN4LX0
10
ENF
11
ENM
2
ISETF
1
ISETM
SY7726POC
C3
U405
LX
ISET
LED2
LED1
PWMB1NC
C410
1
NC
2
D_GND
LCM_AVDD [30]
LCM_AVEE [30]
1 2
U401
VOUT0
VOUT1
AGND03PGND
GND
7
15
2
R / 42.2K/ o hm / 0201 / 1%
A1
A2
A3
D_GND
C403
5
C / 2.2 / uF / 1 6V
6
LX1
9
8
12
LED1
14
LED2
AGND1
SY7803
13
D401
1
D_GND
R418
C463
C462
C / 33 / pF / 50V
C / 33 / pF / 50V
D_GND
3
FLASH_LED [21]
C406
C / 1/ uF / 060 3 /50V
2
SH403
SHORT / 4MIL
1
D_GND
FLASH_LEDA [21]
B461
C461
C / 33 / pF / 5 0V
D_GND
HPZ1608D102- R60TF
LCM_LEDA [30]
LCM_LEDK_2 [30]
LCM_LEDK_1 [30]
Title
Title
Title
Amman
Amman
Amman
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
04_POWER_ LCMBIAS_BL_FLASH
04_POWER_ LCMBIAS_BL_FLASH
04_POWER_ LCMBIAS_BL_FLASH
4 38Wednesday, April 0 1, 2020
4 38Wednesday, April 0 1, 2020
4 38Wednesday, April 0 1, 2020
1
V1.0
V1.0
V1.0
1
PL403
4.7 / uH / 2520
1
AVDD
BSTO2
BSTO1
AVEE
CFLY1
VSYS
C / 2.2/ uF / 1 0V
GPIO_FLASH_EN[11]
GPIO_FLSAH_CE[11]
I_movie=6800/R_isetf I_movie=6800/R_isetm
R461 R / 0 / ohm / 06 03
VSYS
LCM_PWM[30]
2
D1
LX
E3
D3
E2
A2
C3
C / 2.2 / uF / 1 6V
C415
A3
C414
C / 4.7 / uF / 1 0V /0603
2
SH402
SHORT / 4MIL
1
D_GND
4
1
C401
2
Flash mode enable pin
MOVIE/TORCH mode enable
R450
R / 12K / 0201 /1%
1
C / 1 / uF / 10V /0402
2
1
C426
C / 1 / uF / 10 V / 0201
2
C408
D_GND
D_GND
D_GND
C420
R406
D_GND D_GND
C402
C / 100 / nF / 25V
R451
R / 120K / 0201 /1%
R417
R / 10 / ohm / 04 02
C1
B3
R / 0R / 0201
C416
C / 10 / uF / 16V
D D
C C
Backlight
BL_EN[11]
TP403
B B
LCM BIAS
Address: 0X3E
D_GND
1
C413
C / 4.7 / uF / 6 .3V
D_GND
2
U404
C1
VIN
B1
ENP
A1
ENN
B2
SCL
C2
R421 R / NC / 0201
R422 R / NC / 0201
SDA
B3
PGND1
E1
PGND2
AGNDD2CFLY2
OCP2131WP AD
D_GND
VSYS
GPIO_LCM_BIAS_ENP[10]
GPIO_LCM_BIAS_ENN[10]
SCL6[10 ,26]
SDA6[10,26]
A A
5
5
4
3
2
1
Note: 20-2
U201A
R501
R / 1 / ohm / 020 1
1
VSYS
D D
12
LTVS8H4_5CT5G / NC
D_GND
VR501
D_GND
C501
2 1
C / NC / 0402
D_GND
C509
2 1
C / 10 / uF / 1 0V
For EOS Optional
C C
2
SH501
1
2
SHORT / 4MIL
C / 10 / uF / 1 0V
SH507
1
2
SH502
1
2
SHORT / 20MIL
SH503
1
2
SH508
1
2
SHORT / 20MIL
C503
C502
C / 1 / uF / 10 V
2 1
2 1
C504
C / 10 / uF / 1 0V
2 1
VSYS_SMPS
GND_SMPS
GND_VPROC
GND_VCORE
U / MT6357CRV/A
B2
B1
A4
B4
C4
A5
B5
C5
A8
B8
C8
C9
B9
VSYS_SMPS
GND_SMPS
VSYS_VPROC0
VSYS_VPROC1
VSYS_VPROC2
GND_VPROC0
GND_VPROC1
GND_VPROC2
VSYS_VCORE0
VSYS_VCORE1
VSYS_VCORE2
GND_VCORE0
GND_VCORE1
MT6357
VBUCK CTRL
VPROC IN VPROC
VCOREVCORE IN
VPROC0
VPROC1
VPROC2
VPROC3
VPROC4
VPROC5
VPROC_FB
GND_VPROC_FB
VCORE0
VCORE1
VCORE2
VCORE3
VCORE_FB
GND_VCORE_FB
A6
VPROC
A7
B6
B7
C6
C7
Differential and shielded with GND
C2
4mil
D2
4mil
A9
VCORE
A10
B10
C10
Differential and shielded with GND
D3
4mil
E3
4mil
PL501
PL / 0.47 / uH / 2520
WIP25201 0S-R47ML
1
2
PL502
PL / 0.47 / uH / 2520
WIP25201 0S-R47ML
1
2
Set power inductor
close to PMIC
DVDD_DVFS_6357_ FB [12]
DVDD_DVFS_6357_ GND [12]
Set power inductor
close to PMIC
DVDD_CORE_6357 _FB [12 ]
DVDD_CORE_6357 _GND [12]
DVDD_DVFS
DVDD_CORE
2
VPA_PMU
2
VS1_PMU
2
Set power inductor
close to PMIC
DVDD_MODEM_6357_ FB [12]
DVDD_MODEM_6357_ GND [12 ]
Set power inductor
close to PMIC
Set power inductor
close to PMIC
2
PL503
A13
VSYS_VMODEM0
B13
C505
SH509
1
2
C / 4.7 / uF / 1 0V
2 1
SH504
1
2
SHORT / 20MIL
SH510
C506
1
2
C / 10 / uF / 1 0V
SH505
2 1
1
SHORT / 20MIL
B B
Note 20-1:
A A
Note 20-2:
C507, please choose 0402 size
PMIC Part number notice for MT6765/62/61 platform
MT6765 / 62 CRVMT6357
MT6761 MT6357
PMICMTK Platform
MRV
5
SH511
1
SH506
1
SHORT / 20MIL
GND_VPA
2
C508
2
2 1
C / 4.7 / uF / 10V
GND_VS1
2
4
VSYS_VMODEM1
A12
GND_VMODEM0
B12
GND_VMODEM1
C12
GND_VMODEM2
VPA IN VPA
A2
VSYS_VPA0
A3
VSYS_VPA1
B3
GND_VPA
B14
VSYS_VS1_0
A14
VSYS_VS1_1
A15
VSYS_VS1_2
B15
VSYS_VS1_3
VMODEMVMODEM IN
VS1VS1 IN
VMODEM0
VMODEM1
VMODEM_FB
GND_VMODEM_FB
VPA_FB
VS1_FB
3
B11
VMODEM
C11
E13
D14
VPA
A1
VPA
E4
VS1
A16
VS1_0
B16
VS1_1
E14
PL / 1 / uH / 252 0
MPIM252010E1 R0M-LF
1
Differential and shielded with GND
4mil
4mil
PL504
PL / 1 / uH / 252 0
MPIM252010E1 R0M-LF
1
Feadback from C507
PL505
PL / 1 / uH / 252 0
MPIM252010E1 R0M-LF
1
Feedback from C601/602
DVDD_MODEM
VPA_PMU
VS1_PMU
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
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C
C
C
Date: Sheet
Date: Sheet of
Date: Sheet
C507
C / 2.2 / uF / 6 .3V
2 1
Set cap. C2040 close to
VPA power inductor
Amman
Amman
Amman
Note: 20-1
POWER_MT6357 _Buck
POWER_MT6357 _Buck
POWER_MT6357 _Buck
1
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5 38Wednesday, April 0 1, 2020
5 38Wednesday, April 0 1, 2020
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5 38Wednesday, April 0 1, 2020
V1.0
V1.0
V1.0
5
Note: 21-3
VS1_PMU
D D
VS2_PMU
VSYS
C C
VS1_PMU
EXT_VS2
EXT_VS2_FB[14]
B B
VIO18_PMU
DVDD18_DIG
C601
C / 10 / uF / 1 6V
C608
C / 22 / uF / 1 0V
2 1
Set cap. close to PMIC
R601
R / NC / 0603
1 2
2.1V
R602
SHORT
1 2
1.46V
SH601
1 2
SHORT / 4MIL
Set cap. and shortpad close to PMIC
SH605
SHORT / 4MIL
1 2
C626
C / 1 / uF / 6.3 V
2 1
1 2
SH606
SHORT / 4MIL
C602
C / 22 / uF / 4 V
2 1
1 2
SH604
SHORT / 4MIL
C627
C / 1 / uF / 6.3 V
2 1
Note: 21-3
C603
C / 4.7 / uF / 6 .3V
2 1
C607
C / 2.2 / uF / NC
2 1
Suggest trace width > 40 mil
VS2_PMU
C628
C / 100 / nF / 4V
2 1
VREF
GND_VREF
DVSS18_IO
C621
C / 100 / nF / 6.3V
2 1
DVDD18_DIG
D_GND
4
U201B
U / MT6357CRV/A
LDO IN LDO
C17
VS1_LDO1_0
Note: 21-5
F15
VS1_LDO1_1
F17
VS2_LDO2_2
G14
VSYS_LDO1_0
N17
VSYS_LDO2_1
K7
VSYS_LDO3_2
F13
D_GND0
G8
D_GND1
G7
D_GND2
G9
D_GND3
G12
D_GND4
H6
D_GND5
G10
D_GND6
G11
D_GND7
H7
D_GND8
H8
D_GND9
H9
D_GND10
H10
D_GND11
H11
D_GND12
F12
D_GND13
F11
D_GND14
F10
D_GND15
F9
D_GND16
H12
D_GND17
J6
D_GND18
D7
D_GND19
D8
D_GND20
D6
D_GND21
D9
D_GND22
F5
D_GND23
J7
D_GND24
D10
D_GND25
D11
D_GND26
D12
D_GND27
D13
D_GND28
F6
D_GND29
J8
D_GND30
K12
D_GND31
E6
D_GND32
E7
D_GND33
E8
D_GND34
F7
D_GND35
J9
D_GND36
E11
D_GND37
E9
D_GND38
E10
D_GND39
E12
D_GND40
F8
D_GND41
J11
D_GND42
VREF
T14
VREF
T13
GND_VREF
DIG Power
K10
DVDD18_IO
L10
DVDD18_DIG
J10
DVSS18_IO
MT6357
ALDO
DLDO
SLDO1
VSRAM_PROC
VSRAM_OTHERS
SLDO2
Power Switch
3
1. "Typical Cap" defined in design notice is the minimum cap. to LDO Cout. 2.
NC cap can move to application, if (PCB L<20nH, PCB R<0.2 ohm)
=> value and placement of Cap, please refer design notice
2
Set cap. close to PMIC
L14
VFE28
T4
VXO22
K13
VCN28
H16
VCAMA
T5
VAUX18
L7
VAUD28
VCN33
VLDO28
VMCH
VEMC
VSIM1
VSIM2
VEFUSE
VRF18
VCN18
VCAMD
VCAMIO
VRF12
VDRAM
C604
2 1
P17
L16
K15
VIO28
L15
VMC
N16
L17
J17
K16
M16
VIBR
J14
VUSB
H15
D16
E15
E17
A17
B17
VIO18
E16
G15
G16
H17
R9
TREF
C612
C613
C611
C / 1 / uF / 6.3V
C / 1 / uF / 6.3V
C / 1 / uF / 6.3V
2 1
2 1
2 1
C619
C / 4.7 / uF / 6.3V
2 1
2 1
C625
C622
C / 2.2 / uF / 6.3V
C / 4.7 / uF / 6.3V
2 1
2 1
2 1
C606
C605
C / 2.2 / uF / 6.3V
C620
C623
C / 1 / uF / 6.3V
C / 1 / uF / 6.3V
2 1
2 1
C614
2 1
C / 4.7 / uF / 6.3V
C624
C / 2.2 / uF / 6.3V
2 1
C616
C615
C / 1 / uF / 6.3V
C / 1 / uF / 6.3V
2 1
C / 4.7 / uF / 6.3V
C617
C618
C / 1 / uF / 6.3V
C / 1 / uF / 6.3V
2 1
C / 1 / uF / 6.3V
2 1
2 1
Note: 21-2
Note: 21-1
C609
C / NC / 0201
2 1
SH602
1 2
1
VFE28_PMU
VCN28_PMU
VCAMA_PMU
VAUX18_PMU
VAUD28_PMU
VCN33_PMU
VLDO28_PMU
VIO28_PMU
VMC_PMU
VMCH_PMU
VEMC_PMU
VSIM1_PMU
VSIM2_PMU
VIBR_PMU [30 ]
VUSB_PMU
VEFUSE_PMU
VRF18_PMU
VCN18_PMU
VCAMD_PMU
VCAMIO_PMU
VIO18_PMU
AVDD18_SOC
Note: 21-4
VRF12_PMU
DVDD_SRAM_DVFS
VSRAM_OTHERS_PMU
VDRAM_PMU
TREF_PMU
A A
Please refer to MT6357 design notice.
Note 21-2:
Note 21-3:
Output cap range please follow MT6357CRV LDO design notice
Ext Buck BOM option
w/ EXT VS2 Buck w/o EXT VS2 Buck
C601 10uF 22uF, 0603
5
R602 0-ohm , 0603
R601
NC
Ext. buck option
NC
0-ohm , 0603
4
Note 21-4:
Please set SH602 and SH603 close to C620, making star connection among VIO18_PMU, AVDD18_SOC, and
EMI_VDD1 near to LDO cap. C620
Please also refer to MT6357 design notice for further detail des ign information
Note 21-5: Please connect VS2_LDO1(F15) to VS1_PMU if volt age applied to VCAMD(E17) >= 1.3 V
3
2
Title
Title
Title
Amman
Amman
Amman
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
POWER_MT6357 _LDO
POWER_MT6357 _LDO
POWER_MT6357 _LDO
1
6 38Wednesday, April 0 1, 2020
6 38Wednesday, April 0 1, 2020
6 38Wednesday, April 0 1, 2020
V1.0
V1.0
V1.0
If these power trace can meet LDO layout constraint, these CAP can be NC or removed.
Note 21-1:
5
D D
AU_VIN0_P[18]
AU_VIN0_N[18]
C C
C708
C709
C /NC / 0201
C / NC / 0201
2 1
2 1
P-N pair should be differential pair & shielded with GND
- AU_HPL and AU_HPR should be routed as single end signal,
and be guarded by GND, up and down, left and right respectively
- The suggested layout pattern of AU_HPL/ AU_HPR/ AU_REFN
is " GND AU_HPL AU_REFN AU_HPR GND"
B B
AU_HPL[19]
AU_REFN[19]
AU_HPR[1 9]
C707
C / 10/ nF / 02 01
2 1
Set cap. close to PMIC
4
AUD_CLK_MISO[10]
AUD_DAT_MISO0[10]
AUD_DAT_MISO1[10]
AUD_SYNC_MISO[10]
AUD_CLK_MOSI[10]
AUD_DAT_MOSI0[10]
AUD_DAT_MOSI1[10]
AUD_SYNC_MOSI[10]
P-N pair should be
differential pair & shielded with GND
AU_VIN1_P[19]
AU_VIN1_N[19]
AU_VIN2_P[18]
AU_VIN2_N[18]
P-N pair should be
differential pair & shielded with GND
ACCDET[19]
HP_EINT[19]
AU_LOLP[17]
AU_LOLN[17]
P-N pair should be differential pair & shielded with GND
AU_HSP[18]
AU_HSN[1 8]
P-N pair should be
differential pair & shielded with GND
3
U201D
R16
T17
R17
T16
P16
P15
N14
M14
U / MT6357CRV/A
MT6357
AUDIO IF UL POWER
AUD_CLK_MISO
AUD_DAT_MISO0
AUD_DAT_MISO1
AUD_SYNC_MISO
AUD_CLK_MOSI
AUD_DAT_MOSI0
AUD_DAT_MOSI1
AUD_SYNC_MOSI
AUDIO INPUT
K3
AU_VIN0_P
K4
AU_VIN0_N
K5
AU_VIN1_P
L5
AU_VIN1_N
J4
AU_VIN2_P
J5
AU_VIN2_N
ACCDET
M4
ACCDET
J1
HP_EINT
AUDIO OUTPUT
J2
AU_HPL
H3
AU_REFN
G3
AU_HPR
F4
AU_LOLP
F3
AU_LOLN
G6
AU_HSP
G5
AU_HSN
AVDD28_AUD
AVSS28_AUD
AU_MICBIAS0
AU_MICBIAS1
CHARGE PUMP
AVDD18_AUD
AVSS18_AUD
AU_V18N
2
K1
H5
AVSS28_AUD[19]
L3
M3
C701
C / 1 / uF / 6.3 V
2 1
SH701
SHORT / 4MIL
21
C702
1 2
C703
C / 1 / uF / 6.3V
C / 1 / uF / 6.3V
2 1
VAUD28_PMU
AU_MICBIAS0 [18,30]
AU_MICBIAS1
1
Set cap. and shortpad close to PMIC
G2
F2
D1
F1
FLYP
E2
FLYN
21
AVSS_AUD
21
AU_V18N
FLYP
FLYN
2 1
Set cap. close to PMIC
C704
C / 2.2 / uF / 6 .3V
C705
C / 4.7 / uF / 6 .3V
C706
C / 4.7 / uF / 6 .3V
1 2
SH702
SHORT / 4MIL
1. AVSS18_AUD is connected to GND in very short trace
2. AVSS18_AUD is connected to de-couple cap of
AVDD18_AUD and AU_V18N with 6mil trace respectively
VIO18_PMU
A A
Title
Title
Title
Amman
Amman
Amman
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet
5
4
3
2
POWER_MT6357 _Audio
POWER_MT6357 _Audio
POWER_MT6357 _Audio
1
V1.0
V1.0
V1.0
of
7 38Wednesday, April 0 1, 2020
7 38Wednesday, April 0 1, 2020
7 38Wednesday, April 0 1, 2020
5
D D
EBI0_CLK_P[9]
EBI0_CLK_N[9]
EBI0_DQS0_T[9]
EBI0_DQS0_C[9]
EBI0_DQS1_T[9]
EBI0_DQS1_C[9]
EBI0_DM_0[9]
EBI0_DM_1[9]
EBI0_CS_0[9]
EBI0_CS_1[9]
EBI0_CKE_0[9] EBI1_CKE_0[9]
EBI0_CKE_1[9] EBI1_CKE_1[9]
EBI0_CA_0[9] EBI1_CA_0[9]
EBI0_CA_1[9] EBI1_CA_1[9]
EBI0_CA_2[9] EBI1_CA_2[9]
EBI0_CA_3[9] EBI1_CA_3[9]
EBI0_CA_4[9] EBI1_CA_4[9]
EBI0_CA_5[9] EBI1_CA_5[9]
C C
B B
EMI_VDDQ_FB[14]
EMI_VDD1
EMI_VDDQ
SH810
SHORT / 4MIL
1 2
EMI_VDD2
SH809
SHORT / 4MIL
1 2
EMI_VDD2_FB[14]
4
U801A
R801 R_0201_240R
1 2
J8
J9
D3
E3
D10
E10
C3
C10
H4
H3
G2
J4
J5
H2
J2
H9
H10
H11
J11
A5
C801
C_0201_1uF_6.3V
2 1
CK_T_A
CK_C_A
DQS0_T_A
DQS0_C_A
DQS1_T_A
DQS1_C_A
DMI0_A
DMI1_A
CS0_A
CS1_A_NC
ODT_CA_A
CKE0_A
CKE1_A_NC
CA0_A
CA1_A
CA2_A
CA3_A
CA4_A
CA5_A
ZQ0
LPDDR4X
C802
B2
DQ0_A
C2
DQ1_A
E2
DQ2_A
F2
DQ3_A
F4
DQ4_A
E4
DQ5_A
C4
DQ6_A
B4
DQ7_A
B11
DQ8_A
C11
DQ9_A
E11
DQ10_A
F11
DQ11_A
F9
DQ12_A
E9
DQ13_A
C9
DQ14_A
B9
DQ15_A
EMI_VDD2
EMI_VDDQ
C803
C804
C_0201_1uF_6.3V
C_0201_1uF_6.3V
C_0201_1uF_6.3V
2 1
2 1
2 1
EBI0_DQ0 [9]
EBI0_DQ1 [9]
EBI0_DQ2 [9]
EBI0_DQ3 [9]
EBI0_DQ4 [9]
EBI0_DQ5 [9] EBI1_DQ5 [9]
EBI0_DQ6 [9]
EBI0_DQ7 [9]
EBI0_DQ8 [9] EBI1_DQ8 [9]
EBI0_DQ9 [9]
EBI0_DQ10 [9]
EBI0_DQ11 [9] EBI1_DQ11 [9]
EBI0_DQ12 [9]
EBI0_DQ13 [9]
EBI0_DQ14 [9] EBI1_DQ14 [9]
EBI0_DQ15 [9] EBI1_DQ15 [9]
U801C
A4
VDD2
A9
VDD2
F5
VDD2
F8
VDD2
H1
VDD2
H5
VDD2
H8
VDD2
H12
VDD2
K1
VDD2
K3
VDD2
K10
VDD2
K12
VDD2
N1
VDD2
N3
VDD2
N10
VDD2
N12
VDD2
R1
VDD2
R5
VDD2
R8
VDD2
R12
VDD2
U5
VDD2
U8
VDD2
AB4
VDD2
AB9
VDD2
B3
VDDQ
B5
VDDQ
B8
VDDQ
B10
VDDQ
D1
VDDQ
D5
VDDQ
D8
VDDQ
D12
VDDQ
F3
VDDQ
F10
VDDQ
U3
VDDQ
U10
VDDQ
W1
VDDQ
W5
VDDQ
W8
VDDQ
W12
VDDQ
AA3
VDDQ
AA5
VDDQ
AA8
VDDQ
AA10
VDDQ
F1
VDD1
F12
VDD1
G4
VDD1
G9
VDD1
T4
VDD1
T9
VDD1
U1
VDD1
U12
VDD1
LPDDR4X
C815
C814
C807
C806
C805
C_0201_1uF_6.3V
C_0201_1uF_6.3V
C_0201_1uF_6.3V
2 1
2 1
2 1
C817
C819
C818
C_0201_1uF_6.3V
C_0201_1uF_6.3V
C_0201_1uF_6.3V
2 1
2 1
2 1
C810
C809
C808
C_0201_1uF_6.3V
C_0201_1uF_6.3V
2 1
2 1
C820
C821
C_0201_1uF_6.3V
C_0201_1uF_6.3V
2 1
2 1
C _0603_22uF_6.3V
C _0603_22uF_6.3V
C_0201_1uF_6.3V
2 1
2 1
2 1
C823
C822
C_0201_1uF_6.3V
2 1
C825
C824
C_0201_1uF_6.3V
C _0603_22uF_6.3V
C_0201_1uF_6.3V
2 1
2 1
2 1
3
U801B
R802 R_0201_240R
1 2
T11
RESET_N
P8
CK_T_B
P9
CK_C_B
W3
DQS0_T_B
V3
DQS0_C_B
W10
DQS1_T_B
V10
DQS1_C_B
Y3
DMI0_B
Y10
DMI1_B
R4
CS0_B
R3
CS1_B_NC
T2
ODT_CA_B
P4
CKE0_B
P5
CKE1_B_NC
R2
CA0_B
P2
CA1_B
R9
CA2_B
R10
CA3_B
R11
CA4_B
P11
CA5_B
A8
ZQ1_NC
LPDDR4X
U801D
A1
DNU0
A2
DNU1
A11
DNU2
A12
DNU3
B1
DNU4
B12
DNU5
AA1
DNU6
AA12
DNU7
AB1
DNU8
AB2
DNU9
AB11
DNU10
AB12
DNU11
LPDDR4X
DDR_RESET_N[9]
EBI1_CLK_P[9]
EBI1_CLK_N[9]
EBI1_DQS0_T[9]
EBI1_DQS0_C[9]
EBI1_DQS1_T[9]
EBI1_DQS1_C[9]
EBI1_DM_0[9]
EBI1_DM_1[9]
EBI1_CS_0[9]
EBI1_CS_1[9]
EMI_VDD2EMI_VDD2
EMI_VDDQEMI_VDDQ
A3
VSS
A10
VSS
C1
VSS
C5
VSS
C8
VSS
C12
VSS
D2
VSS
D4
VSS
D9
VSS
D11
VSS
E1
VSS
E5
VSS
E8
VSS
E12
VSS
G1
VSS
G3
VSS
G5
VSS
G8
VSS
G10
VSS
G12
VSS
J1
VSS
J3
VSS
J10
VSS
J12
VSS
K2
VSS
K4
VSS
K9
VSS
K11
VSS
N2
VSS
N4
VSS
N9
VSS
N11
VSS
P1
VSS
P3
VSS
P10
VSS
P12
VSS
T1
VSS
T3
VSS
T5
VSS
T8
VSS
T10
VSS
T12
VSS
V1
VSS
V5
VSS
V8
VSS
V12
VSS
W2
VSS
W4
VSS
W9
VSS
W11
VSS
Y1
VSS
Y5
VSS
Y8
VSS
Y12
VSS
AB3
VSS
AB5
VSS
AB8
VSS
AB10
VSS
DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
DQ8_B
DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B
NC0
NC1
NC2
NC3
NC4
AA2
Y2
V2
U2
U4
V4
Y4
AA4
AA11
Y11
V11
U11
U9
V9
Y9
AA9
R803 R_0201_240R
G11
K5
K8
N5
N8
2
EBI1_DQ0 [9]
EBI1_DQ1 [9]
EBI1_DQ2 [9]
EBI1_DQ3 [9]
EBI1_DQ4 [9]
EBI1_DQ6 [9]
EBI1_DQ7 [9]
EBI1_DQ9 [9]
EBI1_DQ10 [9]
EBI1_DQ12 [9]
EBI1_DQ13 [9]
12
EMI_VDDQ
1
A A
Title
Title
Title
Amman
Amman
Amman
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
POWER_MT6357_Audio
POWER_MT6357_Audio
POWER_MT6357_Audio
D
D
D
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
V1.0
V1.0
V1.0
8 38Wednesday, April 01, 2020
8 38Wednesday, April 01, 2020
8 38Wednesday, April 01, 2020
1
5
D D
C C
B B
Note: 14-1
R901
R / 60.4 / o hm / 0201 / 1%
D_GND
DDR_RESET_N[8]
12
Note: 14-2
4
U901G
MT6761
MT6762-SBS
EBI1_DQ12[ 8]
EBI1_DQ10[ 8]
EBI1_DQ8[8]
EBI1_DQ15[ 8]
EBI1_DQ14[ 8]
EBI1_DQ9[8]
EBI1_DQ11[ 8]
EBI1_DQ13[ 8]
EBI1_CA_1[8]
EBI1_CKE_0[8]
EBI1_CA_0[8]
EBI1_CA_4[8]
EBI1_CKE_1[8]
EBI1_CA_5[8]
EBI1_CA_3[8]
EBI1_CA_2[8]
EBI0_DQ13[ 8]
EBI0_DQ11[ 8]
EBI0_DQ14[ 8]
EBI0_DQ15[ 8]
EBI0_DQ12[ 8]
EBI0_DQ10[ 8]
EBI0_DQ8[8]
EBI0_DQ9[8]
EBI1_DQ3[8]
EBI1_DQ2[8]
EBI1_DQ0[8]
EBI1_DQ1[8]
EBI1_DQ5[8]
EBI1_DQ7[8]
EBI1_DQ4[8]
EBI1_DQ6[8]
MSDC0_DAT7[15]
MSDC0_DAT1[15]
MSDC0_DAT2[15]
MSDC0_DAT0[15,2 6]
MSDC0_DAT3[15]
MSDC0_DAT4[15]
MSDC0_DAT6[15]
MSDC0_DAT5[15]
C13
C15
C14
E15
B15
D15
E16
B17
A17
E18
F18
C18
D19
E19
C19
A19
D10
C11
C10
D12
B13
B11
B12
E11
D20
E20
E21
D21
B20
C22
C21
A21
F16
G16
E23
B4
A26
B24
B23
A23
C24
A25
D24
C26
EMI0_DQ0
EMI0_DQ1
EMI0_DQ2
EMI0_DQ3
EMI0_DQ4
EMI0_DQ5
EMI0_DQ6
EMI0_DQ7
EMI0_DQ8
EMI0_DQ9
EMI0_DQ10
EMI0_DQ11
EMI0_DQ12
EMI0_DQ13
EMI0_DQ14
EMI0_DQ15
EMI0_DQ16
EMI0_DQ17
EMI0_DQ18
EMI0_DQ19
EMI0_DQ20
EMI0_DQ21
EMI0_DQ22
EMI0_DQ23
EMI0_DQ24
EMI0_DQ25
EMI0_DQ26
EMI0_DQ27
EMI0_DQ28
EMI0_DQ29
EMI0_DQ30
EMI0_DQ31
VREF_EMI
NC5
NC6
EMI_EXTR
eMMC (MSDC0)
MSDC0_DAT7
MSDC0_DAT6
MSDC0_DAT5
MSDC0_DAT4
MSDC0_DAT3
MSDC0_DAT2
MSDC0_DAT1
MSDC0_DAT0
EMI_DDR
3
EMI0_CS0_n
EMI0_CS1_n
EMI0_CKE0
EMI0_CKE1
EMI0_DM0
EMI0_DM1
EMI0_DM2
EMI0_DM3
EMI0_CK_T
EMI0_CK_C
EMI0_DQS0_C
EMI0_DQS0_T
EMI0_DQS1_C
EMI0_DQS1_T
EMI0_DQS2_C
EMI0_DQS2_T
EMI0_DQS3_C
EMI0_DQS3_T
EMI0_CA0
EMI0_CA1
EMI0_CA2
EMI0_CA3
EMI0_CA4
EMI0_CA5
EMI0_CA6
EMI0_CA7
EMI0_CA8
EMI0_CA9
MSDC0_RSTB
MSDC0_CMD
MSDC0_CLK
MSDC0_DSL
2
A9
E8
D8
E7
B16
C17
E10
B19
F9
E9
E14
D14
D17
E17
E13
F13
E22
D22
B8
B7
C7
D6
B5
D5
C5
E6
E5
A5
A7
NC7
B9
NC8
C4
NC9
C9
NC10
D4
NC11
D7
NC12
D11
NC13
D18
NC14
C25
B25
D25
B26
EBI0_CS_1 [8]
EBI0_CS_0 [8]
EBI0_CKE_0 [8]
EBI0_CKE_1 [8]
EBI1_DM_1 [8]
EBI1_CS_1 [8]
EBI0_DM_1 [8]
EBI1_DM_0 [8]
EBI0_CLK_P [8]
EBI0_CLK_N [8]
EBI1_DQS1_C [8]
EBI1_DQS1_T [8]
EBI1_CLK_N [8]
EBI1_CLK_P [8]
EBI0_DQS1_C [8]
EBI0_DQS1_T [8]
EBI1_DQS0_C [8]
EBI1_DQS0_T [8]
EBI0_CA_3 [8]
EBI0_CA_2 [8]
EBI0_DQ5 [8]
EBI0_DQ2 [8]
EBI0_DQ7 [8]
EBI0_DQ0 [8]
EBI0_DQ6 [8]
EBI0_DQ3 [8]
EBI0_DQ1 [8]
EBI0_DQ4 [8]
EBI0_DM_0 [8]
EBI0_CA_4 [8]
EBI0_DQS0_C [8]
EBI0_CA_1 [8]
EBI0_DQS0_T [8]
EBI0_CA_5 [8]
EBI0_CA_0 [8]
EBI1_CS_0 [8 ]
MSDC0_RSTB [15 ,26]
MSDC0_CMD [1 5,26]
MSDC0_CLK [1 5]
MSDC0_DSL [1 5,26]
1
A A
Note 14-1: R4001 please select 34.8 ohm (1%) resistor
Title
Title
Title
Amman
Amman
Note 14-2: Please check eMCP LP3 and eMCP LP4X pin mux
5
4
3
2
Amman
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
MT6761_EBI
MT6761_EBI
MT6761_EBI
9 38Wednesday, April 0 1, 2020
9 38Wednesday, April 0 1, 2020
9 38Wednesday, April 0 1, 2020
1
V1.0
V1.0
V1.0
5
U901A
MT6761
MT6762-SBS
PMU_IF
SYSRSTB[2,26]
WATCHDOG[2]
SRCLKENA0[2]
SRCLKENA1[2,31]
D D
RTC32K_CK[2]
PWRAP_SPI0_CSN[2,10]
PWRAP_SPI0_CK[2]
PWRAP_SPI0_MO[2,10]
PWRAP_SPI0_MI[2,10]
AUD_CLK_MOSI[7]
AUD_CLK_MISO[7]
AUD_DAT_MISO0[7]
AUD_DAT_MISO1[7]
AUD_DAT_MOSI0[7,10]
AUD_DAT_MOSI1[7]
AUD_SYNC_MISO[7]
AUD_SYNC_MOSI[7]
C C
"PWRAP_SPI0_CSN" and "AUD_DAT_MOSI0" are bootstrap pin to select which in terface will be the JTAG pin out.
Note 12-3:
PWRAP_SPI0_CSN
B B
Note 12-4: PWRAP_SPI0_MI is DDR type feature in boots trap
PWRAP_SPI0_MI
PWRAP_SPI0_MI
default=PU DDR
E27
K24
L25
M25
H26
K27
L27
M27
K28
J25
G27
J27
J28
K26
K25
H27
J26
F27
W13
W12
D_GND
AC5
AB6
A1
A28
AG1
AG28
AUD_DAT_MOSI0
default=PU
default=PD
HI
HI
LO
(by ext. PD)
LO
(by ext. PD)
Booting interface
DDR
default=PU
LPDDR3
(by ext. PD)
LPDDR4XLOfollow LP4X Ref SCH.
HI
PWRAP_SPI0_MO Booting interface
default=PD
LO
(by ext. PD)
LO
(by ext. PD)
HI
HI
SYSRSTB
WATCHDOG
SRCLKENA0
SRCLKENA1
RTC32K_CK
PWRAP_SPI0_CSN
PWRAP_SPI0_CK
PWRAP_SPI0_MO
PWRAP_SPI0_MI
AUD_CLK_MOSI
AUD_CLK_MISO
AUD_DAT_MISO0
AUD_DAT_MISO1
AUD_DAT_MOSI0
AUD_DAT_MOSI1
AUD_SYNC_MISO
AUD_SYNC_MOSI
Test Pin
TESTMODE
TP_PLLGP
TN_PLLGP
CDM3P5A
CDM5P5A
NC1
NC2
NC3
NC4
LO
HI
LO
HI
LO
HI
(by ext. PU)
LO
HI
(by ext. PU)
(by ext. PU)
(by ext. PU)
MSDC0 pin mux
follow LP3 Ref SCH.
AP_JTAG
N/A
SPI0+EINT8
SPI0+EINT8
MSDC1
LPDDR3
N/A
LPDRR4X
LPDDR4
JTAG Function
follow LPDDR3 Ref SCH.
MD_JTAG
N/A
SPI1+SPI3
N/A
N/A
MSDC0 pin mux
N/A
follow LP4X/LP4 Ref SCH.
follow LP4X/LP4 Ref SCH.
4
USB_DP[26,30]
USB_DM[26,30]
GPIO_GPS_LNA_EN[37]
SCL0[36]
SDA0[36]
MSDC1_CMD[23]
MSDC1_DAT3[23]
MSDC1_DAT2[23]
MSDC1_DAT1[23]
MSDC1_DAT0[23]
AUD_DAT_MOSI0 [7,10]
U901D
MT6761
MT6762-SBS
CONN_Dig.
USB
C27
USB_ID[30]
DRVBUS
CHD_DP[2]
CHD_DM[2]
BOOT_MODE[24,26]
KPCOL1[24]
SCL1[22,36]
SDA1[22,36]
SCL2[21]
SDA2[21]
SCL3[14,26]
SDA3[14,26]
SCL4[21]
SDA4[21]
SCL5[3]
SDA5[3]
SCL6[4,26]
SDA6[4,26]
URXD0[26]
MSDC1_CLK[23]
VIO18_PMU
IDDIG
AB26
DRVBUS
BC
D26
CHD_DP
E26
CHD_DM
KEYPAD
AA1
KPROW0
AB1
KPROW1
AB3
KPCOL0
AB2
KPCOL1
I2C
AB5
SCL0
Touch
AC4
SDA0
AE1
SCL1
Sensor Hub
AF1
SDA1
V4
SCL2
Rear Cam
V3
SDA2
AC21
SCL3
NFC
AC22
SDA3
U6
SCL4
Front Cam
V6
SDA4
AB23
SCL5
Sub PMIC
AC23
SDA5
J3
SCL6
J4
SDA6
UART
AA3
URXD0
AA2
UTXD0[26]
UTXD0
SD (MSDC1)
W26
MSDC1_CLK
W27
MSDC1_CMD
W25
MSDC1_DAT3
AA27
MSDC1_DAT2
Y26
MSDC1_DAT1
Y27
MSDC1_DAT0
12
R1001
R / NC / 0201
PWRAP_SPI0_CSN [2,10]
12
USB_DP
B27
USB_DM
AB27
Note: 12-3
R1005
R / NC / 0201
CONN_IQ
GPIO
CONN_TOP_CLK
CONN_TOP_DATA
CONN_BT_CLK
CONN_BT_DATA
CONN_WF_CTRL0
CONN_WF_CTRL1
CONN_WF_CTRL2
CONN_WB_PTA
CONN_HRST_B
ANT_SEL0
ANT_SEL1
ANT_SEL2
GPIO_EXT0
GPIO_EXT1
GPIO_EXT2
GPIO_EXT3
GPIO_EXT4
GPIO_EXT5
GPIO_EXT6
GPIO_EXT7
GPIO_EXT8
GPIO_EXT9
GPIO_EXT10
GPIO_EXT11
GPIO_EXT12
GPIO_EXT13
GPIO_EXT14
GPIO_EXT15
SRCLKENAI
PWRAP_SPI0_MO[2,10]
3
J6
CONN_TOP_CLK [ 37]
K7
CONN_TOP_DATA [37]
J5
BT_CLK [37]
K8
BT_DATA [37]
H5
WF_CTRL0 [37]
H4
WF_CTRL1 [37]
H3
WF_CTRL2 [37]
G2
CONN_WB_PTA [37]
G3
CONN_HRST_B [37]
G7
CONN_XO_IN_BB [37]
XIN_WBG
K5
K6
K4
F1
GPS_I [37]
GPS_I
G1
GPS_Q [37]
GPS_Q
A3
WF_IP [37]
WF_IP
A2
WF_IN [37]
WF_IN
B1
WF_QP [37]
WF_QP
B2
WF_QN [37]
WF_QN
D2
BT_IP [37]
BT_IP
D1
BT_IN [37]
BT_IN
E3
BT_QP [37]
BT_QP
F3
BT_QN [37]
BT_QN
G23
Rear Cam_AVDD_LDO_EN [21]
F25
BOARD_ID1 [26]
F24
BOARD_ID2 [26]
G24
BOARD_ID3 [26]
F26
FP_RST [22]
G25
GPIO_LCM_BIAS_ENP [4]
H23
FP_VCC_EN [22]
H24
VPL_EN
AA24
GPIO_CHG_EN_0 [3]
Y23
NFC_WKUP
AA23
GPIO_LCM_BIAS_ENN [4]
AD21
GPIO_CTP_RSTB [30]
AD20
CHG_PSEL [3]
AD19
CHG_PG [3]
AC20
NFCPD
AC19
LCD_1.8V_EN [30]
Y1
NFC_CLK_REQ
AC3
PWM0
AE26
INT_SIM1
AF27
SIM/TF_DET [10,23]
INT_SIM2
AB4
EINT_CTP [30]
EINT0
AA7
SIM/TF_DET [10,23]
EINT1
AA5
FP_INT [22]
EINT2
AA4
FIXTURE_META_MODE [26]
EINT3
Y6
PLsensor_EINT [22]
EINT4
Y7
CHG_INT [3]
EINT5
Y4
EINT6
Y3
EINT_ACC_2 [22]
EINT7
AA6
EINT8 [26]
EINT8
W4
SAR_CAP_INT [36]
EINT9
W3
NFC_IRQ
EINT10
W7
CHG_STAT [3]
EINT11
M26
EINT_ACC [22]
EINT12
VIO18_PMU
12
R1009
R / NC / 0201
PWRAP_SPI0_MI [2,10]
12
R1006
Note: 12-4
R / NC/ 0201
2
1
A A
Title
Title
Title
Amman
Amman
Amman
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MT6761_GPIO
MT6761_GPIO
MT6761_GPIO
D
D
D
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
V1.0
V1.0
V1.0
10 38Wednesday, April 01, 2020
10 38Wednesday, April 01, 2020
10 38Wednesday, April 01, 2020
1
5
U901C
RDP2[21]
RDN2[21]
RDP0[21]
RDN0[21]
RCP[21]
RCN[21]
RDP1[21]
RDN1[21]
RDP3[21]
RDN3[21]
RDP2_B[21]
RDN2_B[21]
RDP0_B[21]
RDN0_B[21]
RCP_B[21]
RCN_B[21]
RDP1_B[21]
RDN1_B[21]
RDP3_B[21]
RDN3_B[21]
Macro_RST[21]
R1161 BLM15BA470SN1
1 2
R1162 BLM15BA470SN1
1 2
R1175 BLM15BA470SN1
1 2
R1176 BLM15BA470SN1
1 2
2 1
2 1
2 1
C / 27 / pF / 0201
C1161
C1162
C1164
MT6761
CSI-0
N3
CSI0A_L0P
N4
CSI0A_L0N
N1
CSI0A_L1P
N2
CSI0A_L1N
P1
CSI0A_L2P
P2
CSI0A_L2N
P3
CSI0B_L0P
P4
CSI0B_L0N
R3
CSI0B_L1P
R4
CSI0B_L1N
N5
CSI0B_L2P
P5
CSI0B_L2N
CSI-1
L3
CSI1A_L0P
L4
CSI1A_L0N
L1
CSI1A_L1P
L2
CSI1A_L1N
M1
CSI1A_L2P
M2
CSI1A_L2N
L5
CSI1B_L0P
M5
CSI1B_L0N
M3
CSI1B_L1P
M4
CSI1B_L1N
CSI-2
R1
CSI2A_L0P
R2
CSI2A_L0N
T1
CSI2A_L1P
T2
CSI2A_L1N
T3
CSI2A_L2P
T4
CSI2A_L2N
U3
CSI2B_L0P
U4
CSI2B_L0N
R5
CSI2B_L1P
T5
CSI2B_L1N
CSI Ctrl
V2
CAM_RST0
W6
CAM_PDN0
V1
CAM_RST1
Y2
CAM_PDN1
K3
CAM_RST2
K2
CAM_PDN2
AF23
CAM_RST3
L24
CAM_PDN3
W5
CAM_CLK0
W2
CAM_CLK1
J2
CAM_CLK2
AG24
CAM_CLK3
C / 27 / pF / 0201
D D
DEP_RDP0[21]
DEP_RDN0[21]
DEP_RCP[21]
DEP_RCN[21]
DEP_RDP1[21]
DEP_RDN1[21]
Macr_RDP0[21]
Macr_RDN0[21]
Macr_RCP[21]
Macr_RCN[21]
Macr_RDP1[21]
Macr_RDN1[21]
C C
CAM_RST0[21]
CAM_RST1[21]
DepCAM_RST[21]
CAM_CLK0[21]
B B
CAM_CLK1[21]
CAM_CLK2[21]
CAM_CLK3[21]
2 1
C / 27 / pF / 0201
C1163 C / 27 / pF / 0201
Note 12-1: The de-coupling cap. for REFP (AF18 ball) have to be placed as close to BB as possible.
Note 12-2: To shunt a 1uF capacitor in the AUXIN ADC input to prevent noise coupling . It should
be placed as close to BB as possible. Conn ect the unused AUX ADC input to GND.
Note 12-5: Please set unused IQ pins in NC
Note 13-1: The enable pin of acoustic or optoelectronic devices (e.g. SPK AMP/Backlight/Charg er
OCP/OVP) suggest to use Peripheral_EN[0:5]
If use other GPIOs as enable pin, sug gest to reserve 0201 NC to GND
MT6762-SBS
DSI-0
GPIO
GPO
4
PERIPHERAL_EN0
PERIPHERAL_EN1
PERIPHERAL_EN2
PERIPHERAL_EN3
PERIPHERAL_EN4
PERIPHERAL_EN5
DSI0_CKP
DSI0_CKN
DSI0_D0P
DSI0_D0N
DSI0_D1P
DSI0_D1N
DSI0_D2P
DSI0_D2N
DSI0_D3P
DSI0_D3N
LCM_RST
DISP_PWM
SPI0_CSB
SPI0_CLK
SPI1_CSB
SPI1_CLK
SPI2_CSB
SPI2_CLK
SPI3_CSB
SPI3_CLK
SPI4_CSB
SPI4_CLK
3
U901B
P25
DSI0_CKP [20]
P26
DSI0_CKN [20]
N25
DSI0_D0P [20]
N26
DSI0_D0N [20]
N28
DSI0_D1P [20]
N27
DSI0_D1N [20]
R25
DSI0_D2P [20]
R26
DSI0_D2N [20]
P27
DSI0_D3P [20]
R27
DSI0_D3N [20]
AD26
LCM_RST [30]
AE27
DSI_TE
AD27
DISP_PWM
AD1
SPI0_MI [26]
SPI0_MI
AC1
SPI0_CSB [26]
AC2
SPI0_MO [26]
SPI0_MO
AD2
SPI0_CLK [26]
W24
FP_SPI_MISO [22]
SPI1_MI
U23
FP_SPI_CS [22]
Y24
FP_SPI_MOSI [22]
SPI1_MO
V24
FP_SPI_SCLK [22]
U24
SPI2_MI
SPI2_MO
SPI3_MI
SPI3_MO
SPI4_MI
SPI4_MO
BOARD_ID04 [26]
T26
Error_Flag [30]
T25
AudioPA_ID05 [17,26]
T24
U25
CTP_MI [30]
U26
CTP_CS [30]
V26
CTP_MO [30]
V25
CTP_CLK [30]
U27
SPI4_MI [22]
V28
SPI4_CSB [22]
T27
SPI4_MO [22]
V27
SPI4_CLK [22]
AD22
GPIO_FLSAH_CE [4]
AD24
GPIO_FLASH_EN [4]
AD23
AC24
GPIO_SPK_EN [17]
AE23
GPIO_RED_EN1
AE22
BL_EN [4]
SIM1_SCLK[23]
SIM1_SIO[23]
SIM1_SRST[23]
SIM2_SCLK[23]
SIM2_SIO[23]
SIM2_SRST[23]
RFIC0_BSI_EN[31]
RFIC0_BSI_CK[31]
RFIC0_BSI_D0[31]
RFIC0_BSI_D1[31]
MIPI0_SCLK[32]
MIPI0_SDATA[32]
MIPI1_SCLK[33]
MIPI1_SDATA[33]
MIPI2_SCLK
MIPI2_SDATA
MIPI3_SCLK
MIPI3_SDATA
PRX_TUNER_BPI_BUS14
PRX_TUNER_BPI_BUS13[30]
AIRPORT_BPI_BUS11[30]
SPDT_BPI_BUS9[33]
PRX_TUNER_BPI_BUS8[30]
PRX_TUNER_BPI_BUS7[30]
PRX_TUNER_BPI_BUS6[30]
DRX_TUNER_BPI_BUS5[34]
DRX_TUNER_BPI_BUS4[34]
DRX_TUNER_BPI_BUS3[34]
DRX_SW3_BPI_BUS2[34]
DRX_SW2_BPI_BUS1[34]
DRX_SW1_BPI_BUS0[34]
Note: 13-1
MT6761
MT6762-SBS
SIM
RFIC_Ctrl
RF MIPI
BPI
ABB_IF
AUX IN
REF POWER
MAIN_X26M_IN
TX_BB_IP0
TX_BB_IN0
TX_BB_QP0
TX_BB_QN0
PRX_BB_I0P
PRX_BB_I0N
PRX_BB_I1
PRX_BB_Q0P
PRX_BB_Q0N
PRX_BB_Q1
DRX_BB_I0P
DRX_BB_I0N
DRX_BB_I1
DRX_BB_Q0P
DRX_BB_Q0N
DRX_BB_Q1
DET_QP0
DET_QN0
RFIC_ET0_P
RFIC_ET0_N
VIO18_PMU
DET_IP0
DET_IN0
AUXIN4
AUXIN3
AUXIN2
AUXIN1
AUXIN0
REFP
12
12
AA25
SIM1_SCLK
Y25
SIM1_SIO
AA26
SIM1_SRST
AC25
SIM2_SCLK
AB25
SIM2_SIO
AC26
SIM2_SRST
AE21
RFIC0_BSI_EN
AF22
RFIC0_BSI_CK
AE20
RFIC0_BSI_D0
AF21
RFIC0_BSI_D1
AG22
RFIC0_BSI_D2
AG7
MISC_BSI_CK_0
AF7
MISC_BSI_DO_0
AF5
MISC_BSI_CK_1
AF6
MISC_BSI_DO_1
AE6
MISC_BSI_CK_2
AD6
MISC_BSI_DO_2
AE5
MISC_BSI_CK_3
AD5
MISC_BSI_DO_3
AE2
BPI_PA_VM1
AD3
BPI_PA_VM0
AF24
BPI_BUS15_ANT2
AE3
BPI_BUS14_ANT1
AE25
BPI_BUS13_ANT0
AE24
BPI_BUS12_OLAT1
AD4
BPI_BUS11_OLAT0
AF25
BPI_BUS10
AF26
BPI_BUS9
AD25
BPI_BUS8
AC6
BPI_BUS7
AG4
BPI_BUS6
AG3
BPI_BUS5
AG2
BPI_BUS4
AF4
BPI_BUS3
AF3
BPI_BUS2
AF2
BPI_BUS1
AE4
BPI_BUS0
AUX_IN0_NTC[11]
Thermistor to sense AP
temperature
1. NTC1101must keep a distance about 6~8 mm away from AP and far from
other heat sources 10 mm at least.
2. The distance is the shortest distance from package edge to edge.
AB13
AE9
AD9
AE10
AD10
AF13
AG13
AF15
AF12
AG12
AG15
AD13
AE13
AG16
AD12
AE12
AF16
AG9
AF9
AF10
AG10
AD8
AC9
AC10
APC
AE17
AE18
AE19
AF19
AF20
AF18
R1103
R / 390 / K / 0201 / 1%
NTC1101
NTC / 100K / 0201
6177_i0
6177m_iP
6177m_iN
6177_i1
6177_q0
6177m_qP
6177m_qN
6177_q1
6177_i0
6177m_iP
6177m_iN
6177_i1
6177_q0
6177m_qP
6177m_qN
6177_q1
APC1 [33]
C1101
2 1
REFP
C / 1uF / 0201
C1105
2 1
C / 100 / nF / 4V
D_GND
Note: 12-1
1%
C1102
2 1
C / 1 / uF / 6.3V
PMIC_CLK_BB [2]
LTE_TX_BB0_IP [31]
LTE_TX_BB0_IN [31]
LTE_TX_BB0_QP [31]
LTE_TX_BB0_QN [31]
LTE_PRX_BB0_IP [31]
LTE_PRX_BB0_IN [31]
LTE_PRX_BB0_QP [31]
LTE_PRX_BB0_QN [31]
LTE_DRX_BB0_IP [31]
LTE_DRX_BB0_IN [31]
LTE_DRX_BB0_QP [31]
LTE_DRX_BB0_QN [31]
LTE_DET_BB0_IP [31]
LTE_DET_BB0_IN [31]
LTE_DET_BB0_QP [31]
LTE_DET_BB0_QN [31]
C1108
2 1
C / 1 / uF / 6.3V
2 1
C1103
C / 1 / uF / 6.3V
2
1
Note: 12-5
LCD_NTC [30]
Board_ID_ADC [26]
BAT_ID [16]
AUX_IN1_NTC [32]
AUX_IN0_NTC [11]
C1104
C / 1 / uF / 6.3V
2 1
A A
Title
Title
Title
Amman
Amman
Amman
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MT6761_MIPI and RF Control
MT6761_MIPI and RF Control
MT6761_MIPI and RF Control
D
D
D
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
V1.0
V1.0
V1.0
11 38Wednesday, April 01, 2020
11 38Wednesday, April 01, 2020
11 38Wednesday, April 01, 2020
1
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