Page 1
w
WM8758B
Stereo CODEC with Headphone Driver and Line Out
DESCRIPTION
The WM8758B is a low power, high quality stereo CODEC
designed for portable applications such as MP3 audio player.
The device integrates preamps for stereo differential mics, and
drivers for headphone and differential or stereo line output.
External component requirements are reduced as no separate
microphone or headphone amplifiers are required. Headphone
and line common feedback improves crosstalk and noise
performance.
Advanced on-chip digital signal processing includes a 5-band
equaliser, a mixed signal Automatic Level Control for the
microphone or line input through the ADC as well as a purely
digital limiter function for record or playback. Additional digital
filtering options are available in the ADC path, to cater for
application filtering such as ‘wind noise reduction’ and notch
filter.
The WM8758B digital audio interface can operate in master or
slave mode with an integrated PLL.
The WM8758B operates at analogue supply voltages from 2.5V
to 3.3V, although the digital supply voltages can operate at
voltages down to 1.71V to save power. Additional power
management control enables individual sections of the chip to
be powered down under software control.
BLOCK DIAGRAM
FEATURES
Stereo CODEC:
• DAC SNR 100dB, THD -86dB (‘A’ weighted @ 48kHz)
• ADC SNR 92.5dB, THD -75dB (‘A’ weighted @ 48kHz)
• Headphone Driver
• 40mW per channel output power into 16Ω / 3.3V AVDD2
• Line output
Mic Preamps:
• Stereo Differential or mono microphone Interfaces
• Programmable preamp gain
• Psuedo differential inputs with common mode rejection
• Programmable ALC / Noise Gate in ADC path
• Low-noise bias supplied for electret microphones
Other Features:
• Enhanced 3-D function for improved stereo separation
• Digital playback limiter
• 5-band Equaliser (record or playback)
• Programmable ADC High Pass Filter (wind noise reduction)
• Programmable ADC Notch Filter
• PLL supporting various clocks between 8MHz-50MHz
• Sample rates supported (kHz): 8, 11.025, 12, 16, 22.05, 24,
32, 44.1, 48
• Low power, low voltage
• 2.5V to 3.6V analogue supplies
• 1.71V to 3.6V digital supplies
• 5x5mm 32-lead QFN package
APPLICATIONS
• Portable audio player
VMID
AGND1
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/
MCLK
AVDD1
LRC
BCLK
DACDAT
ADCDAT
SDIN
SCLK
MODE
CSB/GPIO1
Production Data, October 2008, Rev 4.3
Copyright ©2008 Wolfson Microelectronics plc
Page 2
WM8758B Production Data
TABLE OF CONTENTS
DESCRIPTION ....................................................................................................... 1
BLOCK DIAGRAM ................................................................................................. 1
FEATURES................................ ................ ................ ................ ................ ............. 1
APPLICATIONS ..................................................................................................... 1
TABLE OF CONTENTS ......................................................................................... 2
PIN CONFIGURATION ...................... ................ ................ ................ ................ ..... 4
ORDERING INFORMATION .................................................................................. 4
PIN DESCRIPTION ................................................................................................ 5
RECOMMENDED OPERATING CONDITIONS ..................................................... 6
ELECTRICAL CHARACTERISTICS ...................................................................... 7
TERMINOLOGY .......................................................................................................... 12
HEADPHONE OUTPUT PERFORMANCE .......................................................... 13
POWER CONSUMPTION .................................................................................... 14
AUDIO PATHS OVERVIEW ................................................................................. 15
SIGNAL TIMING REQUIREMENTS ..................................................................... 16
SYSTEM CLOCK TIMING ........................................................................................... 16
AUDIO INTERFACE TIMING – MASTER MODE ........................................................ 16
AUDIO INTERFACE TIMING – SLAVE MODE ............................................................ 17
CONTROL INTERFACE TIMING – 3-WIRE MODE .................................................... 18
CONTROL INTERFACE TIMING – 2-WIRE MODE .................................................... 19
INTERNAL POWER ON RESET CIRCUIT .......................................................... 20
RECOMMENDED POWER UP/DOWN SEQUENCE .................................................. 22
DEVICE DESCRIPTION ....................................................................................... 25
INTRODUCTION ..................... ................................... ................................. ................ 25
INPUT SIGNAL PATH ................................................................................................. 26
ANALOGUE TO DIGITAL CONVERTER (ADC) .......................................................... 33
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 37
OUTPUT SIGNAL PATH ............................................................................................. 42
3D STEREO ENHANCEMENT .................................................................................... 49
ANALOGUE OUTPUTS ............................................................................................... 49
DIGITAL AUDIO INTERFACES ................................................................................... 61
AUDIO SAMPLE RATES ............................................................................................. 68
MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ............................................... 68
GENERAL PURPOSE INPUT/OUTPUT ...................................................................... 70
OUTPUT SWITCHING (JACK DETECT) ..................................................................... 72
CONTROL INTERFACE .............................................................................................. 73
RESETTING THE CHIP .............................................................................................. 74
POWER SUPPLIES .................................................................................................... 75
POWER MANAGEMENT ............................................................................................ 75
POP MINIMISATION ................................................................................................... 77
REGISTER MAP ..................... ........... ............ ............ ............ ............ ............ ....... 78
DIGITAL FILTER CHARACTERISTICS ............................................................... 80
TERMINOLOGY .......................................................................................................... 80
DAC FILTER RESPONSES ......................................................................................... 81
ADC FILTER RESPONSES ......................................................................................... 81
HIGHPASS FILTER ..................................................................................................... 82
5-BAND EQUALISER .................................................................................................. 83
w
PD, Rev 4.3, October 2008
2
Page 3
Production Data WM8758B
APPLICATIONS INFORMATION ......................................................................... 87
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 87
PACKAGE DIAGRAM .......................................................................................... 88
IMPORTANT NOTICE .......................................................................................... 89
ADDRESS: .................................................................................................................. 89
w
PD, Rev 4.3, October 2008
3
Page 4
WM8758B Production Data
PIN CONFIGURATION
2526272829303132
LIP
LIN
L2/GPIO2
RIP
RIN
R2/GPIO3
LRC
BCLK
1
2
3
4
5
6
7
8
TOP VIEW
24
AGND2
23
ROUT2
22
OUT3
OUT4
21
20
LINE_COM
19
HP_COM
18
MODE
17
SDIN
161514131211109
ORDERING INFORMATION
ORDER CODE TEMPERATURE
RANGE
WM8758BGEFL/V -40°C to +85°C 32-lead QFN (5 x 5 mm)
WM8758BGEFL/RV -40°C to +85°C 32-lead QFN (5 x 5 mm)
Note:
Reel quantity = 3,500
PACKAGE MOISTURE
(Pb-free)
(Pb-free, tape and reel)
SENSITIVITY LEVEL
MSL3 260oC
MSL3 260oC
PEAK SOLDERING
TEMPERATURE
w
PD, Rev 4.3, October 2008
4
Page 5
Production Data WM8758B
PIN DESCRIPTION
PIN NAME TYPE DESCRIPTION
1 LIP
2 LIN
3 L2/GPIO2
4 RIP
5 RIN
6 R2/GPIO3
7 LRC
8 BCLK
9 ADCDAT
10 DACDAT
11 MCLK
12 DGND
13 DCVDD
14 DBVDD
15 CSB/GPIO1
16 SCLK
17 SDIN
18 MODE
19 HP_COM
20 LINE_COM
21 OUT4
22 OUT3
23 ROUT2
24 AGND2
25 LOUT2
26 AVDD2
27 VMID
28 AGND1
29 ROUT1
30 LOUT1
31 AVDD1
32 MICBIAS
Note:
It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
Analogue Input Left MIC pre-amp positive input
Analogue Input Left MIC pre-amp negative input
Analogue Input Left channel line input/secondary mic pre-amp positive input/GPIO2 pin
Analogue Input Right MIC pre-amp positive input
Analogue Input Right MIC pre-amp negative input
Analogue Input Right channel line input/secondary mic pre-amp positive input/GPIO3
pin
Digital Input / Output DAC and ADC sample rate clock
Digital Input / Output Digital audio bit clock
Digital Output ADC digital audio data output
Digital Input DAC digital audio data input
Digital Input Master clock input
Supply Digital ground
Supply Digital core logic supply
Supply Digital buffer (I/O) supply
Digital Input / Output 3-Wire control interface chip select / GPIO1 pin
Digital Input 3-Wire control interface clock input / 2-wire control interface clock input
Digital Input / Output 3-Wire control interface data input / 2-Wire control interface data input
Digital Input Control interface selection
Analogue Input Headphone ground common feedback input
Analogue Input Line out ground common feedback input
Analogue Output Right line output / mono mix output
Analogue Output Left line output / mono mix output
Analogue Output Line output right 2
Supply Analogue ground (return path for ROUT2/LOUT2)
Analogue Output Line output left 2
Supply Analogue supply (supply for output amplifiers ROUT2/LOUT2)
Reference Decoupling for ADC and DAC reference voltage
Supply Analogue ground (return path for all input amplifiers, PLL, ADC and
DAC, internal bias circuits, output amplifiers LOUT1, ROUT1 and
OUT3/OUT4 on AVDD1 AGND1)
Analogue Output Line or headphone output right 1
Analogue Output Line or headphone output left 1
Supply Analogue supply (feeds all input amplifiers, PLL, ADC and DAC, internal
bias circuits, output amplifiers LOUT1, ROUT1))
Analogue Output Microphone bias
w
PD, Rev 4.3, October 2008
5
Page 6
WM8758B Production Data
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
DBVDD, DCVDD, AVDD1, AVDD2 supply voltages
Voltage range digital inputs
Voltage range analogue inputs
Storage temperature prior to soldering
Storage temperature after soldering
Notes
1. Analogue and digital grounds must always be within 0.3V of each other.
2. All digital and analogue supplies are internally independent (i.e. not connected).
3. Analogue supply voltages should not be less than digital supply voltages.
4. DBVDD must be greater than or equal to DCVDD.
of this device.
CONDITION MIN MAX
-0.3V +3.63V
DGND -0.3V DVDD +0.3V
AGND1 -0.3V AVDD1 +0.3V
30°C max / 85% RH max
-65°C +150°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL TEST
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supply range
Ground
Notes
1. Analogue supply voltages must not be less than digital supply voltages.
2. DBVDD must be greater than or equal to DCVDD.
DCVDD 1.71
DBVDD 1.71 3.3 3.6 V
AVDD1, AVDD2 2.5
DGND, AGND1, AGND2 0
CONDITIONS
MIN TYP MAX UNIT
1,2
1.8 3.6 V
1
3.3 3.6 V
V
w
PD, Rev 4.3, October 2008
6
Page 7
Production Data WM8758B
L
ELECTRICAL CHARACTERISTICS
Test Conditions
DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Microphone Preamp Inputs (LIP, LIN, RIP, RIN, L2, R2)
Full-scale Input Signal Level –
Single-ended input via LIN/RIN
Full-scale Input Signal Level –
Pseudo-differential input
Mic PGA equivalent input noise At 35.25dB
Input resistance (LIN, RIN) R
Input resistance (LIN, RIN) R
Input resistance (LIN, RIN) R
Input resistance (LIP, RIP) R
Input resistance (L2, R2) R
Input resistance (L2, R2) R
Input resistance (L2, R2) R
Input resistance (L2, R2) R
Input Capacitance C
Maximum Programmable Gain +35.25 dB
Minimum Programmable Gain
Programmable Gain Step Size
MIC Mute Attenuation
MIC Gain Boost
L2, R2 Line Input Programmable Gain
Maximum Gain from L/R2 input
to boost/mixer
Minimum Gain from L/R2 input
to boost/mixer
L2/R2 boost step size
L2/R2 Mute attenuation
OUT4 to Left or Right Input Boost Record Path
Maximum Gain
Minimum Gain
Gain step size
Mute attenuation
Automatic Level Control (ALC)
Target Record Level
Programmable gain
V
INFS
V
INFS
gain
MICIN
MICIN
MICIN
MICIP
L2R2
L2R2
L2R2
L2R2
MICIN
PGABOOST = 0dB
AVDD1/3.3 Vrms
INPPGAVOL = 0dB
PGABOOST = 0dB
INPPGAVOL = 0dB
AVDD1*0.7/
3.3
Vrms
0 to 20kHz 150 uV
Gain set to 35.25dB 1.6 kΩ
Gain set to 0dB 46 kΩ
Gain set to -12dB 71 kΩ
90 kΩ
L/RIP2INPPGA = 1,
90 kΩ
L/R2_2BOOSTVOL = 000
/RIP2INPPGA = 0, Gain set
11 kΩ
to 6dB
L/RIP2INPPGA = 0,
22 kΩ
Gain set to 0dB
L/RIP2INPPGA = 0,
60 kΩ
Gain set to -12dB
10 pF
-12 dB
Guaranteed monotonic 0.75 dB
INPPGAMUTEL/R=1
PGABOOSTL/R=0
PGABOOSTL/R=1
Gain adjusted by
+6 dB
100
0
20
dB
dB
dB
L2_2BOOSTVOL
R2_2BOOSTVOL
Gain adjusted by
-12 dB
L2_2BOOSTVOL
R2_2BOOSTVOL
Guaranteed monotonic 3 dB
100 dB
+6 dB
-12 dB
Guaranteed monotonic 3 dB
100 dB
-22.5 -1.5 dB
-12 35.25
w
7
PD, Rev 4.3, October 2008
Page 8
WM8758B Production Data
Test Conditions
DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, T
stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Analogue to Digital Converter (ADC) - Input from LIN/P and RIN/P, PGA and boost gains=0dB
Signal to Noise Ratio (Note 5,6) SNR
Total Harmonic Distortion
(Note 7)
Total Harmonic Distortion + Noise
(Note 7)
Channel Separation (Note 8)
Analogue to Digital Converter (ADC) - Input from L2, R2
Signal to Noise Ratio (Note 5,6) SNR
Total Harmonic Distortion
(Note 7)
Total Harmonic Distortion + Noise
(Note 7)
Channel Separation (Note 8)
THD
THD+N
THD
THD+N
= +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
A
A-weighted
AVDD1=AVDD2=3.0V
A-weighted
AVDD1=AVDD2=2.5V
22Hz to 20kHz
AVDD1=AVDD2=3.0V
22Hz to 20kHz
AVDD1=AVDD2=2.5V
-12dBFS Input
AVDD1=AVDD2=3.0V
-12dBFS Input
AVDD1=AVDD2=2.5V
-12dBFS Input
AVDD1=AVDD2=3.0V
-12dBFS Input
AVDD1=AVDD2=2.5V
1kHz full scale input signal 100 dB
A-weighted
AVDD1=AVDD2=3.0V
A-weighted
AVDD1=AVDD2=2.5V
22Hz to 20kHz
AVDD1=AVDD2=3.0V
22Hz to 20kHz
AVDD1=AVDD2=2.5V
-3dBFS Input
AVDD1=AVDD2=3.0V
-3dBFS Input
AVDD1=AVDD2=2.5V
-3dBFS Input
AVDD1=AVDD2=3.0V
-3dBFS Input
AVDD1=AVDD2=2.5V
1kHz input signal 100 dB
92.5 dB
91.5 dB
90 dB
90 dB
-75 dB
-75 dB
-72 dB
-72 dB
85 92.5 dB
92.5 dB
90 dB
90 dB
-83 -75 dB
-66 dB
-81 -70 dB
-65 dB
w
PD, Rev 4.3, October 2008
8
Page 9
Production Data WM8758B
Test Conditions
DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, T
stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DAC to L/R Mix to Line-Out (LOUT1/ROUT1 with 10kΩ / 50pF load, analogue volume controls set to 0dB)
Full-scale output
Signal to Noise Ratio (Note 5,6)
Total Harmonic Distortion
(Note 7)
Total Harmonic Distortion + Noise
(Note 7)
Channel Separation (Note 8)
Ground noise rejection
DAC to L/R Mix to Line-Out (LOUT2/ROUT2 with 10kΩ / 50pF load, analogue volume controls set to 0dB)
Full-scale output
Signal to Noise Ratio (Note 5,6)
Total Harmonic Distortion
(Note 7)
Total Harmonic Distortion + Noise
(Note 7)
Channel Separation (Note 8)
Ground noise rejection
PGA gains set to 0dB AVDD1/3.3 Vrms
SNR A-weighted
THD full-scale signal
THD+N full-scale signal
PGA gains set to 0dB AVDD1/3.3 Vrms
SNR A-weighted
THD full-scale signal
THD+N full-scale signal
= +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
A
100 dB
AVDD1=AVDD2=3.0V
A-weighted
AVDD1=AVDD2=2.5V
22Hz to 20kHz
AVDD1=AVDD2=3.0V
22Hz to 20kHz
AVDD1=AVDD2=2.5V
AVDD1=AVDD2=3.0V
full-scale signal
AVDD1=AVDD2=2.5V
AVDD1=AVDD2=3.0V
full-scale signal
AVDD1=AVDD2=2.5V
1kHz signal 100 dB
10mV, 20kHz noise on
HPCOM, HPCOM enabled
AVDD1=AVDD2=3.0V
A-weighted
AVDD1=AVDD2=2.5V
22Hz to 20kHz
AVDD1=AVDD2=3.0V
22Hz to 20kHz
AVDD1=AVDD2=2.5V
AVDD1=AVDD2=3.0V
full-scale signal
AVDD1=AVDD2=2.5V
AVDD1=AVDD2=3.0V
full-scale signal
AVDD1=AVDD2=2.5V
1kHz signal 100 dB
10mV, 20kHz noise on
LCOM, LCOM enabled
96 dB
95.5 dB
93.5 dB
-86 dB
-86 dB
-84 dB
-84 dB
40 dB
95 100 dB
96 dB
95.5 dB
93.5 dB
-87 -80 dB
-82 dB
-85 -75 dB
-80 dB
40 dB
w
PD, Rev 4.3, October 2008
9
Page 10
WM8758B Production Data
Test Conditions
DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, T
stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DAC to L/R Mix to Headphone (LOUT1/ROUT1, analogue volume controls set to 0dB)
Full-scale output
Signal to Noise Ratio (Note 5,6)
Total Harmonic Distortion
(Note 7)
Total Harmonic Distortion + Noise
(Note 7)
Channel Separation (Note 8)
Ground noise rejection
DAC to L/R Mix to Headphone (LOUT2/ROUT2, analogue volume controls set to 0dB)
Full-scale output
Signal to Noise Ratio (Note 5,6)
Total Harmonic Distortion
(Note 7)
Channel Separation (Note 8)
Ground noise rejection
Bypass Paths to Output Mixers
Maximum PGA gain into mixer +6 dB
Minimum PGA gain into mixer
PGA gain step into mixer
Mute attenuation
Analogue Outputs (LOUT1, ROUT1, LOUT2, ROUT2)
Maximum Programmable Gain
Minimum Programmable Gain
Programmable Gain step size
Mute attenuation
PGA gains set to 0dB AVDD1/3.3 Vrms
SNR A-weighted 100 dB
THD P
THD+N P
PGA gains set to 0dB AVDD1/3.3 Vrms
SNR A-weighted 90 97 dB
THD P
= +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
A
22Hz to 20kHz 95.5 dB
= 20mW
o
RL=16Ω
Po = 20mW
RL=32Ω
= 20mW
o
RL=16Ω
Po = 20mW
RL=32Ω
1kHz signal 100 dB
10mV, 20kHz noise on
HPCOM, HPCOM enabled
22Hz to 20kHz 95.5 dB
= 20mW
o
RL=16Ω
Po = 20mW
RL=32Ω
1kHz signal 100 dB
10mV, 20kHz noise on
LCOM, LCOM enabled
-15 dB
Guaranteed monotonic 3 dB
100 dB
+6 dB
-57 dB
Guaranteed monotonic 1 dB
1kHz, full scale signal 85 dB
-75 dB
-79 dB
-75 dB
-79 dB
40 dB
-79 dB
-82 dB
40 dB
w
PD, Rev 4.3, October 2008
10
Page 11
Production Data WM8758B
Test Conditions
DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, T
stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
MIC PGA to Input Boost to OUT3/OUT4 outputs (with 10kΩ / 50pF load)
Full-scale output voltage, 0dB
gain (Note 9)
Signal to Noise Ratio (Note 5,6)
Total Harmonic Distortion
(Note 7)
Total Harmonic Distortion + Noise
(Note 7)
Channel Separation
MIC PGA Bypass to LOUT1/ROUT1 (with 16Ω load)
Full-scale output voltage, 0dB
gain (Note 9)
Signal to Noise Ratio (Note 5,6)
Total Harmonic Distortion
(Note 7)
Total Harmonic Distortion + Noise
(Note 7)
Channel separation
AVDD2/3.3 Vrms
SNR A-weighted
THD full-scale signal
THD+N full-scale signal
100 dB
AVDD1/3.3 Vrms
SNR A-weighted
THD -5dBFS signal
THD+N -5dBFS signal
1kHz full scale signal 100 dB
= +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
A
90 98 dB
AVDD1=AVDD2=3.0V
A-weighted
AVDD1=AVDD2=2.5V
22Hz to 22kHz
AVDD1=AVDD2=3.0V
22Hz to 22kHz
AVDD1=AVDD2=2.5V
AVDD1=AVDD2=3.0V
full-scale signal
AVDD1=AVDD2=2.5V
AVDD1=AVDD2=3.0V
full-scale signal
AVDD1=AVDD2=2.5V
AVDD1=AVDD2=3.0V
A-weighted
AVDD1=AVDD2=2.5V
22Hz to 22kHz
AVDD1=AVDD2=3.0V
22Hz to 22kHz
AVDD1=AVDD2=2.5V
AVDD1=AVDD2=3.0V
-5dBFS signal
AVDD1=AVDD2=2.5V
AVDD1=AVDD2=3.0V
-5dBFS signal
AVDD1=AVDD2=2.5V
96 dB
95.5 dB
93.5 dB
-84 dB
-82 dB
-82 dB
-80 dB
90 100 dB
96 dB
95.5 dB
93.5 dB
-87 -75 dB
-69 dB
-85 -73 dB
-68 dB
w
PD, Rev 4.3, October 2008
11
Page 12
WM8758B Production Data
Test Conditions
DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, T
stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Microphone Bias
Bias Voltage
Bias Current Source
Output Noise Voltage
V
MBVSEL=0 0.9*AVDD1 V
MICBIA S
I
for V
MICBIAS
Vn 1kHz to 20kHz 15 nV/√Hz
Digital Input / Output
Input HIGH Level
Input LOW Level
Output HIGH Level
Output LOW Level
VIH 0.7×DBV
V
0.3×
IL
V
I
OH
V
I
OL
TERMINOLOGY
1. Signal-to-noise ratio (dB) – SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. THD+N (dB) – THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
3. Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
4. THD (dB) – THD is a ratio of the rms value of the first seven harmonics compared to the rms value of the
fundamental.
= +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
A
MBVSEL=1 0.65*AVDD1 V
within +/-3% 3 mA
MICBIA S
V
DD
V
DBVDD
=1mA 0.9×DBV
OL
V
DD
-1mA 0.1x
OH
V
DBVDD
w
PD, Rev 4.3, October 2008
12
Page 13
Production Data WM8758B
HEADPHONE OUTPUT PERFORMANCE
SNR Graphs TBA:
SNR vs AVDD1=AVDD2 L/ROUT1 (DAC path) for 16Ω, 32Ω
SNR vs AVDD1=AVDD2 L/ROUT2 (DAC path) for 16Ω, 32Ω
THD+N Graphs TBA:
THD+N vs output power (Analogue in to L/ROUT1) 16Ω, 32Ω
Plots for AVDD1=AVDD2=2.7, 3.0, 3.3, 3.6V
THD+N vs output power (Analogue in to L/ROUT2) 16Ω, 32Ω
Plots for AVDD1=AVDD2=2.7, 3.0, 3.3, 3.6V
PSRR Graphs TBA:
AVDD1 PSRR vs Frequency (DAC to L/ROUT1), 16Ω
AVDD1 PSRR vs Frequency (DAC to L/ROUT2), 16Ω
AVDD2 PSRR vs Frequency (DAC to L/ROUT2), 16Ω
w
PD, Rev 4.3, October 2008
13
Page 14
WM8758B Production Data
POWER CONSUMPTION
TYPICAL SCENARIOS
Estimated current consumption for typical scenarios are shown below.
All measurements are made with quiescent signal.
Power delivered to the load is not included.
Control
Register
Clocking
Scheme
(Unless
otherwise
specified)
Load
register
settings (Hex
values)
DCVDD (V)
DCVDD (mA)
DBVDD (V)
DBVDD (mA)
AVDD1 (V)
AVDD1 (mA)
AVDD2 (V)
(mW)
Total Power
AVDD2 (mA)
Operational
Mode
OFF No cl ocks None
Standby
L/ROUT1
L/ROUT2
OUT3/OUT4 St ereo line out
ADC Stereo Record (psue do MIC)
ADC Stereo Record (line in) Clocks on N/A
L/ROUT1 Master mode
BYPASS to OUT3/O UT4
Slave Mode
MCLK =
12.288Mhz
LRC = 48kHz
BCLK =
3.048MHz
No clocks None
Clocks on
Clocks on None
Clocks on None
Clocks on
Master mode / MCLK=13MHz None
No clocks
Ω
All default
R1= 009, R49 = 006
None
R1=009, R2=180, R3=06F, R4=050, R6=000,
R32=001, R33= 001
R1=009, R3=0 6F, R4=050, R11=024, R17 =004,
R6=000, R32= 001, R33=001
R1=1FF, R3=1EF , R4=050, R6=000, R38=001,
R1=OCD, R2=1BF, R4=050, R6=000, R2C=033,
N/A
R2D=110, R2F=000 , R2E=110, R30=000
R1=0CD, R2=1BF, R4=050, R6=000, R2F=050,
R1=029, R2=180, R3=00F, R4=050, R6=149,
R32=001, R33=00 1, R24=007,R25=023, R26=1 EA,
None
R1=0CD, R2=03C, R3=180, R2F =050, R38=004,
R39=001
R30=050
R27=126
R30=050, R39= 004
3.3 0.001 3.3 0 3.3 0.01 3.3 0 0.036
2.5 0 2.5 0 2.5 0.008 2.5 0 0.020
1.8 0 1.8 0 2.5 0.008 2.5 0 0.020
3.3 0.001 3.3 0 3.3 0.145 3.3 0 0.482
2.5 0 2.5 0 2.5 0.115 2.5 0 0.288
1.8 0 1.8 0 2.5 0.115 2.5 0 0.288
3.3 6.8 3.3 0.008 3.3 5.8 3.3 0 .7 43.916
2.5 4.8 2.5 0.005 2.5 4.3 2.5 0 .5 24.013
1.8 3.2 1.8 0.003 2.5 4.3 2.5 0 .5 17.765
3.3 6.8 3.3 0.008 3.3 5.1 3.3 0 .7 41.606
2.5 4.8 2.5 0.005 2.5 3.8 2.5 0 .5 22.763
1.8 3.2 1.8 0.003 2.5 3.8 2.5 0 .5 16.515
3.3 6.88 3.3 0.008 3.3 5.1 3.3 0.7 4 1.870
2.5 4.82 2.5 0.005 2.5 3.8 2.5 0.5 2 2.813
1.8 3 .2 1. 8 0.003 2.5 3.8 2.5 0.5 1 6.515
3.3 7 .3 3. 3 0.04 3.3 8.1 3.3 0 50.952
2.5 5 .1 2. 5 0.03 2.5 6.5 2.5 0 29.075
1.8 3.45 1.8 0.02 2.5 6. 5 2.5 0 22.496
3.3 7 .5 3. 3 0.04 3.3 7.6 3.3 0 49.962
2.5 5.2 2.5 0.03 2.5 6.05 2.5 0 28.200
1.83.551.80.022.56.052.5 0 21.551
3.3 3.06 3.3 7.9 3.3 7.1 3.3 0 59.5 98
2.5 2.18 2.5 3.5 2.5 5.24 2.5 0 27.300
1.8 3 .7 1. 8 1.6 2 .5 5.24 2.5 0 22.640
3.3 0.001 3.3 0 .001 3.3 2.15 3.3 0 7.1 02
2.5 0 2.5 0 2 .5 1. 54 2.5 0 3.8 50
1.8 0 1.8 0 2 .5 1. 54 2.5 0 3.8 50
w
PD, Rev 4.3, October 2008
14
Page 15
Production Data WM8758B
AUDIO PATHS OVERVIEW
Figure 1 Audio Paths Overview
w
PD, Rev 4.3, October 2008
15
Page 16
WM8758B Production Data
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
t
MCLKL
MCLK
Figure 2 System Clock Timing Requirements
Test Conditions
DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND=AGND1=AGND2=0V, T
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
System Clock Timing Information
T
MCLK cycle time
MCLK duty cycle
Note:
1. PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.
MCLKY
T
MCLKD S
t
MCLKH
t
MCLKY
= +25oC, Slave Mode
A
MCLK=SYSCLK (=256fs) 81.38 ns
MCLK input to PLL
60:40 40:60
Note 1
20 ns
AUDIO INTERFACE TIMING – MASTER MODE
w
Figure 3 Digital Audio Data Timing – Master Mode (see Control Interface)
PD, Rev 4.3, October 2008
16
Page 17
Production Data WM8758B
Test Conditions
DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND=AGND1=AGND2=0V, T
=+25oC, Master Mode, fs=48kHz,
A
MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER SYMBOL MIN TYP MAX UNIT
Audio Data Input Timing Information
LRC propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
t
10 ns
DL
t
10 ns
DDA
t
10 ns
DST
t
10 ns
DHT
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 4 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND=AGND1=AGND2=0V, T
=+25oC, Slave Mode, fs=48kHz,
A
MCLK= 256fs, 24-bit data, unless otherwise stated.
PARAMETER SYMBOL MIN TYP MAX UNIT
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
LRC set-up time to BCLK rising edge
LRC hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
t
50 ns
BCY
t
20 ns
BCH
t
20 ns
BCL
t
10 ns
LRSU
t
10 ns
LRH
t
10 ns
DH
t
10 ns
DD
Note:
BCLK period should always be greater than or equal to MCLK period.
w
PD, Rev 4.3, October 2008
17
Page 18
WM8758B Production Data
CONTROL INTERFACE TIMING – 3-WIRE MODE
3-wire mode is selected by connecting the MODE pin high.
Figure 5 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND = AGND1 = AGND2 = 0V, T
MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER SYMBOL MIN TYP MAX UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes that will be suppressed
t
80 ns
SCS
t
200 ns
SCY
t
80 ns
SCL
t
80 ns
SCH
t
40 ns
DSU
t
40 ns
DHO
t
40 ns
CSL
t
40 ns
CSH
t
40 ns
CSS
t
0 5 ns
ps
=+25oC, Slave Mode, fs=48kHz,
A
w
PD, Rev 4.3, October 2008
18
Page 19
Production Data WM8758B
CONTROL INTERFACE TIMING – 2-WIRE MODE
2-wire mode is selected by connecting the MODE pin low.
SDIN
SCLK
t
3
t
6
t
1
t
9
t
5
t
2
t
7
t
3
t
4
t
8
Figure 6 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND=AGND1=AGND2=0V, T
=+25oC, Slave Mode, fs=48kHz,
A
MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER SYMBOL MIN TYP MAX UNIT
Program Register Input Information
SCLK Frequency
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
Pulse width of spikes that will be suppressed
0 526 kHz
t1 1.3 us
t2 600 ns
t
600 ns
3
t
600 ns
4
t
100 ns
5
t
300 ns
6
t
300 ns
7
t
600 ns
8
t
900 ns
9
t
0 5 ns
ps
w
PD, Rev 4.3, October 2008
19
Page 20
WM8758B Production Data
INTERNAL POWER ON RESET CIRCUIT
Figure 7 Internal Power on Reset Circuit Schematic
The WM8758B includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used to
reset the digital logic into a default state after power up. The POR circuit is powered from AVDD1
and monitors DCVDD. It asserts PORB low if AVDD1 or DCVDD is below a minimum threshold.
Figure 8 Typical Power up Sequence where AVDD1 is Powered before DCVDD
Figure 8 shows a typical power-up sequence where AVDD1 comes up first. When AVDD1 goes
above the minimum threshold, V
asserted low and the chip is held in reset. In this condition, all writes to the control interface are
ignored. Now AVDD1 is at full supply level. Next DCVDD rises to V
and all registers are in their default state and writes to the control interface may take place.
On power down, where AVDD1 falls first, PORB is asserted low whenever AVDD1 drops below the
minimum threshold V
pora_off
.
, there is enough voltage for the circuit to guarantee PORB is
pora
w
and PORB is released high
pord_on
PD, Rev 4.3, October 2008
20
Page 21
Production Data WM8758B
Figure 9 Typical Power up Sequence where DCVDD is Powered before AVDD1
Figure 9 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that
DCVDD is already up to specified operating voltage. When AVDD1 goes above the minimum
threshold, V
, there is enough voltage for the circuit to guarantee PORB is asserted low and the
pora
chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD1
rises to V
, PORB is released high and all registers are in their default state and writes to the
pora_on
control interface may take place.
On power down, where DCVDD falls first, PORB is asserted low whenever DCVDD drops below the
minimum threshold V
pord_off
.
SYMBOL MIN TYP MAX UNIT
V
V
pora_on
V
pora_off
V
pord_on
V
pord_off
pora
0.4 0.6 0.8 V
0.9 1.2 1.6 V
0.4 0.6 0.8 V
0.5 0.7 0.9 V
0.4 0.6 0.8 V
Table 1 Typical POR Operation (typical values, not tested)
Notes:
If AVDD1 and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating
level but do not go below V
pora_off
or V
) then the chip will not reset and will resume normal
pord_off
operation when the voltage is back to the recommended level again.
The chip will enter reset at power down when AVDD1 or DCVDD falls below V
pora_off
or V
pord_off
. This
may be important if the supply is turned on and off frequently by a power management system.
The minimum t
period is maintained even if DCVDD and AVDD1 have zero rise time. This
por
specification is guaranteed by design rather than test.
w
PD, Rev 4.3, October 2008
21
Page 22
WM8758B Production Data
RECOMMENDED POWER UP/DOWN SEQUENCE
In order to minimise output pop and click noise, it is recommended that the WM8758B device is
powered up and down under control using the following sequences:
Power Up:
1. Turn on external power supplies. Wait for supply voltage to settle.
2. Set low bias mode, BIASCUT = 1.
3. Enable HPCOM = 1, LINECOM = 1.
4. Mute all Outputs and set PGAs to minimum gain, R52 to R57 = 0x140h.
5. Enable L/ROUT1
6. Enable L/ROUT2
7. Enable VMID independent current bias, POBCTRL = 1.
8. Enable required DACs and mixers.
9. Enable VMIDSEL=01, BIASEN = 1 and BUFIOEN = 1
10. Setup digital interface, input amplifiers, PLL, ADCs and DACs for desired operation.
11. Wait 100ms to allow VMID to rise sufficiently before unmuting outputs
12. Unmute L/ROUT1 and set desired volume, e.g. for 0dB R52 and R53 = 0x139h.
13. Unmute L/ROUT2 and set desired volume, e.g. for 0dB R54 and R55 = 0x139h.
14. Disable VMID independent current bias, POBCTRL = 0.
Power Down:
1. Disable Thermal shutdown
2. Enable VMIDTOG = 1
3. Disable VMIDSEL=00 and BUFIOEN=0
4. Wait for VMID to discharge
5. Power off registers R1, R2, R3 = 0x000h
6. Remove external power supplies
Notes:
1. Charging time constant is determined by impedance selected by VMIDSEL and the value of
decoupling capacitor connected to VMID pin.
2. It is possible to interrupt the power down sequence and power up to VMID before the allocated
VMID discharge time.
w
PD, Rev 4.3, October 2008
22
Page 23
Production Data WM8758B
V
por_on
V
Power Supply
pora
DGND
V
por_off
POR
2
I
S Clocks
ADC Internal
State
Analogue Inputs
ADCDAT pin
(Note 3)
ADCEN bit
No Power
POR Undefined
POR
DNC
t
adcint
Power down Init Normal Operation Normal OperationInitPD Power down
t
midrail_on
(Note 1) (Note 2)
AVDD/2
GD
ADC enabled ADC enabledADC off
INPPGAEN bit
VMIDSEL/
BIASEN bits
(Note 4)
Figure 10 ADC Power Up and Down Sequence (not to scale)
SYMBOL MIN TYPICAL MAX UNIT
t
300 ms
midrail_on
t
>6 s
midrail_off
t
adcint
2/fs n/fs
ADC Group Delay 29/fs n/fs
Table 2 Typical POR Operation (typical values, not tested)
Device Ready
DNC
GD
INPPGA enabled
VMID enabled
Internal POR active
t
adcint
t
midrail_off
GD
GD
w
Notes:
1. The analogue input pin charge time, t
is determined by the VMID pin charge time. This
midrail_on,
time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance
and AVDD power supply rise time.
2. The analogue input pin discharge time, t
capacitor discharge time. The time, t
midrail_off
is determined by the analogue input coupling
midrail_off,
, is measured using a 1μF capacitor on the
analogue input but will vary dependent upon the value of input coupling capacitor.
3. While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system
noise but no significant digital output will be present.
4. The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for
normal ADC operation.
5. ADCDAT data output delay from power up - with power supplies starting from 0V - is
determined primarily by the VMID charge time. ADC initialisation and power management bits
may be set immediately after POR is released; VMID charge time will be significantly longer
and will dictate when the device is stabilised for analogue input.
6. ADCDAT data output delay at power up from device standby (power supplies already applied)
is determined by ADC initialisation time, 2/fs.
PD, Rev 4.3, October 2008
23
Page 24
WM8758B Production Data
V
por_on
Power Supply
V
pora
DGND
V
por_off
POR
2
S Clocks
I
DAC Internal State
Line Out Outputs
HP Outputs
DACDAT pin
DACEN bit
Analogue outputs
enable bits
VMIDSEL/
BIASEN bits
(Note 6)
No Power
POR Undefined
t
por
DNC
t
Power down Init Normal Operation Normal OperationInitPD Power down
t
line_midrail_on
(Note 1)
AVDD/2
t
hp_midrail_on
(Note 4)
AVDD/2
DAC disabled DAC disabled
dacint
GD
DAC enabled DAC enabled
Device Ready
DNC
GD GD
DAC off
Analogue outputs enabled
VMID enabled
Figure 11 DAC Power Up and Down Sequence (not to scale)
SYMBOL MIN TYPICAL MAX UNIT
t
line_midrail_on
t
line_midrail_off
t
hp_midrail_on
t
hp__midrail_off
300 ms
>6 s
300 ms
>6 s
t
dacint
2/fs n/fs
DAC Group Delay 29/fs n/fs
Table 3 Typical POR Operation (typical values, not tested)
(Note 2)
Internal POR active
t
dacint
t
(Note 3)
line_midrail_off
t
(Note 5)
hp_midrail_off
w
Notes:
1. The lineout charge time, t
line_midrail_on,
is determined by the VMID pin charge time. This time is
dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and
AVDD power supply rise time. The values above were measured using a 4.7μF capacitor.
2. It is not advisable to allow DACDAT data input during initialisation of the DAC. If the DAC data
value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue
outputs. The same is also true if the DACDAT is removed at a non-zero value, and no mute
function has been applied to the signal beforehand.
3. The lineout discharge time, t
line_midrail_off,
is determined by the VMID pin discharge time. This
time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance.
The values above were measured using a 4.7μF capacitor.
4. The headphone charge time, t
hp_midrail_on,
is dependent upon the value of VMID decoupling
capacitor and VMID pin input resistance and AVDD power supply rise time. The values above
were measured using a 4.7μF VMID decoupling capacitor.
5. The headphone discharge time, t
hp_midrail_off,
is dependent upon the value of VMID decoupling
capacitor and VMID pin input resistance. The values above were measured using a 4.7μF
VMID decoupling capacitor.
6. The VMIDSEL and BIASEN bits must be set to enable analogue output midrail voltage and for
normal DAC operation.
PD, Rev 4.3, October 2008
24
Page 25
Production Data WM8758B
DEVICE DESCRIPTION
INTRODUCTION
The WM8758B is a low power audio codec combining a high quality stereo audio DAC and ADC, with
flexible line and microphone input and output processing.
FEATURES
The chip offers great flexibility in use, and so can support many different modes of operation as
follows:
MICROPHONE INPUTS
Two pairs of stereo microphone inputs are provided, allowing a pair of stereo microphones to be
pseudo-differentially connected, with user defined gain. The provision of the common mode input pin
for each stereo input allows for rejection of common mode noise on the microphone inputs (level
depends on gain setting chosen). A microphone bias is output from the chip which can be used to
bias both microphones. The signal routing can be configured to allow manual adjustment of mic
levels, or to allow the ALC loop to control the level of mic signal that is transmitted.
Total gain through the microphone paths of up to +55.25dB can be selected.
PGA AND ALC OPERATION
A programmable gain amplifier is provided in the input path to the ADC. This may be used manually
or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the
recording volume constant.
ADC
The stereo ADC uses a 24-bit high-order oversampling architecture to deliver optimum performance
with low power consumption.
HI-FI DAC
The hi-fi DAC provides high quality audio playback suitable for all portable audio hi-fi type
applications, including MP3 players and portable disc players of all types.
OUTPUT MIXERS
Flexible mixing is provided on the outputs of the device. A stereo mixer is provided for the stereo
headphone or line outputs, LOUT1/ROUT1, and additional summers on the OUT3/OUT4 outputs
allow for an optional differential or stereo line output on these pins. Gain adjustment PGAs are
provided for the LOUT1/ROUT1 and LOUT2/ROUT2 outputs, and signal switching is provided to
allow for all possible signal combinations.
OUT3 and OUT4 can be configured to provide an additional stereo or mono differential lineout from
the output of the DACs, the mixers or the input microphone boost stages. They can also provide a
midrail reference for pseudo differential inputs to external amplifiers. OUT3 and OUT4 should not be
used as a buffered midrail reference in capless mode.
AUDIO INTERFACES
The WM8758B has a standard audio interface, to support the transmission of stereo data to and from
the chip. This interface is a 3 wire standard audio interface which supports a number of audio data
formats including:
2
• I
S
• DSP/PCM Mode (a burst mode in which LRC sync plus 2 data packed words are
transmitted)
• MSB-First, left justified
• MSB-First, right justified
The interface can operate in master or slave modes.
w
CONTROL INTERFACES
To allow full software control over all features, the WM8758B offers a choice of 2 or 3 wire control
interface. It is fully compatible and an ideal partner for a wide range of industry standard
microprocessors, controllers and DSPs.
Selection of the mode is via the MODE pin. In 2 wire mode, the address of the device is fixed as
0011010b.
PD, Rev 4.3, October 2008
25
Page 26
WM8758B Production Data
CLOCKING SCHEMES
WM8758B offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided
to the DAC and ADC. A PLL is included which may be used to generate these clocks in the event
that they are not available from the system controller. This PLL can accept a range of common input
clock frequencies between 8MHz and 50MHz to generate high quality audio clocks. If this PLL is not
required for generation of these clocks, it can be reconfigured to generate alternative clocks which
may then be output on the GPIO pins and used elsewhere in the system.
POWER CONTROL
The design of the WM8758B has given much attention to power consumption without compromising
performance. It operates at very low voltages, includes the ability to power off any unused parts of
the circuitry under software control, and includes standby and power off modes.
INPUT SIGNAL PATH
The WM8758B has a number of flexible analogue inputs. There are two input channels, Left and
Right, each of which consists of an input PGA stage followed by a boost/mix stage which drives into
the hi-fi ADC. Each input path has three input pins which can be configured in a variety of ways to
accommodate single-ended, differential or dual differential microphones. A bypass path exists from
the output of the boost/mix stage into the output left/right mixers.
MICROPHONE INPUTS
The WM8758B can accommodate a variety of microphone configurations including single ended and
differential inputs. The inputs to the left differential input PGA are LIN, LIP and L2. The inputs to the
right differential input PGA are RIN, RIP and R2.
In single-ended microphone input configuration the microphone signal should be input to LIN or RIN
and the internal NOR gate configured to clamp the non-inverting input of the input PGA to VMID.
In differential mode the larger signal should be input to LIP or RIP and the smaller (e.g. noisy ground
connection) should be input to LIN or RIN.
w
Figure 12 Microphone Input PGA Circuit
The input PGAs are enabled by the IPPGAENL/R register bits.
REGISTER
ADDRESS
R2
Power
Management
2
Table 4 Input PGA Enable Register Settings
BIT LABEL DEFAULT DESCRIPTION
2 INPPGAENL 0 Left channel input PGA enable
3 INPPGAENR 0 Right channel input PGA enable
0 = disabled
1 = enabled
0 = disabled
1 = enabled
PD, Rev 4.3, October 2008
26
Page 27
Production Data WM8758B
REGISTER
ADDRESS
R44
Input
Control
Table 5 Input PGA Control
BIT LABEL DEFAULT DESCRIPTION
0 LIP2INPPGA 1 Connect LIP pin to left channel input PGA
amplifier positive terminal.
0 = LIP not connected to input PGA
1 = input PGA amplifier positive terminal
connected to LIP (constant input
impedance)
1 LIN2INPPGA 1 Connect LIN pin to left channel input PGA
negative terminal.
0 = LIN not connected to input PGA
1 = LIN connected to input PGA amplifier
negative terminal.
2 L2_2INPPGA 0 Connect L2 pin to left channel input PGA
positive terminal.
0 = L2 not connected to input PGA
1 = L2 connected to input PGA amplifier
positive terminal (constant input
impedance).
4 RIP2INPPGA 1 Connect RIP pin to right channel input
PGA amplifier positive terminal.
0 = RIP not connected to input PGA
1 = right channel input PGA amplifier
positive terminal connected to RIP
(constant input impedance)
5 RIN2INPPGA 1 Connect RIN pin to right channel input
PGA negative terminal.
0 = RIN not connected to input PGA
1 = RIN connected to right channel input
PGA amplifier negative terminal.
6 R2_2INPPGA 0 Connect R2 pin to right channel input PGA
positive terminal.
0 = R2 not connected to input PGA
1 = R2 connected to input PGA amplifier
positive terminal (constant input
impedance).
w
INPUT PGA VOLUME CONTROLS
The input microphone PGAs have a gain range from -12dB to +35.25dB in 0.75dB steps. The gain
from the LIN/RIN input to the PGA output and from the L2/R2 amplifier to the PGA output are always
common and controlled by the register bits INPPGAVOLL/R[5:0]. These register bits also affect the
LIP pin when LIP2INPPGA=1, the L2 pin when L2_2INPPGA=1, the RIP pin when RIP2INPPGA=1
and the L2 pin when L2_2INPPGA=1.
When the Automatic Level Control (ALC) is enabled the input PGA gains are controlled
automatically and the INPPGAVOLL/R bits should not be used.
PD, Rev 4.3, October 2008
27
Page 28
WM8758B Production Data
REGISTER
ADDRESS
R45
Left channel
input PGA
volume
control
R46
Right
channel
input PGA
volume
control
R32
ALC control
1
Table 6 Input PGA Volume Control
BIT LABEL DEFAULT DESCRIPTION
5:0 INPPGAVOLL 010000 Left channel input PGA volume
000000 = -12dB
000001 = -11.25db
.
010000 = 0dB
.
111111 = +35.25dB
6 INPPGAMUTEL 0 Mute control for left channel input PGA:
0 = Input PGA not muted, normal
operation
1 = Input PGA muted (and disconnected
from the following input BOOST stage).
7 INPPGAZCL 0 Left channel input PGA zero cross
8 INPPGAVU Not
latched
5:0 INPPGAVOLR 010000 Right channel input PGA volume
6 INPPGAMUTER 0 Mute control for right channel input
7 INPPGAZCR 0 Right channel input PGA zero cross
8 INPPGAVU Not
latched
8:7 ALCSEL 00 ALC function select:
enable:
0 = Update gain when gain register
changes
1 = Update gain on 1
gain register write.
INPPGA left and INPPGA right volume
do not update until a 1 is written to
INPPGAVU (in reg 45 or 46)
(See “Volume Updates” below)
000000 = -12dB
000001 = -11.25db
.
010000 = 0dB
.
111111 = +35.25dB
PGA:
0 = Input PGA not muted, normal
operation
1 = Input PGA muted (and disconnected
from the following input BOOST stage).
enable:
0 = Update gain when gain register
changes
1 = Update gain on 1st zero cross after
gain register write.
INPPGA left and INPPGA right volume
do not update until a 1 is written to
INPPGAVU (in reg 45 or 46)
(See “Volume Updates” below)
00 = ALC off
01 = ALC right only
10 = ALC left only
11 = ALC both on
st
zero cross after
w
PD, Rev 4.3, October 2008
28
Page 29
Production Data WM8758B
VOLUME UPDATES
Volume settings will not be applied to the PGAs until a ‘1’ is written to one of the INPPGAVU bits.
This is to allow left and right channels to be updated at the same time, as shown in Figure 13.
Figure 13 Simultaneous Left and Right Volume Updates
If the volume is adjusted while the signal is a non-zero value, an audible click can occur as shown in
Figure 14.
Figure 14 Click Noise During Volume Update
In order to prevent this click noise, a zero cross function is provided. When enabled, this will cause
the PGA volume to update only when a zero crossing occurs, equalizer click noise as shown in
Figure 15.
w
PD, Rev 4.3, October 2008
29
Page 30
WM8758B Production Data
Figure 15 Volume Update Using Zero Cross Detection
If there is a long period where no zero-crossing occurs, a timeout circuit in the W M8758B will
automatically update the volume. The volume updates will occur between one and two timeout
periods, depending on when the INPPGAVU bit is set as shown in Figure 16.
w
Figure 16 Volume Update after Timeout
PD, Rev 4.3, October 2008
30
Page 31
Production Data WM8758B
INPUT BOOST
Each of the stereo input PGA stages is followed by an input BOOST circuit. The input BOOST circuit
has 3 selectable inputs: the input microphone PGA output, the L2/R2 input pin (can be used as a
line input, bypassing the input PGA), and OUT4 mixer output. These three inputs can be mixed
together and have individual gain boost/adjust as shown in Figure 17.
Figure 17 Input Boost Stage
The input PGA paths can have a +20dB boost (PGABOOSTL/R=1), a 0dB pass through
(PGABOOSTL/R=0) or be completely isolated from the input boost circuit (INPPGAMUTEL/R=1).
REGISTER
ADDRESS
R47
Left Input
BOOST
control
R48
Right Input
BOOST
control
Table 7 Input BOOST Stage Control
BIT LABEL DEFAULT DESCRIPTION
8 PGABOOSTL 1 Boost enable for left channel input
PGA:
0 = PGA output has +0dB gain
through input BOOST stage.
1 = PGA output has +20dB gain
through input BOOST stage.
8 PGABOOSTR 1 Boost enable for right channel input
PGA:
0 = PGA output has +0dB gain
through input BOOST stage.
1 = PGA output has +20dB gain
through input BOOST stage.
w
PD, Rev 4.3, October 2008
31
Page 32
WM8758B Production Data
REGISTER
ADDRESS
R42
OUT4 to ADC
R47
Left channel
Input BOOST
control
R48
Right channel
Input BOOST
control
BIT LABEL DEFAULT DESCRIPTION
8:6 OUT4_2ADCVOL 000 Cont rols t he OUT4 to ADC input
boost stage:
000 = Path disabled
(disconnected)
001 = -12dB gain through boost
stage
010 = -9dB gain through boost
stage
…
111 = +6dB gain through boost
stage
5 OUT4_2LNR 0 OUT4 to L or R ADC input
0 = Right ADC input
1 = Left ADC input
6:4 L2_2BOOSTVOL 000 Controls the L2 pin to the left
channel input boost stage:
000 = Path disabled
(disconnected)
001 = -12dB gain through boost
stage
010 = -9dB gain through boost
stage
…
111 = +6dB gain through boost
stage
6:4 R2_2BOOSTVOL 000 Controls the R2 pin to the right
channel input boost stage:
000 = Path disabled
(disconnected)
001 = -12dB gain through boost
stage
010 = -9dB gain through boost
stage
…
111 = +6dB gain through boost
stage
w
Table 8 Input BOOST Stage Control
The BOOST stage is enabled under control of the BOOSTEN register bit.
REGISTER
ADDRESS
R2
Power
management
2
Table 9 Input BOOST Enable Control
BIT LABEL DEFAULT DESCRIPTION
4 BOOSTENL 0 Left channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
5 BOOSTENR 0 Right channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
PD, Rev 4.3, October 2008
32
Page 33
Production Data WM8758B
A
r
r
MICROPHONE BIASING CIRCUIT
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type
microphones and the associated external resistor biasing network. Refer to the Applications
Information section for recommended external components. The MICBIAS voltage can be altered via
the MBVSEL register bit. When MBVSEL=0, MICBIAS=0.9*AVDD1 and when MBVSEL=1,
MICBIAS=0.65*AVDD1. The output can be enabled or disabled using the MICBEN control bit.
REGISTER
ADDRESS
R1
Power
management 1
Table 10 Microphone Bias Enable Control
REGISTER
ADDRESS
R44
Input control
Table 11 Microphone Bias Voltage Control
The internal MICBIAS circuitry is shown in Figure 18. Note that the maximum source current
capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit
the MICBIAS current to 3mA.
BIT LABEL DEFAULT DESCRIPTION
4 MICBEN 0 Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
BIT LABEL DEFAULT DESCRIPTION
8 MBVSEL 0 Microphone Bias Voltage Control
0 = 0.9 * AVDD1
1 = 0.65 * AVDD1
VMID
Figure 18 Microphone Bias Schematic
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8758B uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback
and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full
Scale input level is proportional to AVDD1. With a 3.3V supply voltage, the full scale level is 1.0V
Any voltage greater than full scale may overload the ADC and cause distortion.
internal
resisto
internal
resisto
MICBEN
GND1
MBVSEL=0
MICBIAS
MICBIAS
= 1.8 x VMID
= 0.9 X AVDD
MBVSEL=1
MICBIAS
= 1.3 x VMID
= 0.65 X AVDD
rms
.
ADC DIGITAL FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface. The
digital filter path for each ADC channel is illustrated in Figure 19.
w
PD, Rev 4.3, October 2008
33
Page 34
WM8758B Production Data
Figure 19 ADC Digital Filter Path
The ADCs are enabled by the ADCENL/R register bit.
REGISTER
ADDRESS
R2
Power
management 2
Table 12 ADC Enable Control
BIT LABEL DEFAULT DESCRIPTION
0 ADCENL 0 Enable ADC left channel:
0 = ADC disabled
1 = ADC enabled
1 ADCENR 0 Enable ADC right channel:
0 = ADC disabled
1 = ADC enabled
The polarity of the output signal can also be changed under software control using the
ADCLPOL/ADCRPOL register bit. The oversampling rate of the ADC can be adjusted using the
ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power
operation and when ADCOSR=1 the oversample rate is 128x which gives best performance.
REGISTER
ADDRESS
R14
ADC Control
Table 13 ADC Control
BIT LABEL DEFAULT DESCRIPTION
0 ADCLPOL 0 ADC left channel polarity adjust:
0 = normal
1 = inverted
1 ADCRPOL 0 ADC right channel polarity adjust:
0 = normal
1 = inverted
3 ADCOSR 0 ADC oversample rate select:
0 = 64x (lower power)
1 = 128x (best performance)
SELECTABLE HIGH PASS FILTER
A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two
modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off
frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off
frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown
in Table 15.
w
PD, Rev 4.3, October 2008
34
Page 35
Production Data WM8758B
REGISTER
ADDRESS
R14
ADC Control
Table 14 ADC Enable Control
HPFCUT
[2:0]
000
001
010
011
100
101
110
111
Table 15 High Pass Filter Cut-off Frequencies (HPFAPP=1)
BIT LABEL DEFAULT DESCRIPTION
8 HPFEN 1 High Pass Filter Enable
0 = disabled
1 = enabled
7 HPFAPP 0 Select audio mode or application mode
0 = Audio mode (1
1 = Application mode (2nd order, fc =
HPFCUT)
6:4 HPFCUT 000 Application mode cut-off frequency
See Table 15 for details.
SR=101/100 SR=011/010 SR=001/000
fs (kHz)
8 11.025 12 16 22.05 24 32 44.1 48
82 113 122 82 113 122 82 113 122
102 141 153 102 141 153 102 141 153
131 180 156 131 180 156 131 180 156
163 225 245 163 225 245 163 225 245
204 281 306 204 281 306 204 281 306
261 360 392 261 360 392 261 360 392
327 450 490 327 450 490 327 450 490
408 563 612 408 563 612 408 563 612
st
order, fc = ~3.7Hz)
Note that the High Pass filter values (when HPFAPP=1) are calculated on the assumption that the
SR register bits are set correctly for the actual sample rate as shown in Table 15.
w
PD, Rev 4.3, October 2008
35
Page 36
WM8758B Production Data
π
π
PROGRAMMABLE NOTCH FILTER
A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth,
programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits
NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup
there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup.
REGISTER
ADDRESS
R27
Notch Filter 1
R28
Notch Filter 2
R29
Notch Filter 3
R30
Notch Filter 4
Table 16 Notch Filter Function
BIT LABEL DEFAULT DESCRIPTION
6:0 NFA0[13:7]
7 NFEN
8 NFU
6:0 NFA0[6:0]
8 NFU
6:0 NFA1[13:7]
8 NFU
0-6 NFA1[6:0]
8 NFU
0
0
0
0
0
0
0
0
0
Notch Filter a0 coefficient, bits [13:7]
Notch filter enable:
0 = Disabled
1 = Enabled
Notch filter update. The notch filter
values used internally only update
when one of the NFU bits is set high.
Notch Filter a0 coefficient, bits [6:0]
Notch filter update. The notch filter
values used internally only update
when one of the NFU bits is set high.
Notch Filter a1 coefficient, bits [13:7]
Notch filter update. The notch filter
values used internally only update
when one of the NFU bits is set high.
Notch Filter a1 coefficient, bits [6:0]
Notch filter update. The notch filter
values used internally only update
when one of the NFU bits is set high.
The coefficients are calculated as follows:
)2/tan(1
w
a
Where:
=
0
=
fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz
The actual register values can be determined from the coefficients as follows:
NFA0 = -a0 x 2
NFA1 = -a1 x 212
−
=
0
+
ffw /2
sc
ffw /2
sbb
b
)2/tan(1
w
b
)cos()1(
waa +−=
001
13
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally attenuated over a range from –127dB to 0dB in 0.5dB steps.
The gain for a given eight-bit code X is given by:
0.5 × (G-255) dB for 1 ≤ G ≤ 255; MUTE for G = 0
PD, Rev 4.3, October 2008
w
36
Page 37
Production Data WM8758B
REGISTER
ADDRESS
R15
Left channel
ADC Digital
Volume
R16
Right channel
ADC Digital
Volume
Table 17 ADC Digital Volume Control
BIT LABEL DEFAULT DESCRIPTION
7:0 ADCLVOL
[7:0]
8 ADCVU Not
7:0 ADCRVOL
[7:0]
8 ADCVU Not
11111111
( 0dB )
latched
11111111
( 0dB )
latched
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)
The WM8758B has an automatic PGA gain control circuit, which can function as an input peak
limiter or as an automatic level control (ALC).
Left ADC Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
ADC left and ADC right volume do not
update until a 1 is written to ADCVU (in
reg 15 or 16)
Right ADC Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
ADC left and ADC right volume do not
update until a 1 is written to ADCVU (in
reg 15 or 16)
In input peak limiter mode (ALCMODE bit = 1), a digital peak detector detects when the input signal
goes above a predefined level and will ramp the PGA gain down to prevent the signal becoming too
large for the input range of the ADC. When the signal returns to a level below the threshold, the
PGA gain is slowly returned to its starting level. The peak limiter cannot increase the PGA gain
above its static level.
w
Figure 20 Input Peak Limiter Operation
PD, Rev 4.3, October 2008
37
Page 38
WM8758B Production Data
In ALC mode (ALCMODE bit = 0) the circuit aims to keep a constant recording volume irrespective
of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal
level at the ADC input remains constant. A digital peak detector monitors the ADC output and
changes the PGA gain if necessary.
Figure 21 ALC Operation
The ALC/Limiter function is enabled by setting the register bit ALCSEL. When enabled, the
recording volume can be programmed between –1dB and –22.5dB (relative to ADC full scale) using
the ALCLVL register bits. An upper limit for the PGA gain can be imposed by setting the ALCMAX
control bits and a lower limit for the PGA gain can be imposed by setting the ALCMIN control bits.
ALCHLD, ALCDCY and ALCATK control the hold, decay and attack times, respectively:
Hold time is the time delay between the peak level detected being below target and the PGA gain
beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g. 2.67ms, 5.33ms,
10.67ms etc. up to 43.7s. Alternatively, the hold time can also be set to zero. The hold time is not
active in limiter mode (ALCMODE = 1). The hold time only applies to gain ramp-up, there is no delay
before ramping the gain down when the signal level is above target.
Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up and is given as a
time per gain step, time per 6dB change and time to ramp up over 90% of it’s range. The decay
time can be programmed in power-of-two (2
to 3.36s/6dB.
Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down and is given
as a time per gain step, time per 6dB change and time to ramp down over 90% of it’s range. The
attack time can be programmed in power-of-two (2
3.328us/6dB, etc. to 852ms/6dB.
NB, In peak limiter mode the gain control circuit runs approximately 4x faster to allow reduction of
fast peaks. Attack and Decay times for peak limiter mode are given below.
The hold, decay and attack times given in Table 18 are constant across sample rates so long as the
SR bits are set correctly. E.g. when sampling at 48kHz the sample rates stated in Table 18 will only
be correct if the SR bits are set to 000 (48kHz). If the actual sample rate was only 44.1kHz then the
hold, decay and attack times would be scaled down by 44.1/48.
n
) steps, from 3.3ms/6dB, 6.6ms/6dB, 13.1ms/6dB, etc.
n
) steps, from 832us/6dB, 1.66ms/6dB,
w
PD, Rev 4.3, October 2008
38
Page 39
Production Data WM8758B
REGISTER
ADDRESS
R32
ALC Control
1
R33
ALC Control
2
BIT LABEL DEFAULT DESCRIPTION
8:7 ALCSEL 00 ALC function select
00 = ALC disabled
01 = Right channel ALC enabled
10 = Left channel ALC enabled
11 = Both channels ALC enabled
5:3 ALCMAXGAIN
[2:0]
2:0 ALCMINGAIN
[2:0]
7:4 ALCHLD
[3:0]
3:0 ALCLVL
[3:0]
111
(+35.25dB)
000 (-12dB) Set minimum gain of PGA
0000
(0ms)
1011
(-6dB)
Set Maximum Gain of PGA
111 = +35.25dB
110 = +29.25dB
101 = +23.25dB
100 = +17.25dB
011 = +11.25dB
010 = +5.25dB
001 = -0.75dB
000 = -6.75dB
000 = -12dB
001 = -6dB
010 = 0dB
011 = +6dB
100 = +12dB
101 = +18dB
110 = +24dB
111 = +30dB
ALC hold time before gain is
increased.
0000 = 0ms
0001 = 2.67ms
0010 = 5.33ms
… (time doubles with every step)
1111 = 43.7s
ALC target – sets signal level at ADC
input
1111 = -1.5dBFS
1110 = -1.5dBFS
1101 = -3dBFS
1100 = -4.5dBFS
...... (-1.5dB steps)
0001 = -21dBFS
0000 = -22.5dBFS
w
PD, Rev 4.3, October 2008
39
Page 40
WM8758B Production Data
REGISTER
ADDRESS
R34
ALC Control
3
Table 18 ALC Control Registers
BIT LABEL DEFAULT DESCRIPTION
8 ALCMODE 0 Determines the ALC mode of
7:4 ALCDCY
[3:0]
3:0 ALCATK
[3:0]
0011
(13.1ms/6dB)
0011
(2.9ms/6dB)
0010
(832us/6dB)
0010
(182us/6dB)
operation:
0 = ALC mode
1 = Limiter mode.
Decay (gain ramp-up) time
(ALCMODE ==0)
Per
0000 410us 3.3ms 24ms
0001 820us 6.6ms 48ms
0010 1.64ms 13.1ms 192ms
… (time doubles with every step)
1010
or
higher
Decay (gain ramp-up) time
(ALCMODE ==1)
Per
0000 90.8us 726.4us 5.26ms
0001 181.6us 1.453ms 10.53ms
0010 363.2us 2.905ms 21.06ms
… (time doubles with every step)
1010 93ms 744ms 5.39s
ALC attack (gain ramp-down) time
(ALCMODE == 0)
Per
0000 104us 832us 6ms
0001 208us 1.664ms 12ms
0010 416us 3.328ms 24.1ms
… (time doubles with every step)
1010
or
higher
ALC attack (gain ramp-down) time
(ALCMODE == 1)
Per
0000 22.7us 182.4us 1.31ms
0001 45.4us 363.2us 2.62ms
0010 90.8us 726.4us 5.26ms
… (time doubles with every step)
1010 23.2ms 186ms 1.348s
step
420ms 3.36s 24.576s
step
step
106ms 852ms 6.18s
step
Per
6dB
Per
6dB
Per
6dB
Per
6dB
90% of
range
90% of
range
90% of
range
90% of
range
w
When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input
gain update must be made by writing to the INPPGAVOLL/R register bits.
PD, Rev 4.3, October 2008
40
Page 41
Production Data WM8758B
MINIMUM AND MAXIMUM GAIN
The ALCMINGAIN and ALCMAXGAIN register sets the minimum/maximum gain value that the PGA
can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not
enabled.
PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a
limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is
ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls
below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.
(Note: If ALCATK = 0000, then the limiter makes no difference to the operation of the ALC. It is
designed to prevent clipping when long attack times are used).
NOISE GATE
When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise
pumping”, i.e. loud hissing noise during silence periods. The WM8758B has a noise gate function
that prevents noise pumping by comparing the signal level at the input pins against a noise gate
threshold, NGTH. The noise gate cuts in when:
Signal level at ADC [dBFS] < NGTH [dBFS] + PGA gain [dB] + Mic Boost gain [dB]
This is equivalent to:
Signal level at input pin [dBFS] < NGTH [dBFS]
The PGA gain is then held constant (preventing it from ramping up as it normally would when the
signal is quiet).
The table below summarises the noise gate control register. The NGTH control bits set the noise
gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps.
Levels at the extremes of the range may cause inappropriate operation, so care should be taken with
set–up of the function. The noise gate only operates in conjunction with the ALC and cannot be used
in limiter mode.
REGISTER
ADDRESS
R35
ALC Noise Gate
Control
Table 19 ALC Noise Gate Control
BIT LABEL DEFAULT DESCRIPTION
NGTH
2:0
NGATEN 0 Noise gate function enable
3
000 Noise gate threshold:
000 = -39dB
001 = -45dB
010 = -51db
… (6dB steps)
111 = -81dB
1 = enable
0 = disable
w
PD, Rev 4.3, October 2008
41
Page 42
WM8758B Production Data
OUTPUT SIGNAL PATH
The WM8758B output signal paths consist of digital application filters, up-sampling filters, stereo
Hi-Fi DACs, analogue mixers, stereo headphone and stereo line/mono/midrail output drivers. The
digital filters and DAC are enabled by register bits DACENL and DACENR. The mixers and output
drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is
possible to equalizer the analogue mixing and amplification provided by the WM8758B, irrespective
of whether the DACs are running or not.
The WM8758B DACs receive digital input data on the DACDAT pin. The digital filter block processes
the data to provide the following functions:
Digital volume control
Graphic equaliser
A digital peak limiter.
Sigma-Delta Modulation
High performance sigma-delta audio DAC converts the digital data into an analogue signal.
Figure 22 DAC Digital Filter Path
The analogue outputs from the DACs can then be mixed with the ADC analogue inputs. The mix is
fed to the output drivers for headphone (LOUT1/ROUT1, LOUT2/ROUT2) or line (OUT3/OUT4).
OUT3 and OUT4 have additional mixers which allow them to output different signals to the
headphone and line outputs.
DIGITAL PLAYBACK (DAC) PATH
Digital data is passed to the WM8758B via the flexible audio interface and is then passed through a
variety of advanced digital filters as shown in Figure 22 to the hi-fi DACs. The DACs are enabled by
the DACENL/R register bits.
REGISTER
ADDRESS
R3
Power
Management 3
Table 20 DAC Enable Control
The WM8758B also has a Soft Mute function, which when enabled, gradually attenuates the volume
of the digital signal to zero. When disabled, the gain will ramp back up to the digital gain setting. This
function is enabled by default. To play back an audio signal, it must first be disabled by setting the
SOFTMUTE bit to zero.
BIT LABEL DEFAULT DESCRIPTION
0 DACENL 0 Left channel DAC enable
0 = DAC disabled
1 = DAC enabled
1 DACENR 0 Right channel DAC enable
0 = DAC disabled
1 = DAC enabled
w
PD, Rev 4.3, October 2008
42
Page 43
Production Data WM8758B
REGISTER
ADDRESS
R10
DAC Control
Table 21 DAC Control Register
The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital
interpolation filters. The bitstream data enters the multi-bit, sigma-delta DACs, which convert it to a
high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and
sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and
low distortion.
BIT LABEL DEFAULT DESCRIPTION
DACPOL 0 Left DAC output polarity:
0
0 = non-inverted
1 = inverted (180 degrees phase shift)
1 DACRPOL 0 Right DAC output polarity:
0 = non-inverted
1 = inverted (180 degrees phase shift)
AMUTE 0 Automute enable
2
0 = Amute disabled
1 = Amute enabled
DACOSR 0 DAC oversampling rate:
3
0 = 64x (lowest power & best
performance)
1 = 128x
SOFTMUTE 0 Softmute enable:
6
0 = Enabled
1 = Disabled
The DAC output phase defaults to non-inverted. Setting DACLPOL will invert the DAC output phase
on the left channel and DACRPOL inverts the phase on the right channel.
AUTO-MUTE
The DAC has an auto-mute function which applies an analogue mute when 1024 consecutive zeros
are detected. The mute is released as soon as a non-zero sample is detected. Auto-mute can be
disabled using the AMUTE control bit.
DIGITAL HI-FI DAC VOLUME (GAIN) CONTROL
The signal volume from each Hi-Fi DAC can be controlled digitally. The gain range is –127dB to 0dB
in 0.5dB steps. The level of attenuation for an eight-bit code X is given by:
0.5 × (X-255) dB for 1 ≤ X ≤ 255; MUTE for X = 0
w
PD, Rev 4.3, October 2008
43
Page 44
WM8758B Production Data
REGISTER
ADDRESS
R11
Left DAC
Digital Volume
R12
Right DAC
Digital Volume
Table 22 DAC Digital Volume Control
Note: An additional gain of up to 12dB can be added using the gain block embedded in the
digital peak limiter circuit (see DAC OUTPUT LIMITER section).
BIT LABEL DEFAULT DESCRIPTION
7:0 DACLVOL
[7:0]
8 DACVU Not
7:0 DACRVOL
[7:0]
8 DACVU Not
11111111
( 0dB )
latched
11111111
( 0dB )
latched
Left DAC Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
DAC left and DAC right volume do
not update until a 1 is written to
DACVU (in reg 11 or 12)
Right DAC Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
DAC left and DAC right volume do
not update until a 1 is written to
DACVU (in reg 11 or 12)
5-BAND EQUALISER
A 5-band graphic equalizer function which can be used to change the output frequency levels to suit
the environment. This can be applied to the ADC or DAC path and is described in the 5-BAND
EQUALISER section for further details on this feature.
3-D ENHANCEMENT
The WM8758B has an advanced digital 3-D enhancement feature which can be used to vary the
perceived stereo separation of the left and right channels. Like the 5-band equalizer this feature can
be applied to either the ADC record path or the DAC equalizer path but not both simultaneously.
Refer to the 3-D STEREO ENHANCEMENT section for further details on this feature.
DAC DIGITAL OUTPUT LIMITER
The WM8758B has a digital output limiter function. The operation of this is shown in Figure 23. In
this diagram the upper graph shows the envelope of the input/output signals and the lower graph
shows the gain characteristic.
w
PD, Rev 4.3, October 2008
44
Page 45
Production Data WM8758B
Figure 23 DAC Digital Limiter Operation
The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 23, in
normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the
limiter. Signals above the upper threshold are attenuated at a specific attack rate (set by the
LIMATK register bits) until the signal falls below the threshold. The limiter also has a lower threshold
1dB below the upper threshold. When the signal falls below the lower threshold the signal is
amplified at a specific decay rate (controlled by LIMDCY register bits) until a gain of 0dB is reached.
Both threshold levels are controlled by the LIMLVL register bits. The upper threshold is 0.5dB above
the value programmed by LIMLVL and the lower threshold is 0.5dB below the LIMLVL value.
w
PD, Rev 4.3, October 2008
45
Page 46
WM8758B Production Data
VOLUME BOOST
The limiter has programmable upper gain which boosts signals below the threshold to compress the
dynamic range of the signal and increase its perceived loudness. This operates as an ALC function
with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the
LIMBOOST register bits.
The output limiter volume boost can also be used as a stand alone digital gain boost when the limiter
is disabled.
REGISTER
ADDRESS
R24
DAC digital
limiter control
1
R25
DAC digital
limiter control
2
BIT LABEL DEFAULT DESCRIPTION
3:0 LIMATK 0010 Limiter Attack time (per 6dB gain
7:4 LIMDCY 0011
8 LIMEN 0
3:0 LIMBOOST 0000
change) for 44.1kHz sampling. Note
that these are proportionally related to
sample rate.
0000 = 94us
0001 = 188s
0010 = 375us
0011 = 750us
0100 = 1.5ms
0101 = 3ms
0110 = 6ms
0111 = 12ms
1000 = 24ms
1001 = 48ms
1010 = 96ms
1011 to 1111 = 192ms
Limiter Decay time (per 6dB gain
change) for 44.1kHz sampling. Note
that these are proportionally related to
sample rate:
0000 = 750us
0001 = 1.5ms
0010 = 3ms
0011 = 6ms
0100 = 12ms
0101 = 24ms
0110 = 48ms
0111 = 96ms
1000 = 192ms
1001 = 384ms
1010 = 768ms
1011 to 1111 = 1.536s
Enable the DAC digital limiter:
0=disabled
1=enabled
Limiter volume boost (can be used as a
stand alone volume boost when
LIMEN=0):
0000 = 0dB
0001 = +1dB
0010 = +2dB
… (1dB steps)
1011 = +11dB
1100 = +12dB
1101 to 1111 = reserved
w
PD, Rev 4.3, October 2008
46
Page 47
Production Data WM8758B
REGISTER
ADDRESS
Table 23 DAC Digital Limiter Control
BIT LABEL DEFAULT DESCRIPTION
6:4 LIMLVL 000
Programmable signal threshold level
(determines level at which the limiter
starts to operate)
000 = -1dB
001 = -2dB
010 = -3dB
011 = -4dB
100 = -5dB
101 to 111 = -6dB
5-BAND GRAPHIC EQUALISER
A 5-band graphic equalizer is provided, which can be applied to the ADC or DAC path, together with
3D enhancement, under control of the EQ3DMODE register bit. The ADCs and DACs should be
disabled before changing the EQ3DMODE bit.
By default, the WM8758B operates in low power mode, and the DSP core runs at half of the normal
rate. In DAC low power mode, only 2-Band equalizer functionality is permitted, where only Band 1
(low shelf) and Band 5 (high shelf) can be used. For ADC low power, the equalizer and 3D cannot be
used. To enable full 5-band operation, set M128ENB = 1.
REGISTER
ADDRESS
R18
EQ Control 1
Table 24 EQ and 3D Enhancement DAC or ADC Path Select
BIT LABEL DEFAULT DESCRIPTION
8 EQ3DMODE 1 0 = Equaliser and 3D Enhancement
applied to ADC path
1 = Equaliser and 3D Enhancement
applied to DAC path
w
The equalizer consists of low and high frequency shelving filters (Band 1 and 5) and three peak
filters for the centre bands. Each has adjustable cut-off or centre frequency, and selectable boost
(+/- 12dB in 1dB steps). The peak filters have selectable bandwidth.
REGISTER
ADDRESS
R18
EQ Band 1
Control
Table 25 EQ Band 1 Control
REGISTER
ADDRESS
R19
EQ Band 2
Control
Table 26 EQ Band 2 Control
BIT LABEL DEFAULT DESCRIPTION
4:0 EQ1G 01100
(0dB)
6:5 EQ1C 01 Band 1 Cut-off Frequency:
BIT LABEL DEFAULT DESCRIPTION
4:0 EQ2G 01100
(0dB)
6:5 EQ2C 01 Band 2 Centre Frequency:
8 EQ2BW 0 Band 2 Bandwidth Control
Band 1 Gain Control. See Table 30 for
details.
00 = 80Hz
01 = 105Hz
10 = 135Hz
11 = 175Hz
Band 2 Gain Control. See Table 30 for
details.
00 = 230Hz
01 = 300Hz
10 = 385Hz
11 = 500Hz
0 = narrow bandwidth
1 = wide bandwidth
PD, Rev 4.3, October 2008
47
Page 48
WM8758B Production Data
REGISTER
ADDRESS
R20
EQ Band 3
Control
Table 27 EQ Band 3 Control
REGISTER
ADDRESS
R21
EQ Band 4
Control
Table 28 EQ Band 4 Control
BIT LABEL DEFAULT DESCRIPTION
4:0 EQ3G 01100
(0dB)
6:5 EQ3C 01 Band 3 Centre Frequency:
8 EQ3BW 0 Band 3 Bandwidth Control
BIT LABEL DEFAULT DESCRIPTION
4:0 EQ4G 01100
(0dB)
6:5 EQ4C 01 Band 4 Centre Frequency:
8 EQ4BW 0 Band 4 Bandwidth Control
Band 3 Gain Control. See Table 30 for
details.
00 = 650Hz
01 = 850Hz
10 = 1.1kHz
11 = 1.4kHz
0 = narrow bandwidth
1 = wide bandwidth
Band 4 Gain Control. See Table 30 for
details
00 = 1.8kHz
01 = 2.4kHz
10 = 3.2kHz
11 = 4.1kHz
0 = narrow bandwidth
1 = wide bandwidth
REGISTER
ADDRESS
R22
EQ Band 5
Gain Control
Table 29 EQ Band 5 Control
GAIN REGISTER GAIN
00000 +12dB
00001 +11dB
00010 +10dB
…. (1dB steps)
01100 0dB
01101 -1dB
11000 to 11111 -12dB
Table 30 Gain Register Table
See also Figure 49 to Figure 66 for equaliser and high pass filter responses.
BIT LABEL DEFAULT DESCRIPTION
4:0 EQ5G 01100
(0dB)
6:5 EQ5C 01 Band 5 Cut-off Frequency:
Band 5 Gain Control. See Table 30 for
details.
00 = 5.3kHz
01 = 6.9kHz
10 = 9kHz
11 = 11.7kHz
w
PD, Rev 4.3, October 2008
48
Page 49
Production Data WM8758B
3D STEREO ENHANCEMENT
The WM8758B has a digital 3D enhancement option to increase the perceived separation between
the left and right channels. Selection of 3D for record or playback is controlled by register bit
EQ3DMODE. Switching this bit from record to playback or from playback to record may only be done
when ADC and DAC are disabled. The W M8758B control interface will only allow EQ3DMODE to be
changed when ADC and DAC are disabled (ie ADCENL = 0, ADCENR = 0, DACENL = 0 and
DACENR = 0).
The DEPTH3D setting controls the degree of stereo expansion.
When 3D enhancement is used, it may be necessary to attenuate the signal by 6dB to avoid limiting.
In ADC low power mode (See Power Management section), the equaliser and 3D cannot be used. To
enable 3D enhancement and 5-band EQ operation, set M128ENB = 1.
REGISTER
ADDRESS
R41 (29h)
3D Control
Table 31 3D Stereo Enhancement Function
BIT LABEL DEFAULT DESCRIPTION
3:0 DEPTH3D[3:0] 0000 Stereo depth
0000 = 0% (minimum 3D effect)
0001 = 6.67%
....
1110 = 93.3%
1111 = 100% (maximum 3D effect)
ANALOGUE OUTPUTS
The WM8758B has three sets of stereo analogue outputs. These are:
The outputs LOUT2 and ROUT2 are powered from AVDD2 and are capable of driving a 1V rms
signal (AVDD1/3.3).
LOUT1, ROUT1, OUT3 and OUT4 are powered from AVDD1.
LOUT1, ROUT1, LOUT2 and ROUT2 have individual analogue volume PGAs with -57dB to +6dB
gain ranges.
There are four output mixers in the output signal path, the left and right channel mixers which control
the signals to headphone (and optionally the line outputs) and also dedicated OUT3 and OUT4
mixers.
LEFT AND RIGHT OUTPUT CHANNEL MIXERS
The left and right output channel mixers are shown in Figure 24. These mixers allow the ADC
bypass and the DAC left and right channels to be combined as desired. This allows a mono mix of
the DAC channels to be performed as well as mixing in speech from the input bypass path.
The bypass inputs have individual volume control from -15dB to +6dB and the DAC volume can be
adjusted in the digital domain if required. The output of these mixers is connected to both the stereo
headphone drivers (LOUT1, ROUT1, LOUT2 and ROUT2) and can optionally be connected to the
OUT3 and OUT4 mixers.
• LOUT1 and ROUT1 which can be used as headphone or line drivers.
• LOUT2 and ROUT2 – which can be used as headphone or line drivers.
• OUT3 and OUT4 – can be configured as a stereo line out (OUT3 is left output and
OUT4 is right output). OUT4 can also be used to provide a mono mix of left and
right channels.
w
PD, Rev 4.3, October 2008
49
Page 50
WM8758B Production Data
w
Figure 24 Left/Right Output Channel Mixers
PD, Rev 4.3, October 2008
50
Page 51
Production Data WM8758B
REGISTER
ADDRESS
R43
Output mixer
control
R43
Output mixer
control
R49
Output mixer
control
R50
Left channel
output mixer
control
R51
Right channel
output mixer
control
BIT LABEL DEFAULT DESCRIPTION
8 BYPL2RMIX 0 Left bypass path (from the Left
7 BYPR2LMIX 0 Right bypass path (from the right
5 DACR2LMIX 0 Right DAC output to left output
6 DACL2RMIX
0 DACL2LMIX
1 BYPL2LMIX 0 Left bypass path (from the left
4:2 BYPLMIXVOL 000 Left bypass volume contol to output
0 DACR2RMIX 0 Right DAC output to right output
1 BYPR2RMIX 0 Right bypass path (from the right
4:2 BYPRMIXVOL 000 Right bypass volume control to
0
0
channel input PGA stage) to right
output mixer
0 = not selected
1 = selected
channel input PGA stage) to Left
output mixer
0 = not selected
1 = selected
mixer
0 = not selected
1 = selected
Left DAC output to right output mixer
0 = not selected
1 = selected
Left DAC output to left output mixer
0 = not selected
1 = selected
channel input PGA stage) to left
output mixer
0 = not selected
1 = selected
channel mixer:
000 = -15dB
001 = -12dB
…
101 = 0dB
110 = +3dB
111 = +6dB
mixer
0 = not selected
1 = selected
channel input PGA stage) to right
output mixer
0 = not selected
1 = selected
output channel mixer:
000 = -15dB
001 = -12dB
…
101 = 0dB
110 = +3dB
111 = +6dB
w
PD, Rev 4.3, October 2008
51
Page 52
WM8758B Production Data
REGISTER
ADDRESS
R3
Power
management
3
Table 32 Left and Right Output Mixer Control
HEADPHONE OUTPUTS (LOUT1 AND ROUT1)
The headphone outputs LOUT1 and ROUT1 can drive a 16Ω or 32Ω headphone load, either through
DC blocking capacitors, or DC-coupled to a buffered midrail reference (LOUT2 or ROUT2), saving a
capacitor (capless mode). When using capless mode, AVDD1 and AVDD2 should use the same
supply to equalize supply rejection. OUT3 and OUT4 should not be used as a buffered midrail
reference in capless mode.
Each headphone output has an analogue volume control PGA with a gain range of -57dB to +6dB as
shown in Figure 25.
In order to provide common mode rejection of ground noise on the left and right outputs, a
headphone common ground feedback option is provided. HP_COM input may be used as HPCOM
common ground feedback signal. This signal is compared to the chip internal midrail voltage and the
difference used as the reference input to the headphone output buffer amplifier, as shown in Figure
25, and in more detail in the analog internal circuit diagram.
BIT LABEL DEFAULT DESCRIPTION
2 LMIXEN 0 Left output channel mixer enable:
0 = disabled
1= enabled
3 RMIXEN 0 Right output channel mixer enable:
0 = disabled
1 = enabled
Figure 25 Headphone Outputs LOUT1 and ROUT1
Headphone Output using DC Blocking Capacitors: with
HPCOM common mode feedback applied
Figure 26 Recommended Headphone Output Configurations
w
DC Coupled Headphone Output: no HPCOM feedback
PD, Rev 4.3, October 2008
52
Page 53
Production Data WM8758B
When DC blocking capacitors are used, their capacitance and the load resistance together
determine the lower cut-off frequency of the output signal, f
improving the bass response. Smaller capacitance values will diminish the bass response.
Assuming a 16Ω load and C1, C2 = 220µF:
fc = 1 / 2π RLC1 = 1 / (2π x 16Ω x 220µF) = 45 Hz
The AC coupling capacitor into the HP_COM feedback input requires to be a much smaller value,
typically 4.7uF as the internal resistance it is driving into is typically 22kohm.
In the DC coupled configuration, the headphone pseudo-ground is connected to the buffered midrail
reference pin (LOUT2 or ROUT2). The L/ROUT2 pins can be configured as a DC output driver by
setting the LOUT2MUTE and ROUT2MUTE register bits. The DC voltage on VMID in this
configuration is equal to the DC offset on the LOUT1 and ROUT1 pins therefore no DC blocking
capacitors are required. This saves space and material cost in portable applications.
It is not recommended to use DC-coupling to line inputs of another device. Although the built-in short
circuit protection on the headphone outputs would be tolerant of shorts to ground, such a connection
may be noisy, and may not function properly if the other device is grounded. DC-coupled
configurations should only be used with headphones.
. Increasing the capacitance lowers fc,
c
COMMON MODE DEFAULT
The common mode feedback mode is enabled by writing a 1 to HP_COM or LINE_COM (reg 49 bits
7 and 8). Under normal operation these registers defaults 0 (common mode disabled). However the
polarity of these registers can be inverted by using 2-wire control interface mode and holding the
CSB_GPIO1 pin high. In this mode of operation HP_COM=0 enables HP common mode, and
HP_COM=1 disables HP common mode. Similarly LINE_COM=0 enables LINE common mode and
LINE_COM=1 disables LINE common mode. Note that if the CSB_GPIO1 is configured as a GPIO
the operation of HP_COM and LINE_COM revert back to non-inverted operation.
w
PD, Rev 4.3, October 2008
53
Page 54
WM8758B Production Data
REGISTER
ADDRESS
R49 8 HP_COMEN 0 Headphone common ground enable:
R52
LOUT1
Volume
control
R53
ROUT1
Volume
control
Table 33 OUT1 Volume Control
BIT LABEL DEFAULT DESCRIPTION
1 = Use external common ground
0 = use internal VMID
0 Function inverts if MODE = 2-wire
And CSB/GPIO1 = ‘hi’
0 = Use external common ground
1 = Use internal VMID
7 LOUT1ZC 0 Headphone volume zero cross
6 LOUT1MUTE 0 Left headphone output mute:
5:0 LOUT1VOL 111001 Left headphone output volume:
8 HPVU
7 ROUT1ZC
6 ROUT1MUTE
5:0 ROUT1VOL
8 HPVU
Not latched
0
0
111001
Not latched
enable:
1 = Change gain on zero cross only
0 = Change gain immediately
0 = Normal operation
1 = Mute
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
LOUT1 and ROUT1 volumes do not
update until a 1 is written to HPVU
(in reg 52 or 53)
Headphone volume zero cross
enable:
1 = Change gain on zero cross only
0 = Change gain immediately
Right headphone output mute:
0 = Normal operation
1 = Mute
Right headphone output volume:
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
LOUT1 and ROUT1 volumes do not
update until a 1 is written to HPVU
(in reg 52 or 53)
w
HEADPHONE OUTPUTS (LOUT2 AND ROUT2)
The outputs LOUT2 and ROUT2 are designed to drive two headphone loads of 16Ω or 32Ω or line
outputs (See Headphone Output and Line Output sections, respectively). Each output has an
individual volume control PGA, a mute and an enable control bit as shown in Figure 27. LOUT2 and
ROUT2 output the left and right channel mixer outputs respectively.
The LOUT2/ROUT2 outputs also have the option of incorporating common ground feedback from
the output signal ground, via a connection to the LINE_COM input. This common ground feedback
signal should be AC-coupled via a 4.7uF capacitor as for the headphone common mode feedback
path. AC coupling of these outputs if they are used as LINE level outputs requires similar 1 to 4.7uF
AC coupling capacitors depending upon LINE load resistance.
PD, Rev 4.3, October 2008
54
Page 55
Production Data WM8758B
Figure 27 LOUT2 and ROUT2 Headphone Configuration with Feedback
w
Figure 28 LOUT2 and ROUT2 Line Output Configuration with Feedback
The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any
combination of the DAC output and the bypass path (output of the input boost stage). The
LOUT2/ROUT2 volume is controlled by the LOUT2VOL/ ROUT2VOL register bits. Gains over 0dB
may cause clipping if the input signal is too high. The LOUT2MUTE/ ROUT2MUTE register bits
cause these outputs to be muted (the output DC level is driven out). The output pins remain at the
same DC level, so that no click noise is produced when muting or un-muting.
REGISTER
ADDRESS
R49 7 LINE_COMEN 0 Line common ground enable:
Table 34 Line Common Control
BIT LABEL DEFAULT DESCRIPTION
1 = Use external common ground
0 = use internal VMID
0 Function inverts if MODE = 2-wire
And CSB/GPIO1 = ‘hi’
0 = Use external common ground
1 = Use internal VMID
PD, Rev 4.3, October 2008
55
Page 56
WM8758B Production Data
REGISTER
ADDRESS
R54
LOUT2
Volume
control
R55
ROUT2
Volume
control
Table 35 OUT2 Volume Control
BIT LABEL DEFAULT DESCRIPTION
7 LOUT2ZC 0 LOUT2 volume zero cross enable:
1 = Change gain on zero cross only
0 = Change gain immediately
6 LOUT2MUTE 0 Left output mute:
0 = Normal operation
1 = Mute
5:0 LOUT2VOL 111001 Left output volume:
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
8 SPKVU
7 ROUT2ZC
6 ROUT2MUTE
5:0 ROUT2VOL
8 SPKVU
Not latched
0
0
111001
Not latched
LOUT2 and ROUT2 volumes do not
update until a 1 is written to SPKVU
(in reg 54 or 55)
ROUT2 volume zero cross enable:
1 = Change gain on zero cross only
0 = Change gain immediately
Right output mute:
0 = Normal operation
1 = Mute
Right output volume:
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
LOUT2 and ROUT2 volumes do not
update until a 1 is written to SPKVU
(in reg 54 or 55)
w
ZERO CROSS TIMEOUT
A zero-cross timeout function is provided so that if zero cross is enabled on the input or output PGAs
the gain will automatically update after a timeout period if a zero cross has not occurred. This is
enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital
and is equal to 2
REGISTER
ADDRESS
R7
Additional
Control
Table 36 Timeout Clock Enable Control
21
* SYSCLK period.
BIT LABEL DEFAULT DESCRIPTION
0 SLOWCLKEN 0 Slow clock enable. Used for both the
jack insert detect debounce circuit and
the zero cross timeout.
0 = slow clock disabled
1 = slow clock enabled
PD, Rev 4.3, October 2008
56
Page 57
Production Data WM8758B
OUT3/OUT4 MIXERS AND OUTPUT STAGES
The OUT3/OUT4 pins provide an additional stereo line output, a mono output, or a differential line
output. There is a dedicated analogue mixer for OUT3 and one for OUT4 as shown in Figure 29.
The OUT3 and OUT4 output stages are powered from AVDD1 and AGND1.
w
Figure 29 OUT3 and OUT4 Mixers
OUT3 can provide a midrail reference, a left line output, or a mono mix line output.
OUT4 can provide a midrail reference, a right line output, or a mono mix line output.
Note: OUT3 and OUT4 should not be used as a buffered midrail pseudo GND in capless mode.
A 6dB attenuation function is provided for OUT4, to prevent clipping during mixing of left and right
signals. This function is enabled by the OUT4ATTN register bit.
PD, Rev 4.3, October 2008
57
Page 58
WM8758B Production Data
REGISTER
ADDRESS
R56
OUT3 mixer
control
R57
OUT4 mixer
control
Table 37 OUT3/OUT4 Mixer Registers
BIT LABEL DEFAULT DESCRIPTION
6 OUT3MUTE 0 0 = Output stage outputs OUT3 mixer
1 = Output stage muted – drives out
VMID. Can be used as VMID reference
in this mode. (Not to be used for
Capless HP pseudo GND)
3 OUT4_2OUT3 0 OUT4 mixer output to OUT3
0 = disabled
1 = enabled
2 BYPL2OUT3 0 Left ADC input to OUT3
0 = disabled
1 = enabled
1 LMIX2OUT3 0 Left DAC mixer to OUT3
0 = disabled
1 = enabled
0 LDAC2OUT3 1 Left DAC output to OUT3
0 = disabled
1 = enabled
7 OUT3_2OUT4 0 OUT3 mixer output to OUT4
0 = disabled
1 = enabled
6 OUT4MUTE 0 0 = Output stage outputs OUT4 mixer
1 = Output stage muted – drives out
VMID. Can be used as VMID reference
in this mode. (Not to be used for
Capless HP pseudo GND)
5 OUT4ATTN 0 0 = OUT4 normal output
1 = OUT4 attenuated by 6dB
4 LMIX2OUT4 0 Left DAC mixer to OUT4
0 = disabled
1 = enabled
3 LDAC2OUT4 0 Left DAC to OUT4
0 = disabled
1 = enabled
2 BYPR2OUT4 0 Right ADC input to OUT4
0 = disabled
1 = enabled
1 RMIX2OUT4 0 Right DAC mixer to OUT4
0 = disabled
1 = enabled
0 RDAC2OUT4 1 Right DAC output to OUT4
0 = disabled
1 = enabled
w
PD, Rev 4.3, October 2008
58
Page 59
Production Data WM8758B
ENABLING THE OUTPUTS
Each analogue output of the W M8758B can be independently enabled or disabled. The analogue
mixer associated with each output has a separate enable bit. All outputs are disabled by default. To
save power, unused parts of the WM8758B should remain disabled.
Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled
(BUFIOEN=0), as this may cause pop noise (see “Power Management” and “Applications
Information” sections).
REGISTER
ADDRESS
R1
Power
Management
1
R2
Power
Management
2
R3
Power
Management
3
Note: All “Enable” bits are 1 = ON, 0 = OFF
Table 38 Output Stages Power Management Control
BIT LABEL DEFAULT DESCRIPTION
2 BUFIOEN 0 Unused input/output bias buffer enable
6 OUT3MIXEN 0 OUT3 mixer enable
7 OUT4MIXEN 0 OUT4 mixer enable
8 ROUT1EN 0 ROUT1 output enable
7 LOUT1EN 0 LOUT1 output enable
6 SLEEP 0 0 = Normal device operation
1 = Supply current reduced in device
standby mode (see note)
2 LMIXEN 0 Left mixer enable
3 RMIXEN 0 Right mixer enable
5 ROUT2EN 0 ROUT2 output enable
6 LOUT2EN 0 LOUT2 output enable
7 OUT3EN 0 OUT3 enable
8 OUT4EN 0 OUT4 enable
Note: The SLEEP bit R2[6] should only be used when the device is already in standby mode. The
SLEEP bit prevents the MCLK from propagating round the device when the external MCLK signal
cannot be removed.
THERMAL SHUTDOWN
To protect the WM8758B from becoming too hot, a thermal sensor has been built in. If the chip
temperature reaches approximately 150°C and the TSDEN and TSOPCTRL bit are set, then all
outputs will be disabled to avoid further increase of the chip temperature.
Additionally, when the device is too hot and TSDEN is set, then the WM8758B de-asserts GPIO bit
11, a virtual GPIO that can be set up to generate an interrupt to the CPU (see “GPIO and Interrupt
Control” section).
REGISTER
ADDRESS
R49
Output Control
Table 39 Thermal Shutdown
BIT LABEL DEFAULT DESCRIPTION
1 TSDEN 0
2 TSOPCTRL 0 Thermal Shutdown Output enable
Thermal Sensor Enable
0 = disabled
1 = enabled
0 = Disabled
1 = Enabled, i.e. all outputs will be
disabled if TI set, i.e. temperature above
150ºC
UNUSED ANALOGUE INPUTS/OUTPUTS
Whenever an analogue input/output is disabled, it remains connected to a voltage source (AVDD1/2)
through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance
between the voltage buffer and the output pins can be controlled using the VROI control bit. The
default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. If
a high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the
resistance to about 30kΩ.
w
PD, Rev 4.3, October 2008
59
Page 60
WM8758B Production Data
REGISTER
ADDRESS
R49
Table 40 Disabled Outputs to VREF Resistance
A dedicated buffer is available for biasing unused analogue I/O pins as shown in Figure 30. This
buffer can be enabled using the BUFIOEN register bit.
Figure 30 summarises the bias options for the output pins.
BIT LABEL DEFAULT DESCRIPTION
0 VROI 0 VREF (AVDD1/2) to analogue output
resistance
0 = approx 1kΩ
1 = approx 30 kΩ
w
Figure 30 Unused Input/Output Pin Tie-off Buffers
L/ROUT2EN/
OUT3/4EN
0 0
0 1
1 X
Table 41 Unused Output Pin Bias Options
VROI OUTPUT CONFIGURATION
1kΩ to AVDD1/2
30kΩ to AVDD1/2
Output enabled (DC level=AVDD1/2)
PD, Rev 4.3, October 2008
60
Page 61
Production Data WM8758B
DIGITAL AUDIO INTERFACES
The audio interface has four pins:
• ADCDAT: ADC data output
• DACDAT: DAC data input
• LRC: Data Left/Right alignment clock
• BCLK: Bit clock, for synchronisation
The clock signals BCLK, and LRC can be outputs when the WM8758B operates as a master, or
inputs when it is a slave (see Master and Slave Mode Operation, below).
Five different audio data formats are supported:
• Left justified
• Right justified
• I2S
• DSP mode A
• DSP mode B
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8758B audio interface may be configured as either master or slave. As a master interface
device the WM8758B generates BCLK and LRC and thus controls sequencing of the data transfer on
ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In
slave mode (MS=0), the WM8758B responds with data to clocks it receives over the digital audio
interfaces.
In master mode, the BCLK and LRC clocks are not stopped when the ADC’s are disabled using
register R2[1:0] and the DAC’s are disabled using register R3{[:0]. The ADCDAT pin continuously
outputs the last word of data which was transmitted when the ADC was disabled. To prevent this in
master mode, it is necessary to disable the ADC’s R2[1:0] and DAC’s R3{[:0] and remove the MCLK
input clock OR by switching the digital audio interface to slave mode.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRC
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRC transition.
Figure 31 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition.
All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and
sample rate, there may be unused BCLK cycles after each LRC transition.
w
PD, Rev 4.3, October 2008
61
Page 62
WM8758B Production Data
Figure 32 Right Justified Audio Interface (assuming n-bit word length)
2
S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The
In I
other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency
and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of
the next.
Figure 33 I2S Audio Interface (assuming n-bit word length)
In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A)
rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the LRC pulse shown in Figure 34 and Figure
35. In device slave mode, Figure 36 and Figure 37, it is possible to use any length of LRC pulse less
than 1/fs, providing the falling edge of the LRC pulse occurs greater than one BCLK period before the
rising edge of the next LRC pulse.
1/fs
1 BCLK
LRCLK
BCLK
LEFT CHANNEL RIGHT CHANNEL
DACDAT /
ADCDAT
n-2 n-1
Input Word Length (WL)
n321
LSBMSB
n-2 n-1
n321
Figure 34 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)
w
PD, Rev 4.3, October 2008
62
Page 63
Production Data WM8758B
1/fs
1 BCLK
LRC
BCLK
RIGHT CHANNEL
n-2 n-1
n321
DACDAT /
ADCDAT
LEFT CHANNEL
n-2 n-1
Input Word Length (WL)
n321
LSBMSB
Figure 35 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master)
1/fs
1 BCLK
LRCLK
BCLK
DACDAT /
ADCDAT
1 BCLK
falling edge can occur anywhere i n this area
LEFT CHANNEL RIGHT CHANNEL
n321
n-2 n-1
Input Word Length (WL)
LSBMSB
n-2 n-1
n321
Figure 36 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)
w
1/fs
1 BCLK
LRC
BCLK
DACDAT /
ADCDAT
LEFT CHANNEL
Input Word Length (WL)
falling edge can occur anywher e in this area
RIGHT CHANNEL
n321
n-2 n-1
LSBMSB
n-2 n-1
n321
Figure 37 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave)
1 BCLK
PD, Rev 4.3, October 2008
63
Page 64
WM8758B Production Data
REGISTER
ADDRESS
R4
Audio
Interface
Control
R5 0 LOOPBACK 0 Digital loopback function
Table 42 Audio Interface Control
Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the
device will operate in 24-bit mode.
BIT LABEL DEFAULT DESCRIPTION
0 MONO 0 Selects between stereo and mono
1 ADCLRSWAP 0 Controls whether ADC data appears in
2 DACLRSWAP 0 Controls whether DAC data appears in
4:3 FMT 10 Audio interface Data Format Select:
6:5 WL 10 Word length
7 LRP 0 RJ, LJ & I2S modes – LRC polarity
8 BCP 0 BCLK polarity
device operation:
0 = Stereo device operation
1 = Mono device operation. Data
appears in ‘left’ phase of LRC.
‘right’ or ‘left’ phases of LRC clock:
0 = ADC left data appear in ‘left’ phase
of LRC and right data in ‘right’ phase
1 = ADC left data appear in ‘right’ phase
of LRC and right data in ‘left’ phase
‘right’ or ‘left’ phases of LRC clock:
0 = DAC left data appear in ‘left’ phase
of LRC and right data in ‘right’ phase
1 = DAC left data appear in ‘right’ phase
of LRC and right data in ‘left’ phase
00 = Right Justified
01 = Left Justified
2
10 = I
S format
11 = DSP/PCM mode
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits (see note)
0 = normal LRC polarity
1 = invert LRC polarity
DSP Mode – mode A/B select
0 = MSB is available on 2
edge after LRC rising edge (mode A)
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
0 = normal
1 = inverted
0 = No loopback
1 = Loopback enabled, ADC data output
is fed directly into DAC data input.
nd
BCLK rising
w
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised
below.
Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK
and LRC are outputs. The frequency of BCLK and LRC in master mode is controlled with BCLKDIV.
These are divided down versions of master clock. This may result in short BCLK pulses at the end of
a LRC if there is a non-integer ratio of BCLKs to LRC clocks.
PD, Rev 4.3, October 2008
64
Page 65
Production Data WM8758B
REGISTER
ADDRESS
R6
Clock
Generation
Control
Table 43 Clock Control
BIT LABEL DEFAULT DESCRIPTION
0 MS 0 Sets the chip to be master over LRC
and BCLK
0 = BCLK and LRC clock are inputs
1 = BCLK and LRC clock are outputs
generated by the WM8758B (MASTER)
4:2 BCLKDIV 000 Configures the BCLK and LRC output
frequency, for use when the chip is
master over BCLK.
000 = divide by 1 (BCLK=SYSCLK)
001 = divide by 2 (BCLK=SYSCLK/2)
010 = divide by 4
011 = divide by 8
100 = divide by 16
101 = divide by 32
110 = reserved
111 = reserved
7:5 MCLKDIV 010 Sets the scaling for either the MCLK or
PLL clock output (under control of
CLKSEL)
000 = divide by 1
001 = divide by 1.5
010 = divide by 2
011 = divide by 3
100 = divide by 4
101 = divide by 6
110 = divide by 8
111 = divide by 12
8 CLKSEL 1 Controls the source of the clock for all
internal operation:
0 = MCLK
1 = PLL output
w
The CLKSEL bit selects the internal source of the Master clock from the PLL (MCLK=1) or from
MCLK (MCLKSEL=0). When the internal clock is switched from one source to another using the
CLKSEL bit, the clock originally selected must generate at least one falling edge after CLKSEL has
changed for the switching of clocks to be successful.
EXAMPLE:
If the PLL is the current source of the internal clock (CLKSEL=1) and it is required to switch to the
MCLK, change CLKSEL to select MCLK (CLKSEL=0) and then disable PLL (PLLEN=0).
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data
from the ADC audio interface is fed directly into the DAC data input.
COMPANDING
The WM8758B supports A-law and µ-law companding on both transmit (ADC) and receive (DAC)
sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate
value to the DAC_COMP or ADC_COMP register bits respectively.
PD, Rev 4.3, October 2008
65
Page 66
WM8758B Production Data
REGISTER
ADDRESS
R5
Companding
Control
Table 44 Companding Control
Companding involves using a piecewise linear approximation of the following equations (as set out
by ITU-T G.711 standard) for data compression:
µ-law (where µ=255 for the U.S. and Japan):
F(x) = ln( 1 + µ|x|) / ln( 1 + µ) -1 ≤ x ≤ 1
law (where A=87.6 for Europe):
BIT LABEL DEFAULT DESCRIPTION
2:1 ADC_COMP 0 ADC companding
00 = off
01 = reserved
10 = μ-law
11 = A-law
4:3 DAC_COMP 0 DAC companding
00 = off
01 = reserved
10 = μ-law
11 = A-law
5 WL8 0 0 = off
1 = device operates in 8-bit mode.
F(x) = A|x| / ( 1 + lnA) } for x ≤ 1/A
F(x) = ( 1 + lnA|x|) / (1 + lnA) } for 1/A ≤ x ≤ 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for µ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB’s
of data.
Companding converts 13 bits (µ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The
input data range is separated into 8 levels, allowing low amplitude signals better precision than that
of high amplitude signals. This is to exploit the operation of the human auditory system, where
louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).
Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to
use 8 BCLK’s per LRC frame. When using DSP mode B, this allows 8-bit data words to be output
consecutively every 8 BCLK’s and can be used with 8-bit data words using the A-law and u-law
companding functions.
BIT7 BIT[6:4] BIT[3:0]
SIGN EXPONENT MANTISSA
Table 45 8-bit Companded Word Composition
w
PD, Rev 4.3, October 2008
66
Page 67
Production Data WM8758B
u-law Companding
120
100
80
60
40
Companded Output
20
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Normalised Input
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Normali sed Output
Figure 38 μ-Law Companding
120
100
80
60
40
Companded Output
20
0
0 0.2 0.4 0.6 0.8 1
Figure 39 A-Law Companding
A-law Companding
Normalised Input
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Normal ised Output
w
PD, Rev 4.3, October 2008
67
Page 68
WM8758B Production Data
AUDIO SAMPLE RATES
The WM8758B filter characteristics for the ADCs and the DACs are set using the SR register bits.
The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these
values and assume a 256fs master clock rate.
If a sample rate that is not explicitly supported by the SR register settings is required then the
closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack,
decay and hold times will scale appropriately.
REGISTER
ADDRESS
R7
Additional
Control
Table 46 Sample Rate Control
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
The WM8758B has an on-chip phase-locked loop (PLL) circuit that can be used to:
BIT LABEL DEFAULT DESCRIPTION
3:1 SR
000 Approximate sample rate (configures the
coefficients for the internal digital filters):
000 = 48kHz
001 = 32kHz
010 = 24kHz
011 = 16kHz
100 = 12kHz
101 = 8kHz
110-111 = reserved
Generate master clocks for the WM8758B audio functions from another external clock, e.g. in
telecoms applications.
Generate and output (on pin CSB/GPIO1) a clock for another part of the system that is derived from
an existing audio master clock.
Figure 40 shows the PLL and internal clocking on the WM8758B.
The PLL can be enabled or disabled by the PLLEN register bit.
REGISTER
ADDRESS
R1
Power
management 1
Table 47 PLLEN Control Bit
BIT LABEL DEFAULT DESCRIPTION
5 PLLEN 0 PLL enable
0 = PLL off
1 = PLL on
w
PD, Rev 4.3, October 2008
68
Page 69
Production Data WM8758B
Figure 40 PLL and Clock Select Circuit
w
The PLL frequency ratio R = f
PLLN = int R
PLLK = int (2
EXAMPLE:
MCLK=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a
selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f
R = 98.304 / 12 = 8.192
PLLN = int R = 8
k = int ( 224 x (8.192 – 8)) = 3221225 = 3126E9h
REGISTER
ADDRESS
R36
PLL N value
R37
PLL K value
1
R38
PLL K Value
2
R39
PLL K Value
3
Table 48 PLL Frequency Ratio Control
24
BIT LABEL DEFAULT DESCRIPTION
4 PLLPRESCALE 0 0 = MCLK input not divided (default)
3:0 PLLN 1000 Integer (N) part of PLL input/output
5:0 PLLK [23:18] 0Ch Fractional (K) part of PLL1
8:0 PLLK [17:9] 093h
8:0 PLLK [8:0] 0E9h
(see Figure 40) can be set using the register bits PLLK and PLLN:
2/f1
(R-PLLN))
= 4 x 2 x 12.288MHz = 98.304MHz.
2
1= Divide MCLK by 2 before input to
PLL
frequency ratio. Use values greater
than 5 and less than 13.
input/output frequency ratio (treat as
one 24-digit binary number).
PD, Rev 4.3, October 2008
69
Page 70
WM8758B Production Data
E
The PLL performs best when f
are shown below.
DESIRED
MCLK
(MHz)
19.68 11.29 90.3168 2 2 9.178537 9h 2DB492h 1001 (XX9h) 000001011 (00Bh) 011011010 (0Dah) 010010010 (092h)
19.68 12.288 98.304 2 2 9.990243 9h FD809Fh 1001 (XX9h) 000111111 (03Fh) 011000000 (0C0h) 010011111 (09Fh)
Table 49 PLL Frequency Examples
OUTPUT
(SYSCLK)
(f1)
14.4 11.29 90.3168 1 2 6.272 6h 45A1Cah 0110 (XX6h) 000010001 (011h) 011010000 (0D0h) 111001010 (1Cah)
14.4 12.288 98.304 1 2 6.826667 6h D3A06Eh 0110 (XX6h) 000110100 (034h) 111010000 (1D0h) 001101110 (06Eh)
19.2 11.29 90.3168 2 2 9.408 9h 6872Afh 1001 (XX9h) 000011010 (01Ah) 000111001 (039h) 010101111 (0Afh)
19.2 12.288 98.304 2 2 10.24 Ah 3D70A3h 1010 (XXAh) 000001111 (00Fh) 010111000 (0B8h) 010100011 (0A3h)
19.8 11.29 90.3168 2 2 9.122909 9h 1F76F7h 1001 (XX9h) 000000111 (007h) 110111011 (1BBh) 011110111 (0F7h)
19.8 12.288 98.304 2 2 9.929697 9h EE009Eh 1001 (XX9h) 000111011 (03Bh) 100000000 (100h) 010011110 (09Eh)
(MHz)
12
1.2889025 90.31122 1 2 7.525935 7h 86A3ACh 0111 (XX7h) 000100001 (021h) 101010001 (151h) 110101100 (1ACh)
12 12.288 98.304 1 2 8.192 8h 3126E8h 1000 (XX8h) 000001100 (00Ch) 010010011 (093h) 011101000 (0E8h)
13 11.29 90.3168 1 2 6.947446 6h F28BD4h 0110 (XX6h) 000111100 (03Ch) 101000101 (145h) 111010100 (1D4h)
13 12.288 98.304 1 2 7.561846 7h 8FD525h 0111 (XX7h) 000100011 (023h) 111101010 (1Eah) 100100101 (125h)
24
1.2889025 90.31122 2 2 7.525935 7h 86A3ACh 0111 (XX7h) 000100001 (021h) 101010001 (151h) 110101100 (1ACh)
24 12.288 98.304 2 2 8.192 8h 3126E8h 1000 (XX8h) 000001100 (00Ch) 010010011 (093h) 011101000 (0E8h)
26 11.29 90.3168 2 2 6.947446 6h F28BD4h 0110 (XX6h) 000111100 (03Ch) 101000101 (145h) 111010100 (1D4h)
26 12.288 98.304 2 2 7.561846 7h 8FD525h 0111 (XX7h) 000100011 (023h) 111101010 (1Eah) 100100101 (125h)
27 11.29 90.3168 2 2 6.690133 6h B0AC93h 0110 (XX6h) 000101100 (02Ch) 001010110 (056h) 010010011 (093h)
27 12.288 98.304 2 2 7.281778 7h 482296h 0111 (XX7h) 000010010 (012h) 000010001 (011h) 010010110 (096h)
f2
(MHz)
R N K N
PRESCALE DIVIDE
POSTSCALE DIVID
is around 90MHz. Its stability peaks at N=8. Some example settings
2
K REGISTERS
REGISTER
R36[3:0]
R37 R38 R39
GENERAL PURPOSE INPUT/OUTPUT
The WM8758B has three dual purpose input/output pins.
• CSB/GPIO1: CSB / GPIO1 pin
• L2/GPIO2: Left channel line input / headphone detection input
• R2/GPIO3: Right channel line input / headphone detection input
The GPIO2 and GPIO3 functions are provided for use as jack detection inputs.
The GPIO1 and GPIO2 functions are provided for use as jack detection inputs or general purpose
outputs.
The default configuration for the CSB/GPIO1 is to be an input.
When setup as an input, the CSB/GPIO1 pin can either be used as CSB or for jack detection,
depending on how the MODE pin is set.
Table 50 illustrates the functionality of the GPIO1 pin when used as a general purpose output.
w
PD, Rev 4.3, October 2008
70
Page 71
Production Data WM8758B
REGISTER
ADDRESS
R8
GPIO
Control
6 GPIO1GPD 0 GPIO1 Internal pull-down enable:
7 GPIO1GPU 0 GPIO1 Internal pull-up enable:
8 GPIO1GP 0 GPIO1 Open drain enable
Table 50 CSB/GPIO Control
Note: If MODE is set to 3 wire mode, CSB/GPIO1 is used as CSB input irrespective of the
GPIO1SEL[2:0] bits.
BIT LABEL DEFAULT DESCRIPTION
2:0 GPIO1SEL 000 CSB/GPIO1 pin function select:
000 = input (CSB / Jack detection:
depending on MODE setting)
001 = reserved
010 = Temp ok
011 = Amute active
100 = PLL clk output
101 = PLL lock
110 = logic 0
111 = logic 1
3 GPIO1POL 0 GPIO1 Polarity invert
0 = Non inverted
1 = Inverted
5:4 OPCLKDIV 00 PLL Output clock division ratio
00 = divide by 1
01 = divide by 2
10 = divide by 3
11 = divide by 4
0 = Internal pull-down disabled
1 = Internal pull-down enabled
0 = Internal pull-up disabled
1 = Internal pull-up enabled
0 = Open drain disabled
1 = Open drain enabled
w
For further details of the jack detect operation see the OUTPUT SWITCHING section.
PD, Rev 4.3, October 2008
71
Page 72
WM8758B Production Data
OUTPUT SWITCHING (JACK DETECT)
When the device is operated using a 2-wire interface the CSB/GPIO1 pin can be used as a switch
control input to automatically disable one set of outputs and enable another. The L2/GPIO2 and
R2/GPIO3 pins can also be used for this purpose.
The GPIO pins have an internal de-bounce circuit when in this mode in order to prevent the output
enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a
slow clock with period 2
Note that the GPIOPOL bit is not relevant for jack detection, it is the signal detected at the pin which
is used.
The switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2,
OUT3 and OUT4 has 2 associated enables. OUT1_EN_0, OUT2_EN_0, OUT3_EN_0 and
OUT4_EN_0 are the output enable signals which are used if the selected jack detection pin is at
logic 0 (after de-bounce). OUT1_EN_1, OUT2_EN_1, OUT3_EN_1 and OUT4_EN_1 are the output
enable signals which are used if the selected jack detection pin is at logic 1 (after de-bounce).
Similar to the output enables, VMID can be output to OUT3. This VMID output can be configured to
be on/off depending on the jack detection input polarity of VMID_EN_0 and VMID_EN_1.
The jack detection enables operate as follows:
All OUT_EN signals have an AND function performed with their normal enable signals (in Table 38).
When an output is normally enabled at per Table 38, the selected jack detection enable (controlled
by selected jack detection pin polarity) is set 0, it will turn the output off. If the normal enable signal is
already OFF (0), the jack detection signal will have no effect due to the AND function.
During jack detection if the user desires an output to be un-changed whether the jack is in or not,
both the JD_EN settings i.e. JD_EN0 and JD_EN1, should be set to 0000.
21
x MCLK.
The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the
VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should
set to 0 for all JD_EN0 or JD_EN1 settings.
If jack detection is not enabled (JD_EN=0), the output enables default to all 1’s, allowing the outputs
to be controlled as normal via the normal output enables found in Table 38. Similarly the VMID_EN
signal defaults to 0 allowing the VMID driver to be controlled via the normal enable bit.
w
PD, Rev 4.3, October 2008
72
Page 73
Production Data WM8758B
REGISTER
ADDRESS
R9
GPIO control
R13 3:0 JD_EN0 0000 Output enables when selected jack
Table 51 Jack Detect Register Control Bits
BIT LABEL DEFAULT DESCRIPTION
5:4 JD_SEL 00 Pin selected as jack detection input
00 = GPIO1
01 = GPIO2
10 = GPIO3
11 = Reserved
6 JD_EN 0 Jack Detection Enable
0 = disabled
1 = enabled
8:7 JD_VMID 00 [7] VMID_EN_0
[8] VMID_EN_1
detection input is logic 0.
0000 = OUT1_EN_0
0001 = OUT2_EN_0
0010 = OUT3_EN_0
0011 = OUT4_EN_0
0100-1111 = Reserved
7:4 JD_EN1 0000 Output enables when selected jack
detection input is logic 1
0000-0011 = Reserved
0100 = OUT1_EN_1
0101 = OUT2_EN_1
0110 = OUT3_EN_1
0111 = OUT4_EN_1
1000-1111 = Reserved
CONTROL INTERFACE
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
The control interface can operate as either a 3-wire or 2-wire control interface. The MODE pin
determines the 2 or 3 wire mode as shown in Table 52.
The WM8758B is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are register address bits that select which control
register is accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 data bits
in each control register.
Table 52 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB/GPIO latches in a complete control word consisting of the last 16 bits.
MODE INTERFACE FORMAT
Low 2 wire
High 3 wire
w
PD, Rev 4.3, October 2008
73
Page 74
WM8758B Production Data
Figure 41 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8758B supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit
address of each register in the WM8758B).
The WM8758B operates as a slave device only. The controller indicates the start of data transfer
with a high to low transition on SDIN while SCLK remains high. This indicates that a device address
and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next
eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received
matches the address of the WM8758B, the WM8758B responds by pulling SDIN low on the next
clock pulse (ACK). If the address is not equalized or the R/W bit is ‘1’ when operating in write only
mode, the WM8758B returns to the idle condition and waits for a new start condition and valid
address.
During a write, once the WM8758B has acknowledged a correct address, the controller sends the
first byte of control data (B15 to B8, i.e. the WM8758B register address plus the first bit of register
data). The WM8758B then acknowledges the first data byte by driving SDIN low for one clock cycle.
The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of
register data), and the W M8758B acknowledges again by pulling SDIN low.
Transfer is complete when there is a low to high transition on SDIN while SCLK is high. After a
complete sequence the W M8758B returns to the idle state and waits for another start condition. If a
start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN
changes while SCLK is high), the control interface returns to the idle condition.
Figure 42 2-Wire Serial Control Interface
In 2-wire mode the WM8758B has a fixed device address, 0011010.
In 2-wire mode the CSB/GPIO1 pin controls the inversion of the HP_COM and LINE_COM register
bits. When CSB/GPIO1 is set, these register bits are inverted (providing CSB/GPIO1 is not
configured as a GPIO). See the section titled COMMON MODE DEFAULT for more details.
RESETTING THE CHIP
The WM8758B can be reset by performing a write of any value to the software reset register
(address 0h). This will cause all register values to be reset to their default values. In addition to this
there is a Power-On Reset (POR) circuit which ensures that the registers are initially set to default
when the device is powered up.
SDIN
SCLK
DEVICE ADDRES S
(7 BITS)
RD / WR
BIT
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
register ad dress and
1st regis ter data bit
ACK
(LOW)
CONTROL BYTE 1
(BITS 7 TO 0)
remaining 8 b its of
register da ta
ACK
(LOW)
STOPSTART
w
PD, Rev 4.3, October 2008
74
Page 75
Production Data WM8758B
POWER SUPPLIES
The WM8758B requires four separate power supplies:
• AVDD1 and AGND1: Analogue supply, powers all internal analogue functions and
output drivers LOUT1, ROUT1, OUT3 and OUT4. AVDD1 must be between 2.5V and
3.6V and has the most significant impact on overall power consumption (except for
power consumed in the headphones). Higher AVDD will improve audio quality.
• AVDD2 and AGND2: Output driver supplies, power LOUT2 and ROUT2. AVDD2 must
be between 2.5V and 3.6V. AVDD2 can be tied to AVDD1, but it requires separate
layout and decoupling capacitors to curb harmonic distortion.
• DCVDD: Digital core supply, powers all digital functions except the audio and control
interfaces. DCVDD must be between 1.71V and 3.6V, and has no effect on audio
quality. The return path for DCVDD is DGND, which is shared with DBVDD.
• DBVDD must be between 1.71V and 3.6V. DBVDD return path is through DGND.
It is possible to use the same supply voltage for all four supplies. However, digital and analogue
supplies should be routed and decoupled separately on the PCB to keep digital switching noise out
of the analogue signal paths.
POWER MANAGEMENT
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode.
Under the control of ADCOSR128 the oversampling rate may be doubled. 64x oversampling results
in a slight decrease in noise performance compared to 128x but lowers the power consumption of
the device.
REGISTER
ADDRESS
R14
ADC control
Table 53 ADC Oversampling Rate Selection
BIT LABEL DEFAULT DESCRIPTION
3 ADCOSR128 0 ADC oversample rate select
0 = 64x (lowest power)
1 = 128x (best SNR)
w
LOW POWER MODE
If only DAC or ADC functionality is required, the WM8758B can be put into a low power mode. In
this mode, the DSP core runs at half of the normal rate, reducing digital power consumption of the
core by half. For DAC low power only, 3D enhancement with 2-Band equalizer functionality is
permitted, where only Band 1 (low shelf) and Band 5 (high shelf) can be used. For ADC low power,
the equalizer and 3D cannot be used.
REGISTER
ADDRESS
R7
Additional Ctrl
Table 54 DSP Core Low Power Mode Control
BIT LABEL DEFAULT DESCRIPTION
8 M128ENB 0 0 = low power mode enabled
1 = low power mode disabled
PD, Rev 4.3, October 2008
75
Page 76
WM8758B Production Data
There are 3 modes of low power operation, as detailed below. The device will not enter low power
unless in one of these register configurations, regardless of M128ENB.
FUNCTION REGISTER BITS SETTING DESCRIPTION
ADC low power M128ENB
ADCENL
ADCENR
DACENL
DACENR
EQ3DMODE
DAC low power M128ENB
ADCENL
ADCENR
DACENL
DACENR
Table 55 DSP Core Low Power Modes for ADC Only and DAC Only Modes
VMID
The analogue equalizer will not operate unless VMID is enabled. The impedance of the VMID
resistor string, together with the decoupling capacitor on the VMID pin will determine the startup time
of the VMID circuit.
REGISTER
ADDRESS
R1
Power
management 1
Table 56 VMID Impedance Control
BIT LABEL DEFAULT DESCRIPTION
1:0 VMIDSEL 00 Reference string impedance to VMID pin
0
1
1
0
0
1 (DAC path)
0
0
0
1
1
Either or both of ADCENL and
ADCENR must be set (mono or
stereo mode)
Either or both of DACENL and
DACENR must be set (mono or
stereo mode)
EQ3DMODE = 0: EQ in ADC path
EQ3DMODE = 1: EQ in DAC path
(Determines startup time):
00 = off (250kΩ VMID to AGND1)
01 = 100kΩ
10 = 500kΩ
11 = 10kΩ (for fast startup)
w
BIASEN
The analogue amplifiers will not operate unless BIASEN is enabled.
REGISTER
ADDRESS
R1
Power
management 1
Table 57 Analogue Bias Control
BIT LABEL DEFAULT DESCRIPTION
3 BIASEN 0 Analogue amplifier bias control
0 = disabled
1 = enabled
HALFOPBIAS
HALFOPBIAS halves the bias current to the output drivers (OUT1, OUT2, OUT3). Setting
HALFOPBIAS will reduce the quiescent current from AVDD by 0.5mA but will degrade the THD+N
significantly.
REGISTER
ADDRESS
R61
Bias Control
Table 58 HALFOPBIAS Control
Wolfson’s recommendation is: Do not use HALFOPBIAS
BIT LABEL DEFAULT DESCRIPTION
0 HALFO
PBIAS
0 HALFOPBIAS (Do not use)
0 = disabled
1 = enabled (Reduces AVDD current by
0.5mA)
PD, Rev 4.3, October 2008
76
Page 77
Production Data WM8758B
POP MINIMISATION
POBCTRL
WM8758B has two bias generators. A noisy bias derived from AVDD and a low noise bias derived
from VMID. POBCTRL is use to switch between the two bias generators. During power up, the
AVDD derived bias is available as soon as AVDD is applied; the VMID derived bias is available once
the VMID node has charged up.
VMIDTOG
Fast VMID discharge is enabled using VMIDTOG bit. Setting to 1 opens a low impedance discharge
path from VMID to GND. This function can be used during power down to reduce the discharge time
of the VMID decoupling capacitor. Must be set to 0 for normal operation.
REGISTER
ADDRESS
R42
OUT4 to ADC
Table 59 POBCTRL and VMIDTOG Control
BIT LABEL DEFAULT DESCRIPTION
2 POB
CTRL
4 VMID
TOG
0 POBCTRL (Use during power Up. Reset
when VMID bias is stable)
0 = Bias derived from VMID
1 = Bias derived from AVDD
0 Fast VMID discharge
0 = normal operation
1 = enabled (used during power-down
sequence
POBCTRL should be asserted during power up to minimize pops and then de-asserted at the end of
the power up sequence to give best performance. Refer to Recommended Power Up/Down
Sequence
w
PD, Rev 4.3, October 2008
77
Page 78
WM8758B Production Data
REGISTER MAP
ADDR
B[15:9]
DEC HEX (HEX)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
19 13 EQ2 – peak 1 EQ2BW 0 EQ2C EQ2G 02C
20
21
22
24 18 DAC Limiter 1 LIMEN LIMDCY LIMATK 032
25
27
28
29
30
32
33
34
35
36
37
38
39
41
42
43
REGISTER
NAME
00 Software Reset Software reset
01 Power manage’t 1 0 OUT4MIX
02 Power manage’t 2 ROUT1EN LOUT1EN
03 Power manage’t 3 OUT4EN OUT3EN LOUT2EN
04 Audio Interface BCP LRP WL FMT DLRSWAP
05 Companding ctrl 0 0 0 WL8 DAC_COMP ADC_COMP LOOP
06 Clock Gen ctrl CLKSEL MCLKDIV BCLKDIV 0 MS 140
07 Additional ctrl M128ENB 0 0 0 0 SR SLOWCLK
08 GPIO Stuff GPIO1GP GPIO1GPU
09 Jack detect control
0A DAC Control 0 0 SOFT
0B Left DAC digital Vol
0C Right DAC dig’l Vol
0D Jack Detect Control
0E ADC Control HPFEN HPFAPP HPFCUT ADCOSR
0F Left ADC Digital
Vol
10 Right ADC Digital
Vol
12 EQ1 – low shelf EQ3DMODE
14 EQ3 – peak 2 EQ3BW 0 EQ3C EQ3G 02C
15 EQ4 – peak 3 EQ4BW 0 EQ4C EQ4G 02C
16 EQ5 – high shelf 0 0 EQ5C EQ5G 02C
19 DAC Limiter 2 0 0 LIMLVL LIMBOOST 000
1B Notch Filter 1 NFU NFEN NFA0[13:7] 000
1C Notch Filter 2 NFU 0 NFA0[6:0] 000
1D Notch Filter 3 NFU 0 NFA1[13:7] 000
1E Notch Filter 4 NFU 0 NFA1[6:0] 000
20 ALC control 1 ALCSEL 0 ALCMAX ALCMIN 038
21 ALC control 2 0 ALCHLD ALCLVL 00B
22 ALC control 3 ALCMODE ALCDCY ALCATK 032
23 Noise Gate 0 0 0 0 0 NGEN NGTH 000
24 PLL N 0 0 0 0 PLLPRE
25 PLL K 1 0 0 0 PLLK[23:18] 00C
26 PLL K 2 PLLK[17:9] 093
27 PLL K 3 PLLK[8:0] 0E9
29 3D control DEPTH3D 000
OUT4 to ADC OUT4_2ADCVOL OUT4_2
2A
2B Beep control BYPL2
B8 B7 B6 B5 B4 B3 B2 B1 B0 DEF’T
VAL
OUT3MIX
EN
SLEEP BOOST
GPIO1GPD
JD_VMID1 JD_VMID0 JD_EN JD_SEL 0 0 0 0 000
MUTE
DACVU DACLVOL 0FF
DACVU DACRVOL 0FF
0 JD_EN1 JD_EN0 000
ADCVU ADCLVOL 0FF
ADCVU ADCRVOL 0FF
0 EQ1C EQ1G 12C
BYPR2
RMIX
LMIX
PLLEN MICBEN BIASEN BUFIOEN
EN
BOOST
ENR
ROUT2EN 0 RMIXEN LMIXEN DACENR DACENL 000
0 0 DACOSR
LNR
0 0 0 0 DELEN2 0 0 000
ENL
OPCLKDIV GPIO1POL
SCALE
VMIDTOG OUT2DEL POBCTRL DELEN OUT1DEL 000
INPGA
ENR
128
128
INPPGA
ENL
AMUTE DACRPOL
0 ADCRPOL
PLLN[3:0] 008
VMIDSEL 000
ADCENR ADCENL 000
ALRSWAP MONO 050
000
BACK
000
EN
GPIO1SEL[2:0] 000
DACLPOL 000
ADCLPOL 100
w
PD, Rev 4.3, October 2008
78
Page 79
Production Data WM8758B
ADDR
B[15:9]
DEC HEX (HEX)
44
45
46
47
48
49
50
51
52
53
54
55
56
57
61
Table 59 WM8758B Register Map
REGISTER
NAME
2C Input ctrl MICBVSEL 0 R2_2
2D Left INP PGA gain
ctrl
2E Right INP PGA
gain ctrl
2F Left ADC Boost ctrl
30 Right ADC Boost
ctrl
31 Output ctrl HP_COM LINE_COM
32 Left mixer ctrl 0 0 BYPLMIXVOL BYPL2
33 Right mixer ctrl 0 0 BYPRMIXVOL BYPR2
34 LOUT1 (HP)
volume ctrl
35 ROUT1 (HP)
volume ctrl
36 LOUT2 (SPK)
volume ctrl
37 ROUT2 (SPK)
volume ctrl
38 OUT3 mixer ctrl 0 0 OUT3
39 OUT4 (MONO)
mixer ctrl
3D Bias Control BIASCUT 0 HALF
B8 B7 B6 B5 B4 B3 B2 B1 B0 DEF’T
VAL
INPPGA
INPGAVU INPPGA
ZCL
INPGAVU INPPGA
ZCR
PGA
BOOSTL
PGA
BOOSTR
OUT1VU LOUT1ZC LOUT1
OUT1VU ROUT1ZC
OUT2VU LOUT2ZC LOUT2
OUT2VU ROUT2ZC
0 OUT
3_2OUT4
INPPGA
MUTEL
INPPGA
MUTER
0 L2_2BOOSTVOL 0 000 100
0 R2_2BOOSTVOL 0 000 100
DACL2
RMIX
MUTE
ROUT1
MUTE
MUTE
ROUT2
MUTE
MUTE
OUT4
MUTE
I_IPGA
RIN2
INPPGA
DACR2
LMIX
0 0 OUT4_
OUT4
ATTN
0 BUFBIAS[1:0] ADCBIAS[1:0] HALFOP
RIP2
INPPGA
OUT4
ENDEL
LMIX2
OUT4
0 L2_2
INPPGA
INPPGAVOLL 010
INPPGAVOLR 010
OUT3
ENDEL
2OUT3
LDAC2
OUT4
TSOP
CTRL
LOUT1VOL 039
ROUT1VOL 039
LOUT2VOL 039
ROUT2VOL 039
BYPL2
OUT3
BYPR2
OUT4
LIN2
INPPGA
TSDEN VROI 002
LMIX
RMIX
LMIX2
OUT3
RMIX2
OUT4
LIP2
INPPGA
DACL2
LMIX
DACR2
RMIX
LDAC2
OUT3
RDAC2
OUT4
BIAS
003
001
001
001
001
000
w
PD, Rev 4.3, October 2008
79
Page 80
WM8758B Production Data
DIGITAL FILTER CHARACTERISTICS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC Filter
Passband
Passband Ripple
Stopband
Stopband Attenuation
Group Delay
ADC High Pass Filter
High Pass Filter Corner
Frequency
DAC Filter
Passband
Passband Ripple
Stopband
Stopband Attenuation
Group Delay
Table 60 Digital Filter Characteristics
+/- 0.025dB 0 0.454fs
-6dB 0.5fs
+/- 0.025 dB
0.546fs
f > 0.546fs -60 dB
21/fs
-3dB 3.7 Hz
-0.5dB 10.4
-0.1dB 21.6
+/- 0.035dB 0 0.454fs
-6dB 0.5fs
+/-0.035 dB
0.546fs
f > 0.546fs -55 dB
29/fs
TERMINOLOGY
1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)
2. Pass-band Ripple – any variation of the frequency response in the pass-band region
w
PD, Rev 4.3, October 2008
80
Page 81
Production Data WM8758B
DAC FILTER RESPONSES
20
0
-20
-40
-60
-80
Response (dB)
-100
-120
-140
-160
00.5 11.5 22.5
Freque ncy (fs)
Figure 43 DAC Digital Filter Frequency Response
3.05
3
2.95
2.9
2.85
2.8
Respons e (dB)
2.75
2.7
2.65
2.6
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (fs)
Figure 44 DAC Digital Filter Ripple (128xOSR)
(128xOSR)
20
0
-20
-40
-60
-80
Response (dB)
-100
-120
-140
-160
00.5 11.5 22.5
Freque ncy (fs)
3.05
3
2.95
2.9
2.85
2.8
Response (dB)
2.75
2.7
2.65
2.6
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (fs)
Figure 45 DAC Digital Filter Frequency Response (64xOSR) Figure 46 DAC Digital Filter Ripple (64xOSR)
ADC FILTER RESPONSES
0
-20
-40
-60
Response (dB)
-80
-100
-120
00.511.522.53
Frequency (Fs)
Figure 47 ADC Digital Filter Frequency Response Figure 48 ADC Digital Filter Ripple
0.2
0.15
0.1
0.05
0
-0.05
Res ponse (dB)
-0.1
-0.15
-0.2
0 0.1 0. 2 0 .3 0.4 0.5
Frequency (Fs)
PD, Rev 4.3, October 2008
w
81
Page 82
WM8758B Production Data
HIGHPASS FILTER
The WM8758B has a selectable digital highpass filter in the ADC filter path. This filter has two
modes, audio and applications. In audio mode the filter is a 1
3.7Hz. In applications mode the filter is a 2nd order high pass filter with a selectable cut-off
frequency.
5
0
-5
-10
-15
-20
Response (dB)
-25
-30
-35
-40
0 5 10 15 20 25 30 35 40 45
Frequency (Hz)
Figure 49 ADC Highpass Filter Response, HPFAPP=0
10
0
-10
-20
-30
Response (dB)
-40
-50
-60
0 200 400 600 800 1000 1200
Frequency (Hz)
10
0
-10
-20
-30
-40
Response (dB)
-50
-60
-70
-80
0 200 400 600 800 1000 1200
st
order IIR with a cut-off of around
Frequency (Hz)
Figure 50 ADC Highpass Filter Responses (48kHz),
HPFAPP=1, all cut-off settings shown.
10
0
-10
-20
-30
-40
-50
Response (dB)
-60
-70
-80
-90
0 200 400 600 800 1000 1200
Frequency (Hz)
Figure 52 ADC Highpass Filter Responses (12kHz),
HPFAPP=1, all cut-off settings shown.
w
Figure 51 ADC Highpass Filter Responses (24kHz),
HPFAPP=1, all cut-off settings shown.
PD, Rev 4.3, October 2008
82
Page 83
Production Data WM8758B
5-BAND EQUALISER
The WM8758B has a 5-band equalizer which can be applied to either the ADC path or the DAC
path. The plots from Figure 53 to Figure 66 show the frequency responses of each filter with a
sampling frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of
±12dB, and secondly a sweep of the gain from -12dB to +12dB for the lowest cut-off/centre
frequency of each filter.
15
10
5
0
Magnitude (dB)
-5
-10
-15
-1
0
1
2
3
4
10
10
10
10
Frequency (Hz)
10
5
10
10
15
10
5
0
Magnitude (dB )
-5
-10
-15
-1
0
1
2
3
4
10
10
10
10
10
Frequency (Hz)
10
5
10
Figure 53 EQ Band 1 Low Frequency Shelf Filter Cut-offs Figure 54 EQ Band 1 Gains for Lowest Cut-off Frequency
15
10
5
0
Magnitude (dB)
-5
15
10
5
0
Magnitude (dB )
-5
-10
-15
-1
0
1
2
3
4
10
10
10
10
Frequency (Hz)
10
5
10
10
Figure 55 EQ Band 2 – Peak Filter Centre Frequencies,
EQ2BW=0
15
10
5
0
Magnitude (dB)
-5
-10
-15
-2
-1
0
1
2
3
10
10
10
10
Frequency (Hz)
10
4
10
10
-10
-15
-1
0
10
10
1
10
Frequency (Hz)
Figure 56 EQ Band 2 – Peak Filter Gains for Lowest Cut-off
Frequency, EQ2BW=0
Figure 57 EQ Band 2 – EQ2BW=0, EQ2BW=1
w
2
3
4
10
10
10
5
10
PD, Rev 4.3, October 2008
83
Page 84
WM8758B Production Data
B
15
10
5
0
Magnitude (dB)
-5
-10
-15
-1
0
1
2
3
4
10
10
10
10
10
Frequency (Hz)
10
5
10
Figure 58 EQ Band 3 – Peak Filter Centre Frequencies, EQ3
15
10
5
0
Magnitude (dB)
-5
15
10
5
0
Magnitude (dB)
-5
-10
-15
-1
0
1
2
3
4
10
10
10
10
10
Frequency (Hz)
10
5
10
Figure 59 EQ Band 3 – Peak Filter Gains for Lowest Cut-off
Frequency, EQ3BW=0
-10
-15
-2
-1
0
1
2
3
10
10
10
10
10
Frequency (Hz)
10
4
10
Figure 60 EQ Band 3 – EQ3BW=0, EQ3BW=1
w
PD, Rev 4.3, October 2008
84
Page 85
Production Data WM8758B
B
15
10
5
0
Magnitude (dB)
-5
-10
-15
-1
0
1
2
3
4
10
10
10
10
10
Frequency (Hz)
10
5
10
Figure 61 EQ Band 4 – Peak Filter Centre Frequencies, EQ3
15
10
5
0
Magnitude (dB)
-5
15
10
5
0
Magnitude (dB)
-5
-10
-15
-1
0
1
2
3
4
10
10
10
10
10
Frequency (Hz)
10
5
10
Figure 62 EQ Band 4 – Peak Filter Gains for Lowest Cut-off
Frequency, EQ4BW=0
-10
-15
-2
-1
0
1
2
3
10
10
10
10
10
Frequency (Hz)
10
4
10
Figure 63 EQ Band 4 – EQ3BW=0, EQ3BW=1
15
10
5
0
Magnitude (dB)
-5
-10
-15
-1
0
1
2
3
4
10
10
10
10
10
Frequency (Hz)
10
5
10
15
10
5
0
Magnitude (dB)
-5
-10
-15
-1
0
1
2
3
4
10
10
10
10
10
Frequency (Hz)
10
5
10
Figure 64 EQ Band 5 High Frequency Shelf Filter Cut-offs Figure 65 EQ Band 5 Gains for Lowest Cut-off Frequency
w
PD, Rev 4.3, October 2008
85
Page 86
WM8758B Production Data
Figure 66 shows the result of having the gain set on more than one channel simultaneously. The
blue traces show each band (lowest cut-off/centre frequency) with ±12dB gain. The red traces show
the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EqxBW=0 for the
peak filters.
20
15
10
5
0
Magnitude (dB)
-5
-10
-15
-1
10
Figure 66 Cumulative Frequency Boost/Cut
0
10
10
1
2
10
Frequency (Hz )
3
10
4
10
5
10
w
PD, Rev 4.3, October 2008
86
Page 87
Production Data WM8758B
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 67 External Component Diagram
w
PD, Rev 4.3, October 2008
87
Page 88
WM8758B Production Data
PACKAGE DIAGRAM
FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH
DM044.B
A3
C
25
24
A
17
SEATING PLANE
16 15
e
D2
EXPOSED
GROUND
PADDLE
B
BOTTOM VIEW
SIDE VIEW
A3
b
Exposed lead
6
32
9
G
DETAIL 2
1
8
b
DETAIL 1
L
E2
1
M
A
A1
DETAIL 2
D
INDEX AREA
4
(D/2 X E/2 )
E
2 X
A
BCbbb
Cccc
5
C0.08
Caaa
2 X
Caa a
R = 0.3MM x 45
EXPOSED
GROUND
PADDLE
DETAIL 1
TOP VIEW
o
NOM
0.85
0.02
0.25
5.00 BSC
3.10
5.00 BSC
0.50 BSC
0.625
Dimensions (mm)
MAX NOTE
0.90
0.05
0.300.20
3.15
3.153.103.05
1
2
2
Symbols
A
A1
A3
b
D
D2
E
E2
e
G
L
MIN
0.80
0
0.203 REF
3.05
0.35 0.40 0.45
Tolerances of Form and Position
aaa
bbb
ccc
REF:
NOTES:
1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP.
2. FALLS WITHIN JEDEC, MO-220, VARIATION VHHD-5.
3. ALL DIMENSIONS ARE IN MILLIMETRES.
4. THE TERMINAL #1 IDENTIF IER AND TERMINAL NUMBERING CONVENTION SHALL C ONFORM TO JEDEC 95-1 SPP-002 .
5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SL UG AS WELL AS THE TERMINALS.
6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
JEDEC, MO-220, VARIATION VHHD-5.
0.15
0.10
0.10
w
PD, Rev 4.3, October 2008
88
Page 89
Production Data WM8758B
IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Any use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or
services might be or are used. Any provision or publication of any third party’s products or services does not constitute
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document
belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is
not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any
reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: [email protected]
w
PD, Rev 4.3, October 2008
89
Page 90
Loading...