wolfson WM8746 User Manual

w

24-bit, 192kHz 6-Channel DAC with Volume Control

WM8746

DESCRIPTION

WM8746 is a high performance 6-channel DAC designed for audio applications such as DVD, home theatre systems, and digital TV. The WM8746 supports data input word lengths from 16 to 32-bits and sampling rates up to 192kHz. The WM8746 can convert up to 6 channels at sample rates from 8 to 192kHz. Additionally WM8746 supports 2 channels at 192kHz and 4 channels at 96kHz simultaneously.

The WM8746 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and 6 DACs in a small 28-pin SSOP package. The WM8746 also includes a digitally controllable mute and attenuator function on each channel.

The WM8746 supports a variety of connection schemes for audio DAC control. The serial control interface provides access to a wide range of features including on-chip mute, attenuation and phase reversal. A hardware controllable interface is also available. It is pin-compatible with the WM8736, (apart from RSTB pin which is typically unused).

The WM8746 is an ideal device to interface to AC-3, DTS, and MPEG audio decoders for surround sound applications, or for use in “universal” high definition audio players supporting DVD-A formats.

BLOCK DIAGRAM

ML/I2S MC/IWL

BCP

IWL[1:0]

LRP

FMT[1:0]

MUTE

MD/DM MODE MUTESCKI

CONTROL

PL[3:0]

INTERFACE

UPDATE

LxA[23:0]

RxA[23:0]

ATC

PDWN

FEATURES

• 6-Channel DAC

• Audio Performance

− 106dB SNR (‘A’ weighted @ 48kHz) DAC

− -95dB THD

• DAC Sampling Frequency: 8kHz – 192kHz

• 3-Wire Serial Control Interface

• Programmable Audio Data Interface Modes

2

S, Left, Right Justified or DSP

− I

− 16/20/24/32 bit Word Lengths

• Independent Digital Volume Control on Each Channel with

127.5dB Range in 0.5dB Steps

• 3.0V – 5.5V Supply Operation

• 28-Pin SSOP Package

• Exceeds Dolby Class A Performance Requirements

• Pin Compatible with W M8736

APPLICATIONS

• DVD and DVD ‘Universal’ Players

• Home theatre systems

• Digital broadcast receivers

WM8746

DEEMPH

PDWN

L0A[7:0]

BCKIN

LRCIN

LRCIN2

DIN0

DIN1

DIN2

AUDIO

INTERFACE

DAC CHANNEL CONTROL

R0A[7:0]

L1A[7:0]

R1A[7:0]

L2A[7:0]

R2A[7:0]

Digital

Filter

Digital

Filter

Digital

Filter

WOLFSON MICROELECTRONICS plc

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Sigma

Delta

Modulator

Sigma

Delta

Modulator

Sigma

Delta

Modulator

AVDD2AVDD1AGND2AGND1DVDD DGND

Stereo

DAC

Stereo

DAC

Stereo

DAC

CAP

OUT0L GR0 OUT0R

OUT1L GR1 OUT1R

OUT2L GR2 OUT2R

Production Data, March 2006, Rev 4.0

Copyright 2006 Wolfson Microelectronics plc

WM8746 Production Data

PIN CONFIGURATION

ORDERING INFORMATION

DEVICE

WM8746SEDS -25 to +85oC 28-lead SSOP

WM8746SEDS/R -25 to +85oC 28-lead SSOP

Note:

Reel quantity = 2,000

TEMPERATURE

RANGE

PACKAGE

(Pb-free)

(Pb-free, tape and reel)

MOISTURE

SENSITIVITY LEVEL

MSL1

PEAK SOLDERING

TEMPERATURE

260°C

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WM8746 Production Data

PIN DESCRIPTION

PIN NAME TYPE DESCRIPTION

1 DVDD Supply

2 SCKI Digital input

3 BCKIN Digital input

4 LRCIN Digital input

5 DIN0 Digital input

6 DIN1 Digital input

7 DIN2 Digital input

8 MODE Digital input

Internal pull-up

9 MUTE Digital bidirectional

10 LRCIN2 Digital input

Internal pull-down

11 DGND Supply

12 ML/I2S Digital input

Internal pull-up

13 MC/IWL Digital input

Internal pull-up

14 MD/DM Digital input

15 AVDD2 Supply

16 CAP Analogue output

17 OUT2L Analogue output

18 GR2 Analogue input

19 OUT2R Analogue output

20 AGND1 Supply

21 OUT1L Analogue output

22 GR1 Analogue input

23 OUT1R Analogue output

24 AGND2 Supply

25 OUT0L Analogue output

26 GR0 Analogue input

27 OUT0R Analogue output

28 AVDD1 Supply

Note:

1. Digital input pins have Schmitt trigger input buffers

Digital Positive Supply.

System Clock Input

Audio Data Bit Clock Input.

DAC Sample Rate Clock Input

Channel 0 Serial Audio Data Input.

Channel 1 Serial Audio Data Input.

Channel 2 Serial Audio Data Input.

Control Method Selection Pin.

Low = Software Mode

High = Hardware Control Mode

Mute Control Pin in PCM Mode.

Input Output (Automute Enabled)

Low: Not Mute Low: Mute Off

High: Mute High: Mute On (Zero Flag)

Z: Automute

nd

2

LRCIN for use in mixed 192kHz/96kHz operation (bit 2SPD = ‘hi’)

Digital GND

Software mode: 3-Wire Serial Control Latch

Hardware Mode: Input Format Selection:

Software Mode: 3-Wire Serial Control Clock Input

Hardware mode: Input Word Length Selection:

Software mode: 3-Wire Serial Control Data Input

Hardware mode: De-emphasis selection

Analogue Positive DAC Reference

Analogue Internal Mid-Rail Reference De-Coupling Point

Left Channel 2 Output.

Channel 2 Negative Reference.

Right Channel 2 Output.

Analogue GND

Left Channel 1 Output.

Channel 1 Negative Reference.

Right Channel 1 Output.

Analogue GND

Left Channel 0 Output.

Channel 0 Negative Reference.

Right Channel 0 Output.

Analogue VDD

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WM8746 Production Data

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

CONDITION

Digital supply voltage

Analogue supply voltage

Voltage range digital inputs

Voltage range analogue inputs

Master Clock Frequency 37MHz

Operating temperature range, TA

Storage temperature after soldering

MIN MAX

-0.3V +7V

DGND -0.3V DVDD +0.3V

AGND -0.3V AVDD +0.3V

-25°C +85°C

-65°C +150°C

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WM8746 Production Data

DC ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital supply range

Analogue supply range

Ground

Difference DGND to AGND

Analogue supply current

Digital supply current

Analogue supply current

Digital supply current

Analogue supply current

Digital supply current

Note:

1. The digital supply voltages must not exceed the analogue supply voltages.

AC ELECTRICAL CHARACTERISTICS

Test Conditions

AVDD = DVDD = 5V, AGND = 0V = DGND = 0V, T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital Logic Levels (TTL Levels)

Input LOW level VIL

Input HIGH level VIH

Output LOW VOL

Output HIGH VOH

Analogue Reference Levels

Reference voltage V

Potential divider resistance R

DAC Output (Load = 10kΩ 50pF)

0dBFs Full scale output voltage

SNR (Note 1,2,3)

THD (Note 1,2,3)

THD+N (Dynamic range, Note 2)

DAC channel separation

DVDD 3.0 5.5 V

AVDD1

AVDD2 3.0 5.5 V

,

AGND, GR0,

GR1, DGND 0 V

-0.3 0 +0.3 V

AVDD = 5V 58 mA

DVDD = 5V 22 mA

AVDD = 3.3V 57 mA

DVDD = 3.3V 11 mA

Power down, stop clock 0.4 mA

Power down, stop clock 0.09 mA

= +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.

A

0.8 V

2.0 V

I

= 2mA 0.4 V

OL

I

= 2mA 2.4 V

OH

CAP

AVDD=DVDD=3.3V

Non ‘A’ weighted @ fs

AVDD=DVDD=5V

1kHz, 0dBFs -95 dB

1kHz, -60dBFs -100 -106 dB

100 dB

(AVDD2-

25k Ω

At DAC outputs 1.1 x

A-weighted,

@ fs = 48kHz

A-weighted

@ fs = 96kHz

A-weighted

@ fs = 192kHz

A-weighted,

@ fs = 48kHz

A-weighted

@ fs = 96kHz

= 48kHz

100 106 dB

105 dB

103 dB

GR2)/2

AVDD1/5

V

rms

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WM8746 Production Data

Test Conditions

AVDD = DVDD = 5V, AGND = 0V = DGND = 0V, T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Analogue Output Levels

Output level

Gain mismatch channel-to-channel

Minimum resistance load

Maximum capacitance load

Output d.c. level

Power On Reset (POR)

POR threshold

Notes:

1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth.

2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.

3. CAP decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).

±1 %FSR

5V or 3.3V 100 pF

(AVDD1-

2.0 V

= +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.

A

Load = 10kΩ,

0 dBFS,

(AVDD=5.0V)

Load = 10kΩ,

0 dBFS,

(AVDD=3.3V)

To midrail or a.c.

coupled

To midrail or a.c.

coupled

(AVDD = 3.3V)

1.1 V

0.73

1 kΩ

AGND)/2

rms

V

TERMINOLOGY

1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).

2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).

3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.

4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).

5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.

6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.

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WM8746 Production Data

MASTER CLOCK TIMING

t

SCKIL

SCKI

t

SCKIH

t

SCKIY

Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD = DVDD = 5V, AGND = GR = DGND = 0V, T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

System Clock Timing Information

SCKI System clock pulse width high t

SCKI System clock pulse width low

SCKI System clock cycle time

SCKI Duty cycle

SCKIH

t

SCKIL

t

SCKIY

40:60 60:40

Table 1 Master Clock Timing Requirements

DIGITAL AUDIO INTERFACE TIMING

= +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.

A

13 ns

26 ns

t

BCH

t

BCL

BCLK

t

BCY

DACLRC

t

DS

t

LRH

t

LRSU

DIN0/1/2

t

DH

Figure 2 PCM Digital Audio Data Timing

Test Conditions

AVDD = DVDD = 5V, AGND = GR = DGND = 0V, T

= +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Audio Data Input Timing Information

BCKIN cycle time

BCKIN pulse width high

BCKIN pulse width low

LRCIN set-up time to

t

BCY

t

BCH

t

BCL

t

LB

40 ns

16 ns

8 ns

BCKIN rising edge

LRCIN hold time from

t

BL

8 ns

BCKIN rising edge

DIN0/1/2 set-up time to

t

DS

8 ns

BCKIN rising edge

DIN0/1/2 hold time from

t

DH

8 ns

BCKIN rising edge

Table 2 PCM Digital Audio Timing

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WM8746 Production Data

DIGITAL CONTROL INTERFACE

ML/I2S

t

MCY

t

MCH

t

MCL

MC/IWL

MD/DM

DSU

t

DHO

t

Figure 3 Control Interface Input Timing: 3-Wire Serial Control Mode

Test Conditions

AVDD = DVDD = 5V, AGND = GR = DGND = 0V, T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Program Register Input Information

MC/IWL rising edge to ML/I2S

t

20 ns

SCS

rising edge

MC/IWL pulse cycle time

MC/IWL pulse width low

MC/IWL pulse width high

MD/DM to MC/IWL set-up time

MC/IWL to MD/DM hold time

ML/I2S pulse width low

ML/I2S pulse width high

ML/I2S rising to MC/IW L rising

t

MCY

t

MCL

t

30 ns

MCH

t

20 ns

DSU

t

20 ns

DHO

t

20 ns

MLL

t

20 ns

MLH

t

20 ns

CSS

Table 3 Control Interface Input Timing Information: 3-Wire Serial Control Mode

= +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.

A

80 ns

30 ns

LSB

t

SCS

MLL

t

CSS

t

MLH

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WM8746 Production Data

DEVICE DESCRIPTION

INTRODUCTION

WM8746 is a complete 6-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC and output smoothing filters.

The device is implemented as three separate stereo DACs in a single package and controlled by a single interface. Each DAC has its own data input DIN0/1/2, and LRCIN, BCKIN and SCKI are shared between them. An additional LRCIN2 input is provided to allow for the front channels in a surround system to be run at higher sample rate than the other 4 channels (ie. 192kHz for front channels and 96kHz). In this mode the same SCKI is used for all channels, the front channels being run at twice the over-sampling rate of the other channels.

Control of internal functionality of the device is by either hardware control (pin programmed) or software control (3-wire serial control interface). The MODE pin selects between hardware and software control. In software control mode, an SPI type interface is used. This interface may be asynchronous to the audio data interface. Control data will be re-synchronised to the audio processing internally.

Operation using a system clock of 256fs, 384fs, 512fs or 768fs is provided, selection between clock rates being automatically detected. Sample rates (fs) from less than 8kHz to 96kHz are allowed, provided the appropriate system clock is input. Support is also provided for up to 192kHz using a system clock of 128fs or 192fs.

The audio data interface supports right, left and I serial port interface. W hen in hardware mode, the three serial interface pins become control pins to allow selection of input data format type (I and de-emphasis functions.

2

S interface formats along with a highly flexible DSP

2

S or right justified), input word length (16, 20, 24, or 32-bit)

AUDIO DATA SAMPLING RATES

In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. The external master system clock can be applied directly through the SCKI input pin with no software configuration necessary. Note that on the WM8746, SCKI is used to derive clocks for the DAC path. The DAC path consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the DAC.

The system clock for WM8746 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The system clock is used to operate the digital filters and the noise shaping circuits.

The WM8746 has a system clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 system clocks). If greater than 32 clocks error, the interface defaults to 768fs and maintains the output level at the last sample. The system clock should be synchronised with LRCIN, although the WM8746 is tolerant of phase differences or jitter on this clock. Table 4 shows the typical system clock frequency inputs for the WM8746.

SAMPLING

RATE (FS)

(LRCIN)

32kHz 4.096 6.144 8.192 12.288 16.384 24.576

44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688

48kHz 6.144 9.216 12.288 18.432 24.576 36.864

96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable

192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable

Table 4 System Clock Frequencies Versus Sampling Rate

SYSTEM CLOCK FREQUENCY (MHZ)

128fs 192fs 256fs 384fs 512fs 768fs

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WM8746 Production Data

DIGITAL AUDIO INTERFACE

Audio data is applied to the internal DAC filters via the Digital Audio Interface. Five popular interface formats are supported:

• Left Justified mode

• Right Justified mode

2

S mode

• I

• DSP Mode A

• DSP Mode B

All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, except right justified that does not support 32 bit data. DIN0/1/2 and LRCIN are sampled on the rising, or falling edge of BCKIN.

In left justified, right justified and I inputs. Audio Data for each stereo channel is time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used as a timing reference to indicate the beginning or end of the data words.

In left justified, right justified and I twice the selected word length. LRCIN must be high for at least the word length number of BCKINs and low for at least the same. Any mark to space ratio on LRCIN is acceptable provided the above requirements are met. The WM8746 will automatically detect when data with a LRCIN period of exactly 32 is sent, and select 16 bit mode - overriding any previously programmed word length. Word length will revert to the previously programmed value if a LRCIN period other than 32 is detected.

2

S modes, the digital audio interface receives data on the DIN0/1/2

2

S modes, the minimum number of BCKINs per LRCIN period is

In DSP Mode A or B, all 6 channels are time multiplexed onto DIN0. LRCIN is used as a frame sync signal to identify the MSB of the first word. The minimum number of BCKINs per LRCIN period is 6 times the selected word length. Any mark to space ratio is acceptable on LRCIN provided the rising edge is correctly positioned. (see Figure 7, Figure 8)

LEFT JUSTIFIED MODE

In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN transition. LRCIN is high during the left samples and low during the right samples.

1/fs

LEFT CHANNEL RIGHT CHANNEL

LRCIN

BCKIN

DIN0/1/2

Figure 4 Left Justified Mode Timing Diagram

n-2 n-1

n321

LSBMSB

n-2 n-1

n321

LSBMSB

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WM8746 Production Data

RIGHT JUSTIFIED MODE

In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN transition. LRCIN is high during the left samples and low during the right samples.

1/fs

LEFT CHANNEL RIGHT CHANNE L

LRCIN

BCKIN

DIN0/1/2

n-2 n-1

n321

LSBMSB

n-2 n-1

n321

LSBMSB

Figure 5 Right Justified Mode Timing Diagram

I2S MODE

In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN transition. LRCIN is low during the left samples and high during the right samples.

1/fs

LEFT CHANNEL RIGHT CHANNE L

LRCIN

BCKIN

MSB

1 BCKIN

n-2 n-1

n321

LSB

DIN0/1/2

Figure 6 I

1 BCKIN

MSB

2

S Mode Timing Diagram

n-2 n-1

n321

LSB

DSP MODE A

In DSP mode A, the first bit is sampled on the BCKIN edge following the one which detects a low to high transition on LRCIN.

1 BCKIN

1/fs

1 BCKIN

w

LRCIN

BCKIN

CHANNEL 0

LEFT

DIN0

Input Word Length (IWL)

n21

n-1

LSBMSB

Figure 7 DSP Mode A Timing Diagram

CHANNEL 0

RIGHT

CHANNEL 1

LEFT

n21

n-1

21

CHANNEL 2

RIGHT

n-1

NO VALID DATA

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WM8746 Production Data

DSP MODE B

In DSP mode B, the first bit is sampled on the BCKIN edge which detects a low to high transition on LRCIN.

1/fs

LRCIN

BCKIN

CHANNEL 0

LEFT

DIN0

Input Word Length (IWL)

n-1

LSBMSB

Figure 8 DSP Mode B Timing Diagram

In both DSP modes, DAC0 left is always sent first, followed immediately by data words for the other 5 channels. No BCKIN edges are allowed between the data words. The word order is DAC0 left, DAC0 right, DAC1 left, DAC1 right, DAC2 left, DAC2 right.

SPLIT RATE MODE

The WM8746 can be used with differing sample rates on the front and rear channels. This allows extremely high quality audio to be played on the front two channels whilst the other channels use normal high quality data streams.

CHANNEL 0

RIGHT

n21

CHANNEL 1

LEFT

n21

n-1

21

CHANNEL 2

RIGHT

n-1

NO VALID DATA

n

1

This mode will only work with a front data rate of 192kHz and a rear rate of 96kHz but can be used with all the normal data formats except the two DSP modes and with the system at either 128fs or 192fs see Table 4.

When running in split rate mode all the channels are clocked in using a common BCKIN; the front channels using LRCIN and all the other channels using LRCIN2 see Figure 9.

2/fs

LRCIN

BCKIN

DIN0

LRCIN2

DIN1/2

LEFT CHANNEL

n21n21n21n21

MSB LSB

MSB LSB LSBMSB

LSB

LEFT CHANNEL RIGHT CHANNEL

n21 n21

RIGHT CHANNEL

MSB

LSB

LEFT CHANNEL RIGHT CHANNEL

MSB LSB MSB

Figure 9 Split Rate Audio Mode Timing Diagram

Notes:

2

1. Figure 9 shows the timing for left justified however this is similar for right justified and I

S.

2. The edges of LRCIN and LRCIN2 must be coincidental.

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WM8746 Production Data

MODES OF OPERATION

Control of the various modes of operation for the WM8746 is either by software control over the serial interface ,or by hard-wired pin control. Selection of software or hardware mode is via the MODE pin. The following functions may be controlled either via the serial control interface or by hard wiring of the appropriate pins.

FUNCTION

Input audio data format Right justified

Input word length 16

De-emphasis selection On

Mute On

Input LRCIN polarity Normal

Volume control Lch, Rch

Infinite zero detect On

Power down Chip on

DAC output control See Table 6

OPTIONS

Left justified

2

S format

I

DSP formats

20

24

32

Off

Inverted

individually

Lch, Rch common

Off

Chip off

for all options

SOFTWARE CONTROL

DEFAULT VALUE

PIN 8: MODE = 0

FMT = 00 (default)

FMT = 01

FMT = 10

FMT = 11

IWL[1:0] = 00

IWL[1:0] = 01

IWL[1:0] = 10 (default)

IWL[1:0] = 11

DEEMPH = 1

DEEMPH = 0 (Default)

MUTE = 1

MUTE = 0 (default)

LRP = 0 (default)

LRP = 1

ATC = 0; 0dB (default)

ATC = 1

IZD = 1

IZD = 0 (default)

PWDN = 0 (default)

PWDN = 1

Default is PL[3:0] = 1001, stereo mode Not available in hardware mode

Pin 12, 13: ML/I2S, MC/IWL = 00, 01 or 10

Automute function controlled from MUTE pin

HARDWARE CONTROL

BEHAVIOUR

PIN 8: MODE = 1

Not available in hardware mode

Pin 12, 13: ML/I2S, MC/IWL = 11

Not available in hardware mode

Pin 12, 13: ML/I2S, MC/IWL = 00 (RJ)

Pin 12, 13: ML/I2S, MC/IWL = 01 (RJ)

Pin 12, 13: ML/I2S, MC/IWL = 10 (RJ)

Pin 12, 13: ML/I2S, MC/IWL = 11 (I

Pin 14: MD/DM = 1

Pin 14: MD/DM = 0

Pin 9: MUTE = 1

Pin 9: MUTE = 0

Not available in hardware mode,

default value set

Not available in hardware mode,

gain defaults to 0dB

low = never mute

floating = automute enable

high = mute

Run SCKI

Stop SCKI

2

S)

Table 5 Control Function Summary

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WM8746 Production Data

SOFTWARE CONTROL MODES

DIGITAL AUDIO INTERFACE CONTROL REGISTERS

Interface format is selected via the FMT[1:0] register bits:

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0000011

Interface Control

In left justified, right justified or I2S modes, the LRP register bit controls the polarity of LRCIN. If this bit is set high, the expected polarity of LRCIN will be the opposite of that shown Figure 4, Figure 5 and Figure 6. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced.

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0000011

Interface Control

In DSP modes, the LRCIN register bit is used to select between early and late modes:

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0000011

Interface Control

By default, LRCIN and DIN0/1/2 are sampled on the rising edge of BCKIN and should ideally change on the falling edge. Data sources which change LRCIN and DIN0/1/2 on the rising edge of BCKIN can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN to the inverse of that shown in Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8.

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0000011

Interface Control

The IWL[1:0] bits are used to control the input word length.

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0000011

Interface Control

Note: If 32-bit mode is selected in right justified mode, the WM8746 defaults to 24 bits.

1:0 FMT[1:0] 00 Interface format Select

00 : right justified mode

01: left justified mode

2

10: I

S mode

11: DSP mode A or B

2 LRP 0 LRCIN Polarity

0 : normal LRCIN polarity

1: inverted LRCIN polarity

2 LRP 0 DSP Format

0: Mode A

1: Mode B

3 BCP 0 BCKIN Polarity

0 : normal BCKIN polarity

1: inverted BCKIN polarity

5:4 IWL[1:0] 10 Input Word Length

00 : 16 bit data

01: 20 bit data

10: 24 bit data

11: 32 bit data

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In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8746 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.

The PHASE bits control the orientation of the data output of the three stereo channels. By default all the channels are non-inverting.

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0000011

Interface Control

8:6 PHASE 000 Output phase direction

1 in bit 6 reverses OUT0L/R.

1 in bit 7 reverses OUT1L/R.

1 in bit 8 reverses OUT2L/R.

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MUTE MODES

Setting the MUTE register bit will apply a 'soft' mute to the input of the digital filters:

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0000010

DAC Channel Control

1.5

1

0.5

0

-0.5

-1

-1.5

-2

0 MUTE 0 Soft Mute select

0 : Normal Operation

1: Soft mute all channels

-2.5

0 0.001 0.002 0.003 0.004 0.005 0.006

Time(s)

Figure 10 Application and Release of Soft Mute

Figure 10 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards V with a time constant of approximately 64 input samples. If MUTE is applied for 1024 or more input samples, the outputs will be connected directly to V (infinite zero detect) bit. When MUTE is de-asserted, the output will restart almost immediately from the current input sample.

Note that all other means of muting the DAC channels: setting the PL[3:0] bits to 0, setting the PWDN bit or setting attenuation to 0 will cause much more abrupt muting of the output.

Setting the IZD register bit will enable the infinite zero detect feature:

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0000010

DAC Channel Control

With IZD=1, applying MUTE for 1024 consecutive input samples will cause all outputs to be connected directly to V all 6 channels, and IZD=0. It will be removed as soon as any channel receives a non-zero input.

The MUTE pin can be used as an input. In this case it performs the same function as the MUTE register bit. Driving the MUTE pin high will apply a 'soft' mute. Driving it low again, will remove the MUTE immediately. Note that this hardware mute feature doesn't require the MODE pin to be set high.

4 IZD 0 Internal Analogue Mute Disable

. This also happens if 2048 consecutive zero input samples are applied to

CAP

- this feature can be disabled using the IZD

CAP

0 : Disable Analogue Mute

1: Enable Analogue Mute

CAP

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MUTE PIN DESCRIPTION

0

1

Floating

A diagram showing how the various MUTE modes interact is shown below in Figure 11.

IZD (Register Bit)

AUTOMUTED (Internal

MUTE (Register Bit)

Figure 11 Selection Logic for MUTE Modes

Normal Operation

Mute all DAC channels

MUTE becomes an output to indicate when IZD occurs.

H = IZD detected (MUTE enabled)

L = IZD not detected (MUTE disabled)

Signal)

ΩΩΩΩ

10k

MUTE

SOFTMUTE (Internal Signal)

The MUTE pin behaves as a bi-directional function, that is, as an input to select MUTE or NOTMUTE, or as an output indication of automute operation. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter.

The automute function detects a series of zero value audio samples of 1024 samples long being applied to all 6 channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR’ed through a 10kohm resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert MUTE.

If MUTE is tied low, AUTOMUTED is overridden and will not mute. If MUTE is driven from a source follower, or diode, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external mute circuits. The automute signal is AND’ed with IZD, this qualified mute signal then being OR’ed into the SOFTMUTE control. Therefore, in software mode, automute operation may be controlled with the IZD control bit.

DE-EMPHASIS MODE

Setting the DEEMPH register bit puts all the digital filters into de-emphasis mode:

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0000010

DAC Channel Control

Refer to Figure 18 - Figure 23 for details of the De-Emphasis filtering effects at different sample rates.

In hardware mode (MODE=1) driving the MD/DM pin high has the same effect as setting the DEEMPH bit:

MODE PIN MD/DM PIN DESCRIPTION

0 ignored

1 0

1 1

1 DEEMPH 0 De-emphasis mode select:

0 : Normal Mode

1: De-emphasis Mode

De-Emphasis controlled from DEEMPH register bit

Normal Mode

De-Emphasis Mode

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POWERDOWN MODE

Setting the PWDN register bit immediately connects all outputs to V mode. All trace of the previous input samples is removed, but all control register settings are preserved. When PWDN is cleared again the first 16 input samples will be ignored as the FIR will repeat it's power-on initialisation sequence.

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0000010

DAC Channel Control

2 PWDN 0 Power Down Mode Select:

0 : Normal Mode

1: Power Down Mode

ATTENUATOR CONTROL MODE

Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channels for all three pairs of DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect.

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0000010

DAC Channel Control

3 ATC 0 Attenuator Control Mode:

0 : Right channels use Right

1: Right Channels use Left

DAC OUTPUT CONTROL

The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs:

and selects a low power

CAP

attenuations

Attenuations

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0000010

DAC Control

Table 6 Input to Output Control

8:5 PL[3:0] 1001

PL[3:0] Left

Output

0000 Mute Mute

0001 Left Mute

0010 Right Mute

0011 (L+R)/2 Mute

0100 Mute Left

0101 Left Left

0110 Right Left

0111 (L+R)/2 Left

1000 Mute Right

1001 Left Right

1010 Right Right

1011 (L+R)/2 Right

1100 Mute (L+R)/2

1101 Left (L+R)/2

1110 Right (L+R)/2

1111 (L+R)/2 (L+R)/2

Right Output

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ATTENUATION CONTROL

Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation is 0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 8 Attenuation control bits. All attenuation registers are double latched allowing new values to be pre-latched to several channels before being updated synchronously. Setting the UPDATE bit on any attenuation write will cause all pre-latched values to be immediately applied to the DAC channels. A master attenuation register is also included, allowing all attenuations to be set to the same value in a single write.

REGISTER

ADDRESS

0000000

Attenuation DACL0

0000001

Attenuation DACR0

0000100

Attenuation DACL1

0000101

Attenuation DACR1

Attenuation DACL2

0000111

Attenuation DACR2

Master

Attenuation

(all channels)

Table 7 Attenuation Register Map

BIT LABEL DEFAULT DESCRIPTION

7:0

L0A[7:0] 11111111

8

UPDATE Not latched

7:0

R0A[7:0] 11111111

8

UPDATE Not latched

7:0

L1A[7:0] 11111111

8

UPDATE Not latched

7:0

R1A[7:0] 11111111

8

UPDATE Not latched

7:0

L2A[7:0] 11111111

8

UPDATE Not latched

7:0

R2A[7:0] 11111111

8

UPDATE Not latched

7:0

MASTA[7:0] 11111111

8

UPDATE Not latched

Attenuation data for DACL0 in 0.5dB steps, see Table 8.

(0dB)

Controls simultaneous update of all Attenuation Latches

0: Store DACL0 in intermediate latch (no change to output)

1: Store DACL0 and update attenuation on all channels.

Attenuation data for DACR0 in 0.5dB steps, see Table 8.

(0dB)

Controls simultaneous update of all Attenuation Latches

0: Store DACR0 in intermediate latch (no change to output)

1: Store DACR0 and update attenuation on all channels.

Attenuation data for DACL1 in 0.5dB steps, see Table 8.

(0dB)

Controls simultaneous update of all Attenuation Latches

0: Store DACL1 in intermediate latch (no change to output)

1: Store DACL1 and update attenuation on all channels.

Attenuation data for DACR1 in 0.5dB steps, see Table 8.

(0dB)

Controls simultaneous update of all Attenuation Latches

0: Store DACR1 in intermediate latch (no change to output)

1: Store DACR1 and update attenuation on all channels.

Attenuation data for DACL2 in 0.5dB steps, see Table 8. 0000110

(0dB)

Controls simultaneous update of all Attenuation Latches

0: Store DACL2 in intermediate latch (no change to output)

1: Store DACL2 and update attenuation on all channels.

Attenuation data for DACR2 in 0.5dB steps, see Table 8.

(0dB)

Controls simultaneous update of all Attenuation Latches

0: Store DACR2 in intermediate latch (no change to output)

1: Store DACR2 and update attenuation on all channels.

Attenuation data for all channels in 0.5dB steps, see Table 8. 0001000

(0dB)

Controls simultaneous update of all Attenuation Latches

0: Store MASTA[7:0] in all intermediate latches (no change to

output)

1: Store MASTA[7:0] and update attenuation on all channels.

Note:

The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the relevant DAC. If UPDATE=1, all pre-latched values will be applied from the next input sample. W riting to MASTA[7:0] overwrites any values previously sent to L0A[7:0], L1A[7:0], L2A[7:0], R0A[7:0], R1A[7:0], R2A[7:0].

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DAC OUTPUT ATTENUATION

Register bits [7:0] of L0A and R0A control the left and right channel attenuation of DAC 0. Register bits [7:0] of L1A and R1A control the left and right channel attenuation of DAC 1. Register bits [7:0] of L2A and R2B control the left and right channel attenuation of DAC 2. Register bits [7:0] of MASTA are a register that can be used to control attenuation of all channels.

Table 8 shows how the attenuation levels are selected from the 8-bit words.

XA[7:0] ATTENUATION LEVEL

00(hex) -∞dB (mute)

01(hex) -127.5dB

: :

FE(hex) -0.5dB

FF(hex) 0dB

Table 8 Attenuation Control Levels

EXTENDED INTERFACE CONTROL

It is possible to run the W M8746 channels at different rates with the front two channels running at twice the rate of the rear four channels. In this mode which is enabled by bit 0 of register 9, the interface runs at the faster data rate but pin 10 (LRCIN2) acts as the framing LRCIN for the rear channels see Figure 9.

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0001001

Split rate mode

When the WM8746 receives updates to the volume levels it will, by default, wait for the signal to pass through the V function ensures that minimal distortion is seen on the output when the volume is changed and is applied separately to each channel.

voltage level before applying the change to the output. This zero cross detect

CAP

0

2SPD 0

Activates the split rate mode

0: Normal operation

1: Split rate operation

REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0001001

Zero crossing detect

1

ZCD 0

Controls the ZCD

0: Enabled

1: Disabled

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HARDWARE CONTROL MODES

When the MODE pin is held high the following hardware modes of operation are available.

MUTE AND AUTOMUTE OPERATION

Pin 9 (MUTE) controls selection of MUTE directly, and can be used to enable and disable the automute function, or as an output of the automuted signal.

AUTOMUTED (Internal

Figure 12 Mute Circuit Operation

The MUTE pin behaves as a bi-directional function, that is, as an input to select MUTE or NOTMUTE, or as an output indication of automute operation. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter.

The automute function detects a series of zero value audio samples of 1024 samples long being applied to all 6 channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR’ed through a 10kohm resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert MUTE.

If MUTE is tied low, AUTOMUTED is overridden and will not mute. If MUTE is driven from a source follower, or diode, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external mute circuits.

Signal)

MUTE

10k

ΩΩΩΩ

SOFTMUTE (Internal Signal)

ML/I2S AND MC/IWL INPUT FORMAT SELECTION

In hardware mode, pins 12 and 13 become input controls for selection of input data format type and input data word length, see Table 5. I enough bit clocks are sent.

ML/I2S MC/IWL INPUT DATA MODE

0 0 16-bit right justified

0 1 20-bit right justified

1 0 24-bit right justified

1 1 I2S mode

Table 9 Control of Input Data Format Type and Input Data Word Length

2

S mode is designed to support any word length provided

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MD/DM DE-EMPHASIS

In hardware mode, pin 14 becomes an input control for selection of de-emphasis filtering to be applied. See Table 5.

MD/DM DE-EMPHASIS MODE

0 De-emphasis off

1 De-emphasis on

Table 10 De-emphasis Control

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SOFTWARE CONTROL INTERFACE

The software control interface uses a 3-wire serial control interface. Selection of interface format is achieved by setting the state of the MODE pin.

MODE INTERFACE FORMAT

0 Software Control Mode

1 Hardware Control Mode

Table 11 Control Interface Mode Selection

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

The WM8746 can be controlled using a 3-wire serial interface. MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is use to latch in the program data. The 3wire interface protocol is shown in Figure 13.

ML/I2S

MC/IWL

MD/DM

Figure 13 3-wire Serial Interface

Notes:

1. A[6:0] are Control Address Bits

2. D[8:0] are Control Data Bits

D6D7D8A0A1A2A3A4 D1D2D3D4D5 D0A5A6

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REGISTER MAP

The complete register map is shown below. The detailed description can be found in the relevant text of the device description. There are 9 registers with 9 bits per register. These can be controlled using the Control Interface.

A6 A5 A4 A3 A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0

M0

0 0 0 0 0 0 0 UPDATE L 0A7 L0A 6 L0A 5 L0A 4 L0A 3 L0A 2 L0A 1 L0A 0

M1

0 0 0 0 0 0 1 UPDATE R0A7 R0A 6 R0A 5 R0A 4 R0A 3 R0A 2 R0A 1 R0A 0

M2

0 0 0 0 0 1 0 PL3 PL2 PL1 PL0 IZD ATC PDWN DEEMPH MUTE

M3

0 0 0 0 0 1 1 REV2 REV1 REV0 IWL1 IW L0 BCP LRP FMT1 FMT0

M4

0 0 0 0 1 0 0 UPDATE L 1A7 L1A 6 L1A 5 L1A 4 L1A 3 L1A 2 L1A 1 L1A 0

M5

0 0 0 0 1 0 1 UPDATE R1A7 R1A 6 R1A 5 R1A 4 R1A 3 R1A 2 R1A 1 R1A 0

M6

0 0 0 0 1 1 0 UPDATE L 2A7 L2A 6 L2A 5 L2A 4 L2A 3 L2A 2 L2A 1 L2A 0

M7

0 0 0 0 1 1 1 UPDATE R2A7 R2A 6 R2A 5 R2A 4 R2A 3 R2A 2 R2A 1 R2A 0

M8

0 0 0 1 0 0 0 UPDATE MASTA7

M9

0 0 0 1 0 0 1 0 0 0 0 0 0 0 ZCD 2SPD

Table 12 Register Map

REGISTER

ADDRESS

Attenuation DACL0

0000001

Attenuation DACR0

BIT LABEL DEFAULT DESCRIPTION

7:0

8

7:0

8

L0A[7:0] 11111111

(0dB)

UPDATE Not latched

R0A[7:0] 11111111

(0dB)

UPDATE Not latched

Attenuation level of left channel DACL0 in 0.5dB steps, see Table 8. 0000000

Controls simultaneous update of all Attenuation Latches

0: Store DACL0 in intermediate latch (no change to output)

1: Store DACL0 and update attenuation on all channels.

Attenuation level of left channel DACR0 in 0.5dB steps, see Table 8.

Controls simultaneous update of all Attenuation Latches

0: Store DACR0 in intermediate latch (no change to output)

1: Store DACR0 and update attenuation on all channels.

ASTA 6 MASTA 5 MAST A 4 MAST A 3 MAST A 2 MASTA 1 MAST A 0

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REGISTER

ADDRESS

0000010

DAC Control

0000011

Interface Control

BIT LABEL DEFAULT DESCRIPTION

0

MUTE 0

1

DEEMPH 0

2

PWDN 0

3

4 IZD 0 Infinite zero detection circuit control and automute control

8:5 PL[3:0] 1001

1:0 FMT[1:0] 00 Interface format select

3 BCP 0 BCKIN Polarity

5:4 WL[1:0] 10 Input W ord Length

8:6 PHASE 000 Controls the output phase of the three stereo channels

ATC 0

Left and Right DACs soft mute control

0: No Mute

1: Mute

De-emphasis Control

0: Normal Response (see Figure 14 - Figure 17)

1: De-emphasis Response (see Figure 18 - Figure 23)

Left and Right DACs Power-down Control

0: All DACs running, output is active

1: All DACs in power saving mode, output muted

Attenuator Control

0: All DACs use attenuations as programmed.

1: Right chan. DACs use corresponding left DAC attenuations

0: Infinite zero detect disabled

1: Infinite zero detect enabled

DAC Output Control

PL[3:0] Left

0000 Mute Mute 1000 Mute Right

0001 Left Mute 1001 Left Right

0010 Right Mute 1010 Right Right

0011 (L+R)/2 Mute 1011 (L+R)/2 Right

0100 Mute Left 1100 Mute (L+R)/2

0101 Left Left 1101 Left (L+R)/2

0110 Right Left 1110 Right (L+R)/2

0111 (L+R)/2 Left 1111 (L+R)/2 (L+R)/2

LRCIN Polarity or LRCIN Phase 2 LRP 0

Left Justified / Right Justified / I

0: Standard LRCIN Polarity

1: Inverted LRCIN Polarity

Output

00: right justified mode

01: left justified mode

2

10: I

S mode

11: DSP Mode A or B

0: Normal (DIN[2:0] and LRCIN sampled on rising edge)

1: Inverted (DIN[2:0] and LRCIN sampled on falling edge)

00: 16-bit Mode

01: 20-bit Mode

10: 24-bit Mode

11: 32-bit Mode (not supported in right justified mode)

Bit 6 reverses the phase of data output on OUT0L/R.

Bit 7 reverses the phase of data output on OUT1L/R.

Bit 8 reverses the phase of data output on OUT2L/R.

Right Output

2

PL[3:0] Left

S

DSP Mode

0: DSP Mode A

1: DSP Mode B

Output

Right Output

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REGISTER

ADDRESS

0000100

Attenuation DACL1

0000101

Attenuation DACR1

Attenuation DACL2

Attenuation DACR2

0001000

Master

Attenuation

(all channels)

0001001

Extended interface control

Table 13 Register Map Description

BIT LABEL DEFAULT DESCRIPTION

7:0

L1A[7:0] 11111111

8

UPDATE Not latched

7:0

R1A[7:0] 11111111

8

UPDATE Not latched

7:0

L2A[7:0] 11111111

8

UPDATE Not latched

7:0

R2A[7:0] 11111111

8

UPDATE Not latched

7:0

MASTA[7:0] 11111111

8

UPDATE Not latched

0

1

2SPD 0

ZCD 0

Attenuation level of left channel DACL1 in 0.5dB steps. See Table 8

(0dB)

Controls simultaneous update of all Attenuation Latches

0: Store DACL1 in intermediate latch (no change to output)

1: Store DACL1 and update attenuation on all channels.

Attenuation level of right channel DACR1 in 0.5dB steps, see Table 8.

(0dB)

Controls simultaneous update of all Attenuation Latches

0: Store DACR1 in intermediate latch (no change to output)

1: Store DACR1 and update attenuation on all channels.

Attenuation level of left channel DACL2 in 0.5dB steps, see Table 8. 0000110

(0dB)

Controls simultaneous update of all Attenuation Latches

0: Store DACL2 in intermediate latch (no change to output)

1: Store DACL2 and update attenuation on all channels.

Attenuation level of right channel DACR2 in 0.5dB steps, see Table 8. 0000111

(0dB)

Controls simultaneous update of all Attenuation Latches

0: Store DACR2 in intermediate latch (no change to output)

1: Store DACR2 and update attenuation on all channels.

Attenuation data for all channels in 0.5dB steps, see Table 8.

(0dB)

Controls simultaneous update of all Attenuation Latches

0: Store MASTA[7:0] in all intermediate latches (no change to output)

1: Store DACR0 and update attenuation on all channels

Activates the split rate mode where the front channels run at 192kHz and the rear four channels run at 96kHz.

0: Normal operation.

1: Split rate operation.

Controls the operation of the zero crossing detect mechanism which ensures that the volume is only updated on each channel when the signal passes through midrail.

0: Enable zero detect.

1: Disable zero detect.

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DIGITAL FILTER CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Passband

Stopband

Passband Ripple

Stopband Attenuation

±0.05 dB 0.444fs dB

-3dB 0.487fs ±0.05 dB

f > 0.555fs -60 dB

Table 14 Digital Filter Characteristics

DAC FILTER RESPONSES

0

-20

-40

-60

Response (dB)

-80

-100

-120 0 0.5 1 1.5 2 2.5 3

Frequency (Fs)

Figure 14 DAC Digital Filter Frequency Response

– 44.1, 48 and 96kHz

0.2

0.15

0.1

0.05

0

Response (dB)

-0.05

-0.1

-0.15

-0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency (Fs)

Figure 15 DAC Digital Filter Ripple –44.1, 48 and 96kHz

0

-20

-40

Response (dB)

-60

-80

0 0.2 0.4 0.6 0.8 1

Frequency (Fs)

Figure 16 DAC Digital Filter Frequency Response

– 192kHz

0.2

0

-0.2

-0.4

Response (dB)

-0.6

-0.8

-1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency (Fs)

Figure 17 DAC Digital Filter Ripple – 192 kHz

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DIGITAL DE-EMPHASIS CHARACTERISTICS

0

-2

-4

-6

Response (dB)

-8

-10 0 2 4 6 8 10 12 14 16

Frequency (kHz)

Figure 18 De-Emphasis Frequency Response (32kHz)

1

0.5

0

-0.5

-1

Response (dB)

-1.5

-2

-2.5

-3 0 2 4 6 8 10 12 14 16

Frequency (kHz)

Figure 19 De-Emphasis Error (32kHz)

0

-2

-4

-6

Response (dB)

-8

-10 0 5 10 15 20

Frequency (kHz)

Figure 20 De-Emphasis Frequency Response (44.1kHz)

0

-2

-4

-6

Response (dB)

-8

-10 0 5 10 15 20

Frequency (kHz)

Figure 22 De-Emphasis Frequency Response (48kHz)

0.4

0.3

0.2

0.1

0

Response (dB)

-0.1

-0.2

-0.3

-0.4 0 5 10 15 20

Frequency (kHz)

Figure 21 De-Emphasis Error (44.1kHz)

1

0.8

0.6

0.4

0.2

0

-0.2

Response (dB)

-0.4

-0.6

-0.8

-1 0 5 10 15 20

Frequency (kHz)

Figure 23 De-Emphasis Error (48kHz)

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APPLICATIONS INFORMATION

RECOMMENDED EXTERNAL COMPONENTS

Figure 24 External Components Diagram

RECOMMENDED EXTERNAL COMPONENTS VALUES

COMPONENT

REFERENCE

C1 and C5 10µF

C2 to C4 0.1µF

C6 to C11 10µF Output AC coupling caps to remove midrail DC level from outputs.

C12 0.1µF C13 10µF C14 10µF

R1 33Ω

Table 15 External Components Description

SUGGESTED

VALUE

DESCRIPTION

De-coupling for DVDD and AVDD1.

Reference de-coupling capacitors for CAP pin.

Filtering for AVDD2. Omit if AVDD low noise.

Filtering for AVDD2. Use 0Ω if AVDD low noise.

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DECOUPLING APPLICATIONS INFORMATION

SUPPLY PINS DESCRIPTION

PIN NAME TYPE DESCRIPTION

1 DVDD Supply

11 DGND Supply

15 AVDD2 Supply

16 CAP Analogue output

20 AGND1 Supply

24 AGND2 Supply

28 AVDD1 Supply

DC ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Analogue supply current

Digital supply current

Analogue supply current

Digital supply current

For proper decoupling, 0.1µF surface-mount ceramic capacitors are recommended for AVDD1, AVDD2, DVDD and CAP. Also recommended are 10µF capacitors for AVDD, DVDD and CAP. These are a general guideline and are dependent on the amount of noise present in the system.

AVDD = 5V 58 mA

DVDD = 5V 22 mA

AVDD = 3.3V 57 mA

DVDD = 3.3V 11 mA

Digital Positive Supply.

Digital GND

Analogue Positive DAC Reference

Analogue Internal Mid-Rail Reference De-Coupling Point

Analogue GND

Analogue VDD

If there is excessive noise on the supply, such as may be present in a commercial DVD receiver with motors and switching amplifiers, additional filtering will be required. The supply AVDD2 is the reference voltage for the DAC. It has no supply noise rejection, so any noise on this pin will affect the DAC outputs. There is not much current drawn on this supply pin. Supply AVDD1 does have supply rejection and draws most of the analogue supply current.

DECOUPLING EXAMPLES

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Figure 25 Decoupling Example 1

In Figure 25, there is a single analogue supply that is fairly noisy. The AVDD1 and DVDD pins can tolerate this, but the AVDD2 needs additional filtering. The schematic illustrates a suitable solution.

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WM8746 Production Data

It is important that the supply pins are connected correctly. If AVDD1 and AVDD2 pins had both been connected to the 10Ω resistor, the performance would be worse. The value of 10Ω is too high and will cause an increase in THD. This is because currents drawn by AVDD1 will affect the reference voltage on AVDD2. A full-scale output FFT plot will show increased harmonics, because the output current drawn modulates the reference voltage.

4.7µF ceramic capacitors are becoming available in 0805 package with Y5V dielectric. W hilst they do not have quite as good performance as 10µF, it is possible to use them instead. Their capacitance goes down significantly with supply voltage, but at 3.3V (VDD) and 1.65V (CAP pin), the drop is not too great, if a 10V-rated part is used. As they are already in a low-inductance package, the 0.1µF is no longer necessary. See Figure 26 for an example.

Figure 26 Decoupling Example 2

RECOMMENDED ANALOGUE LOW-PASS FILTER (OPTIONAL)

4.7k

Ω

4.7k

Ω

+VS

_

10u

F

+

10k

1.8k

Ω

Figure 27 Recommended Low Pass Filter (Optional)

1.0nF

7.5K

Ω

+

-VS

680pF

51

Ω

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WM8746 Production Data

PACKAGE DIMENSIONS

DM007.EDS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)

b

28

1

A2

A1

A

D

e

15

E1 E

14

0.10

-C-

C

SEATING PLANE

GAUGE PLANE

ΘΘΘΘ

0.25

c

L

1

Dimensions

Symbols

(mm)

MIN NOM MAX A A

1

A

2

b c D e E E

1

L

1

θθθθ

REF:

NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-15 0, VARIATI ON = AH. REFER TO THIS SPECIF ICATION FOR FURTHER DETAI LS.

----- -----

0.05 ----- 0.25

1.65 1.75 1.85

0.22 0.30 0.38

0.09 ----- 0.25

9.90 10.20 10.50

0.65 BSC

7.40 7.80 8.20

5.00 5.30 5.60

0.55 0.75 0.95

o

0

1.25 REF

o

4

JEDEC.95, MO-150

2.0

o

8

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WM8746 Production Data

IMPORTANT NOTICE

Wolfson Microelectronics plc (W M) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof.

Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.

Resale of WM’s products or services with statements different from or beyond the parameters product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.

stated by WM for that

ADDRESS:

Wolfson Microelectronics plc

Westfield House

26 Westfield Road

Edinburgh

EH11 2QB

United Kingdom

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Email :: [email protected]

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wolfson WM8746 User Manual

24-bit, 192kHz 6-Channel DAC with Volume Control

WM8746

DESCRIPTION

BLOCK DIAGRAM

FEATURES

APPLICATIONS

TABLE OF CONTENTS

PIN CONFIGURATION

ORDERING INFORMATION

PIN DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS

TERMINOLOGY

MASTER CLOCK TIMING

DIGITAL AUDIO INTERFACE TIMING

DIGITAL CONTROL INTERFACE

DEVICE DESCRIPTION

INTRODUCTION

AUDIO DATA SAMPLING RATES

DIGITAL AUDIO INTERFACE

MODES OF OPERATION

SOFTWARE CONTROL MODES

HARDWARE CONTROL MODES

SOFTWARE CONTROL INTERFACE

REGISTER MAP

DIGITAL FILTER CHARACTERISTICS

DAC FILTER RESPONSES

DIGITAL DE-EMPHASIS CHARACTERISTICS

APPLICATIONS INFORMATION

RECOMMENDED EXTERNAL COMPONENTS

RECOMMENDED EXTERNAL COMPONENTS VALUES

DECOUPLING APPLICATIONS INFORMATION

SUPPLY PINS DESCRIPTION

DC ELECTRICAL CHARACTERISTICS

DECOUPLING EXAMPLES

RECOMMENDED ANALOGUE LOW-PASS FILTER (OPTIONAL)

PACKAGE DIMENSIONS

IMPORTANT NOTICE

ADDRESS: