Wistron Nirvana 13 Schematic

5

4

3

2

1

Nirvana 13 UMA Schematics Document

D D

Sandy Bridge

Intel PCH

C C

2011-01-18 REV : A00

B B

DY :None Installed 10mW: External circuit for 10mW solution installed. BT: Stand alone BT Module. GSENSOR_ADI: Stuff for ADI G-Sensor. VCCSA_PWM: Stuff for VCCSA PWM solution. VCCSA_LDO: Stuff for VCCSA LDO solution. P2800A1: Stuff for P2800EA1

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Cover

Nirvana 13

1 103Tuesday, January 18, 201 1

1

A00

5

Nirvana 13 UMA Block Diagram (6 layers)

D D

4

Intel CPU

Sandy Bridge

4,5,6,7,8,9,10, 11,12,13

3

DDRIII 1066/1333 Channel A

DDRIII 1066/1333 Channel B

2

Project Code: 91.4ID01.001 PCB P/N :10261 Revision : -1

DDRIII 1066/1333

Slot 1

Slot 2

PCB LAYER

UMA

L1:Top L2:VCC L3:Signal L4:Signal L5:GND L6:Bottom

1

CPU DC/DC

VT1316+VT1317

INPUTS

5V_S5

OUTPUTS

VCC_CORE

SYSTEM DC/DC

VT1316+VT1317

INPUTS

5V_S5

OUTPUTS

VCC_GFXCORE

SYSTEM DC/DC

TPS51461/APL5916

INPUTS

5V_S5

OUTPUTS

0D85V_S0

SYSTEM DC/DC

TPS51216

INPUTS

DCBATOUT

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

SYSTEM DC/DC

42

44

48

46

45

TPS51218

FDIx4x2

C C

HDMI

LCD

51

49

HDMI

LVDS(Single Channel)

PCH Cougar Point

CRT

SD/MMC+/MS/ MS Pro/xD/SDXC

(8 in 1)

50

Card Reader

RTS5138

74

Bluetooth V3.0

Finger Print

B B

CAMERA w/ Digital MIC

HP

MIC IN

RGB CRT

32

63

64

49

USB 2.0 x 1

CODEC

IDT 92HD87B1

USB2.0 x 4

HDA

29

ETHERNET (10/100/1000Mb)

SPI

Flash ROM

4MB

60

DMIx4

Intel

14 USB 2.0/1.1 ports

High Definition Audio

SATA ports (6)

PCIE ports (8)

LPC I/F

ACPI 1.1

17,18,19,20,21,22,23,24,25,26

SMBus

LPC Bus

KBC

ADC

PCIE x 1

PCIE x 1,USB2.0 x 1

USB2.0 x 1

SATA x 1

SATA x 2

Free Fall Sensor

79

10/100/1000 LOM

Realtek

RTL8111E-VB

USB3.0 Controller

NEC uPD720200F1

Mini-Card

WWAN

Mini-Card

802.11a/b/g

USB CHARGE

PI5USB14550

65

57 57

(On Daughter Board)

RJ45 CONN

USB3.0 x 2

SIM

ESATA/USB Combo

HDD

56

ODD

56

INPUTS

DCBATOUT

OUTPUTS

1D05V_VTT

TI CHARGER

BQ24745

INPUTS

+DC_IN_S5

+PBATT

OUTPUTS

DCBATOUT

SYSTEM DC/DC

TPS51427

INPUTS

DCBATOUT 5V_S5

26

SYSTEM DC/DC

INPUTS

3D3V_S5

INPUTS OUTPUTS

26

1D5V_S3

5V_S5

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5 15V_S5

TPS51311

OUTPUTS

1D8V_S0

Switches

1D5V_S0

5V_S0

3D3V_S03D3V_S5

40

41

47

36

NUVOTON

NPCE795PA

27

A A

1CH SPEAKER

Touch PAD

69 69

5

4

Int. KB

DAC

Thermal Sensor

Main:ENEP2800

FAN Controller

Main:ENEP2793

3

28

Fan

28

25

55

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Tuesday, January 04, 201 1

Date: Sheet of

Tuesday, January 04, 201 1

Date: Sheet of

Tuesday, January 04, 201 1

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Nirvana 13

1

2 103

A00

5

PCH Strapping

Huron River Schematic Checklist Rev.1_0

Name Schematics Notes

SPKR

INIT3_3V# Weak internal pull-up. This signal should not be pulled low. Leave as "No Connect".

GNT3#/GPIO55

D D

GNT2#/GPIO53 GNT1#/GPIO51

INTVRMEN

DF_TVS

SATA1GP /GPIO19

C C

HDA_SDO

HDA_SYNC

GPIO15

DSWVRMEN

B B

GPIO28

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Enable when Pull-up.

No Reboot Mode with TCO Disabled:

GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail.

Integrated 1.05 V VRM Enable / Disable

Integrated 1.05 V VRMs is enabled when high. This signal should always be pulled high

DMI and FDI Tx/Rx Termination Voltage

Weak internal pull-down. It needs to be connected to PROC_SELECT with a 1K±5% pull-up resistor to PCH VCCPNAND rail and a 4.7K±5% series resistor.

Boot BIOS Strap bit 0

This Signal has a weak internal pull-up. Note: This field determines the destination of accesses to the BIOS memory range. This strap is used in conjunction with Boot BIOS Destination Selection 1 strap. Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI 0 0 LPC

Signal has a weak internal pull-down. Default: the security measures defined in the Flash Descriptor will be in effect. Pull-up: the Flash Descriptor Security will be overridden. This strap should only be asserted high via external pull-up in manufacturing or debug environments ONLY.

On-Die PLL Voltage Regulator Voltage Select

This signal has a weak internal pull-down. On Die PLL VR is supplied by 1.5 V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform.

TLS Confidentiality

Low - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality This signal has a weak internal pull-down. NOTE: A strong pull-up may be needed for GPIO functionality

Deep S4/S5 Well On-Die Voltage Regulator Enable

This signal enables the internal Deep Sleep 1.05 V regulators. This signal must be always pulled-up to VccRTC.

On-Die PLL Voltage Regulator

This signal has a weak internal pull-up. The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled. If not used, 8.2-kΩ to 10-kΩ pull-up to +V3.3A power-rail.

4

3

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[2]

CFG[4]

CFG[6:5]

CFG[7]

POWER PLANE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_S5

PCI-Express Static Lane Reversal

Display Port Presence strap

PCI-Express Port Bifurcation Straps

PEG DEFER TRAINING

VOLTAGE DESCRIPTION

5V

3.3V

1.8V

1.5V

1.05V

0.95 - 0.85V

0.75V

0.35V to 1.5V

0.4 to 1.25V

5V

1.5V

0.75V

6V-14.1V 6V-14.1V 5V 5V

3.3V

3.3V3D3V_LAN_S5

3.3V

1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded Display Port.

Enabled - An external Display Port device is

0:

connectd to the Embedded Display Port

11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled

1:

PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

0:

Voltage Rails

ACTIVE IN

S0

S3

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

2

Huron River Schematic Checklist Rev.1_0

CPU Core Rail Graphics Core Rail

AC Brick Mode only

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

Default Value

0

1

11

1

USB Table

PCIE Routing

LANE1

LANE2

LANE3

LANE4

A A

LANE5

LANE6

LANE7

X

LAN (I/O Board)

Mini Card2(WWAN)

Mini Card1(WLAN)

USB3.0

X

SATA Table

SATA

Pair

0

1

2

3

4

5

Device

HDD1

N/A

ODD

ESATA

LANE8 X

Pair

0

1

2

3

4

5

6

7

8

9

10

11

12

13

5

4

Device

X

ESATA / USB COMBO

Fingerprint

BLUETOOTH

Mini Card2 (WWAN)

CARD READER

X

Mini Card1 (WLAN)

CAMERA

X

SMBus ADDRESSES

2

I C / SMBus Ad dresses

Device

EC SMBus 1 Battery Capacity Board

EC SMBus 2 PCH MXM LCD Thermal Sensor

PCH SMBus CK505 Clock Generator SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot

3

Address Hex Bus Ref Des

HURON RIVER ORB

KBC_SDA1/KBC_SCL1 KBC_SDA1/KBC_SCL1

KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2

PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

Nirvana 13

3 103Wednesd ay, December 22, 20 10

1

A00

5

4

3

2

1

SSID = CPU

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

1 OF 9

CPU1A

D D

C C

B B

NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Lane reversal does not apply to FDI sideband signals.

1D05V_V TT

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

DMI_TXN[3:0 ](19)

DMI_TXP[3:0 ](19)

DMI_RXN[3:0](19)

DMI_RXP[3:0](19)

FDI_TXN[7:0 ](19)

FDI_TXP[7:0 ](19)

FDI_FSYNC0(19) FDI_FSYNC1(19)

FDI_INT(19)

FDI_LSYNC0(19) FDI_LSYNC1(19)

R402 24D9R2F -L-GPR402 24D9R2F -L-GP

1 2

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DP_COMP

B27 B25 A25 B24

B28 B26 A24 B23

G21 E22 F21 D21

G22 D22 F20 C21

A21 H19 E19 F18 B21 C20 D18 E17

A22 G19 E20 G18 B20 C19 D19 F17

H20

H17

A18 A17 B16

C15 D15

C17 F16 C16 G15

C18 E16 D16 F15

J18 J17

J19

SANDY

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI0_LSYNC FDI1_LSYNC

EDP_COMPIO EDP_ICOMPO EDP_HPD

EDP_AUX EDP_AUX#

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3

SANDY

DMI

Intel(R) FDI

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11

PCI EXPRESS* - GRAPHICS

PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

1 OF 9

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_IRCOM P_R

R401 24D9R2F -L-GPR401 24D9R2F -L-GP

1 2

NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect

1D05V_V TT

Stuff to disable internal graphics function for power saving.

A A

NOTE: Select a Fast FET similar to 2N7002E whose rise/ fall time is less than 6 ns. If HPD on eDP interface is disabled, connect it to CPU VCCIO via a 10-kΩ pull-Up resistor on the motherboard.

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU 1/7(PEG/DMI/FDI/eDP)

Size Document N umber Rev

Date: Sheet of

CPU 1/7(PEG/DMI/FDI/eDP)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

4 103Tuesday, January 18, 201 1

A00

5

SSID = CPU

H_SNB_IVB#(18)

1D05V_VTT

R501

D D

R501

1 2

62R2J-GP

H_PROCHOT#

CRB : 47pf CEKLT:43pf

12

C502

C502 SC47P50V2JN-3GP

SC47P50V2JN-3GP

20100622 V1.2

Connect EC to PROCHOT# through inverting OD buffer.

H_PECI(22,27)

H_PROCHOT#(27,40,42)

H_THERMTRIP#(22,36)

1

TP501TPAD14-GP TP501TPAD14-GP

1

TP502TPAD14-GP TP502TPAD14-GP

R513

1 2

56R2J-4-GP

4

SKTOCC#_R

H_CATERR#

H_PROCHOT#_R

AN34

AL33

AN33

AL32

AN32

C26

CPU1B

SNB_IVB#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

SANDY

3

2 OF 9

A28

BCLK

A27

BCLK#

CLK_DP_P_R

MISCTHERMALPWR MANAGEMENT

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

DDR3

MISC

DDR3

MISC

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

A16

CLK_DP_N_R

A15

R8

SM_RCOMP_0

AK1

SM_RCOMP_1

A5

SM_RCOMP_2

A4

Signal Routing Guideline: SM_RCOMP keep routing length l ess than 500 mils.

RN502

2 3 1

SRN1KJ-7-GP

R502

1 2

4K99R2F-L-GP

R506 140R2F-GPR506 140R2F-GP

1 2

R507 25D5R2F-GPR507 25D5R2F-GP

1 2

R508 200R2F-L-GPR508 200R2F-L-GP

1 2

CLK_EXP_P (20) CLK_EXP_N (20)

4

1D05V_VTT

20110104 A00: merge R512,R514 to RN502 1k array resistor. 20110113 A00: Swap RN502 base on swap report.

2

SM_DRAMRST# (37)

1

Disabling Guidelines: If motherboard only supports e xternal graphics: Connect DPLL_REF_SSCLK on Proc essor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Pro cessor to VCCP through 1K +/- 5% resistorpowe r (~15 mW) may be wasted.

R503

1 2

C C

PLT_RST#(18,27,65,71,82)

B B

A A

PLT_RST#(18,27,65,71,82)

H_CPUPWRGD_R

10KR2J-3-GP

R510

1 2

1K5R2F-2-GP

Buffered reset to CPU

5

H_PM_SYNC(19)

H_CPUPWRGD(22,36)

PM_DRAM_PWRGD(19,37)

VDDPWRGOOD(37)

12

R509

R509 750R2F-GP

750R2F-GP

U501

1

IN B

VCC

2

DY

IN A

GND3OUT Y

74VHC1G09DFT2G-GP

73.01G09.AAH

1D05V_VTT

DY

5

4

12

DY

12

R518

R518 75R2J-1-GP

75R2J-1-GP

1 2

R504

H_CPUPWRGD_R

0R0402-PAD

VDDPWRGOOD

R505

0R2J-2-GP

DY

BUF_CPU_RST#

C501

C501 SC220P50V2KX-3GP

SC220P50V2KX-3GP

3D3V_S0

12

DY

R517 43R2J-GP

AM34

AP33

AR33

C503

C503 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

DY

4

PM_SYNC

UNCOREPWRGOOD

V8

SM_DRAMPWROK

RESET#

SANDY

BUF_CPU_RST#BUFO_CPU_RST#

12

R515

DY

0R2J-2-GP

XDP_DBRESET#

JTAG & BPM

XDP_DBRESET# (19)

3

PRDY# PREQ#

TCK

TMS

TRST#

TDO

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

AP29 AP27

XDP_TCLK

AR26

XDP_TMS

AR27

XDP_TRST#

AP30

XDP_TDI

AR28

TDI

XDP_TDO

AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

XDP_DBRESET#

RN501

XDP_TDI XDP_TMS XDP_TDO XDP_TCLK

XDP_TRST#

XDP_DBRESET#

Title

Size Document Number Rev

Date: Sheet of

RN501

1

8

2

7

3

6

4 5

SRN51J-1-GP

R511 51R2J-2-GPR511 51R2J-2-GP

1 2

20100722 Modify: Change R516 10K from 1K

CPU 2/7(THERMAL/CLOCK/PM )

Nirvana 13

2

1D05V_VTT

3D3V_S0

R516

R516 10KR2J-3-GP

10KR2J-3-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

5 103Tuesday, January 18, 2011

1

A00

5

4

3

2

1

SSID = CPU

3 OF 9

CPU1C

SANDY

M_A_DQ[6 3:0](14)

D D

C C

B B

M_A_DQ[6 3:0]

M_A_BS0(14) M_A_BS1(14) M_A_BS2(14)

M_A_CAS #(14) M_A_RAS #(14) M_A_W E#(14 )

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ1 0 M_A_DQ1 1 M_A_DQ1 2 M_A_DQ1 3 M_A_DQ1 4 M_A_DQ1 5 M_A_DQ1 6 M_A_DQ1 7 M_A_DQ1 8 M_A_DQ1 9 M_A_DQ2 0 M_A_DQ2 1 M_A_DQ2 2 M_A_DQ2 3 M_A_DQ2 4 M_A_DQ2 5 M_A_DQ2 6 M_A_DQ2 7 M_A_DQ2 8 M_A_DQ2 9 M_A_DQ3 0 M_A_DQ3 1 M_A_DQ3 2 M_A_DQ3 3 M_A_DQ3 4 M_A_DQ3 5 M_A_DQ3 6 M_A_DQ3 7 M_A_DQ3 8 M_A_DQ3 9 M_A_DQ4 0 M_A_DQ4 1 M_A_DQ4 2 M_A_DQ4 3 M_A_DQ4 4 M_A_DQ4 5 M_A_DQ4 6 M_A_DQ4 7 M_A_DQ4 8 M_A_DQ4 9 M_A_DQ5 0 M_A_DQ5 1 M_A_DQ5 2 M_A_DQ5 3 M_A_DQ5 4 M_A_DQ5 5 M_A_DQ5 6 M_A_DQ5 7 M_A_DQ5 8 M_A_DQ5 9 M_A_DQ6 0 M_A_DQ6 1 M_A_DQ6 2 M_A_DQ6 3

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AK8

AK9 AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9 AF9

C5

SA_DQ0

D5

SA_DQ1

D3

SA_DQ2

D2

SA_DQ3

D6

SA_DQ4

C6

SA_DQ5

C2

SA_DQ6

C3

SA_DQ7

F10

SA_DQ8

F8

SA_DQ9 SA_DQ10

G9

SA_DQ11

F9

SA_DQ12

F7

SA_DQ13

G8

SA_DQ14

G7

SA_DQ15

K4

SA_DQ16

K5

SA_DQ17

K1

SA_DQ18

J1

SA_DQ19

J5

SA_DQ20

J4

SA_DQ21

J2

SA_DQ22

K2

SA_DQ23

M8

SA_DQ24 SA_DQ25

N8

SA_DQ26

N7

SA_DQ27 SA_DQ28

M9

SA_DQ29

N9

SA_DQ30

M7

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37

AJ5

SA_DQ38

AJ6

SA_DQ39

AJ8

SA_DQ40 SA_DQ41

AJ9

SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55

V6

SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

3 OF 9

SA_CLK0

SA_CLK#0

SA_CKE0

SA_CLK1

SA_CLK#1

SA_CKE1

SA_CLK2

SA_CLK#2

SA_CKE2

SA_CLK3

SA_CLK#3

SA_CKE3

SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3

SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQS #0 M_A_DQS #1 M_A_DQS #2 M_A_DQS #3 M_A_DQS #4 M_A_DQS #5 M_A_DQS #6 M_A_DQS #7

M_A_DQS 0 M_A_DQS 1 M_A_DQS 2 M_A_DQS 3 M_A_DQS 4 M_A_DQS 5 M_A_DQS 6 M_A_DQS 7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIM0_ CLK_DDR0 (14) M_A_DIM0_ CLK_DDR#0 (14) M_A_DIM0_ CKE0 (14)

M_A_DIM0_ CLK_DDR1 (14) M_A_DIM0_ CLK_DDR#1 (14) M_A_DIM0_ CKE1 (14)

M_A_DIM0_ CS#0 (14) M_A_DIM0_ CS#1 (14)

M_A_DIM0_ ODT0 (14 ) M_A_DIM0_ ODT1 (14 )

M_A_DQS #[7:0] (14 )

M_A_DQS [7:0] (14)

M_A_A[15 :0] (1 4)

CPU1D

M_B_DQ[6 3:0](15)

M_B_DQ[6 3:0]

M_B_BS0(15) M_B_BS1(15) M_B_BS2(15)

M_B_CAS #(15) M_B_RAS #(15) M_B_W E#(15 )

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ1 0 M_B_DQ1 1 M_B_DQ1 2 M_B_DQ1 3 M_B_DQ1 4 M_B_DQ1 5 M_B_DQ1 6 M_B_DQ1 7 M_B_DQ1 8 M_B_DQ1 9 M_B_DQ2 0 M_B_DQ2 1 M_B_DQ2 2 M_B_DQ2 3 M_B_DQ2 4 M_B_DQ2 5 M_B_DQ2 6 M_B_DQ2 7 M_B_DQ2 8 M_B_DQ2 9 M_B_DQ3 0 M_B_DQ3 1 M_B_DQ3 2 M_B_DQ3 3 M_B_DQ3 4 M_B_DQ3 5 M_B_DQ3 6 M_B_DQ3 7 M_B_DQ3 8 M_B_DQ3 9 M_B_DQ4 0 M_B_DQ4 1 M_B_DQ4 2 M_B_DQ4 3 M_B_DQ4 4 M_B_DQ4 5 M_B_DQ4 6 M_B_DQ4 7 M_B_DQ4 8 M_B_DQ4 9 M_B_DQ5 0 M_B_DQ5 1 M_B_DQ5 2 M_B_DQ5 3 M_B_DQ5 4 M_B_DQ5 5 M_B_DQ5 6 M_B_DQ5 7 M_B_DQ5 8 M_B_DQ5 9 M_B_DQ6 0 M_B_DQ6 1 M_B_DQ6 2 M_B_DQ6 3

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA9

AA7

AA10

AB8

AB9

SANDY

C9

SB_DQ0

A7

SB_DQ1 SB_DQ2

C8

SB_DQ3

A9

SB_DQ4

A8

SB_DQ5

D9

SB_DQ6

D8

SB_DQ7

G4

SB_DQ8

F4

SB_DQ9

F1

SB_DQ10

G1

SB_DQ11

G5

SB_DQ12

F5

SB_DQ13

F2

SB_DQ14

G2

SB_DQ15

J7

SB_DQ16

J8

SB_DQ17 SB_DQ18

K9

SB_DQ19

J9

SB_DQ20

J10

SB_DQ21

K8

SB_DQ22

K7

SB_DQ23

M5

SB_DQ24

N4

SB_DQ25

N2

SB_DQ26

N1

SB_DQ27

M4

SB_DQ28

N5

SB_DQ29

M2

SB_DQ30

M1

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54

R6

SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

4 OF 9

SB_CLK0

SB_CLK#0

SB_CKE0

SB_CLK1

SB_CLK#1

SB_CKE1

SB_CLK2

SB_CLK#2

SB_CKE2

SB_CLK3

SB_CLK#3

SB_CKE3

SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_B_DQS #0 M_B_DQS #1 M_B_DQS #2 M_B_DQS #3 M_B_DQS #4 M_B_DQS #5 M_B_DQS #6 M_B_DQS #7

M_B_DQS 0 M_B_DQS 1 M_B_DQS 2 M_B_DQS 3 M_B_DQS 4 M_B_DQS 5 M_B_DQS 6 M_B_DQS 7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIM0_ CLK_DDR0 (15) M_B_DIM0_ CLK_DDR#0 (15) M_B_DIM0_ CKE0 (15)

M_B_DIM0_ CLK_DDR1 (15) M_B_DIM0_ CLK_DDR#1 (15) M_B_DIM0_ CKE1 (15)

M_B_DIM0_ CS#0 (15) M_B_DIM0_ CS#1 (15)

M_B_DIM0_ ODT0 (15 ) M_B_DIM0_ ODT1 (15 )

M_B_DQS #[7:0] (15 )

M_B_DQS [7:0] (15)

M_B_A[15 :0] (1 5)

SANDY

A A

5

4

3

SANDY

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU 3/7(DDR)

Nirvana 13

1

A00

6 103Tuesday, January 18, 201 1

A00

SSID = CPU

5

4

3

2

1

CFG7

1

TP713 TPAD14-G PTP713 TPAD14-G P

1

TP714 TPAD14-G PTP714 TPAD14-G P

CFG4

CFG2

DY

12

R701

1KR2J-1-GP

DY

12

R702

R702 1KR2J-1-G P

1KR2J-1-G P

12

DY

R704

1KR2J-1-GP

R705

R705 1KR2J-1-G P

1KR2J-1-G P

PEG Static Lane Reversal

CFG2

1: Normal Opera tion; Lane # definition m atches socket p in map definiti on

0:Lane Reversed

Display Port Pr esence Strap

R703

R703 3K3R2F-2 -GP

3K3R2F-2 -GP

CFG4

PCIE Port Bifur cation Straps

CFG[6:5]

11: x16 - Devic e 1 functions 1 and 2 disabled

10: x8, x8 - De vice 1 function 1 enabled ; fu nction 2 disabl ed 01: Reserved - (Device 1 funct ion 1 disabled ; function 2 en abled) 00: x8,x4,x4 - Device 1 functi ons 1 and 2 ena bled

PEG DEFER TRAIN ING

CFG7

1: PEG Train im mediately follo wing xxRESETB d e assertion

0: PEG Wait for BIOS for train ing

1: Disabled; No Physical Displ ay Port attached to Emb edded Display P ort

0: Enabled; An external Displa y Port device i s connected to the Embedded D isplay Port

5 OF 9

CPU1E

AK28

CFG0

AK29 AL26 AL27 AK26 AL29

AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27

AK31 AN29

AJ31

AH31

AJ33

AH33

AJ26

F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29

B18 A19

B4 D1

J20

J15

CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

RSVD#AJ31 RSVD#AH31 RSVD#AJ33 RSVD#AH33

RSVD#AJ26

RSVD#B4 RSVD#D1

RSVD#F25 RSVD#F24 RSVD#F23 RSVD#D24 RSVD#G25 RSVD#G24 RSVD#E23 RSVD#D23 RSVD#C30 RSVD#A31 RSVD#B30 RSVD#B29 RSVD#D30 RSVD#B31 RSVD#A30 RSVD#C29

RSVD#J20 RSVD#B18 RSVD#A19

RSVD#J15

D D

CFG2

CFG4 CFG5 CFG6 CFG7

M3 - Processor Generated

C C

SO-DIMM VREF_DQ

M_VREF_ DQ_DIMM0 M_VREF_ DQ_DIMM1

R707 0R2J-2-GP

M_VREF_ CA_DIMM0

M_VREF_ CA_DIMM1

R707 0R2J-2-GP

R706 0R2J-2-GP

DY

R708 0R2J-2-GP

1 2

DY

R709 0R2J-2-GP

1 2

DY

1 2

DY

M_VREF_ DQ_DIMM0_C M_VREF_ DQ_DIMM1_C

R711

1KR2F-3-G P

20 mils

R710 0R2J-2-GP

1 2

DY

B B

B4:VREF_DQ CHA

D1:VREF_DQ CHB

12

R712

1KR2F-3-G P

H_VCCP_ SEL

SANDY

RESERVED

5 OF 9

RSVD#L7

RSVD#AG7

RSVD#AE7 RSVD#AK2

RSVD#W8

RSVD#AT26

RSVD#AM33

RSVD#AJ27

RSVD#T8

RSVD#J16 RSVD#H16 RSVD#G16

RSVD#AR35

RSVD#AT34 RSVD#AT33

RSVD#AP35

RSVD#AR34

RSVD#B34 RSVD#A33 RSVD#A34 RSVD#B35 RSVD#C35

RSVD#AJ32

RSVD#AK32

RSVD#AH27

RSVD#AN35 RSVD#AM35

RSVD#AT2 RSVD#AT1 RSVD#AR1

L7 AG7 AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

AN35 AM35

AT2 AT1 AR1

RSVD#AN 35 RSVD#AM 35

CFG5

CFG6

SANDY

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU 4/7(RESERVED)

Size Document N umber Rev

Date: Sheet of

CPU 4/7(RESERVED)

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

7 103Wednesd ay, December 22, 20 10

1

A00

5

4

3

2

1

SSID = CPU

D D

POWER

CPU1F

SANDY

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

SANDY

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

CORE SUPPLY

VCC_CORE

PROCESSOR CORE POWER

VCC_CORE

C C

DY

B B

53A

12

C801

DY

SC10U6D3V5KX-1GP

12

C820

SC22U6D3V5MX-2GP

12

C816

SC22U6D3V5MX-2GP

12

C837

SC22U6D3V5MX-2GP

VCC Output Decoupling Recommendation: 4 x 470 uF at Bottom Socket Edge 8 x 22 uF at Top Socket Cavity 8 x 22 uF at Top Socket Edge 8 x 22 uF at Bottom Socket Cavity

12

C802

SC10U6D3V5KX-1GP

12

C819

DY

SC22U6D3V5MX-2GP

12

C821

SC4D7U6D3V5KX-3GP

12

C836

SC10U6D3V5KX-1GP

12

C804

C811

C803

SC10U6D3V5KX-1GP

C818

SC10U6D3V5KX-1GP

C822

SC22U6D3V5MX-2GP

C835

SC10U6D3V5KX-1GP

C811

DY

SC10U6D3V5KX-1GP

12

C815

C817

SC22U6D3V5MX-2GP

12

C823

C824

SC22U6D3V5MX-2GP

12

C834

C833

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

12

SC10U6D3V5KX-1GP

12

C826

C825

SC22U6D3V5MX-2GP

C832

SC22U6D3V5MX-2GP

C827

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

12

C831

C828

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

SENSE LINES SVID

PEG AND DDR

VCCIO_SENSE VSSIO_SENSE

6 OF 9

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

VCCIO Output Decoupling Recommendation: 2 x 330 uF (3 x 330 uF for 2012 capable designs) 5 x 22 uF & 5 x 0805 no-stuff at Bottom 7 x 22 uF & 2 x 0805 no-stuff at Top

12

C806

C805

DY

SC10U6D3V3MX-GP

No-stuff sites outside the soc ket may be removed. No-stuff sites inside the sock et cavity need to remain.

H_CPU_SVIDALR T# H_CPU_SVIDC LK H_CPU_SVIDD AT

R803 43R2J-GPR803 43R2J-GP

1 2

20101231 A00: Merge R801,R802 to RN801 100 ohm array resistor. 20110113 A00: Change RN801 to 100 ohm 1% (66.10156.04L). 20110113 A00: Swap RN801 base on swap report.

VCC_CORE

SRN100F-1-G P

VCCIO_SENSE ( 45) VSSIO_SENSE (45)

12

C807

DY

SC10U6D3V3MX-GP

RN801

2 3

R2

1

R1

12

C808

DY

12

C809

SC10U6D3V5KX-1GP

SC10U6D3V3MX-GP

12

C829

C830

SC10U6D3V5KX-1GP

SC4D7U6D3V5KX-3GP

12

C839

C810

SC10U6D3V5KX-1GP

C842

SC10U6D3V5KX-1GP

C839

C838

SC10U6D3V5KX-1GP

SC4D7U6D3V5KX-3GP

1D05V_VTT

12

C844

C843

SC10U6D3V5KX-1GP

SC4D7U6D3V5KX-3GP

These resistors need to close to power IC.

4

VR_SVID_ALERT#

H_CPU_SVIDC LK

H_CPU_SVIDD AT

VR_SVID_ALERT# (42)

H_CPU_SVIDC LK (42)

H_CPU_SVIDD AT (42)

R805 75R2J-1-GPR805 75R2J-1-GP

1 2

R806 54D9R2F-L1-GP

1 2

DY

R804 130R2F-1-GPR804 130R2F-1-GP

1 2

VCCSENSE (42) VSSSENSE ( 42)

1D05V_VTT

C840

SC10U6D3V5KX-1GP

C845

SC10U6D3V5KX-1GP

12

C841

1D05V_VTT

SC10U6D3V5KX-1GP

SANDY

A A

5

SANDY

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU 5/7(VCC_CORE)

Nirvana 13

1

8 103Tuesday, January 18, 2011

A00

5

VAXG Output Decoupling Recommendation:

SSID = CPU

VCC_GFX CORE

2 x 470 uF at Bottom Socket Edge 2 x 22 uF at Top Socket Cavity 4 x 22 uF at Top Socket Edge 2 x 22 uF at Bottom Socket Cavity 4 x 22 uF at Bottom Socket Edge

PROCESSOR VAXG: 33A

D D

C C

DY

12

C901

SC10U6D3V5KX-1GP

DY

12

C902

C903

SC4D7U6D3V5KX-3GP

12

C908

SC10U6D3V3MX-GP

12

C904

SC4D7U6D3V5KX-3GP

12

DY

Removed DIS_ONLY Disable Resistor. R904,R905,R901,R903

Disabling Guidelines for External Graphics Designs: Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed. Can be left floating (Gfx VR keeps VAXG rail from floating)

B B

if the VR is stuffed

1D8V_S0

PROCESSOR VCCPLL: 1.2A

12

C923

SC10U6D3V5KX-1GP

4

POWER

CPU1G

AT24

VAXG

AT23

VAXG

12

C906

C905

SC22U6D3V5MX-2GP

SC4D7U6D3V5KX-3GP

12

C921

C920

DY

SC10U6D3V3MX-GP

12

C924

C922

SC1U10V2KX-1GP

AT21 AT20 AT18

AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17

AM24 AM23 AM21 AM20 AM18 AM17

AL24

AL23

AL21

AL20

AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG

B6

VCCPLL

A6

VCCPLL

A2

VCCPLL

SANDY

POWER

SANDY

GRAPHICS

1.8V RAIL

3

SENSE

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

VAXG_SENSE

VSSAXG_SENSE

LINES

SM_VREF

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCSA_SENSE

FC_C22

VCCSA_VID1

7 OF 9

AK35 AK34

Refer to the la test Huron Rive r Mainstream PD G (Doc# 436735) for more detail s on S3 power reduction imple mentation.

VSS_AXG _SENSE (42)

+V_SM_VREF_CNT should have 10 mil trace width

+V_SM_V REF_CNT

AL1

Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

PROCESSOR VDDQ: 10A

12

C909

C910

DY

C910

DY

SC10U6D3V3MX-GP

PROCESSOR VCCSA: 6A

12

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

VCCUSA_ SENSE

H_FC_C2 2 VCCSA_S EL

12

23

C916

1

SC10U6D3V5KX-1GP

RN901

RN901 SRN1KJ-7 -GP

SRN1KJ-7 -GP

C915

2

+V_SM_V REF_CNT (37)

12

C911

DY

SC10U6D3V3MX-GP

0D85V_S 0

12

C917

SC10U6D3V5KX-1GP

VCCUSA_ SENSE (48)

H_FC_C2 2 (48) VCCSA_S EL (48)

1

20101231 A00: Merge R906,R907 to RN902 100 ohm array resistor. 20110113 A00: Change RN801 to 100 ohm 1% (66.10156.04L). 20110113 A00: Swap RN902 base on swap report.

RN902

VCC_AXG _SENSE VSS_AXG _SENSE

1D5V_S0

12

C912

SC10U6D3V5KX-1GP

12

C913

C914

TC901

79.33719.20L

SC10U6D3V5KX-1GP

SC4D7U6D3V5KX-3GP

2nd = 77.C3371.13L

VDDQ Output Decoupling Recommendation: 1 x 330 uF 6 x 10 uF

VCCSA Output Decoupling Recommendation: 1 x 330 uF 2 x 10 uF at Bottom Socket Cavity 1 x 10 uF at Bottom Socket Edge

2 3 1

SRN100F -1-GP

12

DY

ST330U2VDM-4-GP

C907

12

RN902

SCD1U10V2KX-5GP

R2

R1

12

DY

C918

VCC_GFX COREVCC_AXG _SENSE (42)

4

12

DY

C919

SCD1U10V2KX-5GP

1D5V_S3

12

DY

C925

SCD1U10V2KX-5GP

4

VCCPLL Output Decoupling Recommendation: 1 x 330 uF 2 x 1 uF 1 x 10 uF

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU 6/7(VCC_GFX_CORE)

Size Document N umber Rev

Date: Sheet of

CPU 6/7(VCC_GFX_CORE)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

9 103Tuesday, January 18, 201 1

1

A00

5

4

3

2

1

SSID = CPU

9 OF 9

8 OF 9

CPU1H

AT35

VSS

AT32

VSS

AT29

VSS

AT27

VSS

AT25

VSS

AT22

VSS

D D

C C

B B

AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34

K35 K32 K29 K26

H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11

CPU1I

T35

VSS

T34

VSS

T33

VSS

T32

VSS

T31

VSS

T30

VSS

T29

VSS

T28

VSS

T27

VSS

T26

VSS

P9

VSS

P8

VSS

P6

VSS

P5

VSS

P3

VSS

P2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L33

VSS

L30

VSS

L27

VSS

L9

VSS

L8

VSS

L6

VSS

L5

VSS

L4

VSS

L3

VSS

L2

VSS

L1

VSS VSS VSS VSS VSS

J34

VSS

J31

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H9

VSS

H8

VSS

H7

VSS

H6

VSS

H5

VSS

H4

VSS

H3

VSS

H2

VSS

H1

VSS VSS VSS VSS VSS VSS VSS VSS VSS

F34

VSS

F31

VSS

F29

VSS

SANDY

VSS

9 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

SANDY

A A

5

4

3

SANDY

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU 7/7(VSS)

Nirvana 13

1

A00

10 1 03Wednesday, December 22, 20 10

A00

5

D D

C C

4

3

2

1

(Blanking)

Remove the XDP connector for space saving 6/28

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, December 22, 20 10

Date: Sheet of

Date: Sheet

XDP

NIRVANA 13

Taipei Hsien 221, Taiwan, R.O.C.

11 1 03

of

11 1 03

of

11 1 03

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

12 1 03Wednesday, December 22, 20 10

of

12 1 03Wednesday, December 22, 20 10

of

12 1 03Wednesday, December 22, 20 10

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

13 1 03Wednesday, December 22, 20 10

of

13 1 03Wednesday, December 22, 20 10

of

13 1 03Wednesday, December 22, 20 10

A00

5

4

3

2

1

SSID = MEMORY

DM1

H=9.2mm

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 42-GP

62.10017.N61

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIM0

197

SA0

SA1_DIM0

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_A_RAS# (6) M_A_WE# (6) M_A_CAS# (6)

M_A_DIM0_CS#0 (6) M_A_DIM0_CS#1 (6)

M_A_DIM0_CKE0 (6) M_A_DIM0_CKE1 (6)

M_A_DIM0_CLK_DDR 0 (6) M_A_DIM0_CLK_DDR #0 ( 6)

M_A_DIM0_CLK_DDR 1 (6) M_A_DIM0_CLK_DDR #1 ( 6)

PCH_SMBDAT A (15,20,65,79,82) PCH_SMBCLK (15,20,65,79,82)

TS#_DIMM0_1 (15)

Layout Note: Place these Caps near SO-DIMMA.

PART NUMBER

62.10017.N61

62.10017.F91

20101231 A00: Merge R1401,R1402 to RN1401 10k ohm array resistor. 20100104 A00: Change RN1401 to 0R short pad.

3D3V_S0

12

C1402

C1401

DY

SCD1U10V2KX-5GP

1D5V_S3

SC2D2U10V3KX-1GP

12

TC1401

DY

79.33719.20L

2nd = 77.C3371.13L

ST330U2VDM-4-GP

12

C1414

SC1U6D3V2KX-GP

Height TYPE

9.2mm

SA0_DIM0

SA1_DIM0

1

RN1401

0R4P2R-PAD

RN

4

SODIMM A DECOUPLING

12

C1403

C1404

C1405

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

C1415

SC1U6D3V2KX-GP

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

12

C1417

C1416

SC1U6D3V2KX-GP

23

Thermal EVENT

TS#_DIMM0_1

12

C1407

C1406

DY

SC10U6D3V5KX-1GP

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

3D3V_S0

R1403

1 2

10KR2J-3-GP

12

C1409

C1408

SC10U10V5ZY-1GP

C1410

DY

SC10U6D3V5KX-1GP

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

12

DY

M_A_DQ[63:0](6)

12

C1422

DY

SC1U6D3V2KX-GP

M_A_DIM0_ODT0(6) M_A_DIM0_ODT1(6)

M_VREF_CA_D IMM0 M_VREF_DQ_D IMM0

DDR3_DR AMRST#(15,37)

M_A_A[15:0] (6)

M_A_BS2(6)

M_A_BS0(6) M_A_BS1(6)

C1418

SC10U6D3V5KX-1GP

M_A_DQS#[7:0] (6)

M_A_DQS[7:0] (6)

0D75V_S0

DDR_VREF _S3

R1405

D D

20101224 A00: 0402 0R pad: R1404 R1405.

C C

B B

1 2

12

DDR_VREF _S3

1 2

12

0D75V_S0

R1405 0R0402-PAD

0R0402-PAD

C1423

SCD1U10V2KX-5GP

R1404

R1404 0R0402-PAD

0R0402-PAD

C1411

SCD1U10V2KX-5GP

12

C1419

M_VREF_CA_D IMM0

12

C1425

DY

SC2D2U10V3KX-1GP

M_VREF_DQ_D IMM0

12

C1412

DY

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1420

DY

SC1U6D3V2KX-GP

12

C1424

SCD1U10V2KX-5GP

12

C1413

SCD1U10V2KX-5GP

12

C1421

SC1U6D3V2KX-GP

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

DDR3-DIMM1 SOCKET1

Nirvana 13

1

14 103Tuesday, January 18, 2011

A00

5

SSID = MEMORY

M_B_A[15:0] (6)

C1520

SC1U6D3V2KX-GP

M_B_BS2(6)

M_B_BS0(6) M_B_BS1(6)

M_B_DQ[63:0](6)

12

C1521

SC1U6D3V2KX-GP

M_B_DIM0_ODT0(6) M_B_DIM0_ODT1(6)

M_VREF_CA_D IMM1 M_VREF_DQ_D IMM1

DDR3_DR AMRST#(14,37)

M_B_DQS#[7:0] (6)

M_B_DQS[7:0] (6)

0D75V_S0

D D

DDR_VREF _S3

R1504

R1504 0R0402-PAD

0R0402-PAD

M_VREF_CA_D IMM1

1 2

12

C1523

SCD1U10V2KX-5GP

DDR_VREF _S3

R1503

R1503 0R0402-PAD

0R0402-PAD

C C

B B

1 2

12

C1515

SCD1U10V2KX-5GP

0D75V_S0

12

C1522

C1524

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

20101224 A00: 0402 0R pad: R1503 R1504.

M_VREF_DQ_D IMM1

12

C1516

C1517

12

DY

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1518

SC1U6D3V2KX-GP

C1517

SCD1U10V2KX-5GP

C1519

SC1U6D3V2KX-GP

DY

12

DY

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

H=5.2mm

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 48-GP

62.10017.P41

4

NP1

NP2

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIM1

197

SA0

SA1_DIM1

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_B_RAS# (6) M_B_WE# (6) M_B_CAS# (6)

M_B_DIM0_CS#0 (6) M_B_DIM0_CS#1 (6)

M_B_DIM0_CKE0 (6) M_B_DIM0_CKE1 (6)

M_B_DIM0_CLK_DDR 0 ( 6) M_B_DIM0_CLK_DDR #0 ( 6)

M_B_DIM0_CLK_DDR 1 ( 6) M_B_DIM0_CLK_DDR #1 ( 6)

PCH_SMBDAT A (14,20,65,79,82) PCH_SMBCLK (14,20,65,79,82)

TS#_DIMM0_1 (14)

Layout Note: Place these Caps near SO-DIMMB.

PART NUMBER

62.10017.P41

3

12

C1502

C1501

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

Height TYPE

5.2mm

1D5V_S3

3D3V_S0

SODIMM B DECOUPLING

12

C1503

DY

12

C1511

SA1_DIM1

SA0_DIM1

DY

SC10U10V5ZY-1GP

SCD1U10V2KX-5GP

3D3V_S0

12

R1501

R1501 10KR2J-3-GP

10KR2J-3-GP

12

R1502

R1502 0R0402-PAD

0R0402-PAD

20100104 A00: Change R1502 to 0R0402 short pad.

12

C1504

C1505

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

12

C1513

C1512

SC1U6D3V2KX-GP

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

SO-DIMMB is placed farther from the Processor than SO-DIMMA

12

C1506

SC10U6D3V5KX-1GP

12

C1514

SC1U6D3V2KX-GP

C1508

C1507

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

2

12

C1509

C1510

DY

SC10U6D3V5KX-1GP

1

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

DDR3-DIMM2 SOCKET2

Nirvana 13

1

15 103Tuesday, January 18, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

16 1 03Wednesday, December 22, 20 10

of

16 1 03Wednesday, December 22, 20 10

of

16 1 03Wednesday, December 22, 20 10

1

A00

5

L_DDC_DATA(PAGE17):

D D

RN1702

1 2 3

SRN100K J-6-GP

4

L_BKLT_ EN LVDS_VD D_EN

This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display

Place near PCH

3D3V_S0

RN1703

1 2 3 4 5

SRN2K2J -2-GP

C C

SRN2K2J -2-GP

20100104 A00: Merge RN1701,RN1706 to RN1703 2.2k array resistor.

8 7 6

PCH_HDM I_DATA PCH_HDM I_CLK L_CTRL_ DATA L_CTRL_ CLK

Impedance:90 ohm

Close to PCH side

CRT_GRE EN CRT_BLU E CRT_RED

678

RN1705

RN1705 SRN150F -1-GP

SRN150F -1-GP

123

4 5

B B

4

LVDS_VD D_EN(49)

LVDS_DD C_CLK_R(49,97) LVDS_DD C_DATA_R(49,97)

20101224 A00: Change RN1704 to 0402 0 ohm pad.

12

R1701

R1701 2K37R2F -GP

2K37R2F -GP

LVDSA_C LK#(49) LVDSA_C LK(49)

LVDSA_D ATA0#(49) LVDSA_D ATA1#(49) LVDSA_D ATA2#(49)

LVDSA_D ATA0(49) LVDSA_D ATA1(49) LVDSA_D ATA2(49)

CRT_BLU E(50) CRT_GRE EN(50) CRT_RED(50)

CRT_DDC _CLK(50) CRT_DDC _DATA(50)

CRT_HSYNC(50) CRT_VSYNC(50)

Notes:

3

4 OF 10

PCH1D

L_BKLT_ EN(27)

L_BKLT_ CTRL(49)

TP1701TPAD14 -GP TP170 1TP AD14-GP

RN1704

1 2 3

0R4P2R-P AD

1KR2D-1-G P

R1702

LVDS_DD C_CLK_R LVDS_DD C_DATA_R

L_CTRL_ CLK L_CTRL_ DATA

LVDS_IBG

RN

LVDS_VB G

1

LVDS_VR EFH

4

LVDS_VR EFL

DAC_IREF_ R

12

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGAR-G P-U2-NF

Cougar

Cougar Point

Point

LVDS

CRT

Digital Display Interface

4 OF 10

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

2

DDI Port B Detect:(SDVO_CTRL_ DATA) 1: Port B detected 0: Port B not detected

1

PCH_HDM I_CLK (51) PCH_HDM I_DATA (51)

HDMI_PCH_ DET (51)

HDMI_DATA 2_R# (5 1) HDMI_DATA 2_R (51 ) HDMI_DATA 1_R# (5 1) HDMI_DATA 1_R (51 ) HDMI_DATA 0_R# (5 1) HDMI_DATA 0_R (51 ) HDMI_CLK_ R# (5 1) HDMI_CLK_ R (51 )

Impedance:100 ohm

1K 0.5% 0402.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

PCH 1/9(LVDS/CRT/DDI)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

17 1 03Tuesday, January 18, 2011

1

A00

5

4

3

2

1

SSID = PCH

RN1801

D D

3D3V_S0

INT_PIRQB# INT_PIRQF# INT_PIRQA#

R1801 4K7R2J-2-GP

A16 swap overri de Strap/Top-Bl ock Swap Override j umper

PCI_GNT#3 Low = A16 swap

C C

GNT1#/GPIO51 BOOT BIOS Locat ionSATA1GP/GPIO19

0 0 LPC

0 1 Reserved

B B

A A

PLT_RST #(5,27,65,71 ,82)

RN1801

1 2 3 4 5 6

SRN8K2J -2-GP-U

12

DY

override/Top-Bl ock Swap Override e nabled High = Default

1 2

DY

1 2

DY

R1802

1KR2J-1-G P

R1803

1KR2J-1-G P

10

INT_PIRQD#

9

INT_PIRQE#

8

INT_PIRQC#

7

INT_PIRQG#

PCI_GNT3#

BBS_BIT1

BBS_BIT0

BOOT BIOS Strap

Reserved 01

11

20101231 A00: Merge R1804,R1806 to RN1804 22 ohm array resistor. 20110113 A00: Swap RN1804 base on swap report.

12

DY

5

SPI(Default)

20101224 A00: 0402 0R pad: R1807.

R1816

12

DY

100KR2J-1-GP

HDD_FAL L_INT1(7 9)

SATA_OD D_DA#(56)

USB30_S MI#(82)

KB_LED_ BL_DET(69)

CLK_PCI_L PC(65,7 1)

CLK_PCI_F B(20) CLK_PCI_K BC(27)

R1807

12

0R0402-P AD

C1801

C1801 SC220P5 0V2KX-3GP

SC220P5 0V2KX-3GP

3D3V_S0

BBS_BIT0 (21)

PCI_PLTRS T#

DY

1 2

DGPU_HO LD_RST# DGPU_PW R_EN#

TP1806TPAD1 4-GP TP18 06TPAD14-G P

RN1804

2 3 1

SRN22-3-G P

1 2

EC1802

EC1801

1 2

DY

SC4D7P50V2CN-1GP

4

TP1807TPAD14 -GP TP180 7TP AD14-GP

DGPU_PW M_SELECT#

1

4

R1805

R1805 22R2J-2-G P

22R2J-2-G P

SC4D7P50V2CN-1GP

1 2

RN1803

1 2 3

SRN10KJ -5-GP

3D3V_S0

1

R1812 0R0402-PADR1812 0 R0402-PAD

1 2

R1813 0R0402-PADR1813 0 R0402-PAD

1 2

R1815 0R0402-PADR1815 0 R0402-PAD

1 2

R1817 0R0402-PADR1817 0 R0402-PAD

1 2

R1814

R1814 8K2R2J-3 -GP

8K2R2J-3 -GP

1 2

DGPU_HO LD_RST# DGPU_SE LECT# DGPU_PW R_EN#

TP1801TPAD14 -GP TP180 1TP AD14-GP

TP1802TPAD14 -GP TP180 2TP AD14-GP

4

KBC CLK EMI

R1818 10KR2J-3 -GPR1818 10 KR2J-3-GP

FFS_INT2_ R

3D3V_S5

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

BBS_BIT1

PCI_GNT3#

1

INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

PCI_PME#

1

PCI_PLTRS T#

CLK_PCI_L PC_R CLK_PCI_F B_R CLK_PCI_K BC_R

USB_OC# 2_3

PCH1E

Cougar

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

AH12

AM4 AM5

Y13 K24

L24 AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

K40 K38 H38

G38

C46 C44 E40

D47 E42 F46

G42 G40

C42 D44

K10

H49 H43

K42 H40

H3

C6

J48

Cougar

TP1

Point

TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PME#

PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

COUGAR-G P-U2-NF

OC[3:0]# for Device 29 (Ports 0-7) OC[7:4]# for Device 26 (Ports 8-13)

RN1802

1 2 3 4 5 6

SRN8K2J -2-GP-U

3

NVRAM

RSVD

PCI

USB

10 9 8 7

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

USB_OC# 12_13 USB_OC# 8_9USB_OC# 6_7 USB_OC# 10_11USB_OC# 0_1 USB_OC# 4_5

5 OF 10

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD

DF_TVS

RSVD

RSVD RSVD

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

NV_ALE

AV5

NV_CLE

AY1

NV_RCOM P

AV10

AT8

AY5 BA2

AT12

USB Ext. port 1 (HS)

BF3

External debug port use on Huron river platform

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_RBIAS

C33

B33

USB_OC# 0_1

A14

USB_OC# 2_3

K20

USB_OC# 4_5

B17

USB_OC# 6_7

C16

USB_OC# 8_9

L16

USB_OC# 10_11

A16

USB_OC# 12_13

D14 C14

3D3V_S5

TP1803 TPAD14-GPTP1 803 TPAD14-GP

1

USB_PN1 (57) USB_PP1 (57 ) USB_PN2 (64) USB_PP2 (64 ) USB_PN3 (63) USB_PP3 (63 ) USB_PN4 (82) USB_PP4 (82 ) USB_PN5 (32) USB_PP5 (32 )

USB_PN1 1 (65 ) USB_PP1 1 (65) USB_PN1 2 (49 ) USB_PP1 2 (49)

1 2

R1811

R1811 22D6R2F -L1-GP

22D6R2F -L1-GP

FFS_INT2_ R (79)

2

USB_OC# 0_1 (61)

Title

Size Document N umber Rev

Date: Sheet of

NV_CLE

DMI & FDI Termination Voltage

NV_CLE

Danbury Technol ogy: Disabled when L ow. Enable when Hig h.

USB Table

Pair

X

0

E-SATA / USB Combo

1

Fingerprint

2

BLUETOOTH

3

Mini Card2 (WWAN)

4

CARD READER

5

X

6

X

7

X

8

X

9

X

10

Mini Card1 (WLAN)

11

CAMERA

12

X

13

PCH 2/9(PCI/USB/NVRAM)

Nirvana 13

1D8V_S0

12

R1808

R1808 2K2R2J-2 -GP

2K2R2J-2 -GP

R1809

1 2

1KR2J-1-G P

H_SNB_IVB # (5)

Set to Vss when LOW

Set to Vcc when HIGH

1D8V_S0

12

R1810

R1810 1KR2J-1-G P

1KR2J-1-G P

DY

NV_ALE

Device

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

18 1 03Tuesday, January 18, 2011

1

A00

5

4

3

2

1

1 2

1 2 3 45

12

12 12

12

DMI_RXN[3:0](4)

DMI_RXP[3:0](4)

DMI_TXN[3:0 ](4)

DMI_TXP[3:0 ](4)

DMI_RXN0(4) DMI_RXN1(4) DMI_RXN2(4) DMI_RXN3(4)

DMI_RXP0(4) DMI_RXP1(4) DMI_RXP2(4) DMI_RXP3(4)

DMI_TXN0(4) DMI_TXN1(4) DMI_TXN2(4) DMI_TXN3(4)

DMI_TXP0(4) DMI_TXP1(4) DMI_TXP2(4) DMI_TXP3(4)

1 2

R1903 0R0402-P ADR19 03 0R0402-PA D

1 2

R1925 0R0402-P ADR19 25 0R0402-PA D

1 2

DY

PWRO K

R1907

1 2

0R2J-2-GP

DY

BATLOW # PM_RI# PCH_W AKE# SUS_PW R_ACK

AC_PRES ENT

PM_PW RBTN# PM_SLP_ LAN#

PM_RSMR ST#

DMI_COMP_ R

RBIAS_CPY

SUSACK#SUS_PW R_ACK

SYS_RESET #

R1905

10KR2J-3 -GP

R1923

1 2

0R2J-2-GP

DY

R1906 0R0402-P ADR19 06 0R0402-PA D

1 2

MEPW ROK

PM_RSMR ST#

BATLOW #

PM_RI#

PCH1C

BC24

DMI0RXN

Cougar

BE20 BG18 BG20

BE24 BC20

BJ18

BJ20

AW24 AW20

BB18

AV18

AY24

AY20

AY18 AU18

BJ24

BG25

BH21

C12

K3

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

COUGAR-G P-U2-NF

4

Cougar

DMI1RXN

Point

DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPWRDNACK/GPIO30

PWRBTN#

ACPRESENT/GPIO31

BATLOW#/GPIO72

RI#

DMI

FDI

DMI

FDI

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

System Power Management

SLP_LAN#/GPIO29

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

DSWO DVREN

PCH_DPW ROK

PM_SUS_ STAT#

SUS_CLK

PM_SLP_ S5#

PM_SLP_ A#

PM_SLP_ SUS#

H_PM_SYNC

PM_SLP_ LAN#

3

FDI_TXN[7:0 ] (4) FDI_TXP[7:0 ] (4)

FDI_TXN0 (4) FDI_TXN1 (4) FDI_TXN2 (4) FDI_TXN3 (4) FDI_TXN4 (4) FDI_TXN5 (4) FDI_TXN6 (4) FDI_TXN7 (4)

FDI_TXP0 (4 ) FDI_TXP1 (4 ) FDI_TXP2 (4 ) FDI_TXP3 (4 ) FDI_TXP4 (4 ) FDI_TXP5 (4 ) FDI_TXP6 (4 ) FDI_TXP7 (4 )

FDI_INT (4)

FDI_FSYNC0 (4)

FDI_FSYNC1 (4)

FDI_LSYNC0 (4)

FDI_LSYNC1 (4)

DY

1

PM_RSMR ST#

R1910 0R0402-P ADR19 10 0R0402-PA D

1 2

R1911 10KR2J-3 -GP

1 2

PCH_W AKE# (27)

PM_CLKR UN# (27)

TP1901 TPAD1 4-GPTP190 1 TPA D14-GP

R1913 0R0402-P ADR19 13 0R0402-PA D

1 2

TP1902 TPAD1 4-GPTP190 2 TPA D14-GP

TP1903TPAD14-GPTP1 903TPAD14-GP

TP1904TPAD14-GPTP1 904TPAD14-GP

H_PM_SYNC (5)

TP1905TPAD14-GPTP1 905TPAD14-GP

R1912

1 2

0R0402-P AD

For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)

2.DPWROK and RSMRST# will rise at the same time (connected on board)

3.SLP_SUS# and SUSACK# are left as ‘no connect’

4.SUSWARN# used as SUSPWRDNACK/GPIO30

PM_RSMR ST#

RSMRST# _KBC (27)

PCH_SUS CLK_KBC

EC1901

1 2

DY

SC4D7P50V2CN-1GP

RTC_AUX _S5

PCH_SUS CLK_KBC (27)

PM_SLP_ S4# (27,46)

PM_SLP_ S3# (27,36,37,4 7)

2

DSWODVREN - On Die DSW VR Enab le

HIGH Enabled (DEFAULT)

LOW Disabled

R1917 330KR2J-L1-G PR1917 330KR2J-L1-G P

1 2

DSWO DVREN

PM_CLKR UN#

Title

Size Document N umber Rev

Date: Sheet of

R1918 330KR2J-L1-G P

1 2

DY

R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP

1 2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH 3/9(DM I/FDI/PM)

Nirvana 13

19 1 03Tuesday, January 18, 2011

1

RTC_AUX _S5

3D3V_S0

A00

SSID = PCH

Signal Routing Guideline:

D D

DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

1D05V_V TT

R1901 49D9R2F-GPR1901 49D9R2F-GP

R1902 750R2F-GPR1902 750R2F-GP

SYS_PW ROK

R1926

XDP_DBR ESET#(5)

S0_PW R_GOOD(27,36)

PM_PW RBTN#(27)

DY

SYS_PW ROK(36)

RUNPW ROK(45,46,47 )

3D3V_S0

3D3V_S5

R1926

R1904

5

PWRO K

1 2

R1924 0R0402-P ADR19 24 0R0402-PA D

RN1901

8 7 6

SRN10KJ -6-GP

R1921

100KR2J -1-GP

R1922 10KR2J-3 -GP

R1922 10KR2J-3 -GP R1920 10KR2J-3 -GP

R1920 10KR2J-3 -GP

DY

DY DY

DY

R1908

10KR2J-3 -GP

1 2

10KR2J-3 -GP

C C

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

B B

A A

1 2

100KR2J -1-GP

PM_DRAM _PWRGD(5,37)

SUS_PW R_ACK(27)

AC_PRES ENT(2 7)

5

SSID = PCH

D D

C C

WWAN CLK

WLAN CLK

B B

USB3.0 CLK

A A

PCIE_RXN2(82)

PCIE_RXP2(82) PCIE_TXN2(82) PCIE_TXP2(82)

PCIE_RXN3(82)

PCIE_RXP3(82) PCIE_TXN3(82) PCIE_TXP3(82)

PCIE_RXN4(65)

PCIE_RXP4(65) PCIE_TXN4(65) PCIE_TXP4(65)

PCIE_RXN5(82)

PCIE_RXP5(82) PCIE_TXN5(82) PCIE_TXP5(82)

CLK_PCIE_ WWAN#(82) CLK_PCIE_ WWAN(8 2)

CLK_PCIE_ WWAN_ REQ#(82)

CLK_PCIE_ WLAN_REQ#(65)

CLK_PCIE_ LAN#(82)

LAN CLK

3D3V_S0

PCIECLKRQ1# and PCIECLKRQ2#

CLK_PCIE_ LAN(82)

PCIE_CLK_ LAN_REQ#(82)

RN2018

1 2 3

SRN10KJ -5-GP

C2001 SCD1U10 V2KX-5GPC2001 SCD1U10 V2KX-5GP

1 2

C2002 SCD1U10 V2KX-5GPC2002 SCD1U10 V2KX-5GP

1 2

C2011 SCD1U10 V2KX-5GPC2011 SCD1U10 V2KX-5GP

1 2

C2012 SCD1U10 V2KX-5GPC2012 SCD1U10 V2KX-5GP

1 2

C2005 SCD1U10 V2KX-5GPC2005 SCD1U10 V2KX-5GP

1 2

C2006 SCD1U10 V2KX-5GPC2006 SCD1U10 V2KX-5GP

1 2

C2009 SCD1U10 V2KX-5GPC2009 SCD1U10 V2KX-5GP

1 2

C2010 SCD1U10 V2KX-5GPC2010 SCD1U10 V2KX-5GP

1 2

20101224 A00: Change RN2011~RN2014 to 0402 0 ohm pad.

CLK_PCIE_ WLAN#(65) CLK_PCIE_ WLAN(65)

CLK_PCIE_ USB3#(82)

CLK_PCIE_ USB3(82)

USB3_PE GB_CLKREQ#(82)

PCIE_CLK_ RQ2#

4

CLK_PCIE_ WLAN_REQ#

Support S0 power only

5

RN2011

2 3 1

0R4P2R-P AD

RN2012

1 2 3

0R4P2R-P AD

RN2014

1 2 3

0R4P2R-P AD

RN2013

1 2 3

0R4P2R-P AD

TP2005TP AD14-GP TP200 5TPAD14-GP TP2006TP AD14-GP TP200 6TPAD14-GP

PCIE_TXN2 _C PCIE_TXP2 _C

PCIE_TXN3 _C PCIE_TXP3 _C

PCIE_TXN4 _C PCIE_TXP4 _C

PCIE_TXN5 _C PCIE_TXP5 _C

CLK_PCH _SRC0_N CLK_PCH _SRC0_P

4

RN

CLK_PCH _SRC1_N

4

CLK_PCH _SRC1_P

PCIE_CLK_ RQ2#

RN

CLK_PCH _SRC3_N

4

CLK_PCH _SRC3_P

RN

CLK_PCH _SRC4_N

4

CLK_PCH _SRC4_P

PCIE_CLK_ REQ5#

PEG_B_C LKRQ#

PCIE_CLK_ REQ6#

CLK_PCIE_ NEW_REQ#

1 1

ITPXDP_N ITPXDP_P

4

PCH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1#/GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2#/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4#/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5#/GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

COUGAR-G P-U2-NF

4

3

2 OF 10

Cougar

Cougar Point

Point

W-WAN

LAN

Card Reader

WLAN

USB3.0

PCI-E*

Intel GBE LAN

Dock

SMBALERT#/GPIO11

SMBDATA

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

Link

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_DATA1

CL_RST1#

SMBCLK

SML0CLK

CL_CLK1

EC_SW I#

E12

SMB_CLK

H14

SMB_DAT A

C9

DRAMRST _CNTRL_PCH

A12

SML0_CL K

C8

SML0_DA TA

G12

PCH_GPIO7 4

C13

SML1_CL K

E14

SML1_DA TA

M16

CL_CLK

M7

CL_DATA

T11

CL_RST#

P10

1

TP2001 TPAD1 4-GPTP200 1 TPA D14-GP

1

TP2002 TPAD1 4-GPTP200 2 TPA D14-GP

1

TP2003 TPAD1 4-GPTP200 3 TPA D14-GP

SML1_CL K (27)

SML1_DA TA (27)

NEW CARD

PEG_CLK REQ#_R

XTAL25_IN

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43

F47

H47

K49

3

CLKOUT_ PEG_A_N CLKOUT_ PEG_A_P

CLKOUT_ DMI_N CLKOUT_ DMI_P

CLK_BUF _EXP_N CLK_BUF _EXP_P

CLK_BUF _CPYCLK_N CLK_BUF _CPYCLK_P

CLK_BUF _DOT96_N CLK_BUF _DOT96_P

CLK_BUF _CKSSCD_N CLK_BUF _CKSSCD_P

CLK_BUF _REF14

CLK_PCI_F B

XTAL25_ IN XTAL25_ OUT

XCLK_RC OMP

CLK_48_ USB30

DGPU_PR SNT#

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLOCKS

– Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 – Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2 if more than 2 PCI clocks + PCI loopback are routed.

CLKOUT_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

FLEX CLOCKS

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

XTAL25_OUT

XCLK_RCOMP

1

TP2007 TPAD1 4-GPTP200 7 TPA D14-GP

1

TP2008 TPAD1 4-GPTP200 8 TPA D14-GP

1

TP2009 TPAD1 4-GPTP200 9 TPA D14-GP

RN2010

2 3 1

0R4P2R-P AD

20101224 A00: Change RN2010 to 0402 0 ohm pad.

CLK_PCI_F B (18 )

R2007

1 2

90D9R2F -1-GP

R2016

1 2

22R2J-2-G P

+VCCDIFFC LKN

2

4

PEG_CLK REQ#_R

SMB_DAT A

SMB_CLK

20110112 A00: Change C2007,C2008 to 15pF from 12pF base on vendor's report.

CLK_EXP _N (5) CLK_EXP _P (5)

EC_SW I# (27 )

DRAMRST _CNTRL_PCH (37 )

4

RN

RN2008

2 3 1

SRN10KJ -5-GP

PL 10K FOR Integrated CLOCK GEN mode.

CLK_BUF _DOT96_N CLK_BUF _DOT96_P

CLK_BUF _CKSSCD_N CLK_BUF _CKSSCD_P

CLK_BUF _EXP_N CLK_BUF _EXP_P

CLK_BUF _REF14

need very close to PCH

CLK_PCH _48M (32,97)

RN2020 SRN10 KJ-5-GPRN2020 SRN10 KJ-5-GP

1 2 3

RN2021

2 3 1

SRN10KJ -5-GP

RN2019 SRN10 KJ-5-GPRN2019 SRN10 KJ-5-GP

1 2 3

R2008

1 2

10KR2J-3 -GP

For RTS5138

2

3D3V_S5

DY

4

1

12

R2004

R2004 10KR2J-3 -GP

10KR2J-3 -GP

12

R2005

R2005 10KR2J-3 -GP

10KR2J-3 -GP

3D3V_S0

RN2007

2 3 1

SRN2K2J -1-GP

2nd = 84.DM601.03F

84.2N702.A3F

2N7002K DW-GP

6

5

Q2001

XTAL25_ IN

XTAL25_ OUT

3D3V_S0 3D3V _S0

12

R2012

12

R2010

DY

Title

Size Document N umber Rev

Date: Sheet of

SMB_CLK SMB_DAT A

SML0_DA TA SML0_CL K

SML1_CL K SML1_DA TA

PCIE_CLK_ REQ6# PCH_GPIO7 4

DRAMRST _CNTRL_PCH

4

1

2

34

X2001

R2006

R2006 1M1R2J-G P

1M1R2J-G P

2 3

1 2

10KR2J-3-GP

DY

10KR2J-3-GP

PCH 4/9(PCI-E/SMBUS/CLOCK/CL)

XTAL-25M HZ-155-GP

82.30020.D41

2nd = 82.30020.G71

2nd = 82.30020.G71 3rd = 82.30020.G61

3rd = 82.30020.G61

12

R2013

UMA_DIS# DGPU_PR SNT#

10KR2J-3-GP

12

R2011

3D3V_S5

10KR2J-3-GP

Nirvana 13

4

2 3 1

1 2 3

R2009

1 2

1KR2J-1-G P

PCH_SMB DATA (14,15,65,7 9,82)

PCH_SMB CLK (14,15,65 ,79,82)

C2008

SC15P50 V2JN-2-GP

41

C2007

SC15P50 V2JN-2-GP

UMA_DISCRETE# UMA: 1 1 DIS :0 1 SG(PX) : 0 0 ATI(Muxless) : 1 0

UMA_DIS# (22)

RN2001

1

8

2

7

3

6

4 5

SRN10KJ -6-GP

SRN10KJ -6-GP RN2002

RN2002

1 2 3 4 5

8 7 6

SRN10KJ -6-GP

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

3D3V_S5

RN2003

1

SRN2K2J -1-GP

23

RN2004

23

SRN2K2J -1-GP

1

RN2005

RN2005 SRN2K2J -1-GP

SRN2K2J -1-GP

4

RN2006

4

SRN10KJ -5-GP

12

CLK_PCIE_ WWAN_ REQ#

PCIE_CLK_ LAN_REQ# USB3_PE GB_CLKREQ#

EC_SW I# PCIE_CLK_ REQ5# CLK_PCIE_ NEW_REQ# PEG_B_C LKRQ#

20 1 03Tuesday, January 18, 2011

A00

5

SSID = PCH

RTC_X1

1 2

R2101 10MR2J-L-GPR210 1 10MR2J-L -GP

D D

12

C2101

SC15P50V2JN-2-GP

C C

X2101

1 4

X-32D768 KHZ-67-GP

82.30001.A81

2nd = 82.30001.691

3rd = 82.30001.861

HDA_COD EC_SYNC(29) HDA_COD EC_SDOUT(29)

HDA_COD EC_RST#(29) HDA_COD EC_BITCLK(29)

32

RTC_X2

12

C2102

C2102 SC15P50 V2JN-2-GP

SC15P50 V2JN-2-GP

DY

RN2102

1 2 3

SRN33J-5 -GP-U

R212233R2J-2-GP

12

R212333R2J-2-GP R212 333R2J-2-G P

12

4

HDA_SYNC HDA_SDO UT

HDA_RST # HDA_BITCL K

RTC_AUX _S5

SRN20KJ -1-GP

2 3 1

SC1U6D3 V2KX-GP

Flash Descriptor Security Overide

Low = Default High = Enable

No Reboot Strap

Low = Default High = No Reboot

HDA_SYNC

HDA_SDO UT

HDA_SPK R

HDA_SDOUT

HDA_SPKR

+3VS_+1 .5VS_HDA_IO

DY

R2102 1KR2J-1-G P

1 2

3D3V_S0

B B

NO REBOOT STRAP

DY

R2106 1KR2J-1-G P

1 2

+3VS_+1 .5VS_HDA_IO

R2103 1KR2J-1-G PR21 03 1KR2J-1-GP

This signal has a weak interna l pull down. On Die PLL VR i s supplied by 1 .5V when sampled high, 1 .8 V when sampl ed low. Needs to be pul led High for Hu ron River platf orm. co-operate with R2310

1 2

PLL ODVR VOLTAGE

HDA_SYNC

RUN_ENA BLE

A A

R2117

R2117 100KR2J -1-GP

100KR2J -1-GP

1 2

Low = 1.8V (Default) High = 1.5V

2N7002K -2-GP

G

D

S

Q2101

84.2N702.J31

2ND = 84.2N702.031

5

R2124

33R2J-2-G P

HDA_SYNCHDA_SYNC_ R

12

HDA_COD EC_BITCLK

EC2102

1 2

DY

4

20110110 A00: Merge R2115,R2116 to RN2101.

RN2101

4

C2104

12

C2103

C2103 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

21

G2101

12

GAP-OPEN

INTVRMEN- Integrated SUS

1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs

RTC_AUX _S5

HDA_SPK R(29)

HDA_SDIN0(29)

1M1R2J-G P

R2104

1 2

R2105

330KR2F -L-GP

12

3

RTC_X1

RTC_X2

RTC_RST #

SRTC_RS T#

SM_INTRUD ER#

PCH_INTVR MEN

HDA_BITCL K

HDA_SYNC

HDA_RST #

Notes: ME_UNLOCK (HDA_SDO) connect to EC. Make sure EC drive this pin "low" all the time.

R2107 1KR2J-1-G PR21 07 1KR2J-1-GP

ME_UNLO CK(27)

20100721 Modify: Remove TP2105 and change PCH_GPIO33 to CE.

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

HDA_COD EC_SDOUT

EC2103

1 2

DY

SC4D7P50V2CN-1GP

4

1 2

SPI_CLK_R(27,60)

SPI_CS0#_ R(27,60)

SPI_SI_R(27,60)

SPI_SO_R(27,60)

SPI_CS0#_ RHDA_COD EC_SYNC

EC2101

1 2

DY

HDA_SDO UT

CE(49)

TP2101TPAD14 -GP TP210 1TP AD14-GP

TP2102TPAD14 -GP TP210 2TP AD14-GP

TP2103TPAD14 -GP TP210 3TP AD14-GP

TP2104TPAD14 -GP TP210 4TP AD14-GP

1 2

R2108 33R2J-2-GPR2108 3 3R2J-2-GP

1 2

R2109 33R2J-2-GPR2109 3 3R2J-2-GP

1 2

R2110 33R2J-2-GPR2110 33R2J-2-GP

SC4D7P50V2CN-1GP

CE

PCH_JTA G_TCK_BUF

1

PCH_JTA G_TMS

1

PCH_JTA G_TDI

1

PCH_JTA G_TDO

1

PCH_SPI_C LK

PCH_SPI_C S0#

PCH_SPI_S I

S_GPIO(2 2)

3

PCH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

COUGAR-G P-U2-NF

SATA_DE T#0 INT_SERIRQ

FP_DET#(22 ) PSW_ CLR#(22)

Cougar

Cougar Point

Point

RN2103

1 2 3 4 5

SRN10KJ -6-GP

SRN10KJ -6-GP RN2104

RN2104

4

SRN10KJ -5-GP

JTAG

RTCIHDA

SPI

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ1#/GPIO23

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

3D3V_S0

8 7 6

1 23

1 OF 10

LDRQ0#

SERIRQ

C38 A38 B37 C37

D36

E36 K36

V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

2

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

SATA_DE T#0

BBS_BIT0

2

LPC_AD[0 ..3]

SATA_CO MP

SATA3_C OMP

RBIAS_SAT A3

1

LPC_AD[0 ..3] (27,65,71)

LPC_FRA ME# (27,65,71 )

KB_DET# (69)

INT_SERIRQ (27 )

SATA_RX N0 (56) SATA_RX P0 (56) SATA_TX N0 (56) SATA_TX P0 (5 6)

HDD1

HDD2

SATA_RX N4 (56) SATA_RX P4 (56) SATA_TX N4 (56) SATA_TX P4 (5 6)

SATA_RX N5 (57) SATA_RX P5 (57) SATA_TX N5 (57) SATA_TX P5 (5 7)

1D05V_V TT

R2112 37D4R2F-GPR2112 37D4R2F-GP

1 2

R2113 49D9R2F-GPR2113 49D9R2F-GP

1 2

R2114 750R2F-GPR2114 750R2F-GP

1 2

SATA_LE D# (68)

BBS_BIT0 (18)

Title

PCH 5/9(SPI/RTC/LPC/SATA/IHDA)

Size Document N umber Rev

Date: Sheet of

1D05V_V TT

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

1

21 1 03Tuesday, January 18, 2011

ODD

ESATA

A00

5

3D3V_S0

R2202

1 2

100KR2J -1-GP

3D3V_S0

RN2203

1

4

D D

GPIO27 has a we ak[20K] interna l pull up. To enable on-di e PLL Voltage r egurator, should not plac e external pull down.

C C

B B

A A

2 3

SRN10KJ -5-GP

3D3V_S0

R2220

1 2

10KR2J-3 -GP

PCH_TEM P_ALERT#

MFG_MOD E

EC_SCI#

DGPU_HP D_INTR#

EC_SMI#

DBC_EN

RTC_DET # PCH_GPIO5 7

PCH_GPIO1 5

3G_EN

PCH_GPIO4 8

R2222 10KR2J-3 -GPR2222 10 KR2J-3-GP

1 2

R2223 10KR2J-3 -GPR2223 10 KR2J-3-GP

1 2

RN2201

1 2 3 4 5

SRN10KJ -6-GP

SRN10KJ -6-GP R2214 10KR2J-3 -GP

R2214 10KR2J-3 -GP

1 2

DY

4

1 2

5

H_A20GA TE

H_RCIN#

8 7 6

RN2204

SRN10KJ -5-GP

R2201

1KR2J-1-G P

R2221

10KR2J-3 -GP

SATA_OD D_PRSNT#

3D3V_S0

3D3V_S5

1 23

Note: For PCH debug w ith XDP, need t o NO STUFF R221 8

PSW_ CLR#(21)

4

SSID = PCH

S_GPIO GPIO0

R2218

1 2

R2213 0R0402-P ADR22 13 0R0402-PA D

TP2203

PSW_ CLR#

FP_DET#(21 )

1

1 2

100R2J-2 -GP

EC_SMI#

DGPU_HP D_INTR# VRAM_SIZE 1

EC_SCI#

ICC_EN#

RTC_DET #

PCH_GPIO1 5

PCH_GPIO1 6

DBC_EN

3G_EN

PCH_GPIO2 7

1

PLL_ODV R_EN

DMI_OVRVL TG

FDI_OVRVL TG

MFG_MOD E

GSENSOR _DET

PCH_GPIO4 8

PCH_TEM P_ALERT#

PCH_GPIO5 7

PCH_NCT F_1

PCH_NCT F_2

PCH_NCT F_3

PCH_NCT F_4

S_GPIO(21)

EC_SMI#(27)

EC_SCI#(27 )

RTC_DET #(60 )

SATA_OD D_PRSNT#(56)

DBC_EN(49)

3G_EN(82 )

TPAD14-G P

GAP-OPEN

21

G2201

TP2206TPAD14 -GP TP220 6TP AD14-GP

TP2207TPAD14 -GP TP220 7TP AD14-GP

TP2208TPAD14 -GP TP220 8TP AD14-GP

TP2209TPAD14 -GP TP220 9TP AD14-GP

[VRAM_SIZE1:VRAM_SIZE2] LL=512M / HL=1G / LH=2G

4

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24/MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49

D6

GPIO57

A4

NCTF_VSS#A4

A44

NCTF_VSS#A44

A45

NCTF_VSS#A45

A46

NCTF_VSS#A46

A5

NCTF_VSS#A5

A6

NCTF_VSS#A6

B3

NCTF_VSS#B3

B47

NCTF_VSS#B47

BD1

NCTF_VSS#BD1

BD49

NCTF_VSS#BD49

BE1

NCTF_VSS#BE1

BE49

NCTF_VSS#BE49

BF1

NCTF_VSS#BF1

BF49

NCTF_VSS#BF49

COUGAR-G P-U2-NF

3

6 OF 10

A20GATE

PECI

RCIN#

INIT3_3V#

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

UMA_DIS#

VRAM_SIZE 2

TS_VSS

H_PECI_R

PCH_THE RMTRIP_R

INIT3_3V#

3D3V_S0

ICC_EN#

1 2

R2219 0R0402-P ADR22 19 0R0402-PA D

12

DY

12

DY

12

1 2

Cougar

Cougar Point

Point

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49

GPIO

BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48

CPU/MISC

NCTF

D1,D49,E1,E49,F1,F49

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

PROCPWRGD

THRMTRIP#

NCTF_VSS#BG2

NCTF_VSS#BG48

NCTF_VSS#BH3

NCTF_VSS#BH47

NCTF_VSS#BJ4

NCTF_VSS#BJ44

NCTF_VSS#BJ45

NCTF_VSS#BJ46

NCTF_VSS#BJ5

NCTF_VSS#BJ6

NCTF_VSS#C2

NCTF_VSS#C48

NCTF_VSS#D1

NCTF_VSS#D49

NCTF_VSS#E1

NCTF_VSS#E49

NCTF_VSS#F1

NCTF_VSS#F49

PLL ON DIE VR E NABLE

NOTE:This signa l has a weak in ternal pull-up 20K ENABLED -- HIGH (R2212 UNSTUFF ED) DEFAULT DISABLED -- LOW (R2212 STUFFE D)

PLL_ODV R_EN

3

1 2

DY

R2212

1KR2J-1-G P

2

SATA_OD D_PWRGT (56 )

UMA_DIS# (20)

TP2204

TPAD14-G P

1

R2207

R2207 10KR2J-3 -GP

10KR2J-3 -GP

FDI_OVRVL TG

R2208

R2208 10KR2J-3 -GP

10KR2J-3 -GP

R2209

R2209 10KR2J-3 -GP

10KR2J-3 -GP

DMI_OVRVL TG

R2210

R2210 10KR2J-3 -GP

10KR2J-3 -GP

R2211

TPAD14-G P

TP2205

TPAD14-G P

H_A20GA TE (27)

1 2

DY

H_RCIN# (27)

H_CPUPW RGD (5,36)

R2204 390R2J-1-GPR2 204 390R2J-1 -GP

1 2

TP2201

1

1KR2J-1-G P

2

1

GSENSO R_ADI GSEN SOR_ST

R2205 DY 10K

R2206 100K DY

3D3V_S0

12

GSENSOR_ST

GSENSOR _DET

R2203

0R2J-2-GP

TPAD14-G P

TS Signal Disable Guideline: TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4 should not float on the motherboard. They should be tied to GND directly.

H_PECI (5,2 7)

H_THERM TRIP# (5,36)

12

GSENSOR_ADI

FDI TERMINATION VOLTAGE OVERRI DE

GPIO37 (FDI_OVRVLTG)

LOW - Tx, Rx te rminated to sam e voltage (DC Coupling Mo del DEFAULT)

DMI TERMINATION VOLTAGE OVERRI DE

GPIO36 (DMI_OVRVLTG)

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

LOW - Tx, Rx te rminated to sam e voltage (DC Coupling Mo del DEFAULT)

Integrated Cloc k Chip Enable

ICC_EN#

HIGH (R2211 DY) - DISABLED [DEF AULT]

LOW (R2211)- E NABLED

GPIO8 has a wea k[20K] internal pull up.

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

PCH 6/9(GPIO/CPU)

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

22 1 03Tuesday, January 18, 2011

1

R2205

10KR2J-3 -GP

R2206

100KR2J -1-GP

A00

5

4

3

2

1

SSID = PCH

D D

C C

B B

VCCVRM(Internal PLL and VRMs): A.1.5V for Mobile B.1.8 V for Desktop

(1uFx3)

(10uFx1_0603)

(1uF x4)

0.159A(Totally current of VCCVRM)

6A

1D05V_V TT

2.925A(Total current of VCCIO)

12

C2305

0.266A (Totally VCC3_3 current)

0.042A (Totally current of VCCDMI)

1.3A

12

SC10U6D3V5KX-1GP

C2301

SC10U6D3V5KX-1GP

C2306

SC1U6D3V2KX-GP

(0.1uF x1)

1D5V_S0

12

C2302

TP2301TPAD14 -GP TP230 1TP AD14-GP

12

C2307

TP2302TPAD14 -GP TP230 2TP AD14-GP

1D05V_V TT

SC1U6D3V2KX-GP

1D05V_V TT

SC1U6D3V2KX-GP

3D3V_S0

12

1

12

1

C2303

(10uF x1)

C2308

12

C2304

SC1U6D3V2KX-GP

VCCAPLL EXP

12

C2309

SC1U6D3V2KX-GP

12

C2310

C2310 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

VCCFDIPLL

+1.05VS_ VCC_DMI

PCH1G

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO

BJ22

VCCAPLLEXP

AN16

VCCIO

AN17

VCCIO

AN21

VCCIO

AN26

VCCIO

AN27

VCCIO

AP21

VCCIO

AP23

VCCIO

AP24

VCCIO

AP26

VCCIO

AT24

VCCIO

AN33

VCCIO

AN34

VCCIO

BH29

VCC3_3

AP16

VCCVRM

BG6

VCCAFDIPLL

AP17

VCCIO

AU20

VCCDMI

COUGAR-G P-U2-NF

POWER

Cougar

Cougar Point

Point

VCC CORE

VCCIO

FDI

20101228 A00: 0402 0R pad: R2301.

7 OF 10

VCCADAC

VSSADAC

CRTLVDS

0.001A

U48

U47

(0.1uF/0.01uF x 1) (10uF x1_0603)

+VCCA_D AC_1_2

12

C2313

0.001A

+3VS_VC CA_LVDS

VCC3_3

VCCVRM

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

0.06A

+1.8VS_V CCTX_LVDS

0.266A

12

0.16A

VCCALVDS

VSSALVDS

VCCTX_LVDS

0.042A

VCCDMI

DMI

VCCCLKDMI

AB36

12

+1.05VS_ VCC_DMI

AT20

0.02A

+1.05VS_ VCC_DMI_CCI

VCCSPI

AG16

AG17

AJ16

AJ17

V1

VccDFTERM

NAND / SPI HVCMOS

0.19A

12

C2322

C2322 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

0.02A

12

3D3V_DA C_S0

12

C2314

SCD01U16V2KX-3GP

12

C2316

(0.1uFx1)

C2319

C2319 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

VCCVRM

R2306

0R0402-P AD

0.02A

0R0402-P AD

R2307

0R0402-P AD

C2320

C2320 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

C2321

C2321 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

C2323

C2323 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

SCD1U10V2KX-5GP

0.06A

SCD01U16V2KX-3GP

0.19A

12

C2315

12

R2308

0R0402-P AD

12

0.02A

(1uFx1)

R2301

R2301 0R0402-P AD

0R0402-P AD

L2301

1 2

DY

HCB1608 KF-181-GP

68.00214.051

2nd = 68.00206.041

3rd = 68.00335.081

0.001A

SC10U6D3V5KX-1GP

C2317

12

C2318

SCD01U16V2KX-3GP

3D3V_S0

12

1D05V_V TT

R2304

1 2

0R0603-P AD

R2305

1 2

0R0805-P AD

SC10U6D3V5KX-1GP

20101224 A00: 0402 0R pad: R2301,R2306,R2307,R2308.

1D5V_S0

(1uF x1)

1D05V_V TT

(1uFx1) (10uFx1)

1D8V_S0

(0.1uFx1)

3D3V_S5

3D3V_S0

1D8V_S0

(0.01uF x2) (22uF x1)

3.3V CRT LDO

5V_S5 3D3V_DA C_S0

3D3V_S0

U2301

1

VIN

2

GND EN3NC#4

G9091-33 0T11U-GP

74.09091.J3F

2nd = 74.09198.G7F

3rd = 74.07716.A7F

A A

5

C2311

12

SC1U10V2KX-1GP

4

VOUT

5

4

Current Limit=360mA

12

C2312

SC1U6D3V2KX-GP

3

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

2

Date: Sheet of

PCH 7/9(POWER1)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

A00

23 1 03Wednesday, December 29, 20 10

1

A00

5

4

3

2

1

SSID = PCH

1

TP2405TPAD14 -GP TP240 5TP AD14-GP

1

(10uFx1)

1

12

C2415

12

VCCACLK

+VCCPDS W

DCPSUSB YP

1

+V3.3S_V CC_CLKF33

+VCCAPL L_CPY_PCH

+VCCSUS 1

12

C2407

SC1U6D3V2KX-GP

1D5V_S0

+1.05VS_ VCCA_A_DPL

+1.05VS_ VCCA_B_DPL

+VCCDIFFC LK

(1uFx1)

0.095A

+V1.05S_ SSCVCC

(1uFx1)

+VCCSST

12

TP2406TPAD14 -GP TP240 6TP AD14-GP

1

C2418

SCD1U10V2KX-5GP

12

C2421

SCD1U10V2KX-5GP

C2408

SC1U6D3V2KX-GP

DCPSUS

C2422

SCD1U10V2KX-5GP

TP2401TPAD14 -GP TP240 1TP AD14-GP

0.002A

3D3V_S0

(10uFx1)

(1uFx1) (220uFx1)

SC10U6D3V3MX-GP

C2412

C2413

(1uFx1)

+V3.3S_V CC_CLKF33

C2401

12

C2402

C2402 SC1U10V 2KX-1GP

SC1U10V 2KX-1GP

SC10U6D3V5KX-1GP

1D05V_V TT

(22uFx2_0603) (1uFx3)

12

C2409

C2409 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

(1uFx1) (220uFx1)

12

C2410

C2410 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

SCD1U10 V2KX-5GP

1D05V_V TT

(1uFx1)

D D

C C

1D05V_V TT

B B

1D05V_V TT

A A

L2401

1 2

IND-10UH-21 8-GP

68.10050.10Y

2nd = 68.10090.10B

L2402

L2403

R2404

0R0402-P AD

R2405

0R0402-P AD

12

0.08A

C2443

DY

0.08A

C2444

DY

1 2

IND-10UH-21 8-GP

68.10050.10Y

2nd = 68.10090.10B

1 2

IND-10UH-21 8-GP

68.10050.10Y

2nd = 68.10090.10B

20101224 A00: 0402 0R pad: R2404,R2405.

+1.05VS_ VCCA_A_DPL

12

+1.05VS_ VCCA_B_DPL

12

+VCCDIFFC LK

12

SC1U6D3 V2KX-GP

+V1.05S_ SSCVCC

12

SC1U6D3 V2KX-GP

5

3D3V_S5

(0.1uFx1)

C2403

DY

SC10U6D3V5KX-1GP

12

C2411

R2406

1 2

0R0603-P AD

SC1U6D3 V2KX-GP

12

(0.1uFx1)

(1uFx1)

1D05V_V TT

0.001A

(0.1uFx2) (4.7uFx1_0603)

SC4D7U6 D3V3KX-GP

RTC_AUX _S5

6uA

(0.1uFx2) (1uFx1)

1.01A (Total current of VCCASW)

C2404

SC10U6D3V5KX-1GP

+VCCRTC EXT

(0.1uFx1)

C2414

C2417

R2403

1 2

0R0603-P AD

TP2404TPAD14 -GP TP240 4TP AD14-GP

1D05V_V TT

TP2402TPAD14 -GP TP240 2TP AD14-GP

12

C2406

SC1U6D3V2KX-GP

0.16A (Totally current of VCCVRM

+VCCDIFFC LKN

0.055A

12

SCD1U10 V2KX-5GP

12

4

PCH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3

BH23

VCCAPLLDMI2

AL29

VCCIO

AL24

DCPSUS

AA19

VCCASW

AA21

VCCASW

AA24

VCCASW

AA26

VCCASW

AA27

VCCASW

AA29

VCCASW

AA31

VCCASW

AC26

VCCASW

AC27

VCCASW

AC29

VCCASW

AC31

VCCASW

AD29

VCCASW

AD31

VCCASW

W21

VCCASW

W23

VCCASW

W24

VCCASW

W26

VCCASW

W29

VCCASW

W31

VCCASW

W33

VCCASW

N16

DCPRTC

Y49

VCCVRM

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO

AF33

VCCDIFFCLKN

AF34

VCCDIFFCLKN

AG34

VCCDIFFCLKN

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS

V19

DCPSUS

BJ8

V_PROC_IO

A22

VCCRTC

COUGAR-G P-U2-NF

POWER

Cougar

Cougar Point

Point

Clock and Miscellaneous

CPURTC

PCI/GPIO/LPCMISC

SATA USB

HDA

3

10 OF 10

VCCIO

VCCSUS3_3

VCCIO

V5REF_SUS

DCPSUS

VCCSUS3_3

V5REF

VCCSUS3_3

VCC3_3

VCCIO

VCCAPLLSATA

VCCVRM

VCCIO

VCCASW

VCCSUSHDA

N26

P26

P28

T27

T29

0.097A (Totally current of VCCSUS3_3)

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

1D05V_V TT

+5VA_PC H_VCC5REFSUS

+VCCA_U SBSUS

+5VS_PC H_VCC5REF

SC1U6D3 V2KX-GP

SCD1U10 V2KX-5GP

SC1U6D3 V2KX-GP

+V1.05S_ VCCAPLL_SATA 3

1D5V_S0

1D05V_V TT

SC1U6D3 V2KX-GP

0.01A

C2433

SCD1U10 V2KX-5GP

C2433

3D3V_S5

12

DY

12

C2428

12

C2430

12

C2429

12

C2432

12

C2435

+3VS_+1 .5VS_HDA_IO

(0.1uFx1)

12

C2424

C2424 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

C2434

DY

C2423

C2423 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

C2425

C2425 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

1

C2437

C2437 SC1U10V 2KX-1GP

SC1U10V 2KX-1GP

SC10U6D3V5KX-1GP

2

(1uFx1)

(0.1uFx1)

TP2403 TPAD14-GPTP2 403 TPAD14-GP

0.001A

3D3V_S5

(1uFx1)

12

C2431

C2431 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

(0.1uFx1)

R2411

1 2

DY

0R3J-0-U-G P

1D05V_V TT

(1uFx1)

1D05V_V TT

3D3V_S5

2nd = 83.R2004.B8F

21

D2401

D2401 CH751H-4 0PT-GP

CH751H-4 0PT-GP

83.R0304.A8F

1 2

10R2J-2-G P

12

C2426

C2426 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

R2408

(0.1uFx1)

0.001A

3D3V_S0

21

D2402

D2402 CH751H-4 0PT-GP

CH751H-4 0PT-GP

83.R0304.A8F

2nd = 83.R2004.B8F

3D3V_S0

(0.1uFx2)

3D3V_S0

1D05V_V TT

(1uFx1)

1D05V_V TT

(10uFx1)

+3VS_+1 .5VS_HDA_IO

Title

Size Document N umber Rev

Date: Sheet of

83.R0304.A8F

R2407

1 2

(1uFx1)

10R2J-2-G P

12

C2427

C2427 SC1U10V 2KX-1GP

SC1U10V 2KX-1GP

R2409

1 2

0R0603-P AD

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH 8/9(POWER2)

Nirvana 13

1

5V_S5

5V_S0

3D3V_S5

A00

24 1 03Friday, December 24, 20 10

A00

5

4

3

2

1

SSID = PCHSSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS

AA17

VSS

AA2

VSS

AA3

VSS

AA33

VSS

AA34

VSS

AB11

VSS

AB14

VSS

AB39

VSS

AB4

VSS

AB43

VSS

AB5

VSS

AB7

VSS

AC19

VSS

AC2

VSS

AC21

VSS

AC24

VSS

AC33

VSS

AC34

VSS

AC48

VSS

AD10

VSS

AD11

VSS

AD12

VSS

AD13

VSS

AD19

VSS

AD24

VSS

AD26

VSS

AD27

VSS

AD33

VSS

AD34

VSS

AD36

VSS

AD37

VSS

AD38

VSS

AD39

VSS

AD4

VSS

AD40

VSS

AD42

VSS

AD43

VSS

AD45

VSS

AD46

VSS

AD8

VSS

AE2

VSS

AE3

VSS

AF10

VSS

AF12

VSS

AD14

VSS

AD16

VSS

AF16

VSS

AF19

VSS

AF24

VSS

AF26

VSS

AF27

VSS

AF29

VSS

AF31

VSS

AF38

VSS

AF4

VSS

AF42

VSS

AF46

VSS

AF5

VSS

AF7

VSS

AF8

VSS

AG19

VSS

AG2

VSS

AG31

VSS

AG48

VSS

AH11

VSS

AH3

VSS

AH36

VSS

AH39

VSS

AH40

VSS

AH42

VSS

AH46

VSS

AH7

VSS

AJ19

VSS

AJ21

VSS

AJ24

VSS

AJ33

VSS

AJ34

VSS

AK12

VSS

AK3

VSS

COUGAR-G P-U2-NF

Cougar

Cougar Point

Point

8 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS

AY42

VSS

AY46

VSS

AY8

VSS

B11

VSS

B15

VSS

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

F45

VSS

BB12

VSS

BB16

VSS

BB20

VSS

BB22

VSS

BB24

VSS

BB28

VSS

BB30

VSS

BB38

VSS

BB4

VSS

BB46

VSS

BC14

VSS

BC18

VSS

BC2

VSS

BC22

VSS

BC26

VSS

BC32

VSS

BC34

VSS

BC36

VSS

BC40

VSS

BC42

VSS

BC48

VSS

BD46

VSS

BD5

VSS

BE22

VSS

BE26

VSS

BE40

VSS

BF10

VSS

BF12

VSS

BF16

VSS

BF20

VSS

BF22

VSS

BF24

VSS

BF26

VSS

BF28

VSS

BD3

VSS

BF30

VSS

BF38

VSS

BF40

VSS

BF8

VSS

BG17

VSS

BG21

VSS

BG33

VSS

BG44

VSS

BG8

VSS

BH11

VSS

BH15

VSS

BH17

VSS

BH19

VSS

H10

VSS

BH27

VSS

BH31

VSS

BH33

VSS

BH35

VSS

BH39

VSS

BH43

VSS

BH7

VSS

D3

VSS

D12

VSS

D16

VSS

D18

VSS

D22

VSS

D24

VSS

D26

VSS

D30

VSS

D32

VSS

D34

VSS

D38

VSS

D42

VSS

D8

VSS

E18

VSS

E26

VSS

G18

VSS

G20

VSS

G26

VSS

G28

VSS

G36

VSS

G48

VSS

H12

VSS

H18

VSS

H22

VSS

H24

VSS

H26

VSS

H30

VSS

H32

VSS

H34

VSS

F3

VSS

COUGAR-G P-U2-NF

3

Cougar

Cougar Point

Point

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

PCH 9/9(VSS)

Nirvana 13

1

A00

25 1 03Wednesday, December 22, 20 10

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

26 1 03Wednesday, December 22, 20 10

of

26 1 03Wednesday, December 22, 20 10

of

26 1 03Wednesday, December 22, 20 10

A00

5

SSID = KBC

3D3V_AUX_KBC

1 2

12

D D

20101228 A00: VGA_THRM change to USB_PWR_EN. 20101229 A00: Rename USB_PWR_EN to USB3_PWR_ON.

C C

AFTP2701AFTP2701 AFTP2702AFTP2702 AFTP2703AFTP2703

R2771

R2771 2D2R3-1-U- GP

2D2R3-1-U- GP

12

C2701

SC2D2U10V3KX-1GP

C2704

SCD1U10V2KX-5GP

R2702

1 2

0R0603-PAD

12

DY

USB_PWR _EN#

1

AC_PRESENT

1

E51_TxD

1

C2705

SCD1U10V2KX-5GP

EC_AGND

12

C2706

SCD1U10V2KX-5GP

AC_PRESENT(19)

12

C2707

C2714 SCD1U10V2KX-5GPC2714 SCD1U10V2KX-5GP

SUS_PWR _ACK(19)

USBCHARG ER_CB0(57)

BATT_WH ITE_LED#(68)

S5_ENABLE(36)

LID_CLOSE#(70)

RSMRST#_KBC( 19)

PM_SLP_S4#(19,46)

ME_UNLOCK(21)

WIFI_RF_EN(65) BLUETOOTH _EN(63,65) S0_PWR_GO OD(19 ,36)

TP_LOCK_LED#(68)

USB_PWR _EN#(61)

IMVP_PWRGD(36,42)

EC_AGND

C2708

SCD1U10V2KX-5GP

AD_IA(40)

1 2

PSID_EC(38)

CPU_THR M(28)

FAN1_DAC(28)

LCD_TST( 49)

USB3_PWR _ON(62,82) SYS_THRM(28)

CAP_LED(69)

MEDIA_BTN3#(82)

BAT_IN#(39)

RCID( 38)

12

C2710

C2709

SC2D2U10V3KX-1GP

PCB_VER_AD

MEDIA_BTN2#

USB3_PWR _ON

PSL_IN2 MODEL_ID_DET

ECSMI#_KBC

PSL_IN1 PSL_OUT EC_GPIO72

KBC_VCORF

C2712

C2712 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

SCD1U10V2KX-5GP

3D3V_AUX_KBC _VCC

U2701A

104

VREF

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

79

GPIO2

95

GPIO3/AD6

96

GPIO4/AD5

108

GPIO5/AD4

93

PSL_IN2#_GPIO6

94

GPIO7/AD7

114

GPIO16

6

GPIO24

109

GPIO30

14

GPIO34/CIRRXL

15

GPIO36

80

GPIO41

17

GPIO42/TCK

20

GPIO43/TMS

21

GPIO44/TDI

23

GPIO46/CIRRXM/TRST#

26

GPIO51

73

PSL_IN1_GPIO70

74

PSL_OUT_GPIO71

75

VBKUP

82

GPIO75

83

GPO76/SHBM

84

GPIO77

91

GPIO81

110

GPO82/IOX_LDSH/TEST#

112

GPIO84/IOX_SCLK/XORTR#

107

GPIO97

44

VCORF

NPCE795PA0DX -GP-U

VCC19VCC46VCC76VCC88VCC

GND18GND45GND78GND89GND

VBAT

115

GND

5

116

ROSA Multi GPIO setting

R2711 0R0402-PADR2711 0R0402-PAD

C2719 SCD1U10V2KX- 5GP

CPU_THR M

SYS_THRM

L_BKLT_EN(17)

B B

KBC_PWR BTN#(68)

A A

12

DY

C2721 SCD1U10V2KX- 5GP

12

DY

EC_AGND

1 2

R2761 0R0402-PADR2761 0R0402-PAD

BAT54CPT-GP

3

D2702

2ND = 83.00054.Q81

83.R2003.E81

AC_IN#_KBC

PANEL_BLEN

PSL_IN2

1

83.R2003.E81

2ND = 83.00054.Q81

2

KBC_ON#

2

10mW

1

BAT54CPT-GP

5

R2704

1 2

D2703

3

EC_GPIO72

330KR2J-L1-GP

KBC_ON#_R

AC_IN# (40)

EC_SWI#( 20)

EC_SCI#(22)

EC_SWI#(20)

EC_SCI#( 22)

3D3V_AUX_S5 3D3V _AUX_S5

RN2706

1

4

KBC_ON#_GAT E

23

SRN10KJ-5-G P

C2713

SCD1U10V2KX- 5GP

D2701

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

D2704

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

20101224 A00: 0402 0R pad: R2758,R2759.

C2722

1 2

SCD1U10V2KX- 5GP

G

12

DY

2N7002K-2-GP

G

S

Q2706

84.2N702.J31

2ND = 84.2N702.031

102

4

VDD

AVCC

GPIO11/CLKRUN#

GPIO65/SMI#

ECSCI#/GPIO54

GPIO10/LPCPD#

GPIO67/PWUREQ#

GPIO85/GA20

KBRST#/GPIO86

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1

GPIO17/SCL1

GPIO22/SDA1

GPIO73/SCL2

GPIO74/SDA2

GPIO23/SCL3

GPIO31/SDA3

GPIO47/SCL4

GPIO53/SDA4

F_SDI/F_SDIO1

F_SDIO/F_SDIO0

1 2

EC_AGND

ECSWI#_KBC

3

ECSCI#_KBC

3

ECSWI#_KBC

R2758

12

0R0402-PAD

ECSCI#_KBC

R2759

12

0R0402-PAD

S

Q2703

G

DMP2130L-7-GP

D

2ND = 84.03413.A31

D

84.02130.031

3D3V_AUX_KBC

S5_ENABLE

D

4

3D3V_S0

C2702

SCD1U10V2KX- 5GP

1 OF 2

PLT_RST#_EC

7

LRESET#

2

LCLK

3

LFRAME#

1

LAD3

128

LAD2

127

LAD1

126

LAD0

125

SERIRQ

8 9 29 124 123 121 122

27 25 11 10 71 72

70 69 67 68 119 120 24 28

EC_SPI_CS#_C

90

F_CS0#

EC_SPI_CLK_C

92

F_SCK

EC_SPI_DI_C

86

EC_SPI_DO_C

87

AGND

103

NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connection.

EC_AGND

4

3

3D3V_AUX_KBC

20101224 A00 Modify:

12

C2703

DY

SC2D2U10V3KX- 1GP

SCD1U10V2KX- 5GP

C2711

DY

1 2

SC220P50V2KX-3GP

R2735

12

0R0402-PAD

CLK_PCI_KBC (18)

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

PANEL_BLEN

ECSCI#_KBC

ECSWI#_KBC

AD_IA_HW2

MEDIA_BTN1#

EC_ENABLE#_1

PROCHOT _EC

NOTE: Locate resistors R2719 and R2722 close to the NPCE791L.

LPC_FRAME# (21,65,71)

INT_SERIRQ (21) PM_CLKRUN # (19)

HDMI_IN# (51)

H_A20GATE (22) H_RCIN# (22)

BLON_OUT ( 49)

AD_IA_HW2 (40)

PCH_WA KE# (19)

TPDATA (69) TPCLK (69)

BAT_SCL (39,40) BAT_SDA (39,40) SML1_CLK (20) SML1_DATA (20)

PM_LAN_ENABLE (82)

LCD_TST_EN (49)

33R2J-2-GPR2736 33R2J -2-GPR2736

12

33R2J-2-GPR2719 33R2J -2-GPR2719

12

R2737 0R0402-PADR2737 0R0402-PAD

12

R2722 33R2J-2-GPR2722 33R2J -2-GP

12

EC_GPIO47 High Active

PROCHOT _EC

12

R2732

2ND = 84.2N702.031

100KR2J-1-GP

G

S

2N7002K-2-GP

84.2N702.J31

Change R2724 to 47K from 33K.

PCB_VER_AD

PLT_RST# (5,18,65,71,82)

LPC_AD[0..3] (21,65,71)

<------ TP

Q2702

12

C2717

DY

1 2

EC_AGND

<------ BATTERY / CHARGER <------PCH / eDP

20101224 A00: 0402 0R pad: R2737,R2735.

SPI_CS0#_R (21,60) SPI_CLK_R (21,60)

SPI_SO_R (2 1,60)

SPI_SI_R (21,60)

12

H_PROCHO T#_EC

D

PSL SOLUTION

R2756

EC_GPIO72

1 2

0R0402-PAD

AC_OK

DY

R2767

1 2

G

DY

S

2N7002K-2-GP

84.2N702.J31

1 2

DY

AC_OK(40)

PSL_OUT

2ND = 84.2N702.031

NOTES: Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD.

R2768

0R2J-2-GP

0R2J-2-GP Q2705

Q2705

D

PSL_IN1

KBC_ON#_R

DY

12

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

R2724

R2724 47KR2F-GP

47KR2F-GP

R2726

R2726 100KR2F-L1-GP

100KR2F-L1-GP

X01

X02

A00

Reserved

Reserved 1.65V

100.0KX00

100.0K 33.0K

100.0K 2.24V

100.0K

Reserved 100.0K 215.0K 1.048V

NOTES: The NPCE795P GPIO/PWM outputs that are connected to LEDs have high drive buffers (20mA) and can be connected directly to the LEDs.

FAN_TACH 1(28)

PM_PWRBT N#(19)

PCIE_WAKE#(82) PM_SLP_S3#(19,36,37,47)

CHG_AMBER_L ED#(68)

KBC_BEEP(29)

MEDIA_LED1#(82)

KB_BL_CTRL(69)

AD_IA_HW(40) MEDIA_LED3#(82) MEDIA_LED2#(82)

PWRLED #(68)

E51_RxD(65)

E51_TxD(65)

AMP_MUTE#(29)

PCH_SUSCL K_KBC(19)

R2721 43R 2J-GPR2721 43R2J- GP

1 2 1 2

R2720 0R0402-PADR2720 0R0402-PAD

Need very close to EC

EC_SPI_DI_C

R2773

R2773 100KR2J-1-GP

100KR2J-1-GP

1 2

R2733 0R0402-PADR2733 0R0402-PAD

1D05V_VTT

H_PROCHO T# (5,40,42)

H_PECI(5,22)

PURE_HW _SHUTDOW N#(28,36)

10mW SOLUTION

R2769

R2769 100KR2J-1-GP

100KR2J-1-GP

3D3V_AUX_KBC

3D3V_AUX_KBCRTC_AUX_S5

R2734

1 2

DY

R2763

AC_IN#_KBC

1 2

0R0402-PAD

EC_ENABLE#_1

2ND = 84.2N702.031

20101228 A00: Change R2756,R2763,R2766 to 0R short pad.

3

G

S

2N7002K-2-GP

84.2N702.J31

R2766

1 2

0R0402-PAD

VBACKUP

EC_GPIO72

0R2J-2-GP

PSL_IN1

Q2704

10mW

PSL_IN1

PSL_OUT

KBC_ON#

D

KBC_ON#_RKBC_ON#

ECRST#

C2716

3D3V_AUX_S5

12

2

10.0K

20.0K

47.0K

64.9K

76.8

100.0K

143.0K100.0K 1.358VReserved

174.0KReserved 100.0K

PECI

EC_VTT

12

SCD1U16V2KX-3GP

R2705

R2705 10KR2J-3-GP

10KR2J-3-GP

3.0V

2.75V100.0K

2.48V

2.0V

1.87V

1.204V

U2701B

31

GPIO56/TA1

117

GPIO20/TA2

63

GPIO14/TB1

64

GPIO01/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

81

GPIO66/G_PWM

66

GPIO33/H_PWM

22

GPIO45/E_PWM

16

GPIO40/F_PWM

85

VCC_POR#

113

GPIO87/CIRRXM/SIN_CR

111

GPIO83/SOUT_CR/TRIST#

30

GPIO55/CLKOUT/IOX_DIN_DIO

77

GPIO00/EXTCLK

13

PECI

12

VTT

NPCE795PA0DX -GP-U

E

B

Q2701

C

2nd = 84.03906.F11

C2718

KBSOUT15/GPIO61/XOR_OUT

ECRST#

12

C2715

MMBT3906-4-GP

DY

84.T3906.A11

KBSOUT9/SDP_VIS# KBSOUT10/P80_CLK KBSOUT11/P80_DAT

EC GPIO standard PH/PL

RN2701

4

8 7 6

2

RN2701

SRN4K7J-8-G P

RN2703

SRN100KJ-6-G P

RN2705

SRN10KJ-6-G P

1 2

FAN_TACH 1(28 )

BAT_SCL BAT_SDA

BAT_IN# AC_IN#_KBC

S5_ENABLE ECRST#

EC_ENABLE#_1

E51_RxD

BLUETOOTH _EN

FAN_TACH 1

3D3V_AUX_KBC

MODEL_ID_DET

DY

1 2

EC_AGND

SCD1U10V2KX-5GP

2 OF 2

KBSOUT0/JENK#

KBSOUT1/TCK KBSOUT2/TMS

KBSOUT3/TDI

KBSOUT4/JEN0#

KBSOUT5/TDO

KBSOUT6/RDY#

KBSOUT7 KBSOUT8

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

GPIO60/KBSOUT16 GPIO57/KBSOUT17

KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7

SC1U6D3V2KX-GP

23 1

1 23

1 2 3 45

R2712 10KR2J-3-GPR2712 10KR 2J-3-GP

DY

R2708 10KR2J-3-GP

DY

R2709 10KR2J-3-GP

12

R2710

R2710 143KR2F-GP

143KR2F-GP

12

R2739

R2739 100KR2F-L1-GP

100KR2F-L1-GP

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

54 55 56 57 58 59 60 61

3D3V_AUX_KBC

3D3V_S0

1

MODEL_ID_DET(GPIO07)

DQ15_ATI

DQ15_NVIDIA

DN15_UMA

DN15_ATI

Reserved

DN13_UMA

DN13_ATI

DQ15_Ventura 100.0K 215.0K 1.048V

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

100.0KDQ15_UMA 3.0V

100.0K

10.0K(64.10025.6DL)

20.0K(64.20025.6DL)

33.0K

47.0K(64.47025.6DL)

64.9K(64.64925.6DL)

76.8K

100.0K

143.0K100.0K 1.358V

174.0K100.0K

Notes: The total SPI interface signal between EC and PCH can’t not exceed 6500mil. The mismatch between SPI signal must be within 500mil

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16

USB_DET#

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

KCOL[0..16] (69)

KROW[0..7] (69)

D2705

EC_SMI#(2 2)

EC_SMI# ECSMI#_KBC

1

2

BAS16-6-GP

2ND = 83.00016.F11

20101224 A00: 0402 0R pad: R2760.

R2760

12

0R0402-PAD

3

DY

83.00016.K11

ECSMI#_KBC

MEDIA BUTTON CONTROL

USB_DET#

MEDIA_BTN1#

MEDIA_BTN2#

MEDIA_BTN3#

PCIE_WAKE#

INSTANT_ON#( 82)

USBDET_CO N#(57)

DATA_RECO VERY#(82)

Title

KBC Nuvoton NPCE785P

Size Documen t Number Rev

A2

Date: Sheet of

Date: Sheet

INSTANT_ON#

USBDET_CO N#

DATA_RECO VERY#

Nirvana 13

1 2

R2772 100KR2J-1-GPR2772 100KR2J-1-GP

1 2

R2770 100KR2J-1-GPR2770 100KR2J-1-GP

1 2

R2774 100KR2J-1-GPR2774 100KR2J-1-GP

1 2

R2775 100KR2J-1-GPR2775 100KR2J-1-GP

1 2

R2776 100KR2J-1-GPR2776 100KR2J-1-GP

3

1

3D3V_AUX_KBC

BAT54CPT-GP

MEDIA_BTN1#

1

83.R2003.E81

2ND = 83.00054.Q81

KBC_ON#_R

2

D2706

BAT54CPT-GP

USB_DET#

1

83.R2003.E81

2ND = 83.00054.Q81

KBC_ON#_R

2

D2707

BAT54CPT-GP

MEDIA_BTN2#

1

3

2ND = 83.00054.Q81

2

D2708

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

27 103Tuesday, January 18, 2011

2.75V100.0K

2.48V100.0K

2.24V

2.0V

1.87V

1.65V

1.204V

83.R2003.E81

KBC_ON#_R

of

A00

5

4

3

2

1

SSID = Thermal

D D

C C

B B

12

DY

R2808

R2808 NTC-100K -8-GP

NTC-100K -8-GP

3D3V_DA C_S0

84.03904.L06

2nd = 84.03904.P11

3rd = 84.03904.T11

2.System Sensor, Put on palm rest

12

C2802

SCD1U10V2KX-5GP

Layout notice : Both DXN and DX P routing 10 mi l trace width and 10 mil spacing .

Q2801

3

1

2

PMBS3904-1-GP

SCD1U10V2KX-5GP

12

C2806

C2806 SC470P5 0V3JN-2GP

SC470P5 0V3JN-2GP

Thermal sensor P2800

3D3V_DA C_S0

12

R2803

R2803 107KR2F -GP

107KR2F -GP

P2800A1

87.1 Degree

12

C2805

SCD1U10V2KX-5GP

5 6 7 8

1.H/W T8 Shutdown

P2800_D XP

P2800_D XN

ADJ

R2804

R2804 226KR2F -GP

226KR2F -GP

P2800A1

12

C2807

C2807 SC2200P 50V2KX-2GP

SC2200P 50V2KX-2GP

THERM_S YS_SHDN#_OTZ ADJ

P2800A1

P2800EA 1-GP

VCC

TDR

DXP

TDL

DXN

GND

OTZ

ADJ

U2801

74.02800.A71

20101224 A00 Modify: If stuff P2800EA1 then must stuff R2803,R2804 C2805 but if stuff P28003B0 should be un-stuff.

4 3 2 1

SYS_THRM (27) CPU_THR M (2 7)

FAN_TAC H1(2 7)

PURE_HW _SHUTDOW N#(27,36)

R2807 0R0402-P ADR28 07 0R0402-PA D

AFTP280 1AFTP2801

AFTP280 2AFTP2802

1 2

FAN_TAC H1_C

1

FAN_VCC

1

THERM_S YS_SHDN#_OTZ

Fan controller

R2802 0R2J-2-GP

1 2

DY

5V_S0

FAN1_DA C(27)

For linear FAN

12

C2811

DY

SCD1U10V2KX-5GP

FAN_VCC

*Layout* 10 mil

FAN_TAC H1_C

*Layout* 15 mil

12

C2808

C2809

DY

SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP

R2805

1 2

0R2J-2-GP

Q2802

D

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

U2802

FON#

1

FON#

2

VIN

3

VO

4

VSET

G991P11 U-GP

74.00991.031

2nd = 74.02793.A31

3rd = 74.05606.A71

FAN_VCCFAN_VCC

21

D2802

12

C2810

CH551H-3 0PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

THERM_S YS_SHDN#

S

G

0629 Modify

DY

3D3V_S0

20101228 A00 Modify: Un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805 at X-Build.

GND GND GND GND

SC2200P50V2KX-2GP

12

8 7 6 5

3 2

1

R2809

R2809 100KR2J -1-GP

100KR2J -1-GP

5V_S0

12

C2803

C2804

SC4D7U6D3V3KX-GP

FAN1

5

4

ACES-CON 3-11-GP

20.F0772.003

2nd = 20.F1841.003

SCD1U10V2KX-5GP

RSET = 0.0012T 2 — 0.9308T + 96.147 T=87 ; RSET=24.25ohm

R2806

24K3R2F -1-GP

1 2

DY

U2805_3THERM_S YS_SHDN#

1 2

DY

R2812 0R2J-2-GP

U2805

1

SET

2

GND

DY

OUT#3HYST

G709T1U F-GP

74.00709.A7F

VCC

R2801

DY

U2805_5U2805_1

5

12

4

DY

U2805_4

0R2J-2-GP

150R2F-1 -GP

C2817

SCD1U10 V2KX-5GP

0R2J-2-GP

R2811

12

DY

R2810

DY

Hysterisis is 1 0°C for HYST = VCC, 2°C for HY ST = GND.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

THERMAL P2800 / Fan control

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

THERMAL P2800 / Fan control

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

12

3D3V_S0

12

1

3D3V_DA C_S0

of

28 1 03Tuesday, January 18, 2011

A00

5

SSID = AUDIO

D D

3D3V_S0

Close to codec

12

C2902

C2903

1 2

SC1U6D3V2KX-GP

C C

C2902

C2904

1 2

SCD1U10V2KX-5GP

AUD_DMIC_ CLK(49,97)

AUD_DMIC_ IN0(49 ,97) HDA_COD EC_SDOUT(21) HDA_COD EC_BITCLK(21)

HDA_SDIN0(21)

HDA_COD EC_SYNC(21) HDA_COD EC_RST#(21)

4

R2901

1 2

33R2J-2-G P

3

AUD_SPK _LAUD_SPK _L+

AMP_MUT E#(27)

AMP_MUT E#

+PVDD

Close to codec

AUD_DVD DCORE

12

C2901

C2901 SC10U6D 3V5MX-3GP

SC10U6D 3V5MX-3GP

AUD_DMIC_ CLK AUD_DMIC_ IN0 AUD_V_B HDA_COD EC_SDOUT HDA_COD EC_BITCLK HDA_COD EC_SDIN0

HDA_COD EC_SYNC HDA_COD EC_RST# AUD_PC_ BEEP

U2901

1

DVDD_LV

2

DMIC_CLK/GPIO_1

3

DMIC_0/GPIO_2

4

SDATA_OUT

5

BITCLK

6

SDATA_IN

7

DVDD

8

SYNC

9

RESET#

10

PCBEEP

39

40

41

EAPD

PVDD

THERMAL_PAD

92HD87B 1A5NDGXTBX8-G P

71.92H87.A03

SENSE_A11SENSE_B12PORTF_L13PORTF_R14PORTC_L15PORTC_R16VREFFILT17CAP218VREFOUT_A19VREFOUT_C

+AVDD

AUD_VREG

34

31

35

32

33

36

37

38

PVSS

PVDD

AVDD2

PORTD_-L

PORTD_-R

PORTD_+L

PORTD_+R

20

VREG/+2_5V

CAP+ CAP-

AVSS2

PORTB_R

PORTB_L

AVSS2

PORTA_R

PORTA_L

AVDD1

V-

AUD_SPK _L- (5 8)

AUD_SPK _L+ (5 8)

30 29 28 27 26 25 24 23 22 21

PUMP_CA PP

PUMP_CA PN

AUD_HP1 _JACK_R AUD_HP1 _JACK_L

AUD_EXT _MIC_R AUD_EXT _MIC_L

+AVDD

C2905

1 2

SCD1U10V2KX-5GP

1 2

R2906 60D4R2F-GPR2906 60D 4R2F-GP R2905 60D4R2F-GPR2905 60D 4R2F-GP

2

R2902

1 2

0R0603-P AD

C2906

SC1U10V2KX-1GP

1 2 1 2

0R0603-P AD

12 12

12

C2914

C2914 SC2D2U1 0V3KX-1GP

SC2D2U1 0V3KX-1GP

C2922 SC1U10V 3KX-3GPC2 922 SC1U1 0V3KX-3GP C2921 SC1U10V 3KX-3GPC2 921 SC1U1 0V3KX-3GP

5V_S0 +PVDD

Put C2921 and C2922 close to codec

12

C2908

C2909

1 2

AUD_HP1 _JACK_R2 (58)

AUD_HP1 _JACK_L2 (58)

MIC_IN_R (58) MIC_IN_L (58)

C2909

SCD1U10V2KX-5GP

1

1 2

12

C2910

SC1U10V2KX-1GP

1 2

SC10U6D3V5MX-3GP

R2903

R2903 0R0603-P AD

0R0603-P AD

R2904

R2904 0R0603-P AD

0R0603-P AD

5V_S0

3D3V_S0

AUD_SENSE_B

12

R2908

R2908 10KR2J-3 -GP

10KR2J-3 -GP

AMP_MUT E#

AUD_VRE FOUT_B

HDA_COD EC_BITCLK_1

12

C2907

C2923

SC1U10V 2KX-1GP

B B

C2907

DY

SC4D7P5 0V2CN-1GP

R2907

1 2

DY

47R2J-2-G P

HDA_COD EC_BITCLK

AUD_PC_BEEP Trace width>15 mils

AUD_PC_ BEEP

C2912 SCD1U10 V2KX-5GPC2912 SCD1U10 V2KX-5GP

C2913 SCD1U10 V2KX-5GPC2913 SCD1U10 V2KX-5GP

G2901

G2901 DUMMY-C2

DUMMY-C2

1 2

12

AUD_SENSE_A

SB_SPKR _R

KBC_BEE P_R

AUD_PC_BEEP

AUD_CAP2

AUD_VREFOUT_B

AUD_VREFFLT

120KR2J -L-GP

R2909

1 2

R2910

470KR2J -2-GP

From PCH

HDA_SPK R (21)

KBC_BEE P (27)

From EC

Azalia I/F EMI

HDA_COD EC_SDOUT

12

R2912

R2912 47R2J-2-G P

47R2J-2-G P

DY

PCH_AZ_CODEC_SDOUT1

A A

12

C2920

DY

SCD1U10 V2KX-5GP

5

AUD_SEN SE_A

+AVDD

12

R2915

R2915 2K49R2F -GP

2K49R2F -GP

12

C2919

C2919 SC1000P 50V3JN-GP-U

SC1000P 50V3JN-GP-U

Close to Pin13

4

R2913

1 2

20KR2F-L -GP

R2919

39K2R2F -L-GP

AUD_HP1 _JD# (58)

AUD_SEN SE_B

12

EXT_MIC_J D# (58)

Close to Pin14

3

+AVDD

12

AUD_CAP 2

AUD_VRE FFLT

AUD_V_B

AUD_VRE G

R2916

R2916 2K49R2F -GP

2K49R2F -GP

R2918

R2918 20KR2F-L -GP

20KR2F-L -GP

12

C2918

C2917

C2918

SC10U6D3V5MX-3GP

SC4D7U6D3V3KX-GP

SC10U6D3V5MX-3GP

Close to codec

AUD_VRE FOUT_B

SRN4K7J -8-GP

MIC_IN_L(58) MIC_IN_R(58)

2

RN2901

12

C2915

C2916

SC1U6D3V2KX-GP

SC10U6D3V5MX-3GP

SC1U6D3V2KX-GP

1

23

4

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Audio Codec 92HD87B1

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

29 1 03Tuesday, January 18, 2011

1

A00

of

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

30 1 03Wednesday, December 22, 20 10

of

30 1 03Wednesday, December 22, 20 10

of

30 1 03Wednesday, December 22, 20 10

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Reserved

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

31 1 03Wednesday, December 22, 20 10

of

31 1 03Wednesday, December 22, 20 10

of

31 1 03Wednesday, December 22, 20 10

1

A00

5

SSID = SDIO

4

3

2

1

D D

48MHz clock input trace of characteristic impedance (Zo) must be 50



±15%.

3D3V_CA RD_S0

3D3V_CARD_S0

CLK_PCH _48M(20,97)

PCH GPIO67(48M) confirm with SW

XD_D7 SP14 SP13 SP12

C3201

RREF

1 2

DY

3D3V_S0

MAX 0.4A

3D3V_CA RD_S0

12

DY

C3204

C3203

SCD1U10 V2KX-4GP

C C

SCD1U10 V2KX-4GP

1 2

C3204 SC4D7U6 D3V3KX-GP

SC4D7U6 D3V3KX-GP

DY

SC100P5 0V2JN-3GP

R3201

1 2

6K2R2F-G P

USB_PN5 _R USB_PP5 _R

V18

12

C3202

C3202 SC1U10V 2KX-1GP

SC1U10V 2KX-1GP

1 2 3 4 5 6

25

RREF DM DP 3V3_IN CARD_3V3 V18

GND

23

24

CLK_IN

XD_CD#7SP18SP29SP310SP411SP5

SP11

U3201

U3201 RTS5138 -GR-GP

RTS5138 -GR-GP

22

SP1119SP1220SP1321SP14

SP10

XD_D7

GPIO0

SP9 SP8 SP7 SP6

71.05138.003

12

SP5 SP4 SP3 SP2 SP1 XD_CD#

XD_D7 (74) SP14 (74 ) SP13 (74 ) SP12 (74 ) SP11 (74 )

18 17 16 15 14 13

SP10

SP9 SP8 SP7 SP6

SP5 (74 ) SP4 (74 ) SP3 (74 ) SP2 (74 ) SP1 (74 ) XD_CD# (74)

SP10 (74 )

SP9 (74 ) SP8 (74 ) SP7 (74 ) SP6 (74 )

12

C3206

C3206 SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

Close to chip

12

C3207

C3207 SC4D7U6 D3V5KX-3GP

SC4D7U6 D3V5KX-3GP

The maximum range of the PMOS output current

1. xD-Picture Card: 250mA

B B

2. SD/MMC Card: 250mA

3. MS/MSPRO/Duo-HG: 250mA

The pin2 / pin3 (DM/DP) of RTS5138 chip trace layout with differential characteristic impedance (Zdiff) is 90Ω± 10%

POWER TRACE

1.RTS5138: pin 4 (3V3_IN) trace fixed width is 30 mils (minimum).

2.RTS5138: pin 5 (CARD_3V3) trace fixed width is 30 mils (minimum).

R3211

USB_PP5(18)

1 2

0R0402-P AD

USB_PP5 _R

3.RTS5138: pin 6 (V18) trace fixed width is 12 mils (minimum). Keep the trace routing lengths as short as possible.

4.RTS5138: pin 1(RREF) trace fixed width is 12 mils (minimum).

5.RTS5138: pin 1(RREF) trace must far away 48MHz clock trace.

6.De-coupling and Bulk capacitor should place near to RT5138 chip and Combo Socket.

7.It is recommended that use of ferrites bead on power trace.

8.Via size: Pad>=32 mils, Finished hole>=16 mils.

A A

5

4

3

USB_PN5(18 )

20101227 A00: Change R3210,R3211 to 0R 0402 pad. 20100104 A00: Remove TR3201.

2

R3210

1 2

0R0402-P AD

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

USB_PN5 _R

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Card Reader RTS5138

Nirvana 13

32 1 03Tuesday, January 18, 2011

1

A00

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

33 1 03Wednesday, December 22, 20 10

of

33 1 03Wednesday, December 22, 20 10

of

33 1 03Wednesday, December 22, 20 10

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

34 1 03Wednesday, December 22, 20 10

of

34 1 03Wednesday, December 22, 20 10

of

34 1 03Wednesday, December 22, 20 10

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

35 1 03Wednesday, December 22, 20 10

of

35 1 03Wednesday, December 22, 20 10

of

35 1 03Wednesday, December 22, 20 10

1

A00

5

PS_S3CNTRL

IMVP_PWRGD(27,42)

Q3603

G

S

2N7002K-2-GP

D

2

3

1

D3602

D3602 BAS16-6-GP

BAS16-6-GP

83.00016.K11

2ND = 83.00016.F11

SSID = Reset.Suspend

D D

S0_PWR_GO OD(19 ,27)

4

20101224 A00: 0402 0R pad: R3614.

R3614

0R0402-PAD

12

C3612

SCD01U50V2KX- 1GP

SYS_PWROK

Power Sequence

12

DY

SYS_PWROK (1 9)

3

H_CPUPW RGD(5,22)

3V_5V_EN(41)

20100723 Default stuff R3622 PH Resistor to fix Annie demo board SLP_S3 abnormal issue from Annie team updated.

1D05V_VTT

H_PWRG D_R

R3601

1 2

1KR2J-1-GP

DY

12

DY

R3602

200KR2J-L1-GP

R3622

12

56R2J-4-GP

B

12

C3602

DY

SCD1U10V2KX- 5GP

2ND = 83.00016.F11

83.00016.K11

BAS16-6-GP

2

3

1

D3601

1 2

R3603 1KR2J-1-GPR3603 1KR2J-1-G P

0621 Modify: Change R3603 to 1K from 2K 0402.

E

DY

Q3601

Q3601 CHT2222APT- GP

CHT2222APT- GP

C

2

H_THERMT RIP# (5,22)

PURE_HW _SHUTDOW N# (27,28)

S5_ENABLE (2 7)

1

SSID = Reset.Suspend

Run Power

C C

3D3V_AUX_S5

PS_S3CNTRL

R3606

1 2

100KR2J-1-GP

2N7002KDW -GP

84.2N702.A3F

2nd = 84.DM601.03F

PM_SLP_S3#(19,27,37,47)

RUN_ENABL E

Q3602

5

6

123 4

GGDDSS

PS_S3CNTRL (37)

15V_S5

1 2

R3604

R3604 100KR2J-1-GP

100KR2J-1-GP

1 2

R3607

1 2

R3605

10KR2J-3-GP

5V_RUN_ENA BLE

3.3V_RUN_EN ABLE

AO4468 MAX 9A

Rds(on) = 18.5mOhm

2nd = 84.08882.037

84.04468.037

5V_S5 5V_S0

AO4468-GP

6

D

7

D

8

D

12

C3608

C3608 SCD01U50V2KX- 1GP

SCD01U50V2KX- 1GP

Rds(on) = 18.5mOhm AO4468 MAX 11.6A

2nd = 84.08882.037

84.04468.037

3D3V_S5

AO4468-GP

6

D

7

D

8

D

U3602

12

C3605

C3605 SCD01U50V2KX- 1GP

SCD01U50V2KX- 1GP

U3602

U3601

+5V_RUN

+5V_RUN Comsumption

45

G D

G D S

S S

S

45

G D

3

S

2

S

1

S

3 2 1

3D3V_S0

12

Peak current 7.73A

12

C3603

C3603 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

+3.3V_RUN

+3.3V_RUN Comsumption Peak current 8.14A

C3604

C3604 SC10U6D3V5KX- 1GP

SC10U6D3V5KX- 1GP

1

+1.5V_RUN_CPU Comsumption Peak current 10A

B B

+1.5V_RUN for Mini-Card Comsum ption Peak current 1A

1 2

1D5V_S3 1D5V_S0

TPCA8062-H-GP MAX 28A Rds(on) = 4.1~5.4m OHM

U3606

S

D

S

D

8

S

D

S

D

7

S

D

S

D

6

GD

TPCA8062-H- GP

R3630

10KR2J-3-GP

SCD01U50V2KX- 1GP

1.5V_RUN_EN ABLE

C3610

12

TPCA8062-H- GP

84.08062.037

2nd = 84.00460.037

3rd = 84.00312.037

1 2 3 45

1D5V_S0

MAX Current ? mA Design Current ? mA

Total= 11.39A

12

C3609

C3609 SC10U6D3V5KX- 1GP

SC10U6D3V5KX- 1GP

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A2

Nirvana 13

Date: Sheet

5

4

3

2

Date: Sheet

Taipei Hsie n 221, Taiwan, R.O.C.

Power Plane Enable

36 103Tuesday, Januar y 18, 2011

1

36 103Tuesday, Januar y 18, 2011

A00

of

5

Close to CPU

D D

S3 Power Reduction Circuit Processor VREF_DQ Implementation

M_VREF_ DQ_DIMM0

R3708 0R0402-P ADR37 08 0R0402-PA D

1 2

4

+V_SM_V REF

R3707

R3707 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q3708

D

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

S

G

RUN_ENA BLE

R3705

R3705 100KR2J -1-GP

100KR2J -1-GP

1 2

3

+V_SM_V REF_CNT (9)

2

Close to DIMM S3 Power Reduction Circuit SM_DRAMPWROK

1D5V_S00D75V_S 0

12

R3703

R3703 22R2J-2-G P

22R2J-2-G P

Q3701_D

D

S

G

PS_S3CN TRL(36)

2

Q3701

Q3701 2N7002K -2-GP

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

PS_S3CN TRL

G

DY

12

Q3702_D

D

DY

R3704

R3704 220R2J-L 2-GP

220R2J-L 2-GP

S

1

Q3702

Q3702 2N7002K -2-GP

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

C C

B B

PM_DRAM _PWRGD(5,19)

A A

PM_DRAM _PWRGD(5,19)

SM_DRAMPWROK mu st have a maxim um of 15ns rise or fall time over VDDQ * 0.5 5± 200mV and th e edge must be monotonic

5

R3717

1 2

DY

0R2J-2-GP

S3 Power Reduction

5

PS_S3CN TRL(36)

3D3V_S0

12

R3713

200R2F-L -GP

0D75V_E N

VDDPW RGOOD_R

2N7002K -2-GP

G

S

Q3704

84.2N702.J31

2ND = 84.2N702.031

PM_SLP_ S3#(19,27,36,4 7)

U3701

1

2

3

TC7SZ08 FU-2-GP

73.7SZ08.EAH

2ND = 73.01G08.L04

3rd = 73.7SZ08.DAH

5

4

0D75V_E N

D

1 2

DY

R3716 22R2J-2-GP

DY

Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK

1D5V_S03D3V_S0

CEKLT V1.0: PCH to 1K,CUP to 200R

12

R3702

200R2F-L -GP

DY

VDDPW RGOOD_R

PS_S3CN TRL

R3721

39R2J-L-G P

G

DY

12

D

Q3707_D

1.05VTT_ PWRGD (45,4 8)

12

R3710

R3710 0R0402-P AD

0R0402-P AD

12

C3705

C3705 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

R3719

1 2

910R2F-G P

Q3707

DY

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

S

20101224 A00: 0402 0R pad: R3710.

0D75V_E N (46)

12

R3720

R3720 750R2F-G P

750R2F-G P

3

SM_DRAM RST#(5)

VDDPW RGOOD (5)

Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK

R3709

1 2

DY

2ND = 84.2N702.031

84.2N702.J31

Q3703

S

G

2N7002K -2-GP

SCD047U 16V2KX-1-GP

2

1D5V_S3

12

R3706

R3706 1KR2J-1-G P

1KR2J-1-G P

0R2J-2-GP

C3703

DRAMRST _CNTRL_PCH

12

Title

Size Document N umber Rev

A3

Date: Sheet of

S3 Power Reduction Circuit SM_DRAMRST#

SM_DRAM RST#_D

D

1 2

12

C3702

C3702 SC100P5 0V2JN-3GP

SC100P5 0V2JN-3GP

S3 Power Reduction

Nirvana 13

R3718

1KR2J-1-G P

DRAMRST _CNTRL_PCH (20)

DDR3_DR AMRST# (14,15)

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

37 1 03Tuesday, January 18, 2011

1

A00

5

D D

PR3804

PS_ID_R PS_ID_1

PS_ID_R(82)

C C

1 2

0R0402-P AD

+DC_IN AD+

Place close to BTB connector

B B

AFTP380 1AFTP 3801 AFTP380 2AFTP 3802 AFTP380 3AFTP 3803

1 1 1

PS_ID_R +DC_IN +DC_IN

4

PR3801

15KR2J-1 -GP

DY

2 1

15KR2J-1 -GP

100KR2J -1-GP

PD3804

PD3804 B240A-13 -GP

B240A-13 -GP

PR3803

PQ3802

PMBS390 4-1-GP

1 2

PQ3802_ 1

1 2

FDV301N -NL-GP

D

1

PQ3801

PR3808

1 2

DY

33R2J-2-G P

280mils or Copper Shape

KA

PD3801

PD3801 1SMB22A T3G-GP-U

1SMB22A T3G-GP-U

83.22R03.03G

2ND = 83.P6SBM.AAG

2

84.03904.L06

2nd = 84.03904.P11

3rd = 84.03904.T11

3

PSID_DISABLE #_R

G

SD

This cap should be used only as last resort for EMI suppression.

12

PC3801

DY

SCD1U50 V3KX-GP

3

PS_ID

5V_S5

12

PR3802

PR3802 10KR2J-3 -GP

10KR2J-3 -GP

1 2

33R2J-2-G P

RCID(27 )

12

PC3804

PR3807

SC1U25V5KX-1GP

12

PR3810

PU3801_G

PR3811

PR3811 47KR3J-L -GP

47KR3J-L -GP

1 2

PR3812

PR3812 100KR2J -1-GP

100KR2J -1-GP

DY

1 2

1 2 3 4 5

240KR3-GP

Id=-12A Qg=-25nC Rdson=10~38mohm

83.00099.T11

2nd = 83.00099.K11

3rd = 83.BAV99.D11

PU3801

S

D

S

D

S

S S

S G D

G D

AO4407A -GP

8

D

7

D

6

2

3D3V_S5

2

2N7002K -2-GP

G

D

DY

S

PQ3803

84.2N702.J31

2ND = 84.2N702.031

12

PC3805

DY

SCD01U50V2KX-1GP

3

12

1

PD3803

PD3803 BAV99-5-G P-U

BAV99-5-G P-U

PC3802

DY

SCD01U50V2KX-1GP

12

3D3V_S5

PC3803

SCD01U50V2KX-1GP

12

PR3806

PR3806 2K2R2J-2 -GP

2K2R2J-2 -GP

12

PC3806

SC10U25V6KX-1GP

1

PSID_EC (27)

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

DCIN Jack

Nirvana 13

38 1 03Tuesday, January 18, 2011

of

38 1 03Tuesday, January 18, 2011

of

38 1 03Tuesday, January 18, 2011

1

A00

5

4

3

2

1

BT+

BATT_SE NSE(40)

D D

BAT_SCL(2 7,40) BAT_SDA(27,40) BAT_IN#(27)

C C

G3901

GAP-CLOS E-PWR-3-GP

12

20101224 A00:

Rename PRN3901 to PN3901.

SCD1U50 V3KX-GP

PN3901

4 5 3 2 1

SRN33J-7 -GP

C3902

12

6 7 8

EC3901

DY

AFTP390 2AFTP 3902 AFTP390 3AFTP 3903 AFTP390 4AFTP 3904 AFTP390 5AFTP 3905

12

EC3902

12

DY

SC10P50V2JN-4GP

C3901

C3901 SC2200P 50V2KX-2GP

SC2200P 50V2KX-2GP

AFTP390 1AFTP 3901

SC10P50V2JN-4GP

PBAT_PR ES1#

1

PBAT_SM BDAT1

1

PBAT_SM BCLK1

1

BT+

1

KA

DY

PBAT_SM BCLK1 PBAT_SM BDAT1 PBAT_PR ES1#

BAT_ALE RT

1

PD3902

1SMA18AT3G-GP

400mils or Copper Shape

Batt Connecter

BATT1

10

1

2 3 4 5 6 7 8 9

11

TCN-CON9 -3-GP

20.81327.009

For actual location, need to be swap all pin

Placement: Close to Batt Connector

BAT_IN#

B B

A A

5

3

D3902

D3902 BAV99-5-G P-U

BAV99-5-G P-U

1

2

83.00099.T11

2nd = 83.00099.K11

3rd = 83.BAV99.D11

4

BAT_SDA

3

D3903

D3903 BAV99-5-G P-U

BAV99-5-G P-U

1

2

83.00099.T11

2nd = 83.00099.K11

3rd = 83.BAV99.D11

BAT_SCL

3

D3901

D3901 BAV99-5-G P-U

BAV99-5-G P-U

1

2

83.00099.T11

2nd = 83.00099.K11

3rd = 83.BAV99.D11

3

3D3V_AU X_KBC

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

BATT CONN

Nirvana 13

1

A00

39 1 03Tuesday, January 18, 2011

of

39 1 03Tuesday, January 18, 2011

of

39 1 03Tuesday, January 18, 2011

A00

5

4

3

2

1

SSID = Charger

AD+

Id=-12A Qg=-25nC Rdson=10~38mohm

D D

C C

B B

AD+

12

PR4009

316KR3F-2-GP

PR4009

316KR3F-2-GP

12

PR4014 49K9R2F-L-GPPR4014 49K9R2F-L-GP

CHG_AGND

1 2

AD_IA(27)

PR4025

This Resistor must be 1% tolerance.

PWR_CH G_ACOK

PWR_CH G_REF

PC4010

PR4016

SCD01U50V2KX-1GP

PR4001

20KR2J-L2-GP

12

8K45R2F-2-GPDYPR4025

8K45R2F-2-GP

DY

1 2

DC_IN_D

12

10KR2F-2-GP

12

SC220P50V2JN-3GP

PC4024

PC4026

AC_IN#(27)

SCD1U10V2KX- 5GP

280mils or Copper Shape

PU4002

S

D

S

D

1

8

S

D

S

D

2

7

S

D

S

D

3

6

GD

45

AO4407A-GP

84.04407.F37

2nd = 84.P1403.B37

84.2N702.A3F

PR4004

2nd = 84.DM601.03F

10KR2J-3-GP

3 4

2

1

PR4033

20R5F-1GP

AC_OK

12

PR4021

PR4021 4K7R2J-2-GP

4K7R2J-2-GP

1 2

PC4021

PC4021 SC150P50V2JN-3 GP

SC150P50V2JN-3 GP

PWR_CHG_FBO1

12

DY

SCD1U50V3KX-GP

PC4033

AD+_G_2

PQ4001

5

6

2N7002KDW -GP

1 2

3D3V_AUX_KBC

BAT_SCL(27,39)

BAT_SDA(27,39)

PR4022

200KR2F-L-GP

1 2

PC4022

SC2200P50V2KX-2G P

12

SC56P50V2JN-2G P

DY

PC4027

SCD01U50V2KX- 1GP

SCD01U50V2KX-1GP

12

2N7002K-2-GP

DY

84.2N702.J31

2ND = 84.2N702.031

AD+_G_1

1 2

12

PC4001

PC4001 SCD1U10V2KX- 5GP

SCD1U10V2KX- 5GP

CHG_AGND

PR4526_01

PC4025

1 2

PQ4002

20101222 A00 Power/Brian: Change PR4047 to 174k ohm from 121k ohm.

12

Change PR4035 to 300k from 49.9k. Change PR4031 to 150k from 0 ohm.

PR4003

100KR2J-1-GP

PQ4003

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

1 2

AD_IA_HW(27)

1 2

PC4003

SCD47U50V5KX- 1GP

PR4012

1 2

0R0402-PAD

12

PR4027

1 2

0R0402-PAD

12

PC4029

DY

D

G

AC_OK

84.2N702.J31

PR4034

0R0402-PAD

PWR_CH G_DCIN

PWR_CH G_ACIN

PWR_CH G_ACOK

PWR_CH G_SCL

PWR_CH G_SDA

CHG_AGND

PWR_CH G_VICM PWR_CH G_FBO

PWR_CH G_EAI PWR_CH G_EAO PWR_CH G_REF

DY

SC1U6D3V2KX-GP

PQ4003_G

PWR_CH G_CE

12

PC4030

AC_OK (27)

PR4005

10KR2F-2-GP

20101222 A00 Power/Brian: Change PR4034 to 0 ohm pad. Stuff PQ4003.

PG4007 GAP-CLOSE-PW R-3-GPPG4007 GAP-CLOSE-PW R-3-GP

PG4008 GAP-CLOSE-PW R-3-GPPG4008 GAP-CLOSE-PW R-3-GP

PR4026

PR4026 7K5R2F-1-GP

7K5R2F-1-GP

PC4028

S

G

CHG_AGND

SCD1U10V2KX-5GP

PQ4003_D

D

22

11

13

10

14

12

S

2

9

8

6 5 4 3 7

PWR_CH G_REF

12

PR4035

PR4035 300KR2F-L-GP

300KR2F-L-GP

PR4031

PR4031 150KR2F-L-GP

150KR2F-L-GP

1 2

CHG_AGND

PU4001

DCIN

ACIN

VDDSMB

ACOK

SCL

SDA

NC#14

VICM

FBO EAI EAO VREF CE GND

BQ24745RHDR -GP

AD_IA_HW2( 27)

AD+_TO_SYS BT+

D01R2512F-4-G P

12

PG4002

GAP-CLOSE-P WR-3-GP

12

PR4047

PR4047 174KR2F-GP

174KR2F-GP

PR4533_02

12

PR4008

PR4008 0R0402-PAD

0R0402-PAD

1 2

ICREF

PC4002

PC4002 SCD1U50V3KX- GP

SCD1U50V3KX- GP

CHG_AGND

1

ICREF

GND

29

CHG_AGND

PR4040

10KR2J-3-GP

PWR_CH G_CSSP

28

CSSP

CSSN

ICOUT

BOOT

VDDP

UGATE

PHASE

LGATE

PGND

CSOP

CSON

NC#16

VFB

PR4029

1 2

0R0402-PAD

3D3V_AUX_S5

12

DY

20101222 A00 Power/Brian: Change PR4036 to 0 ohm pad. Stuff PQ4004. Change PR4037 to 76.8k ohm from 49.9k ohm.

SCD1U50V3KX- GP

PWR_CH G_CSSN

27

PWR_CH G_ICOUT

26

PWR_CH G_BOOT

25

PWR_CH G_VDDP

21

PWR_CH G_UGATE

24

PWR_CH G_PHASE

23

PWR_CH G_LGATE

20

19

PWR_CH G_CSOP

18

PWR_CH G_CSON

17

16

15

PWR_CH G_VFB

CHG_AGND

PQ4004

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

1 2

PR4036

0R0402-PAD

PR4002

1 2

DY

PR4007

PR4007 0R2J-2-GP

0R2J-2-GP

PC4005

1 2

12

DY

PQ4004_G

DCBATOUT

12

PG4003

GAP-CLOSE-P WR-3-GP

PR4524_03

12

PR4010

20101222 A00

0R0402-PAD

Power/Brian: Change PR4032 to 0 ohm pad.

H_PROCHO T#(5,27,42)

PC4004

1 2

SCD1U50V3KX-GP

CHG_AGND

PWR_CH G_BST1

PR4017

PR4017 0R0603-PAD

0R0603-PAD

PR4018

1 2

0R0603-PAD

PR4028

1 2

0R0402-PAD

PC4032

G

CHG_AGND

SCD1U25V2ZY-1GP

PQ4004_D

D

PC4014

PC4014 SC220P50V2JN-3 GP

SC220P50V2JN-3 GP

12

DY

PR4030

CHG_AGND

12

S

K A

SD103AWS-1-GP

83.1R504.A8F

2nd = 83.1R504.B8F

PC4012

PC4012 SCD1U50V3KX- GP

SCD1U50V3KX- GP

1 2

DY

CHG_AGND

1K8R6J-GP

PR4037

PR4037 76K8R2F-GP

76K8R2F-GP

ICREF

PR4013

33R3J-2-GP

33R3J-2-GP PD4001

PD4001

1 2

PC4020

SCD1U50V3KX-GP

BATT_SENSE (39)

1 2

12

DY

CHG_AGND

1 2

PC4011

PC4011 SCD1U50V3KX- GP

SCD1U50V3KX- GP

PC4023

PC4023 SCD1U50V3KX- GP

SCD1U50V3KX- GP

1 2

400mils or Copper Shape

1 2

PG4001

GAP-CLOSE-PWR-3-GP

PG4005

PG4006

PG4004

GAP-CLOSE-PWR-3-GP

1 2

160mils or Copper Shape

PR4032

0R0402-PAD

12

678

DDD

PC4006

DY

SC1U6D3V2KX-GP

12

PC4013

PC4013 SC3300P50V3KX-1G P

SC3300P50V3KX-1G P

DY

84.00412.037

1 2

CHG_AGND

PWR_CH G_LX1

PR4023

PR4023 0R0402-PAD

0R0402-PAD

GD

4 5

678

DDD

GD

4 5

PR4020

1 2

0R0402-PAD

SSS

123

SSS

123

PU4004 Id=12A

PU4004

Qg=3.8nC Rdson=24~30mohm

SIS412DN-T1-GE3-GP

PL4001

PU4005

Id=7.5A DCR=23mohm(Max) Size=10*10

SIS412DN-T1-GE3-GP

PU4005 Id=16A Qg=7.3nC Rdson=13.5~16.5mohm

GAP-CLOSE-PWR-3-GP

PWR_DC BATOUT_CHG

12

PL4001

1 2

IND-5D6UH- 48-GP-U1

PWR_CH G_CSOP_1

AD+

PR4006

470KR2J-2-GP

PWR_DC BATOUT_CHG

12

PC4007

PC4008

SC10U25V6KX-1GP

BT+_R

PG4010

GAP-CLOSE-PWR-3-GP

PU4003

S

D

S

D

1

8

S

D

S

D

2

7

S

D

S

D

3

6

G D

4 5

AO4407A-GP

12

84.04407.F37

2nd = 84.P1403.B37

12

PC4009

SCD1U50V3KX-GP

12

EC4001

EC4002

DY

SC2200P50V2KX-2GP

SCD1U25V2ZY-1GP

Charger Current=1.4~3.6A

PR4019

1 2

D01R2512F-4-G P

1 2

PG4009

GAP-CLOSE-PWR-3-GP

PG4009_1

PR4024

PR4024 0R0402-PAD

0R0402-PAD

1 2

DY

1 2

CHG_AGND

BT+

12

SC10U25V6KX-1GP

PC4016

PC4017

PC4015

PC4031

SCD1U50V3KX-GP

Id=-12A Qg=-25nC Rdson=10~38mohm

240mils or Copper Shape

12

PC4034

SC10U25V6KX-1GP

SCD1U50V3KX-GP

PC4018

PC4019

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Documen t Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CHARGER BQ24745

Nirvana 13

1

40 103Tuesday, January 18, 2011

A00

5

20110110 A00: Change PG4110,PG4112,PG4114~PG4119,PG4122,PG4126,PG4129,PG4131,PG4133,PG4135~PG4138,PG4140,PG4142 to ZZ.CLOSE.001.

5V_S5

D D

C C

Connect VFB1to GND for fixe 5V opteration

B B

5V_PWR

PG4110 GAP-CLO SE-PWR-3- GPP G4110 GAP-CLOSE- PWR-3-GP

1 2

PG4112 GAP-CLO SE-PWR-3- GPP G4112 GAP-CLOSE- PWR-3-GP

1 2

PG4114 GAP-CLO SE-PWR-3- GPP G4114 GAP-CLOSE- PWR-3-GP

1 2

PG4115 GAP-CLO SE-PWR-3- GPP G4115 GAP-CLOSE- PWR-3-GP

1 2

PG4116 GAP-CLO SE-PWR-3- GPP G4116 GAP-CLOSE- PWR-3-GP

1 2

PG4117 GAP-CLO SE-PWR-3- GPP G4117 GAP-CLOSE- PWR-3-GP

1 2

PG4119 GAP-CLO SE-PWR-3- GPP G4119 GAP-CLOSE- PWR-3-GP

1 2

PG4122 GAP-CLO SE-PWR-3- GPP G4122 GAP-CLOSE- PWR-3-GP

1 2

PG4124 GAP-CLO SE-PWR-3- GPP G4124 GAP-CLOSE- PWR-3-GP

1 2

PG4126 GAP-CLO SE-PWR-3- GPP G4126 GAP-CLOSE- PWR-3-GP

1 2

PG4129 GAP-CLO SE-PWR-3- GPP G4129 GAP-CLOSE- PWR-3-GP

1 2

PG4131 GAP-CLO SE-PWR-3- GPP G4131 GAP-CLOSE- PWR-3-GP

1 2

PG4133 GAP-CLO SE-PWR-3- GPP G4133 GAP-CLOSE- PWR-3-GP

1 2

PG4135 GAP-CLO SE-PWR-3- GPP G4135 GAP-CLOSE- PWR-3-GP

1 2

PG4136 GAP-CLO SE-PWR-3- GPP G4136 GAP-CLOSE- PWR-3-GP

1 2

PG4137 GAP-CLO SE-PWR-3- GPP G4137 GAP-CLOSE- PWR-3-GP

1 2

PG4138 GAP-CLO SE-PWR-3- GPP G4138 GAP-CLOSE- PWR-3-GP

1 2

PG4140 GAP-CLO SE-PWR-3- GPP G4140 GAP-CLOSE- PWR-3-GP

1 2

PG4142 GAP-CLO SE-PWR-3- GPP G4142 GAP-CLOSE- PWR-3-GP

1 2

20101224 A00: Rename PTC4101~PTC4103 to PT4101~PT4103.

Vout(5V)=VFB1*(1+R1/R2)

12

PC4112

SC1KP50V2KX-1GP

Design Current = 16A

25.1A<OCP< 29.3A

5V_PWR

12

PT4101

PT4102

ST220U6D3VDM-20GP

20101230 A00: Change PR4119 to 0R short pad.

12

PC4113

PC4114

SCD1U50V3KX-GP

SC10U25V6KX-1GP

1 2

IND-1D5UH- 34-GP

68.1R510.10J

12

68.1R510.10J

PC4119

PG4125

12

SCD1U10V2KX-4GP

GAP-CLOSE-PWR-3-GP

PWR_5V_VOUT1

12

PR4117

PR4117 0R2J-2-GP

0R2J-2-GP

DY

12

PR4119

0R0402-PAD

PWR_5V3D 3_AGND

15V_S5

20110110 A00: Change PG4139,PG4141 to ZZ.CLOSE.001.

PC4115

PL4102

PG4139GAP-CLOS E-PWR-3-G P P G4139GAP-CLOSE-PW R-3-GP

PG4141GAP-CLOS E-PWR-3-G P P G4141GAP-CLOSE-PW R-3-GP

SC10U25V6KX-1GP

12

15V_PWR

12

PC4129

SC10U25V6KX-1GP

PWR_5V_SN UB

SCD1U25V2ZY-1 GP

20110118 A00: Remove PU4101,PU4106 and add PT4105 100uF at PWR_DCBATOUT_5V3D3V.

PC4116

SC10U25V6KX-1GP

84.00172.037

PU4102

12

DY

PC4120

PU4108

12

SC680P50V2KX-2GP

DY

PR4113

2D2R6J-3-GP

PR4119_2

12

PC4126

1 2

PR4124

PR4124 24D9R3F-GP

24D9R3F-GP

PC4128

SCD1U25V2ZY-1 GP

4

20101230 A00: Change PR4103,PR4104 to 0R0805 short pad.

PWR_DC BATOUT_5V3D3V

PT4105

12

678

SE100U25VM-L1-G P

DDD

SIR172DP-T1-GE3-GP

SIR460DP-T1-GE3-GP

PD4102

1

2

BAT54SW- 2-GP

PD4103

1

2

BAT54SW- 2-GP

1 2

PR4125

PR4125 200KR2J-L1-GP

200KR2J-L1-GP

PWR_5V3D 3_AGND

79.10712.L02

2nd = 79.10712.6JL

5V_C_1

3

PC4125

PC4125 SCD1U25V2ZY-1 GP

SCD1U25V2ZY-1 GP

5V_C_2

3

PC4127

PC4127 SCD1U25V2ZY-1 GP

SCD1U25V2ZY-1 GP

15V_C_1

12

PR4127

PR4127 39KR2J-GP

39KR2J-GP

PWR_5V3D 3_AGND

SSS

123

D

SSS

123

678

12

10V_C

15V_C

G D

4 5

DDD

G

4 5

3

5V_AUX_S5

PR4102 10R3J-3-GPPR4102 10R3J-3-GP

12

PC4102

SC4D7U10V5KX- 1GP

DCBATOUT

12

PC4104

SCD1U25V3KX- GP

PWR_5V3D 3_AGND

CLOSE TO PIN 10

12

PC4117

SCD1U25V3KX- GP

PWR_5V_T RIP1

1 2

3V/5V_POK

PR4111

PWR_5V3D 3V_EN

200KR2F-L-GP

PWR_5V_D RVH1 PWR_5V_LL1

12

PC4121

SCD1U25V3KX-GP

PWR_5V__VB ST1_1 PW R_5V__VBST1 PWR_3D3V_ VBST2 P WR_3D3V_VBST 2_1

1 2

123

SKIPSEL GND FLOAT/VREF2 V5IN Mode Auto Skip OOA. PWM Only

TONSEL GND VREF2 or Float V5FILT Ch1 400 kHz 400 kHz 200 kHz Ch2 500 kHz 300 kHz 300 kHz

PR4103

0R0805-PAD

1 2

PR4104

0R0805-PAD

12

PR4115

2D2R3-1-U- GP

5V_AUX_S5

PD4101

PD4101 BAT54-7-F-G P

BAT54-7-F-G P

PC4103

1 2

SC1U25V3KX-1- GP

PU4103

33

GND

9

VSW

10

VOUT1

11

VFB1

12

TRIP1

13

PGOOD1

14

EN1

15

DRVH1

16

LL1

PWR_5V__D RVL1

8

7

LDO

LDOREFIN

TPS51427RHBR -GP

VBST117DRVL118V5DRV19NC#2020GND21PGND22DRVL223VBST2

12

PC4101

SC1U25V3KX-1- GP

+5V_VCC1

1 2

12

PR4107

PR4107 0R2J-2-GP

0R2J-2-GP

DY

1 2

DY

PR4108 0R2J- 2-GP

PWR_5V3D3V_VIN

1 2

SC1U25V3KX-1- GP

PWR_5V3D3V_TONSEL

3

6

2

4

1

5

VIN

VREF2

VREF3

V5FILT

TONSEL

EN_LDO

REFIN2

TRIP2

VOUT2 SKIPSEL PGOOD2

EN2

DVRH2

LL2

24

20101230 A00: Change PR4116 to 0R0603 short pad.

PWR_3D3V _DRVL2

PG4143 GAP-CLO SE-PWR-3- GPP G4143 GAP-CLOSE- PWR-3-GP

1 2

PWR_5V3D 3_AGND

200KR2J-L1-GP

PWR_5V3D 3V_VREF2

+5V_VCC1

12

PC4106

PWR_5V3D 3_AGND

PWR_5V3D 3V_REFIN2

32

PWR_3D3V _TRIP2

31

PWR_3D3V _VOUT2

30

PWR_5V3D 3V_SKIPSEL

29

3V/5V_POK

28

PWR_5V3D 3V_EN

27

PWR_3D3V _DVRH2

26

PWR_3D3V _LL2

25

SCD1U25V3KX- GP

PR4116

1 2

0R0603-PAD

20110110 A00: Change PG4143 to ZZ.CLOSE.001.

PWR_5V3D 3V_EN

12

PR4122

PC4105

SC1U25V3KX-1-GP

+5V_VCC1PWR_5V3D3V_ VREF3

12

DY

PR4105

PR4106

PR4106 0R2J-2-GP

0R2J-2-GP

1 2

20101230 A00: Change PR4106 to 0R0603 short pad.

DY

PR4109

1 2

0R2J-2-GP

PR4101 187KR2F -GPPR4101 18 7KR2F-GP

1 2

DY

PR4110

0R2J-2-GP

12

PC4122

3D3V_S5

12

3V/5V_POK

5V_AUX_S5

12

PC4131

SC1U10V3KX-3GP

0R0603-PAD

PU4104

AON7410-GP

678

DDD

84.07410.A37

GD

4 5

678

DDD

PU4107

PU4107 AON7702-GP

AON7702-GP

84.07702.037

GD

4 5

12

CLOSE TO PIN 30

PC4123

PC4123 SCD1U25V3KX- GP

SCD1U25V3KX- GP

PWR_5V3D 3_AGND

1 2

PR4120 2KR2J-1-G PPR4120 2KR2J- 1-GP

PR4123

PR4123 100KR2J-1-GP

100KR2J-1-GP

PU4105

1

VIN

2

GND EN3NC#4

G9091-330T11U-G P

74.09091.J3F

2nd = 74.09198.G7F

3rd = 74.07716.A7F

PWR_DC BATOUT_5V3D3V

12

PC4107

SSS

123

12

DY

PWR_3D3V _SNUB

SSS

12

PR4112

123

DY

2D2R6J-3-GP

3V_5V_EN ( 36)

2

3D3V_AUX_S5

5

VOUT

4

12

PC4132

SC1U10V3KX-3GP

12

SC10U25V6KX-1GP

PL4101

1 2

IND-2D2UH- 46-GP-U

68.2R210.20B

PC4118

PC4118 SC680P50V2KX-2GP

SC680P50V2KX-2GP

12

PC4108

SC10U25V6KX-1GP

PG4121

PWR_5V3D 3_AGND

V_REFIN2=VREF2*PR4109/(PR4109+PR4105) Vout(3.3V)=V_REFIN2*(1+R1/R2)

12

PC4110

PC4109

SC1KP50V2KX-1GP

SCD1U50V3KX-GP

12

GAP-CLOSE-PWR-3-GP

PG4121_2

PR4114

PR4114 0R0402-PAD

0R0402-PAD

1 2

20101230 A00: Change PR4114 to 0R short pad.

PR4118

DY

0R2J-2-GP

1 2

20110110 A00: Change PG4102~PG4109,PG4111,PG4113 to ZZ.CLOSE.001.

DCBATOUT

PC4111

SCD1U50V3KX-GP

12

PC4124

SCD1U10V2KX-4GP

77.22271.27L

PWR_DC BATOUT_5V3D3V

PG4102 GAP-CLO SE-PWR-3- GPP G4102 GAP-CLOSE- PWR-3-GP

1 2

PG4103 GAP-CLO SE-PWR-3- GPP G4103 GAP-CLOSE- PWR-3-GP

1 2

PG4104 GAP-CLO SE-PWR-3- GPP G4104 GAP-CLOSE- PWR-3-GP

1 2

PG4105 GAP-CLO SE-PWR-3- GPP G4105 GAP-CLOSE- PWR-3-GP

1 2

12

PG4107GAP-CLOS E-PWR-3-G P P G4107GAP-CLOSE-PW R-3-GP

12

PG4108GAP-CLOS E-PWR-3-G P P G4108GAP-CLOSE-PW R-3-GP

12

PG4109GAP-CLOS E-PWR-3-G P P G4109GAP-CLOSE-PW R-3-GP

12

PG4111GAP-CLOS E-PWR-3-G P P G4111GAP-CLOSE-PW R-3-GP

12

PG4113GAP-CLOS E-PWR-3-G P P G4113GAP-CLOSE-PW R-3-GP

12

Design Current = 7.4A

11.6A<OCP< 13.7A

3D3V_PWR

12

PT4103

ST220U6D3VDM-20GP

Connect REFIN2 to V5FILT for fixed 3.3V operation

20110110 A00:

DCBATOUT

12

PT4104

PT4104 SE100U25VM-L1-G P

SE100U25VM-L1-G P

79.10712.L02

79.10712.L02 2nd = 79.10712.6JL

2nd = 79.10712.6JL

Add PT4104 47uF. 20110112 A00: Change PT4104 to 100uF.

1

PG4106GA P-CLOSE-PW R-3-GP PG4106GAP-CLOSE- PWR-3-GP

3D3V_S5

20110110 A00: Change PG4118,PG4120,PG4123,PG4101,PG4127,PG4130,PG4132,PG4134 to ZZ.CLOSE.001.

PG4118

12

GAP-CLOSE-P WR-3-GP

PG4120

12

GAP-CLOSE-P WR-3-GP

PG4123

12

GAP-CLOSE-P WR-3-GP

PG4101

12

GAP-CLOSE-P WR-3-GP

PG4127

12

GAP-CLOSE-P WR-3-GP

PG4130

12

GAP-CLOSE-P WR-3-GP

PG4132

12

GAP-CLOSE-P WR-3-GP

PG4134

12

GAP-CLOSE-P WR-3-GP

A A

5

1A= 40mils

0.5A= 20mils

0.375A= 15mils

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Documen t Number Rev

A2

Nirvana 13

Date: Sheet of

Date: Sheet

4

3

2

Date: Sheet

Taipei Hsie n 221, Taiwan, R.O.C.

TPS51427_5V/3D3V

41 103Tuesday, January 18, 2011

1

41 103Tuesday, January 18, 2011

A00

of

5

SSID = CPU.Regulator

4

3

2

1

12

PR4204

PR4204 1R2F-GP

1R2F-GP

SCD1U25V3KX-GP

GND_131 6

PWR_ VCORE_DB0(43) PWR_ VCORE_DB1(43) PWR_ VCORE_DB2(43)

1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2

PQ4201_ D

PQ4201

5V_S5

12

PR4205

PR4205 1R2F-GP

1R2F-GP

12

PC4213

SCD1U25V3KX-GP

GND_131 6

PWR_ VCORE_VDD5

PWR_ VCORE_VDD3 PWR_ VCORE_VDD3

PWR_ VCORE_IMON1 PWR_ VCORE_IMON2

DB0_GFX(44) DB1_GFX(44) DB2_GFX(44)

PWR_ VCORE_R_OSC PWR_ VCORE_R_REF1 PWR_ VCORE_R_REF2

PWR_ VCORE_R_SEL0 PWR_ VCORE_R_SEL1 PWR_ VCORE_R_SEL2 PWR_ VCORE_R_SEL3 PWR_ VCORE_R_SEL4 PWR_ VCORE_R_SEL5 PWR_ VCORE_R_SEL6

5V_S5

12

PR4253

PR4253 1KR2F-3-G P

1KR2F-3-G P

DY

DS

DY

3D3V_S01D05V_V TT

20101231 A00: Change PR4209,PR4212 to PN4201 10k array resistor. 20110113 A00:

PR420854D9R2F-L1-GP PR420854D9R2F-L1-GP

PR4210130R2F-1-GP PR4210130R2F-1-GP

12

PC4201

PU4201

12

43 42

21 25

37 36 35 33 32 31

24 23 27 28

41 22 26

2

1 48 47 46 45 44

20101223 A00: Power/Brian: Change PU4201 to 74.01316.F33.

PQ4201_ G

G

12

0R2J-2-GP

PC4211

DY

SC220P5 0V2JN-3GP

VDD5

VDD3 VDD3

IMON1 IMON2

DB10 DB11 DB12 DB20 DB21 DB22

IDES1_N IDES1_P IDES2_N IDES2_P

R_OSC R_REF1 R_REF2

R_SEL0 R_SEL1 R_SEL2 R_SEL3 R_SEL4 R_SEL5 R_SEL6

VT1316M AFQX-041-GP

74.01316.F33

5V_S5

12

PR4207

PR4207 100R2F-L 1-GP-U

100R2F-L 1-GP-U

DY

PQ4203_ G

PC4428

12

SC4700P 50V2KX-1GP

DY

PR4240

12

DY

TEMP_SENSE1 TEMP_SENSE2

SPHASE1_0 SPHASE1_1 SPHASE1_2

VR_ENABLE

VR1_READY VR2_READY

PQ4203

AO7401-G P

DCMDRP1 DCMDRP2

SENSE1-

SENSE1+

SENSE2-

SENSE2+

SPHASE2

VCLK VDIO

VR_TT#

ALERT#

NC#17 NC#20

GND GND GND

G

3

18 19

PWR_ VCORE_SENSE1 -

14

PWR_ VCORE_SENSE1 +

13

PWR_ VCORE_SENSE2 -

15

PWR_ VCORE_SENSE2 +

16

PWR_ VCORE_TEMP_S ENSE1

29 30

40 39 38 34

5 4

6 10 8

PWR_ VCORE_VR2_DE LAY

9

7

17 20

49 11 3

DY

D S

GND_131 6

12

SCD047U25V2KX-GP

PC4218

12

SCD047U25V2KX-GP

PWR_ VCORE_DB1 (43)

D85V_PW RGD (4 8)

Swap RN4201 base on swap report.

1

23

PN4201

PN4201 SRN10KJ -5-GP

SRN10KJ -5-GP

4

PWR_ VCORE_DCMDRP 1 PWR_ VCORE_DCMDRP 2

PR4217 0R0402-PADPR 4217 0R040 2-PAD PR4218 0R0402-PADPR 4218 0R040 2-PAD PR4219 0R0402-PADPR 4219 0R040 2-PAD PR4220 0R0402-PADPR 4220 0R040 2-PAD

TEMP_SE NSE_GFX

PWR_ VCORE_SPHASE _0 PWR_ VCORE_SPHASE _1

PR4233

PWR_ VCORE_TEMP_S ENSE1_R

1 2

5K76R2F -2-GP

PC4219

12

PR4238

43K2R2F-L-GP

1 2 1 2 1 2 1 2

12

PWR_ VCORE_SPHASE _0 (43 ) PWR_ VCORE_SPHASE _1 (43 )

1 2

PR4223 100KR2F-L1-G PPR422 3 100KR2F -L1-GP

NTCG104QH224HT

PR4239

PR4239 NTC-220K -2-GP

NTC-220K -2-GP

1D05V_P WR

GND_131 6

2

VSSSENS E (8) VCCSENS E (8) VSS_AXG _SENSE (9) VCC_AXG _SENSE (9)

PR4254

1 2

0R0402-P AD

SPHASE_ GFX (44)

H_CPU_S VIDCLK (8)

H_CPU_S VIDDAT (8)

D85V_PW RGD (4 8)

H_PROCH OT# (5,27,4 0)

IMVP_PW RGD (27,36 )

VR_SVID_A LERT# (8)

H_PROCH OT#

12

PR4243

PR4243 48K7R3F -1-GP

48K7R3F -1-GP

12

PR4249

PR4249 1K54R2F -GP

1K54R2F -GP

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

20101227 A00: Change PR4217~PR4220,PR4254 to 0R 0402 pad.

TEMP_SE NSE_GFX_R

12

PR4255

61K9R2F -GP

1 2

PR4224 100KR2F-L1-G PPR422 4 100KR2F -L1-GP

12

PR4256

PR4256 NTC-220K -2-GP

NTC-220K -2-GP

NTCG104QH224HT

1D05V_P WR

PWR_ VCORE_DB1

12

PR4244

PR4244 221KR2F -GP

221KR2F -GP

PWR_ VCORE_DCMDRP 1

12

20101012

PC4228

PC4228 SC2200P 50V2KX-2GP

SC2200P 50V2KX-2GP

VT1316+1317_CPU_CORE(1/3)

Nirvana 13

20101012

12

PR4245

PR4245 158KR2F -GP

158KR2F -GP

12

PR4250

PR4250 5K11R2F -L1-GP

5K11R2F -L1-GP

GND_131 6

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

42 1 03Tuesday, January 18, 2011

1

H_PROCH OT#

DB1_GFX

12

PR4246

PR4246 475KR3F -GP

475KR3F -GP

PWR_ VCORE_DCMDRP 2

12

PC4229

PC4229 SC2200P 50V2KX-2GP

SC2200P 50V2KX-2GP

of

A00

3D3V_PW R

D D

1D05V_P WR

12

PR4215

DY

100R2F-L 1-GP-U

12

C C

B B

A A

PR4221

PR4221 6K98R2-G P

6K98R2-G P

PC4214

SCD022U16V2KX-3GP

GND_131 6

12

PR4216

DY

100R2F-L 1-GP-U

PC4231

12

SCD022U16V2KX-3GP

1 2

PG4203

PG4203 GAP-CLOS E-PWR

GAP-CLOS E-PWR

5

GND_131 6

12

PR4222

PR4222 8K87R2F -2-GP

8K87R2F -2-GP

1KR2F-3-G P

DMN601K -7-GP

PWR_ VCORE_IDES1_N(43) PWR_ VCORE_IDES1_P(43)

IDES_N_GF X(44 ) IDES_P_GF X(44)

PR4251

DY

PQ4202

12

DY

GND_131 6

PQ4202_ DPWR_V CORE_IDES1_P

DS

PWR_ VCORE_IDES1_N PWR_ VCORE_IDES1_P

PR42251 30KR2F-GP PR422513 0KR2F-GP PR42264 4K2R2D-GP PR 422644K2R2D-GP PR42294 4K2R2D-GP PR 422944K2R2D-GP

PR423123K7R2F -GP PR423123 K7R2F-GP PR423239K2R2F -L-GP PR423 239 K2R2F-L-GP PR423439K2R2F -L-GP PR423 439 K2R2F-L-GP PR423532K4R2F -1-GP PR423 532 K4R2F-1-GP PR423627K4R2F -GP PR423627 K4R2F-GP PR423739K2R2F -L-GP PR423 739 K2R2F-L-GP PR42013K74R2F -GP PR42013K 74R2F-GP

G

DMN601K -7-GP

4

5

PR4202

1 2

6K19R2F -GP

1 2

PC4202 SC1KP50V2KX-1G PPC4 202 SC1KP5 0V2KX-1GP

4

PR4203

1 2

11K3R2F -2-GP

PWR_ VCORE_IDES1_N_ 2

12

PC4203

PC4203 SC4700P 50V2KX-1GP

SC4700P 50V2KX-1GP

3

5V_S5

12

PC4204

PC4208

2

12

PC4205

12

PC4206

PC4209

PC4210

12

PC4207

1

D D

PR4213

1 2

6K19R2F -GP

PC4212

PWR_ VCORE_IDES0_P_ 1

1 2

SC1KP50 V2KX-1GP

PWR_ VCORE_SPHASE _0(42)

C C

PWR_ VCORE_IDES1_N(42)

PWR_ VCORE_IDES1_P(42)

B B

PWR_ VCORE_IDES1_N

PWR_ VCORE_IDES1_P

SC1KP50 V2KX-1GP

PR4230

1 2

6K19R2F -GP

1 2

PC4216 SC1KP50V2KX-1G PPC4 216 SC1KP5 0V2KX-1GP

PWR_ VCORE0_IDES_P_ 1

12

PR4206

3K09R2F -1-GP

PR4214

1 2

11K3R2F -2-GP

5V_S5

PR4227

1 2

11K3R2F -2-GP

PWR_ VCORE_IDES1_N_ 1

PWR_ VCORE1_IDES_P_ 1

PR4241

3K09R2F -1-GP

PWR_ VCORE0_IDES_N PWR_ VCORE0_IDES_P

PWR_ VCORE_DB0(42) PWR_ VCORE_DB1(42) PWR_ VCORE_DB2(42)

PR4211

1 2

10R2J-2-G P

SCD1U25 V3KX-GP

12

PC4217

PC4217 SC4700P 50V2KX-1GP

SC4700P 50V2KX-1GP

12

PC4215

C6

E6

PU4202

A5

IDES_N

A4

IDES_P

A6

DB0

A1

DB1

B1

DB2

B6

SPHASE

74.01317.B3Z

AGND

A2

B2

E3

PG4201

GAP-CLOS E-PWR

GND_131 7S_1

74.01317.B3Z

1 2

A3

AVDD

B3

AGND

B4

AGND

B5

AGND

PU4202_AVDD

12

VT1317S FCX-001-GP

G6

VDDHC4VDDHC5VDDH

VDDHE4VDDHE5VDDH

VDDHG4VDDHG5VDDH

VDDHJ4VDDHJ5VDDH

GNDC1GNDC2GND

GNDE1GNDE2GND

GNDJ1GNDJ2GND

J3

C3

G3

5V_S5

PC4220

SC10U6D3V3MX-GP

J6

VX#H1 VX#H2 VX#H3 VX#H4 VX#H5 VX#H6 VX#D1 VX#D2 VX#D3 VX#D4 VX#D5 VX#D6 VX#F6 VX#F5 VX#F4 VX#F3 VX#F2 VX#F1

GNDG1GNDG2GND

12

PC4221

SC10U6D3V3MX-GP

H1 H2 H3 H4 H5 H6 D1 D2 D3 D4 D5 D6 F6 F5 F4 F3 F2 F1

12

SC10U6D3V3MX-GP

PWR_ VCORE_VX0

12

PC4222

PC4223

SC10U6D3V3MX-GP

SC1U10V2KX-1GP

SCD1U25V3KX-GP

SC10U6D3V3MX-GP

20101231 A00: Power/Brian: change PL4201 to 68.2415N.101 from 68.10110.10G.

12

PC4225

PC4224

SC1U10V2KX-1GP

SCD1U25V3KX-GP

4

3

PL4201

PL4201 IND-240NH-G P

IND-240NH-G P

1

2

68.2415N.101

12

PC4226

SCD1U25V3KX-GP

VCC_COR E

C6

E6

G6

J3

VDDHG4VDDHG5VDDH

GNDJ1GNDJ2GND

VDDHJ4VDDHJ5VDDH

G3

J6

PWR_ VCORE_VX1

H1

VX#H1

H2

VX#H2

H3

VX#H3

H4

VX#H4

H5

VX#H5

H6

VX#H6

D1

VX#D1

D2

VX#D2

D3

VX#D3

D4

VX#D4

D5

VX#D5

D6

VX#D6

F6

VX#F6

F5

VX#F5

F4

VX#F4

F3

VX#F3

F2

VX#F2

F1

VX#F1

GNDG1GNDG2GND

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

VT1316+1317_CPU_CORE(2/3)

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

VT1316+1317_CPU_CORE(2/3)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

43 1 03Tuesday, January 18, 2011

of

43 1 03Tuesday, January 18, 2011

of

43 1 03Tuesday, January 18, 2011

1

A00

PU4203

PR4247

1 2

6K19R2F -GP

PC4227

SC1KP50 V2KX-1GP

PWR_ VCORE_SPHASE _1(42)

A A

5

PWR_ VCORE_IDES1_P_ 1

1 2

4

PR4248

1 2

11K3R2F -2-GP

5V_S5

PWR_ VCORE1_IDES_N PWR_ VCORE1_IDES_P

PWR_ VCORE_DB0(42) PWR_ VCORE_DB1(42) PWR_ VCORE_DB2(42)

PR4242

1 2

10R2J-2-G P

PC4230

SCD1U25 V3KX-GP

PU4203_AVDD

12

PU4203

A5

IDES_N

A4

IDES_P

A6

DB0

A1

DB1

B1

DB2

B6

SPHASE

A3

AVDD

B3

AGND

B4

AGND

B5

AGND

VT1317S FCX-001-GP

A2

B2

GND_131 7S_2

3

VDDHC4VDDHC5VDDH

VDDHE4VDDHE5VDDH

74.01317.B3Z

GNDC1GNDC2GND

GNDE1GNDE2GND

E3

C3

PG4202

1 2

GAP-CLOS E-PWR

5

D D

PR4402

20101012

IDES_N_GF X(42 )

C C

IDES_P_GF X(42)

1 2

3K24R2F -GP

PC4413

1 2

SC2700P 50V2KX-1-GP

PC4422

1 2

SC2700P 50V2KX-1-GP

PR4406

1 2

20101012

3K24R2F -GP

1 2

IDES_N_GF X_1

IDES_P_GF X_1

1 2

4

PR4403

11KR2F-L -GP

PWR_ AXG_IDES_P_1

PR4404

3K09R2F-1-GP

PR4405

11KR2F-L -GP

DB0_GFX(42) DB1_GFX(42) DB2_GFX(42)

SPHASE_ GFX(42)

PC4414

12

SC4700P 50V2KX-1GP

12

PWR_ AXG_IDES_P

PC4427

SCD1U25 V3KX-GP

5V_S5

12

PR4401

PR4401 10R2J-2-G P

10R2J-2-G P

PWR_AXG_AVDD

12

3

320mils or Copper Shape

5V_S5

12

PWR_ AXG_VXPWR_ AXG_IDES_N

12

PC4418

PC4417

SC10U6D3V3MX-GP

PL4401

1 2

IND-D1UH-26 -GP

68.R1010.10T

SC10U6D3V3MX-GP

PC4415

PC4416

SC10U6D3V3MX-GP

C6

E6

G6

PU4401

A5

IDES_N

A4

IDES_P

A6

DB0

A1

DB1

B1

DB2

B6

SPHASE

A3

AVDD

B3

AGND

B4

AGND

B5

AGND

74.01317.B3Z

AGND

A2

B2

E3

VDDHC4VDDHC5VDDH

VDDHE4VDDHE5VDDH

GNDC1GNDC2GND

GNDE1GNDE2GND

J6

H1

VX#H1

VDDHG4VDDHG5VDDH

VDDHJ4VDDHJ5VDDH

GNDJ1GNDJ2GND

J3

C3

G3

H2

VX#H2

H3

VX#H3

H4

VX#H4

H5

VX#H5

H6

VX#H6

D1

VX#D1

D2

VX#D2

D3

VX#D3

D4

VX#D4

D5

VX#D5

D6

VX#D6

F6

VX#F6

F5

VX#F5

F4

VX#F4

F3

VX#F3

F2

VX#F2

F1

VX#F1

GNDG1GNDG2GND

VT1317S FCX-001-GP

12

PC4420

PC4419

SC1U10V2KX-1GP

0.12UH~0.15UH

0.12UH~0.15UH0.12UH~0.15UH

PC4423

12

PC4402

PC4403

DY

2

12

PC4421

SC1U10V2KX-1GP

SCD1U25V3KX-GP

2120mils or Copper Shape

12

PC4424

PC4401

SC22U6D3V5MX-2GP

12

PC4425

SC22U6D3V5MX-2GP

12

PC4426

SC22U6D3V5MX-2GP

2120mils or Copper Shape

12

PC4404

12

PC4405

12

PC4407

PC4406

12

PC4408

1

VCC_GFX CORE

12

PC4409

12

PC4410

PC4411

12

PC4412

B B

GND_131 7S_3

A A

5

4

1 2

PG4401

PG4401 GAP-CLOS E-PWR

GAP-CLOS E-PWR

3

SC22U6D3V5MX-2GP

2

SC22U6D3V5MX-2GP

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

SC22U6D3V5MX-2GP

VT1316+1317_AXG_CORE(3/3)

Nirvana 13

SC22U6D3V5MX-2GP

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

44 1 03Tuesday, January 18, 2011

1

A00

of

A00

5

DCBATOU T PW R_1D05V_DCBAT OUT

PG4520 GAP-CL OSE-PWRPG4 520 GAP-CLO SE-PWR

1 2

D D

C C

B B

PG4512 GAP-CL OSE-PWRPG4 512 GAP-CLO SE-PWR

1 2

PG4524 GAP-CL OSE-PWRPG4 524 GAP-CLO SE-PWR

1 2

PG4526 GAP-CL OSE-PWRPG4 526 GAP-CLO SE-PWR

1 2

1.05VTT_ PWRGD(37,48)

PR4514 0R0402-PADPR 4514 0R040 2-PAD

RUNPW ROK(19,46,47 )

20101224 A00 Modify: Change PR4514 to 0ohm short pad from 0402 and un-stuff PC4523 at X-Build stage.

1 2

3D3V_S0

PR4501

1 2

75KR2F-G P

12

DY

SC1KP50V2KX-1GP

PC4523

TPS51218 for 1D05V_VTT

PR4519

12

10KR2J-3 -GP

PWR_ 1D05V_TRIP

PWR_ 1D05V_EN

PWR_ 1D05V_CCM

12

PR4520

PR4520 470KR2F -GP

470KR2F -GP

PU4503

1 2 3 4 5

TPS5121 8DSCR-GP-U1

PGOOD TRIP EN VFB CCM

4

GND

VBST

DRVH

V5IN

DRVL

SW

11

PWR_ 1D05V_VBST

10

PWR_ 1D05V_DRVH

9

PWR_ 1D05V_SWPW R_1D05V_V FB

8 7

PWR_ 1D05V_DRVL

6

PWR_ 1D05V_VBST_R

PR4518

1 2

2D2R3-1-U -GP

Id=26.5A Qg=40.6~61nC, Rdson=2.6~3.2mohm

3

PWR_ 1D05V_DCBATO UT

PU4502

Id=14.3A Qg=9.2~14nC Rdson=11~14mohm

PC4525

PC4525 SCD1U25 V3KX-GP

SCD1U25 V3KX-GP

12

5V_S5

PC4527

12

SC1U10V2KX-1GP

PU4504

678

DDD

SSS

GD

SSS

GD

123

4 5

678

DDD

D

DDD

D

SSS

G

123

4 5

VTT_SEN SE_L

VSS_SEN SE_L

12

SIR172DP-T 1-GE3-GP

84.00172.037

SIR460DP-T 1-GE3-GP

84.00460.037

12

DY

12

PC4526

PC4529

SC4D7U25V5KX-GP

Mag. 0.56uH 10*10*4 DCR=1.6~1.8mohm Idc=25A, Isat=40A

1 2

12

PR4522

PR4522 2D2R5F-2 -GP

2D2R5F-2 -GP

DY

PWR_1D05V_SNUB

12

PC4530

DY

SC560P5 0V-GP

PR4515

1 2

0R0402-P AD

PC4532

PC4532 SC1000P 50V3JN-GP-U

SC1000P 50V3JN-GP-U

PR4510

1 2

0R0402-P AD

12

PC4506

SC4D7U25V5KX-GP

PL4502

IND-D56UH-2 7-GP

VTT_SEN SE_L

PWR_ 1D05V_VFB

VSS_SEN SE_L

2

12

PC4531

SCD1U25V3KX-GP

PR4516

PR4516 100R2F-L 1-GP-U

100R2F-L 1-GP-U

PR4523

9K76R2F -1-GP

PR4513

20KR2F-L -GP

PR4517

100R2F-L 1-GP-U

VCCIO_SEN SE (8)

VSSIO_SEN SE (8)

Design Current = 9.9A

15.6A<OCP< 18.3A

1D05V_P WR

12

PC4528

12

20101224 A00: Rename PTC4502,PTC4509 to PT4502~PT4509.

12

PT4502

12

SCD1U10V2KX-4GP

ST330U2VDM-4-GP

79.33719.20L

2nd = 77.C3371.13L

DY

12

PT4509

SCD1U25V3KX-GP

Vout=0.704V*(R1+R2)/R2

1

1D05V_V TT1 D05V_PWR

PG4517 GAP-CL OSE-PWRPG4 517 GAP-CLO SE-PWR

1 2

PG4516 GAP-CL OSE-PWRPG4 516 GAP-CLO SE-PWR

1 2

PG4513 GAP-CL OSE-PWRPG4 513 GAP-CLO SE-PWR

1 2

PG4514 GAP-CL OSE-PWRPG4 514 GAP-CLO SE-PWR

1 2

PG4515 GAP-CL OSE-PWRPG4 515 GAP-CLO SE-PWR

1 2

PG4518 GAP-CL OSE-PWRPG4 518 GAP-CLO SE-PWR

1 2

PG4519 GAP-CL OSE-PWRPG4 519 GAP-CLO SE-PWR

1 2

PG4521 GAP-CL OSE-PWRPG4 521 GAP-CLO SE-PWR

1 2

PG4522 GAP-CL OSE-PWRPG4 522 GAP-CLO SE-PWR

1 2

PG4523 GAP-CL OSE-PWRPG4 523 GAP-CLO SE-PWR

1 2

PG4525 GAP-CL OSE-PWRPG4 525 GAP-CLO SE-PWR

1 2

PG4527 GAP-CL OSE-PWRPG4 527 GAP-CLO SE-PWR

1 2

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51218_1D05V_VTT

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

45 1 03Tuesday, January 18, 2011

of

45 1 03Tuesday, January 18, 2011

of

45 1 03Tuesday, January 18, 2011

1

A00

5

4

3

2

1

SSID = PWR.Plane.Regulator_1p5v0p75v

PC4621

SCD1U10V2KX-4GP

PG4603

PG4604

PG4605

PG4606

+PWR _SRC_1D5V

12

1D5V_PW R

PT4602

12

SE220U2VDM-8GP

12

PT4601

DCBATOU T

5V_S5

1 2

SC10U25V6KX-1GP

IND-D68UH-5 1-GP-U

+PWR _SRC_1D5V

PC4611

SC10U25V6KX-1GP

PL4601

1 2

PR4607

1 2

0R0402-P AD

12

PC4614

SCD1U50V3KX-GP

1 2

DY

PG4607

GAP-CLOSE-PWR-3-GP

PWR_ 1D5V_EN

12

PC4606

PC4606 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

PC4614

SC4D7U25V5KX-GP

12

PC4613

PC4612

1 2

PC4613

1 2

SC10U25V6KX-1GP

PWR_1D5V_VDDQS

D D

RUNPW ROK(19,45 ,47)

12

PR4603

PR4603 10KR2F-2 -GP

10KR2F-2 -GP

C C

PC4603

SCD1U25V3KX-GP

12

1 2

PR4601

PC4602

SCD01U16V2KX-3GP

PR4606

240R2F-1-GP

State S3 S5 VDDR VTTREF VTT

B B

S4/S5

MODE

3D3V_S0

PR4604

PR4604 20KR2J-L 2-GP

20KR2J-L 2-GP

1 2

12

200KR2F-L-GP

82KR2F-1-GP

PR4602

Hi Hi

0D75V_E N

PWR_ 1D5V_EN

PWR_ 1D5V_VREF

PWR_ 1D5V_REFIN

PWR_ 1D5V_MODE

PWR_ 1D5V_TRIP

PWR_ 1D5V_VTTREF

12

PC4610

PC4610 SCD22U6 D3V2KX-1GP

SCD22U6 D3V2KX-1GP

HiLo

0D75V_E N(3 7)

47KR2F-GP

1 2

PR4601_1

12

PR4608

1 2

S0

S3

Lo Lo

PR5003

200k ohm

100k ohm

68k ohm

Frequency Discharge Mode

400kHz

300kHz

47k ohm 400kHz

PU4601

20

PGOOD

17

VTTEN

16

EN/PSV

6

VREF

8

REFIN

19

MODE

18

TRIP

5

VTTREF

21

GND

7

GND

TPS5121 6RUKR-GP

74.51216.073

On

Off(Hi-Z)

Off Off Off

Tracking Discharge

Non-tracking Discharge

VTTGND

On

V5IN

VBST

DRVH

SW

DRVL

PGND

VDDQS

VTTIN

VTT

VTTS

12

PWR_ 1D5V_VBST

15

PWR_ 1D5V_DRVH

14

PWR_ 1D5V_SW

13

TPS5121 6_DRVL

11

10

PWR_ 1D5V_VDDQS

9

2

3

1

4

12

PC4601

SC1U10V3KX-3GP

PR4605

1 2

2D2R3J-2 -GP

+0D75V_ DDR_P

12

PC4615

SCD1U10V2KX-4GP

+0D75V_ DDR_P 0D7 5V_S0

PWR_ 1D5V_VTTREF

12

PC4616

SC10U6D3V5MX-3GP

12

DY

PC4617

PG4601

1 2

GAP-CLOS E-PWR

PG4602

1 2

GAP-CLOS E-PWR

PC4619

PC4619 SCD1U25 V3KX-GP

SCD1U25 V3KX-GP

PR4605_2

1 2

SC10U6D3V5MX-3GP

DDR_VRE F_S3

PR4611

1 2

0R0603-P AD

GD

4 5

DDD

G

4 5

678

DDD

678

SSS

123

D

SSS

123

PU4602

SIR172DP-T 1-GE3-GP

84.00172.037

PC4604

SC1U10V3KX-3GP

PM_SLP_ S4#(19,27)

12

DY

TPS5121 6_PHS_SET

12

DY

1D5V_PW R

PU4603

SIR460DP-T1-GE3-GP

12

PC4609

1 2

PR4612

PR4612 2D2R5F-2 -GP

2D2R5F-2 -GP

PC4622

PC4622 SC330P5 0V2KX-3GP

SC330P5 0V2KX-3GP

20101230 A00: Follow the standard schematics: remove PR4615,PR4616.

20101224 A00 Modify: Change PR4607 to short pad at X-Build.

GAP-CLOS E-PWR

Design Current = 14.45A

22.71A<OCP< 26.84A

12

PC4620

SC4D7U6D3V5KX-3GP

20101224 A00: Rename PTC4601,PTC4602 to PT601~PT4602.

1D5V_PW R 1D5V_S 3

SE220U2VDM-8GP

1 2

PG4608

PG4608 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4609

PG4609 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4610

PG4610 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4611

PG4611 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4612

PG4612 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4613

PG4613 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4614

PG4614 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4615

PG4615 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4616

PG4616 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4617

PG4617 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4618

PG4618 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4619

PG4619 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4620

PG4620 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4621

PG4621 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4622

PG4622 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4623

PG4623 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4624

PG4624 GAP-CLOS E-PWR

GAP-CLOS E-PWR

1 2

PG4625

PG4625 GAP-CLOS E-PWR

GAP-CLOS E-PWR

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51116_+1.5V_SUS

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

46 1 03Tuesday, January 18, 2011

of

46 1 03Tuesday, January 18, 2011

of

46 1 03Tuesday, January 18, 2011

1

A00

5

4

SSID = PWR.Plane.Regulator_1p8v

3

2

1

D D

1A= 40mils

1.5A= 60mils

0.5A= 20mils

3D3V_S5

SCD1U25 V3KX-GP

PU4701

12

C C

12

DY

PR4717

PR4717 57K6R2F -GP

57K6R2F -GP

B B

PC4702 SC 100P50V2JN-3G PPC4702 SC100P 50V2JN-3GP

1 2

PR4705

PWR_ 1D8V_FB_1

1 2

5K9R2F-G P

3D3V_S0

RUNPW ROK(19,45,46 )

PM_SLP_ S3#(19,27,36,3 7)

1 2

PC4718 SC 2200P50V2KX-2 GPPC471 8 SC220 0P50V2KX-2GP

PWR_ 1D8V_PS

PR4707 20KR2J-L2-GPPR4707 20K R2J-L2-GP

1 2

PR4715 10 KR2J-3-GPPR47 15 10KR2 J-3-GP

PWR_ 1D8V_FB

PWR_ 1D8V_COMP

1 2

12

1D8V_EN

PC4703

PC4703 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

VDD

11

AGND

17

PGND

10

FB

9

COMP

2

RES

8

MODE

3

PGOOD

1

EN

TPS5131 1RGTR-GP

74.51311.073

PGND PGND

VBST

SW#5 SW#6 SW#7

13

VIN

14

VIN

15 16

PWR_ 1D8V_VBST PW R_1D8V_VBST _1

4

PWR_ 1D8V_SW

5 6 7

PR4706

1 2

0R0603-P AD

SCD1U25 V3KX-GP

PC4716

SCD1U25 V3KX-GP

PC4708

12

68.2R210.20B

PWR_ 1D8V_VIN

12

PC4715

PC4715 SC10U6D 3V5MX-3GP

SC10U6D 3V5MX-3GP

PL4701

IND-2D2UH-4 6-GP-U

1 2

PC4717

SC2200P 50V2KX-2GP

PC4717

PR4718

PR4718 40D2R2F -GP

40D2R2F -GP

12

PR4702

PWR_1D8V_FB_2

12

PWR_ 1D8V_FB

20KR2F-L-GP

12

PR4716

PR4716 10KR2F-2 -GP

10KR2F-2 -GP

1 2

PG4701

GAP-CLOS E-PWR

1 2

PG4702

GAP-CLOS E-PWR

PC4721

PC4721 SC10U6D 3V5MX-3GP

SC10U6D 3V5MX-3GP

PWR_ 1D8V_RUN 1D8V _S0

12

PC4719

DY

SC10U6D3V5MX-3GP

PC4720

12

PC4707

SCD1U25 V3KX-GP

1 2

GAP-CLOS E-PWR

1 2

GAP-CLOS E-PWR

1 2

GAP-CLOS E-PWR

SC22U6D3V5MX-2GP

3D3V_S5

PG4704

PG4705

PG4706

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51311_ +1.8V_RUN

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

TPS51311_ +1.8V_RUN

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

47 1 03Tuesday, January 18, 2011

of

47 1 03Tuesday, January 18, 2011

of

47 1 03Tuesday, January 18, 2011

1

A00

5

4

3

2

1

TPS51461 for VCCSA

19 20 21 22 23 24 25

VCCSA_PWM

PGND PGND PGND VIN VIN

VCCSA_PWM

VIN GND

VCCSA_PWM

3D3V_S0

12

PR4809

PR4809 4K7R2J-2-GP

4K7R2J-2-GP

PR4808

1 2

0R0402-PAD

VCCSA_PWM

PWR_VC CSA_VID1

PWR_VC CSA_VID0

17

13

18

15

16

VID014VID1

V5FILT

V5DRV

PGOOD

GND1VREF2COMP3SLEW4VOUT5MODE

6

PWR_VCCSA_VREF

PWR_VC CSA_VOUT

PWR_VC CSA_SLEW

12

PR4802

PR4802 4K99R2F-L-GP

4K99R2F-L-GP

PWR_VCCSA_COMP_1PWR_VCCSA_COMPPWR_VCCSA_PGOOD

12

PC4817

PC4817 SC3300P50V3KX-1G P

SC3300P50V3KX-1G P

PC4802

PC4802 SCD22U10V2KX- 1GP

SCD22U10V2KX- 1GP

1 2

PWR_VC CSA_EN

EN

BST SW#11 SW#10

SW#9 SW#8 SW#7

VCCSA_PWM

D85V_PWR GD (4 2)

PR4804

1 2

0R0402-PAD

0R0402-PAD PR4805

PR4805

1 2

0R0402-PAD

12

DY

PC4804

SC1U6D3V2KX- GP

U4801

TPS51461RGER- GP

PWR_VC CSA_BST

12 11 10 9 8

PWR_VC CSA_SW

7

74.51461.043

PC4806

PC4806 SCD01U50V2KX- 1GP

SCD01U50V2KX- 1GP

1 2

DY

PR4812

1 2

1KR2F-3-GP

VCCSA_PWM

VCCSA_SEL (9)

H_FC_C22 (9)

VCCSA_PWM

PR4801

1 2

0R0402-PAD

1 2

PR4811

VCCSA_PWM

1 2

100R2F-L1-GP- U

PR4810

1 2

0R0402-PAD

PR4807

PR4807 0R0603-PAD

0R0603-PAD

VCCSA_PWM

1.05VTT_PW RGD (37,45)

VCCSA_PWM

PWR_VC CSA_BST_R

0D85V_S0

VCCUSA_SEN SE (9)

PC4805

SCD1U25V3KX- GP

VCCSA_PWM

SB modify 2K2 for no run code

1 2

12

PR4803

DY

2D2R5F-2-G P

PWR_VCCSA_SNUB

12

PC4818

DY

SC560P50V-GP

D85V_PWR GD(42)

PL4801

VCCSA_PWM

1 2

IND-D47UH- 22-GP

68.R4710.10M

VCCSA_LDO

1.05VTT_PW RGD(37,45)

3D3V_S0

12

R4807

R4807 2K2R2J-2-GP

2K2R2J-2-GP

SC1U6D3V2KX- GP

Design Current = 4.2A

6.6A<OCP< 7.8A

0D85V_S0

PC4811

PC4810

PC4801

PC4808

PC4809

PC4807

SC22U6D3V5MX-2GP

12

DY

SC22U6D3V5MX-2GP

12

DY

VCCSA_PWM

PC4801

SC22U6D3V5MX-2GP

12

DY

VCCSA_PWM

APL5916 for VCCSA

5V_S5

12

VCCSA_LDO

7

POK

8

EN

VCCSA_LDO

U4802

U4802 APL5916KAI-TRL-GP

APL5916KAI-TRL-GP

74.05916.031

6

5

VIN

9

VIN

VCNTL

3

VOUT

4

VOUT

2

FB

GND

1

PC4823

DY

PC4825

PC4825 SC1U6D3V2KX- GP

SC1U6D3V2KX- GP

12

PC4812

SCD1U25V3KX-GP

VCCSA_LDO

PR4814

10KR2F-2-GP

80K6R2F-GP

VCCSA_LDO

12

R1

PR4815

PC4824

SC10U6D3V5MX-3GP

R2

PC4822

12

VCCSA_LDO

12

VCCSA_LDO

PWR_VC CSA_FB

12

160KR2F-GP

1D05V_VTT

SC10U6D3V5MX- 3GP

12

VCCSA_LDO

12

PR4816

DY

PC4820

SC100P50V2JN-3GP

VCCSA_LDO

Iomax=6A OCP>9A VCCSA=0.85V

20101224 A00: Rename PTC4801 to PT4801.

12

PC4827

VCCSA_LDO

SC10U6D3V5MX-3GP

12

PC4821

DY

PT4801

PT4801 ST100U6D3VBM- 7GP

ST100U6D3VBM- 7GP SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

0D85V_S0

5V_S5

12

VCCSA_PWM

PC4814

SC1U10V2KX-1GP

D D

5V_S5

12

PC4803

VCCSA_PWM

SCD1U25V3KX-GP

C C

VID0 VCCSA

L

12

PC4815

SC4D7U25V5KX-GP

VID1

L

PR4806

PR4806 1R2F-GP

1R2F-GP

12

PC4813

VCCSA_PWM

SC4D7U25V5KX-GP

VCCSA_PWM

H

B B

H

VCCSA_PWM

12

PC4819

VCCSA_PWM

SC4D7U25V5KX-GP

0.9V

0.8VL

0.725VL

0.675V

PC4816

SC2D2U10V3KX-1GP

PWR_VCCSA_V5DRV

SC1U10V2KX-1GP

PQ4801_D

Vout=0.8*(1+R1/R2)

2N7002KDW -GP

VCCSA_SEL VCCSA_PWR

L

A A

5

4

H

0.9V

0.8V

3

2N7002KDW -GP

2nd = 84.DM601.03F

PQ4801

84.2N702.A3F

6

DY

123 4

PQ4801_5

3D3V_S0

5

PR4818

10KR2F-2-GP

PQ4801_G

2

PR4813

1 2

VCCSA_SEL (9)

DY

12

10KR2J-3-GP

DY

PC4826

PC4826 SCD1U10V2KX- 4GP

SCD1U10V2KX- 4GP

12

DY

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Documen t Number Rev

A2

Date: Sheet of

Date: Sheet

Taipei Hsie n 221, Taiwan, R.O.C.

TPS51461_VCCSA

Nirvana 13

1

48 103Tuesday, January 18, 2011

A00

of

SSID = VIDEO

DBC_EN_ C

LVDS CONNECTOR

LCD1

31

NP1

NP2

32

PS-CON30 -GP

20.F1816.030

CAMERA and DIGITAL MIC PIN DEFINE!

DCBATOU T_LCD

1

2 3 4 5 6 7 8 9 10 11 12

LVDSA_C LK_R

13

LVDSA_C LK#_R

14 15

LVDSA_D ATA2_R

16

LVDSA_D ATA2#_R

17 18

LVDSA_D ATA1_R

19

LVDSA_D ATA1#_R

20 21

LVDSA_D ATA0_R

22

LVDSA_D ATA0#_R

23 24 25 26 27 28 29 30

BLON_OU T_C_1 LCD_BRIGH TNESS DBC_EN_ C

USB_CAM ERA# USB_CAM ERA

CE_C

12

1

LCDVDD

C4901

SCD1U10V2KX-5GP

SD103AWS-1-GP

TP4904TPAD14-GPTP4 904TPAD14-GP

R4901

12

33R2J-2-G P

12

R4906

R4906 10KR2J-3 -GP

10KR2J-3 -GP

DY

83.1R504.A8F

2nd = 83.1R504.B8F

PD4901

K A

3D3V_CA MERA_S0

1 2

R49080R2 J-2-GP R 49080R 2J-2-GP

1 2

R49090R2 J-2-GP R 49090R 2J-2-GP

AUD_DMIC_ CLK (29,97)

AUD_DMIC_ IN0 (2 9,97)

TP4903TPAD14-GPTP4 903TPAD14-GP

LVDS_DD C_DATA_R (17,97) LVDS_DD C_CLK_R (17,9 7)

C4902

SC1U6D3 V2KX-GP

1 2

BLON_OU T_C

R4902

R4902 33R2J-2-G P

33R2J-2-G P

3D3V_S0

12

DBC_EN (22)

USB_PN1 2 (18 ) USB_PP1 2 (18)

20101227 A00: Change R4908,R4909,R4903,R4910,R4913~R4916 R4917,R4918 to 0R 0402 pad. 20110111 A00: Change R4908,R4909,R4903,R4910,R4913~R4916 R4917,R4918 to 0R 0402 reisstors.

LVDSA_D ATA2_R LVDSA_D ATA2#_R

LVDSA_D ATA1_R LVDSA_D ATA1#_R

LVDSA_D ATA0_R LVDSA_D ATA0#_R

LVDSA_D ATA2_R LVDSA_D ATA2#_R

LVDSA_D ATA1_R LVDSA_D ATA1#_R

LVDSA_D ATA0_R LVDSA_D ATA0#_R

LVDSA_C LK_R LVDSA_C LK#_R

CE_C

R4903 0R2J-2-GPR4903 0R2J-2-G P

1 2

R4910 0R2J-2-GPR4910 0R2J-2-G P

1 2

R4913 0R2J-2-GPR4913 0R2J-2-G P

1 2

R4914 0R2J-2-GPR4914 0R2J-2-G P

1 2

R4915 0R2J-2-GPR4915 0R2J-2-G P

1 2

R4916 0R2J-2-GPR4916 0R2J-2-G P

1 2

EC4906 SC10P5 0V2JN-4GP

1 2

DY

EC4907 SC10P5 0V2JN-4GP

1 2

DY

EC4908 SC10P5 0V2JN-4GP

1 2

DY

EC4909 SC10P5 0V2JN-4GP

1 2

DY

EC4910 SC10P5 0V2JN-4GP

1 2

DY

EC4911 SC10P5 0V2JN-4GP

1 2

DY

R4917 0R2J-2-GPR4917 0R2J-2-G P

1 2

R4918 0R2J-2-GPR4918 0R2J-2-G P

1 2

DY

12

R4911

33R2J-2-G P

R4912

R4912 10KR2J-3 -GP

10KR2J-3 -GP

L_BKLT_ CTRL (17)

12

SRN2K2J -1-GP

RN9403

LVDS_DD C_CLK_R LVDS_DD C_DATA_R

LVDSA_D ATA2 (1 7) LVDSA_D ATA2# (17)

LVDSA_D ATA1 (1 7) LVDSA_D ATA1# (17)

LVDSA_D ATA0 (1 7) LVDSA_D ATA0# (17)

LVDSA_C LK (1 7) LVDSA_C LK# (17)

CE (2 1)

3D3V_S0

1

23

4

SSID = VIDEO

LCD POWER for ROSA

BAT54CP T-GP

LVDS_VD D_EN(1 7)

LCD_TST _EN(2 7)

LVDS_VD D_EN

R4951

100KR2J -1-GP

12

1

2

83.R2003.E81

2ND = 83.00054.Q81

BLON_OU T_C_1

D4901

BLON_OU T_CLCD_TST _C LCD_TST _C

1 2

3

R4907

1 2

100KR2J -1-GP

DY

R4919

R4919 100KR2J -1-GP

100KR2J -1-GP

R4904

1 2

0R0402-P AD

12

R4905

49K9R2F-L-GP

RN4901

1 2 3

SRN100J -3-GP

U4901

1

EN

2

ENVDDLCDVDD _EN

SCD1U10V2KX-5GP

C4908

12

DY

4

GND OUT3IN#4

G5285T1 1U-GP

74.05285.07F

2nd = 74.09724.09F

BLON_OU T (27)

LCD_TST (27)

IN#5

5

4

3D3V_S0LCDVDD

12

C4907

SC1U10V3KX-3GP

DCBATOU T_LCD DCBATOU T

F4901

12

C4904

20110107 A00: Change F4902 to 0603 0 ohm.

C4905

1 2

SC1KP50V2KX-1GP

Camera Power

F4902

1 2

0R3J-0-U-G P

EC4903

SCD1U10 V2KX-5GP

SCD1U50V3KX-GP

12

POLYSW -1D1A24V-GP-U

69.50007.A31

2nd = 69.50007.A41

3D3V_CA MERA_S03D3V_S0

12

C4903

DY

SC10U6D 3V5KX-1GP

For EMI request

Close to LVDS connector

LCD_BRIGH TNESS LCD_TST _C

LVDSA_C LK# LVDSA_C LK

12

DY

EC4905

DY

SC5D6P50V2CN-1GP

12

EC4904

SC5D6P50V2CN-1GP

12

EC4901

DY

20100104 A00: Remove TR4902.

12

EC4902

DY

SC33P50V2JN-3GP

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

LCD/Inverter Connector

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

LCD/Inverter Connector

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

49 1 03Tuesday, January 18, 2011

A00

5

D D

CRT_RED(17)

CRT_GRE EN(17)

CRT_BLU E(17 )

C C

CRT_RED

CRT_GRE EN

CRT_BLU E

12

R5001

R5002

150R2F-1-GP

12

R5003

150R2F-1-GP

4

L5001

1 2

FCM1608 CF-220T05-GP

L5002

1 2

FCM1608 CF-220T05-GP

L5003

1 2

FCM1608 CF-220T05-GP

12

C5001

C5002

DY

SC10P50V2JN-4GP

12

C5003

DY

SC10P50V2JN-4GP

12

C5004

SC10P50V2JN-4GP

C5006

C5005

SC10P50V2JN-4GP

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

CRT_R

CRT_G

CRT_B

12

3

5V_S0

83.R5003.C8F

500mA

5V_CRT_ S0 5V_CRT_ S0_R

D5001

21

CH551H-3 0PT-GP

CRT_B

3

DY

1

2

FUSE-1D1 A6V-4GP-U

69.50007.691

69.50007.691 2nd = 69.50007.771

2nd = 69.50007.771

D5004

D5004 BAV99PT -GP-U

BAV99PT -GP-U

1

Place closer

F5001

1 2

R5006

1 2

DY

0R3J-0-U-G P

CRT_G

3

DY

2

D5003

D5003 BAV99PT -GP-U

BAV99PT -GP-U

1

2

SCD01U1 6V2KX-3GP

CRT_R

3

DY

2

C5013

D5002

D5002 BAV99PT -GP-U

BAV99PT -GP-U

5V_CRT_ S0_R

12

3D3V_S0

CRT_R

CRT_G

CRT_B

CRT1

16

6 1

7 2 8 3 9 4

10

5

17

D-SUB-15-8 1-GP

CRT_DDC DATA_CON

CRT_HSYNC _CON

CRT_VSYNC _CON

CRT_DDC CLK_CON

12

DY

C5011

1

11

CRT_DDC DATA_CON

12

CRT_HSYNC _CON

13

CRT_VSYNC _CON

14

CRT_DDC CLK_CON

15

12

DY

C5010

12

DY

C5008

C5009

SC18P50V2JN-1-GP

SC100P50V2JN-3GP

CRT DDCDATA & DDCCLK level shift

B B

3D3V_S0

CRT Hsync & Vsync level shift

RN5007

SRN2K2J -1-GP

RN5001

CRT_HSYNC(17) CRT_VSYNC(17)

A A

5

CRT_HSYNC CRT_VSYNC

20101231 A00: Change R5004,R5005 to RN5001 33 ohm array resistor.

RN5001

1 2 3

SRN33J-5 -GP-U

4

CRT_HSYNC _CON CRT_VSYNC _CON

CRT_DDC _DATA(17)

CRT_DDC _CLK(17 )

3

CRT_DDC _CLK

1

23

4

2

3D3V_S0

Q5001

34

2

5

1

6

2N7002K DW-GP

84.2N702.A3F

2nd = 84.DM601.03F

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

5V_CRT_ S0

1

23

RN5003

RN5003 SRN2K2J -1-GP

SRN2K2J -1-GP

4

CRT_DDC DATA_CONCRT_DDC _DATA

CRT_DDC CLK_CON

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CRT Connector

Nirvana 13

50 1 03Tuesday, January 18, 2011

1

A00

of

A00

5

4

3

2

1

SSID = VIDEO

D D

C C

Removed LEVEL SHIFTER base on DELL feedback spec. (No support 220MHZ deep color mode, so can be removed HDMI LEVEL SHIFTER circuit.

RN5102 SRN0J-6-GPRN510 2 SRN0 J-6-GP

HDMI_CLK_ R#(17) HDMI_CLK_ R(17)

HDMI_DATA 0_R#(17) HDMI_DATA 0_R(17)

HDMI_DATA 1_R#(17) HDMI_DATA 1_R(17)

HDMI_DATA 2_R#(17) HDMI_DATA 2_R(17)

20110111 A00: Change R5101~R5108 to 0 ohm array resistors RN5102~RN5105.

2 3 1

RN5103 SRN0J -6-GPRN5103 SRN0J-6 -GP

RN5105 SRN0J -6-GPRN5105 SRN0J-6 -GP

2 3 1

RN5104 SRN0J -6-GPRN5104 SRN0J-6 -GP

HDMI Level Shifter & CONNECTOR

HDMI_PLL_ GND

Q5103

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

5V_S0

12

R5113

R5113 100KR2J -1-GP

100KR2J -1-GP

DY

HDMI_CLK_ R#_1

4

HDMI_CLK_ R_1

HDMI_DATA 0_R#_1 HDMI_DATA 0_R_1

HDMI_DATA 1_R#_1 HDMI_DATA 1_R_1

HDMI_DATA 2_R#_1 HDMI_DATA 2_R_1

C5103 SCD 1U10V2KX-5GPC5103 SCD 1U10V2KX-5GP

1 2

C5104 SCD 1U10V2KX-5GPC5104 SCD 1U10V2KX-5GP

1 2

C5105 SCD 1U10V2KX-5GPC5105 SCD 1U10V2KX-5GP

1 2

C5106 SCD 1U10V2KX-5GPC5106 SCD 1U10V2KX-5GP

1 2

C5110 SCD 1U10V2KX-5GPC5110 SCD 1U10V2KX-5GP

1 2

C5107 SCD 1U10V2KX-5GPC5107 SCD 1U10V2KX-5GP

1 2

C5108 SCD 1U10V2KX-5GPC5108 SCD 1U10V2KX-5GP

1 2

C5109 SCD 1U10V2KX-5GPC5109 SCD 1U10V2KX-5GP

1 2

Close to HDMI Connector

HDMI_PLL_ GND

20100723 Swap RN5106 and RN5107 base in the swap report.

123

678

4 5

RN5106

RN5106 SRN680J -GP

SRN680J -GP

D

G

123

S

678

RN5107

RN5107 SRN680J -GP

SRN680J -GP

4 5

R5123

0R2J-2-GP

DY

1 2

HDMI_CLK_ R_C# HDMI_CLK_ R_C

HDMI_DATA 0_R_C# HDMI_DATA 0_R_C

HDMI_DATA 1_R_C# HDMI_DATA 1_R_C

HDMI_DATA 2_R_C# HDMI_DATA 2_R_C

HDMI CONN

HDMI1

SKT-HDMI23 -GP

22.10296.341

23 21 1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22

R5110

200KR2J -L1-GP

suggestion to stuff 680-ohm for UMA.

B B

20101224 A00: Change RN5117 to 0402 0 ohm pad. 20110111 A00: Change RN5117 to 0 ohm resistor. 20110118 A00: Remove RN5117 for PCH_HDMI_CLK and PCH_HDMI_DATA.

Removed HDMI_IN# CIRCUIT connect to KBC GPIO.

HDMI_DATA 2_R_C

HDMI_DATA 2_R_C# HDMI_DATA 1_R_C

HDMI_DATA 1_R_C# HDMI_DATA 0_R_C

HDMI_DATA 0_R_C# HDMI_CLK_ R_C

HDMI_CLK_ R_C#

DDC_CLK _HDMI DDC_DAT A_HDMI

HPD_HDMI_CON

1 2

R5111 150KR2J -L1-GPR5111 150KR 2J-L1-GP

12

DY

PCH_HDM I_DATA

12

C5102

C5102 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

PMBS390 4-1-GP

HDMI_HPD_ B

3D3V_S0

Q5102

1

3D3V_S0

Q5104

5

6

2N7002K DW-GP

84.2N702.A3F

2nd = 84.DM601.03F

5V_CRT_ S0_R

3

84.03904.L06

2nd = 84.03904.P11

3rd = 84.03904.T11

2

HDMI_HPD_ E

12

R5112

R5112 10KR2J-3 -GP

10KR2J-3 -GP

34

2

1

1 2

R5125 0R0402-P ADR51 25 0R0402-PA D

5V_CRT_ S0_R

4

DDC_CLK _HDMIPCH_HDM I_CLK

DDC_DAT A_HDMI

1

RN5101

RN5101 SRN2K2J -1-GP

SRN2K2J -1-GP

2 3

HDMI_PCH_ DET (17)

Already PH on PCH side.(RN1706)

3D3V_S0

12

DY

R5109

R5109 20KR2J-L 2-GP

20KR2J-L 2-GP

PCH_HDM I_CLK(17)

PCH_HDM I_DATA(1 7)

PCH_HDM I_CLK PCH_HDM I_DATA

Routing Guidelines:

A A

Q5101

2N7002K -2-GP

HPD_HDM I_CON

HDMI_OE#

D

DY

S

G

5

1 2

84.2N702.J31

2ND = 84.2N702.031

DY

R5127

0R2J-2-GP

HDMI_IN# (27)

4

CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm). The total delay on CTRLDATA should be longer than CTRLCLK.

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

HDMI Level Shifter/Connector

Size Document N umber Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

of

51 1 03Tuesday, January 18, 2011

of

51 1 03Tuesday, January 18, 2011

of

51 1 03Tuesday, January 18, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

52 1 03Wednesday, December 22, 20 10

of

52 1 03Wednesday, December 22, 20 10

of

52 1 03Wednesday, December 22, 20 10

A00

5

D D

4

3

2

1

(Blanking)

C C

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

LVDS_Switch

53 1 03Wednesday, December 22, 20 10

1

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

54 1 03Wednesday, December 22, 20 10

of

54 1 03Wednesday, December 22, 20 10

of

54 1 03Wednesday, December 22, 20 10

A00

5

SSID = User.Interface

4

3

2

1

ITP Connector

D D

CPU

TCK(PIN AC5)

C C

B B

H_CPURST# use pull-up Resistor close ITP connector 500 mil ( max ), others place near CPU side.

ITP Connector

TCK(PIN 5)

FBO(PIN 11)

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ITP

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

ITP

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

55 1 03Wednesday, December 22, 20 10

of

55 1 03Wednesday, December 22, 20 10

of

55 1 03Wednesday, December 22, 20 10

1

A00

SSID = SATA

3D3V_S0 5 V_S0

12

C5604

C5601

DY

SATA_TX P0(21) SATA_TX N0(21 )

SATA_RX N0(21)

SATA_RX P0(21)

C5601

DY

SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

C5616 SCD01U1 6V2KX-3GPC5616 SCD01U1 6V2KX-3GP C5615 SCD01U1 6V2KX-3GPC5615 SCD01U1 6V2KX-3GP

1 2 1 2

12

C5605

SC10U10V5ZY-1GP

12

C5606

SCD1U10V2KX-5GP

SATA HDD Connector

HDD1

19

SATA_TX N0_C

SATA_RX N0_C

3D3V_S0

5V_S0

FFS_INT2(79)

TP5602TP AD14-GP TP560 2TPAD1 4-GP

SATA_TX P0_C

C5614SCD01U16V 2KX-3GP C5614SCD01U16V2KX -3GP

12

SATA_TX N0_C

C5613SCD01U16V 2KX-3GP C5613SCD01U16V2KX -3GP

12

SATA_RX N0_C SATA_RX P0_C

HDD1_21

1

3

5

7

9

11

13

15

17

MLX-CONN 18A-S1GP

20.K0229.018

HDD1_20

20

SATA_TX P0_C

2

4

SATA_RX P0_C

6

8

10

12

14

16

18

HDD1_22

2221

TP5601 TPAD1 4-GPTP560 1 TPA D14-GP

1

3D3V_S0

5V_S0

1

TP5603 TPAD1 4-GPTP560 3 TPA D14-GP

ODD Connector

ODD1

8

S1

SATA_TX P4_C

S2

SATA_TX N4_C

S3 S4

SATA_RX 4-_C

S5

SATA_RX 4+_C

S6 S7

P1 P2 P3 P4 P5 P6

9

SKT-SATA 7P+6P-50-GP

62.10065.651

62.10065.651 2nd = 62.10065.221

2nd = 62.10065.221

SATA_RX- and SATA_RX+ Trace Length match within 20 mil

Mars: Exchange ODD and ESATA differential pair each other.

C5612 SCD01U16V 2KX-3GPC5612 SCD01U16V2KX -3GP

1 2

C5611 SCD01U16V 2KX-3GPC5611 SCD01U16V2KX -3GP

1 2

C5607 SCD01U16V 2KX-3GPC5607 SCD01U16V 2KX-3GP

1 2

C5608 SCD01U16V 2KX-3GPC5608 SCD01U16V 2KX-3GP

1 2

SATA_OD D_PRSNT# (2 2)

SATA_OD D_DA#_C

12

R5604

R5604 10KR2J-3 -GP

10KR2J-3 -GP

DY

SATA_RX N4 (21) SATA_RX P4 (21)

ODD_PW R_5V

SATA_OD D_PWRGT SATA_OD D_DA#

AFTP560 1AFTP 5601

SATA_TX P4 (21)

SATA_TX N4 (21 )

12

DY

RN5601

4

SRN10KJ -5-GP

1

R56020R2J-2-GP

SATA_OD D_DA# (18)

3D3V_S0

1 23

SUPPORT ZERO SATA ODD

FFS_INT2

When the drive is powered on, the FET to the MD/DA pin drive is OFF. When the drive is powered off, the FET to the MD/DA pin is ON

5V_S0

R5605

R5605 100KR2J -1-GP

100KR2J -1-GP

1 2

ODD_PWRGT#

SATA_OD D_DA#_C

5

6

Q5601

SATA_OD D_PWRGT SA TA_ODD_DA#

123 4

2N7002K DW-GP

84.2N702.A3F

2nd = 84.DM601.03F

SATA Zero Power ODD

SATA_OD D_PWRGT(22)

U5601

U5601 G547F1P 81U-GP

5V_S0

12

C5609

C5609 SC10U6D 3V5KX-1GP

SC10U6D 3V5KX-1GP

Title

Size Document N umber Rev

A3

Date: Sheet of

G547F1P 81U-GP

EN/EN#4OC#

3

IN#3

2

IN#2

1

GND

74.00547.C79

2ND = 74.02191.079

Current limit Active High typ =>2A

HDD/ODD

Nirvana 13

5

ODD_PW R_5V

6

OUT#6

7

OUT#7

8

OUT#8

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

56 1 03Tuesday, January 18, 2011

A00

5

4

3

2

1

SSID = ESATA

D D

USB CHARGER

U5702

1

S0

2

USB_PN1 _R

C C

S0 S1 0 0 001 1

1

D+

3

D-

4

GND

5

A+

PI5USB145 50AZEE-GP

73.5USB1.003

Auto

D+/- connects to Y+/-

GND

VDD

11

CBUSB_PP1 _R

10

S1

9

Y+

8

Y-

7 6

A-

1 2

R5721 0R0402-P ADR57 21 0R0402-PA D

5V_S5

C5701

1 2

USB_PP1 (18 )

USB_PN1 (18)

USBCHAR GER_CB0 (27)

Switch Control Bit: CB=0 (AM):auto detection charger identification active. CB=1 (PM):connect DP/DM to TDP/TDM.

SCD1U10V2KX-4GP

ESATA CONN

B B

USB_PP1 _R USB_PP1 _C

20100104 A00: Remove R5718,R5719

TR5701

1

WCM2 012F2S-GP-U2

2

69.10084.081

USB_PN1 _CUSB_PN1 _R

34

C5707 SCD01U16V 2KX-3GPC5707 SCD01U16V2KX -3GP

SATA_TX P5(21) SATA_TX N5(21 )

SATA_RX P5(21) SATA_RX N5(21)

1 2

C5708 SCD01U16V 2KX-3GPC5708 SCD01U16V2KX -3GP

1 2

C5705 SCD01U16V 2KX-3GPC5705 SCD01U16V2KX -3GP

1 2

C5702 SCD01U16V 2KX-3GPC5702 SCD01U16V2KX -3GP

1 2

USB_PP1 _C USB_PN1 _C

5V_USB1 _S3

SATA_TX P5_C SATA_TX N5_C

SATA_RX P5_C SATA_RX N5_C

ESATA1

1

VBUS

DT1

6 7

9

3 2

SKT-ESAT A-USB-11P-6-GP-U

DT2

GND

A+

GND

A-

GND B+10GND B-

GND

GND D+

GND D-

GND

22.10321.W11

2nd = 22.10339.261

12 13

4 5 8 11 14 15 16 17

ESATA1_ D1

close to ESATA1

AFTP571 6 AFTE14P-G PAFTP5716 A FTE14P-GP

AFTP571 5

AFTP571 5 AFTP570 3

AFTP570 3

A A

5

4

3

AFTE14P -GP

AFTE14P -GP AFTE14P -GP

AFTE14P -GP

1 1 1

5V_USB1 _S3 USB_PN1 _C USB_PP1 _C

Title

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

R5722

0R0402-P AD

1 2

1

AFTP571 4

AFTP571 4 AFTE14P -GP

AFTE14P -GP

USB/ESATA

Nirvana 13

1

USBDET_ CON# (27)

57 1 03Tuesday, January 18, 2011

1 2

DY

EC5701 SC5 P50V2CN-2GP

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

5

SSID = AUDIO

4

Speaker

3

2

1

Connector

D D

20101224 A00: Change R5803,R5804 to 0603 0 ohm pad.

SPK1

3

1

2

4

JST-CON2 -33-GP

21.D0300.102

1

AFTP580 5AFTP 5805

12

DY

EC5801

MLVG0402220NV05BP-GP-U

40 mils

12

DY

EC5802

MLVG0402220NV05BP-GP-U

AUD_SPK _L-(29)

AUD_SPK _L+(29)

C C

1 2

R5803 0R0603-P ADR5803 0R0603-P AD

1 2

R5804 0R0603-P ADR5804 0R0603-P AD

AFTP580 1AFTP 5801 AFTP580 2AFTP 5802

AUD_SPK _L-_C

AUD_SPK _L+_C

AUD_SPK _L-_C

1

AUD_SPK _L+_C

1

AUD_HP1 _JACK_L2(29)

AUD_HP1 _JACK_R2(29 )

AUD_HP1 _JD#(29 )

AUD_HP1 _JACK_L2 AUD_HP1 _JACK_L2_R

EC5805

SC1KP50 V2KX-1GP

20101224 A00: 0402 0R pad: R5805,R5806.

1 2

R58050R0 402-PAD R58050R0402-P AD

1 2

R58060R0 402-PAD R58060R0402-P AD

12

EC5806

EC5806 SC1KP50 V2KX-1GP

SC1KP50 V2KX-1GP

AFTP581 1AFTP 5811

AFTP580 3AFTP 5803

AFTP580 4AFTP 5804

AUD_HP1 _JACK_R2_RAUD_HP1 _JACK_R2

AUD_HP1 _JD#

1

AUD_HP1 _JACK_L1

1

AUD_HP1 _JACK_R1

1

L5801

1 2

BLM18BD 601SN1D-GP

L5802

1 2

BLM18BD 601SN1D-GP

EC5803

12

SCD01U16V2KX-3GP

AUD_HP1 _JACK_L1

AUD_HP1 _JACK_R1

AUD_HP1 _JD#

12

EC5804

LINE OUT

AFTP581 0AFTP 5810

SCD01U16V2KX-3GP

20101224 A00: Rename LINEOUT1 to LOUT1.

LOUT1

8 7 3 1 4

2 5 6

PHONE-JK 383-GP-U

22.10133.K31

1

MIC IN

B B

600ohm 100MHz 200mA 0.5ohm DC

MIC_IN_L(29 )

MIC_IN_R(2 9)

AFTP580 6AFTP 5806

AFTP580 7AFTP 5807

AFTP580 9AFTP 5809

A A

5

MIC_IN_R

1

MIC_IN_L_C

MIC_IN_R_C

EXT_MIC_J D#

1 2

R5801 BLM18BD 601SN1D-GPR5801 BLM18BD 601SN1D-GP

1 2

R5802 BLM18BD 601SN1D-GPR5802 BLM18BD 601SN1D-GP

EXT_MIC_J D#(29)

4

DY

EC5807

12

MIC_IN_L_CMIC_IN_L

MIC_IN_R_C

EC5808

12

DY

SC100P50V2JN-3GP

1

SC100P50V2JN-3GP

3

MICIN1

8 7 3 1 4

2 5 6

PHONE-JK 383-GP-U

22.10133.K31

AFTP580 8AFTP 5808

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Audio Jack

Nirvana 13

1

A00

58 1 03Tuesday, January 18, 2011

of

58 1 03Tuesday, January 18, 2011

of

58 1 03Tuesday, January 18, 2011

A00

5

D D

4

3

2

1

C C

B B

A A

(Blanking)

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

A00

59 1 03Wednesday, December 22, 20 10

1

A00

5

SSID = Flash.ROM

4

3

2

1

SPI FLASH ROM (4M byte) for PCH

EC6002

DY

12

3D3V_S5

123

678

4 5

SPI_SO SPI_WP #

RN6001

RN6001 SRN4K7J -10-GP

SRN4K7J -10-GP

SPI_HOLD_ 0#

U6001

1

CS#

2

DO

3

WP#

4

VSS

W25 Q32BVSSIG-1-GP

72.25Q32.A01

2nd = 72.25320.C01

2nd = 72.25320.C01 3rd = 72.25P32.C01

3rd = 72.25P32.C01

VCC

HOLD#

CLK

3D3V_S5

8 7 6 5

DI

EC6003

DY

SC4D7P50V2CN-1GP

12

DY

EC6001

SC4D7P50V2CN-1GP

D D

SPI_CS0#_ R(21,27)

SPI_SO_R(21,27)

C C

1 2

R6001 33R2J-2-GPR6001 3 3R2J-2-GP

SC4D7P5 0V2CN-1GP

DY

12

C6001

3D3V_S5

12

C6002

SC10U6D3V5KX-1GP

SPI_CLK_R (21,27) SPI_SI_R (21,27)

Notes: The total SPI interface signal between EC and PCH can’t not exceed 6500mil. The mismatch between SPI signal must be within 500mil

SCD1U10V2KX-5GP

Priority Wistron P/N Manufacturer Vendor P/N

1

2

3

72.25Q32.A01

72.25320.C01

72.25P32.C01

WINDBOND

MXIC

NUMONYX

W25Q32BVSSIG

MX25L3206EM2I-1 2G

M25PX32-VMW6F

B B

SSID = RBATT

RTC_AUX _S5

C6003

SC1U6D3 V2KX-GP

2N7002K -2-GP

A A

RTC_PW R

12

R6003

R6003 10MR2J-L -GP

10MR2J-L -GP

2N7002K -2-GP

G

D

S

Q6002

84.2N702.J31

2ND = 84.2N702.031

5

RTC_DET # (22)

Q6001

3

CH715FP T-GP

1 2

83.R0304.B81

2nd = 83.00040.E81

Width=20mils

3D3V_AU X_S5

2

RTC_PW R

1

4

1 2

TP6002TP AD14-GP TP600 2TPAD1 4-GP

+RTC_VC C

R6002

R6002 1KR2J-1-G P

1KR2J-1-G P

TP6001TP AD14-GP TP600 1TPAD1 4-GP

+RTC_VC C

1

NP1 NP2

1

BAT-0600 03HA002M213Z L-GP

RTC1

1

PWR

2

GND NP1 NP2

62.70014.001

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Flash/RTC

Nirvana 13

A00

60 1 03Tuesday, January 18, 2011

of

60 1 03Tuesday, January 18, 2011

of

60 1 03Tuesday, January 18, 2011

1

A00

5

SSID = USB

4

3

2

1

Close to ESATA Combo connector

Support 2A

U6101

USB POWER SW

D D

Main G547F2P81U-GP P/N:74.00547.A79

12

C6103

C6101

SCD1U10V2KX-5GP

C C

12

at least 80 mil

USB_PW R_EN#(27)

U6101

1

GND

2 3 4

OUT#8

IN#2

OUT#7

IN#3

OUT#6

EN/EN#

G547F2P 81U-GP

74.00547.A79

2nd = 74.00547.079

OC#

8 7 6 5

at least 80 mil

SC1U10V 2KX-1GP

USB_OC# 0_1 (18)

C6102

5V_USB1 _S35V_S5

12

TC6101

TC6101 ST100U6 D3VAM-3-GP

ST100U6 D3VAM-3-GP

80.10715.B1L

2nd = 77.C1071.20L

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

USB2.0 Power SW

61 1 03Tuesday, January 18, 2011

1

of

A00

5

1V_USB30 LDO

4

3

2

1

20101227 A00: Change R6205 to 0R 0402 pad. 20101228 A00: VGA_THRM change to USB_PWR_EN.

D D

20101229 A00: Remove R6205,R6201 and rename USB3_PWR_ON from USB_PWR_EN.

USB3.0 Host

TI 11.8k ohm (64.11825.6DL) 30.9k ohm (64.30925.6DL)

USB3_PW R_ON(27,82)

R6203

U6201

3D3V_S5

12

C6202

SC1U10V 2KX-1GP

SC10U10V5ZY-1GP

C C

C6203

5V_S5

USB3_PW R_ON

12

1

POK

2 3 4

2nd = 74.09025.03D

GND

VEN

GND

VIN

ADJ

VPP

VO

NC#5

G9661-25 ADJF11U-GP

74.09661.07D

9 8 7 6 5

RB

RT

DY

1 2

R6203 7K5R2F-1 -GP

7K5R2F-1 -GP

R6202

R6202 2K37R2F -GP

2K37R2F -GP

1V_USB3 0_LDO_FB (82)

1V_USB3 0

0.6A

Vo = 0.8 * ( 1 + ( RT / RB ) )

12

C6201

SC10U10V5ZY-1GP

RT (R6202) RB (R6203)

2.37k ohm (64.23715.6DL) 7.5k ohm (64.75015.6DL)NEC

VOUT

1.05V

1.1V

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

USB 3.0 Port

Nirvana 13

1

62 1 03Tuesday, January 18, 2011

of

62 1 03Tuesday, January 18, 2011

of

62 1 03Tuesday, January 18, 2011

A00

5

4

3

2

1

SSID = User.Interface

D D

Bluetooth Module

BT1

AFTP6301AFTP6301

AFTP6302AFTP6302

AFTP6304AFTP6304 AFTP6305AFTP6305

C C

AFTP6307AFTP6307

BLUETOOTH_DET#

1

WLAN_ACT BDC_ON

1

BLUETOOTH_EN BT_LED

1

BLUETOOTH_GPIO3

1

BLUETOOTH_GPIO5

1

3 5 7

9 11 13

ACES-CONN14D-GP

20.F1500.014

BT

15 NP1 2

4 6 8 10 12 14 NP2 16

BT_ACT

USB_PP3 USB_PN3

1

AFTP6306AFTP6306

3D3V_S0

12

BT

C6301

SC2D2U6D3V3KX-GP

AFTP6309AFTP6309

USB_PP3(18)

USB_PN3(18)

BT_ACT(65)

BLUETOOTH_EN(27,65)

WLAN_ACT(65)

B B

R6303

1 2

DY

0R2J-2-GP

Q6301

BT_LED

A A

G

BT

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

5

D

WLAN_WW AN_LED#

WLAN_WW AN_LED# (68)

4

12

R6301

DY

EC6301

12

DY

100KR2J-1-GP

BT_ACT BLUETOOTH_EN WLAN_ACT

12

R6302

BT

10KR2J-3-GP

SC220P50V2KX-3GP

3

AFTP6310AFTP6310 AFTP6308AFTP6308 AFTP6311AFTP6311 AFTP6312AFTP6312 AFTP6313AFTP6313

WLAN_ACT

1

BLUETOOTH_EN

1

BT_ACT

1

3D3V_S0

1

USB_PP3

1

USB_PN3

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Bluetooth

Size Document Number Rev

A4

Date: Sheet of

2

Bluetooth

Nirvana 13

63 103Tuesday, January 18, 2011

1

A00

5

3D3V_S0

12

D D

20101227 A00: Change R6403,R6404 to 0R 0402 pad. 20100104 A00: Remove TR6401.

4

C6401

C6401 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

Biometric_USBPP Biometric_USBPN

AFTP40AFTP40

3

FP1

7

1

2 3 4 5 6

8

1

ACES-CON6-7GP

20.K0256.006

2

1

R6403

C C

B B

A A

USB_PN2(18)

USB_PP2(18)

5

R6403

1 2

0R0402-PAD

R6404

1 2

0R0402-PAD

Biometric_USBPN

Biometric_USBPP

4

AFTP42AFTP42 AFTP43AFTP43 AFTP44AFTP44

1 1 1

3

3D3V_S0 Biometric_USBPN Biometric_USBPP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A4

Date: Sheet of

2

Finger Printer Conn

Nirvana 13

64 103Tuesday, January 18, 2011

1

A00

5

4

3

2

1

SSID = Wireless

Mini Card Connector(802.11a/b/g/n)

D D

3D3V_S0 1D5V_S0

C6502

C6501

SCD1U16V2KX-3GP

12

SCD1U16V2KX-3GP

C6503

SC10U6D3V5KX-1GP

DY

12

C6504

SCD1U16V2KX-3GP

WLA N_ACT

C6508

SC220P50V2KX-3GP

E51_RXD(27) E51_TXD(27 )

DY

0R2J-2-GP

1 2 1 2

DY

0R2J-2-GP

12

R6501

R6502

WLA N_LED#(68) WPAN _LED#(68 )

C6505

SC10U6D3V5KX-1GP

12

CLK_PCI_L PC(18,7 1)

C6507

C6506

SCD1U16V2KX-3GP

WLA N_ACT(63)

BT_ACT(63 ) LPC_AD0(21,27,71 ) LPC_AD1(21,27,71 ) LPC_AD2(21,27,71 ) LPC_AD3(21,27,71 )

LPC_FRA ME#(21,27 ,71)

WIFI_RF_ EN(27)

BLUETOO TH_EN(27,6 3)

20101227 A00: Change R6510 to 0R 0603 pad.

SCD1U16V2KX-3GP

R6505 0R2J-2-GP

R6505 0R2J-2-GP R6504 0R2J-2-GP

R6504 0R2J-2-GP R6507 0R2J-2-GP

R6507 0R2J-2-GP R6506 0R2J-2-GP

R6506 0R2J-2-GP R6509 0R2J-2-GP

R6509 0R2J-2-GP

E51_RXD _R E51_TXD _R

3D3V_S0

R6510 0R0603-P ADR6510 0R0 603-PAD

5V_S5

WPAN _LED#

R6511 0R0402-P ADR65 11 0R0402-PA D

20101227 A00: Change R6511 to 0R 0402 pad.

R6508 0R2J-2-GP

1 2

DY

1 2

DY

1 2

DY

1 2

DY

1 2

DY

1 2

R6503

1 2

DY

0R3J-0-U-G P

1D5V_S03D3V_S0

LPC_AD0 _C LPC_AD1 _C LPC_AD2 _C LPC_AD3 _C LPC_FRA ME#_C

+5V_MINI_DEB UG

WPAN _LED#_R

WLA N1

6

1.5V

2

3.3V

28

+1.5V

48

+1.5V

52

+3.3V

24

+3.3VAUX

3

RESERVED#3

5

RESERVED#5

8

RESERVED#8

10

RESERVED#10

12

RESERVED#12

14

RESERVED#14

16

RESERVED#16

17

RESERVED#17

19

RESERVED#19

20

RESERVED#20

37

RESERVED#37

39

RESERVED#39

41

RESERVED#41

43

RESERVED#43

45

RESERVED#45

47

RESERVED#47

49

RESERVED#49

51

RESERVED#51

42

LED_WWAN#

44

LED_WLAN#

46

LED_WPAN#

SKT-MINI52P-42 -GP-U1

62.10043.831

REFCLK+

REFCLK-

PERN0

USB_D-

USB_D+

SMB_CLK

SMB_DATA

WAKE#

CLKREQ#

PERST#

NP1

NP2

NP1

NP2

PERP0

PETN0 PETP0

GND GND GND GND GND GND GND GND GND GND GND GND GND GND

13 11

23 25

31 33

36 38

30 32

1 7 22

4 9 15 18 21 26 27 29 34 35 40 50 53 54

CLK_PCIE_ WLAN (20)

CLK_PCIE_ WLAN# (20)

PCIE_RXN4 (20) PCIE_RXP4 (20)

PCIE_TXN4 (20 ) PCIE_TXP4 (20)

USB_P11 USB_P11 +

PCH_SMB CLK (14,15,20,7 9,82)

PCH_SMB DATA (14,15,20,7 9,82)

CLK_PCIE_ WLAN_REQ# (20)

PLT_RST # (5,18,27,71,82)

USB_P11 -

USB_P11 +

1 2

R6406

0R0402-P AD

1 2

R6405

0R0402-P AD

20101230 A00: Change R4606,R4605 to 0R short pad. 20100104 A00: Remove TR6501.

USB_PN1 1 (18 )

USB_PP1 1 (18)

12

5V_S5

12

C C

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

MINICARD(WLAN)/ITP CONN

Size Document N umber Rev

Date: Sheet of

Date: Sheet

MINICARD(WLAN)/ITP CONN

A3

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

65 1 03Tuesday, January 18, 2011

of

65 1 03Tuesday, January 18, 2011

of

65 1 03Tuesday, January 18, 2011

1

A00

5

D D

C C

4

3

2

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Reserved

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

66 1 03Wednesday, December 22, 20 10

of

66 1 03Wednesday, December 22, 20 10

of

66 1 03Wednesday, December 22, 20 10

1

A00

5

D D

4

3

2

1

(Blanking)

C C

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Nirvana 13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

67 103Wednesday, December 22, 2010

1

A00

5

SSID = User.Interface

D D

RN6801

PWRLED #_C

1

PWRLED #(27) BATT_WH ITE_LED#(27)

CHG_AMBER_L ED#(27)

SATA_LED#(21)

C C

WLAN_W WAN_LED#(63)

WLAN_LED #(65)

WWA N_LED#(82)

WPAN_LED #(65)

WLAN_W WAN_LED#

U6801

1

83.BAT54.U81

2

BAT54A-5-GP

D6801

3

BAS16-6-GP

83.00016.K11

2ND = 83.00016.F11

3

1

2

2 3 4 5

SRN15KJ-2-G P

8

WHITE_LED _BAT#

7

AMBER_LED_BAT #

6

SATA_LED#_C

3D3V_S0

DY

12

R6805

R6805 100KR2J-1-GP

100KR2J-1-GP

4

R6802

1 2

15KR2J-1-GP

PWRLED #_C

SATA_LED#_C

WHITE_LED _BAT#

AMBER_LED_BAT #

LED_WLAN _OUT_R#WLAN_W WAN_LED#

3

Power LED(White)

Q6801

B

PDTA143ET-G P

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

SATA HDD LED(White)

Q6802

R2

B

R1

PDTA143ET-G P

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

Battery LED1(White)

Q6805

B

R1

PDTA143ET-G P

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

5V_S5

R2

E

R1

C

12

EC6801

DY

SC220P50V2KX-3GP

5V_S0

E

SATA_LED_R

C

R2

E

WHITE_LED _BAT

C

DY

5V_AUX_S5

DY

12

Battery LED2(Amber)

Q6804

R2

B

R1

PDTA143ET-G P

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

5V_AUX_S5

E

C

12

DY

20110103 A00: Change R6804,R6806,R6808,R6810 to 620 ohm 5%. 20100106 A00: Change R6804,R6806,R6808,R6810 to 1k ohm 5%.

R6804

1 2

1KR2J-1-GP

1 2

1KR2J-1-GP

20110103 A00: Change R6801 to 1k.

R6806

1 2

1KR2J-1-GP

EC6805

SC220P50V2KX-3GP

R6808

1 2

1KR2J-1-GP

EC6604

SC220P50V2KX-3GP

1 2

R6809 390R2J-1-GPR6809 390R2J-1 -GP

EC6802

EC6802 SC220P50V2KX-3GP

SC220P50V2KX-3GP

WLAN LED (White)

Q6803

R2

B

R1

PDTA143ET-G P

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

5V_S0

E

WLAN_LED

C

DY

12

EC6803

EC6803 SC220P50V2KX-3GP

SC220P50V2KX-3GP

R6810

1 2

1KR2J-1-GP

R6801

SATA_LED

BAT_WHITE

BAT_AMBERAMBER_LED_BAT

LED_WLAN _OUT_B

PWR_LED _BLED_PWR

POWER_S W_LED_B

2

LED BD Connector

LEDBD1

AFTP6801AFTP6801 AFTP6802AFTP6802 AFTP6803AFTP6803 AFTP6804AFTP6804 AFTP6805AFTP6805

AFTP6806AFTP6806 AFTP6807AFTP6807

PWR_LED _B

SATA_LED BAT_WHITE BAT_AMBER LED_WLAN _OUT_B

PWR_LED _B

1

SATA_LED

1

BAT_WHITE

1

BAT_AMBER

1

LED_WLAN _OUT_B

1

KBC_PWR BTN#_C

1

POWER_S W_LED_B

1

7

1

2 3 4 5 6

8

ACES-CON 6-13-GP

20.K0320.006

1

B B

TPLOCK LED

R6807

TP_LOCK_LED#(27)

Need change to LOW actived from K BC GPIO

1 2

15KR2J-1-GP

Q6804_B

Q6812

B

PDTA143ET-G P

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

Power button LED(White)

KBC_PWR BTN#(27)

A A

5

4

5V_S0

R2

E

R1

TP_LOCK_LED_R TP_LOCK_LED_A

C

12

DY

1 2

R6803 100R2J-2-GPR6803 100R2J-2 -GP

POWER_S W_LED_B

EC6806

EC6804

SC220P50V2KX-3GP

KBC_PWR BTN#_C

12

SCD1U10V2KX-5GP

R6813

1 2

390R2J-1-GP

EC6807

SCD1U10V2KX-5GP

12

20.K0320.004

LED1

A K

LED-Y-57-GP

83.01921.P70

20101224 A00: Rename PWRBTN1 to PWRBT1.

PWRBT1

6

4 3 2

1

5

ACES-CON 4-10-GP-U

3

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

LED Bord/Power Button

Size Documen t Number Rev

A2

Date: Sheet of

Date: Sheet

2

Date: Sheet

Taipei Hsie n 221, Taiwan, R.O.C.

Nirvana 13

1

A00

of

68 103Tuesday, January 18, 2011

5

4

3

2

1

SSID = KBC

D D

C C

B B

KB1

JAE-CON3 0-7-GP

20.K0565.030

31 1

KROW 7

2

KROW 6

3

KROW 4

4

KROW 2

5

KROW 5

6

KROW 1

7

KROW 3

8

KROW 0

9

KCOL5

10

KCOL4

11

KCOL7

12

KCOL6

13

KCOL8

14

KCOL3

15

KCOL1

16

KCOL2

17

KCOL0

18

KCOL12

19

KCOL16

20

KCOL15

21

KCOL13

22

KCOL14

23

KCOL9

24

KCOL11

25

KCOL10

26

CAP_LED _R

27 28 29 30 32

1

Internal KeyBoard Connector

1

AFTP72AFTP72

AFTP693 6AFTP 6936

1

AFTP691 1AFTP 6911

1

AFTP691 2AFTP 6912

1

AFTP691 3AFTP 6913

1

AFTP691 4AFTP 6914

1

AFTP691 7AFTP 6917

1

AFTP691 8AFTP 6918

1

AFTP691 5AFTP 6915

1

AFTP691 6AFTP 6916

1

AFTP692 1AFTP 6921

1

AFTP692 2AFTP 6922

1

AFTP691 9AFTP 6919

1

AFTP692 0AFTP 6920

1

AFTP692 5AFTP 6925

1

AFTP692 6AFTP 6926

1

AFTP692 3AFTP 6923

1

AFTP692 4AFTP 6924

1

AFTP692 9AFTP 6929

1

AFTP693 0AFTP 6930

1

AFTP692 7AFTP 6927

1

AFTP692 8AFTP 6928

1

AFTP693 3AFTP 6933

1

AFTP693 4AFTP 6934

1

AFTP693 1AFTP 6931

1

AFTP693 2AFTP 6932

1

AFTP693 5AFTP 6935

AFTP690 1AFTP 6901

1

KB_DET# (21)

CAP_LED _R

KROW [0..7] (27)

KCOL[0..16 ] (2 7)

KB Backlight Connector

5V_S0

R6902

1 2

0R0402-P AD

KB_BL_C TRL(27)

5

0R0402-P AD

R6904

1 2

51KR2J-1 -GP

12

R6903

20101227 A00: Change R6902 to 0R 0402 pad.

KB_LED_ BL_DET(18)

A A

+5V_KB_ BL

12

C6905

C6905 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

KBLIT1

5

KB_LED_ DET_C

12

C6906

SCD1U10V2KX-5GP

100KR2J-1-GP

R6901

R6901 100KR2J -1-GP

100KR2J -1-GP

G

12

1

2 3 4

KB_BL_CTRL#

6

ACES-CON 4-34-GP

20.K0589.004

2nd = 20.K0613.004

DS

Q6901

Q6901 P8503BM G-GP

P8503BM G-GP

84.P8503.031

2nd = 84.03404.C31

+5V_KB_ BL KB_LED_ BL_DET KB_BL_C TRL#

1

AFTP79AFTP79

4

1

AFTP76AFTP76

1

AFTP77AFTP77

1

AFTP78AFTP78

3

CAP LED CONTROL

Q6902

R6905

CAP_LED(27)

CAP_LED:(X01 Low actived) Connect to KB driving internal LED directly.(MAX 25mA)

1 2

15KR2J-1 -GP

TouchPad LOCKED

5V_S0

1

23

SRN10KJ -5-GP

4

TPDATA(27)

TPCLK(27)

DY

C6902

AFTP73AFTP73 AFTP74AFTP74 AFTP75AFTP75

C6902

SC33P50 V2JN-3GP

Q6902

B

PDTA143 ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

CAP_LED _1

RN6901

12

DY

C6903

C6903 SC33P50 V2JN-3GP

SC33P50 V2JN-3GP

5V_S0

1

TPCLK

1

TPDATA

1

20110103 A00: Change R6906 to 620 ohm 5%. 20110106 A00:

5V_S5

R2

E

R1

C

5V_S0

Change R6906 to 1k ohm 5%.

R6906

1 2

1KR2J-1-G P

1 2

DY

R6907 100R2J-2 -GP

CAP_LED _RCAP_LED _Q

CAP_LED _R

TouchPad Connector

12

C6901

C6901 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

TPAD1

6

4 3 2

1

5

1

PTW O-CON4-9-GP-U1

AFTP71AFTP71

2

PTW O-CON4-9-GP-U1

20.K0382.004

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Key Board/Touch Pad/Media Board

Size Document N umber Rev

A3

Date: Sheet

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

69 1 03Tuesday, January 18, 2011

1

A00

5

D D

AFTP80 AFTE14P-GPAFTP80 AFTE14P-GP AFTP81 AFTE14P-GPAFTP81 AFTE14P-GP

3D3V_S5

1

LID_CLOSE#_1

1

4

3D3V_S5

3

2

1

3D3V_S5

12

R7001

DY

100KR2J-1-GP

LID_CLOSE#(27)

C C

DY

B B

LID_CLOSE#

12

C7001

C7001 SCD047U16V2KX-1-GP

SCD047U16V2KX-1-GP

1 2

20101227 A00: Change R7002 to 0R 0402 pad.

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP AFTP82

AFTP82

AFTE14P-GP

R7002

0R0402-PAD

C7002

1

12

LID_CLOSE#_1

20101224 A00: Rename HALLSW1 to LID1.

LID1

1

VCC

2

VOUT

3

GND

TCS20DPR-GP

74.TCS20.03B

74.09132.A7B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Nirvana 13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Hall Sensor

70 103Tuesday, January 18, 2011

1

A00

5

D D

4

3

2

1

3D3V_S0

C C

LPC_AD0(21,27,65) LPC_AD1(21,27,65) LPC_AD2(21,27,65) LPC_AD3(21,27,65)

LPC_FRAME#(21,27,65)

PLT_RST#(5,18,27,65,82)

CLK_PCI_LPC(18,65)

B B

DB1

11

1

2 3 4 5 6 7 8

9 10 12

PAD-10P-177042-GP

ZZ.00PAD.Y41

PCB Footprint = PAD-10P-177042

20101229 A00 Modify: DB1 change to ZZ.00PAD.Y41(solder mask type)

DY

and keep un-stuff at X-Build stage.

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Dubug CONN

Nirvana 13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

71 103Tuesday, January 18, 2011

1

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

72 1 03Wednesday, December 22, 20 10

of

72 1 03Wednesday, December 22, 20 10

of

72 1 03Wednesday, December 22, 20 10

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

73 1 03Wednesday, December 22, 20 10

of

73 1 03Wednesday, December 22, 20 10

of

73 1 03Wednesday, December 22, 20 10

A00

5

SSID = SDIO

4

3

2

1

3D3V_CA RD_S0

D D

DY

12

Close to CARD1

12

DY

C7401

C7402

SCD1U10V2KX-5GP

12

C7403

SCD1U10V2KX-5GP

SCD01U16V2KX-3GP

C7405

C7404

SC10U6D3V5MX-3GP

SC2D2U6D3V3KX-GP

12

SD/XD/MS/MMC+ Card Reader

3D3V_CA RD_S0

C C

B B

SP4(32 ) SP3(32 ) SP13(32) SP12(32)

SP8(32 ) SP6(32 ) SP1(32 ) SP10(32)

SP14(32) SP2(32 ) SP1(32 )

SP9(32 ) SP12(32) SP8(32 ) SP5(32 )

SP11(32) SP9(32 ) SP7(32 ) SP5(32 )

CARD1

P13

SD_VCC

P22

MS_VCC

18

XD_VCC

P4

SD_DAT0

P3

SD_DAT1

P25

SD_DAT2

P23

SD_DATA3

P10

SD_CLK

P1

SD_CD

P2

SD_WP

P19

SD_CMD

P9

MS_BS

P16

MS_INS

P20

MS_SCLK

P12

MS_DATA0

P11

MS_DATA1

P14

MS_DATA2

P18

MS_DATA3

P21

MMC_DATA4

P17

MMC_DATA5

P8

MMC_DATA6

P5

MMC_DATA7

CARD-PUS H-46P-1-GP-U

20.I0129.001

2nd = 20.I0135.001

XD_CD

XD_R/B

XD_RE

XD_CE XD_CLE XD_ALE

XD_WE

XD_WP_IN

XD_D0 XD_D1 XD_D2 XD_D3 XD_D4 XD_D5 XD_D6 XD_D7

SD_WP_COM/SDIO_GND

SD_CD_COM/SDIO_GND

SD_GND SD_GND

MS_GND MS_GND

XD_GND XD_GND

NP1 NP2

1 2 3 4 5 6 7 8

10 11 12 13 14 15 16 17

P26 P27 P7 P15

P6 P24

9 19

NP1 NP2

XD_CD# (32) SP1 (32) SP2 (32) SP3 (32) SP4 (32) SP5 (32) SP6 (32) SP7 (32)

SP8 (32) SP9 (32) SP10 (32) SP11 (32) SP12 (32) SP13 (32) SP14 (32) XD_D7 (32)

SP2SP4S P9SP12 SP5SP14 SP6 SP1SP13 SP7SP10XD_D7 SP8SP11XD_C D#

SP3

For EMI Reserved

12

DY

R7417

47R2J-2-GP

XD_D7_1

DY

XD_CD#_1

12

DY

EC7402

SC220P50V2KX-3GP

A A

5

R7404

R7402

47R2J-2-GP

SP14_1

12

DY

EC7404

EC7403

SC220P50V2KX-3GP

DY

12

DY

R7403

47R2J-2-GP

SP13_1

12

DY

EC7405

SC220P50V2KX-3GP

4

12

DY

R7405

47R2J-2-GP

SP11_1

12

DY

EC7407

SC220P50V2KX-3GP

R7406

47R2J-2-GP

SP12_1

12

EC7406

SC220P50V2KX-3GP

12

DY

R7407

R7408

47R2J-2-GP

SP9_1

SP10_1

12

DY

EC7409

EC7408

SC220P50V2KX-3GP

12

DY

R7410

47R2J-2-GP

SP8_1

12

DY

EC7410

SC220P50V2KX-3GP

12

DY

R7412

47R2J-2-GP

SP6_1

12

DY

EC7412

SC220P50V2KX-3GP

3

R7409

47R2J-2-GP

SP7_1

12

EC7411

SC220P50V2KX-3GP

12

DY

R7414

R7411

47R2J-2-GP

SP4_1

SP5_1

12

DY

EC7413

EC7414

SC220P50V2KX-3GP

12

DY

R7413

47R2J-2-GP

SP3_1

12

DY

EC7415

SC220P50V2KX-3GP

12

DY

R7416

R7415

47R2J-2-GP

SP1_1

SP2_1

12

DY

EC7416

EC7417

SC220P50V2KX-3GP

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CARD Reader CONN

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

CARD Reader CONN

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

74 1 03Tuesday, January 18, 2011

of

74 1 03Tuesday, January 18, 2011

of

74 1 03Tuesday, January 18, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

75 1 03Wednesday, December 22, 20 10

of

75 1 03Wednesday, December 22, 20 10

of

75 1 03Wednesday, December 22, 20 10

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

76 1 03Wednesday, December 22, 20 10

of

76 1 03Wednesday, December 22, 20 10

of

76 1 03Wednesday, December 22, 20 10

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

77 1 03Wednesday, December 22, 20 10

of

77 1 03Wednesday, December 22, 20 10

of

77 1 03Wednesday, December 22, 20 10

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

78 1 03Wednesday, December 22, 20 10

of

78 1 03Wednesday, December 22, 20 10

of

78 1 03Wednesday, December 22, 20 10

A00

5

SSID = User.Interface

4

3

2

1

D D

PCH_SMB CLK(1 4,15,20,65,82) PCH_SMB DATA(14,15,20,6 5,82)

3D3V_S0

C C

For ADI G-sensor : R7901 is required. For ST G-sensor : R7901 need DY

09/0422 (#1) Just pull +3.3V_RUN ~ Ref. Rothschild (#2) FAE/ DY is ok, chip internal pull-up resistors (#3) From spec, Slave ADdress(SAD) is 001110xb Pull HIGH SAD is 0011101b Pull GND SAD is 0011100b

Free Fall Sensor

3D3V_S0

12

SC10U6D 3V5MX-3GP

GSENSOR_ADI

1 2

C7901

PCH_SMB DATA

R7901

HDD_FAL L_SDO

100KR2J -1-GP

12

DY

C7902

C7902 SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

U7901

14

SCL/SPC

13

SDA/SDI/SDO

12

SDO

7

CS

3

RESERVED#3

11

RESERVED#11

DE351DL TR8-GP

74.00351.0B3

2nd = 74.00345.0BZ

Note

- no via, trace, under the sensor (keep out area around 2mm)

- stay away from the screw hole or metal shield soldering joints

- design PCB pad based on our sensor LGA pad size (add 0.1mm)

- solder stencil opening to 90% of the PCB pad size

- mount the sensor near the center of mass of the NB as possible as you can

3D3V_S0

1

6

VDD

VDD_IO

INT1

INT2

GND GND GND GND

12

R7902

R7902 100KR2J -1-GP

100KR2J -1-GP

DY

HDD_FAL L_INT1PCH_SMB CLK

8

9

2 4 5 10

HDD_FAL L_INT1 (18)

12

2nd = 84.DM601.03F

R7904

DY

100KR2J -1-GP

FFS_INT2_ R

2N7002K DW-GP

84.2N702.A3F

Q7901

3D3V_S0

12

R7903

R7903 100KR2J -1-GP

100KR2J -1-GP

FALL_INT2

2

34

5

1 2

DY

1

6

0R2J-2-GP

R7905

5V_S03D3V_S0

12

R7906

R7906 10KR2J-3 -GP

10KR2J-3 -GP

DY

FFS_INT2 (56)

FFS_INT2_ R (18)

B B

Note (1) Keep all signals are the same trace width. (included VDD, GND). (2) No VIA under IC bottom.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Free Fall Sensor

Nirvana 13

79 1 03Tuesday, January 18, 2011

1

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

80 1 03Wednesday, December 22, 20 10

of

80 1 03Wednesday, December 22, 20 10

of

80 1 03Wednesday, December 22, 20 10

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

81 1 03Wednesday, December 22, 20 10

of

81 1 03Wednesday, December 22, 20 10

of

81 1 03Wednesday, December 22, 20 10

A00

5

4

3

2

1

IO Board CONN 80 pin

IOBD1

80

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

20.F1432.080

NP1 1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NP2NP3

PCIE_TXP5 (20)

PCIE_TXN5 (20 )

PCIE_RXP5 (20 ) PCIE_RXN5 (20)

CLK_PCIE_ LAN (20) CLK_PCIE_ LAN# (20)

CLK_PCIE_ WWAN (20) CLK_PCIE_ WWAN# (20)

5V_S5

at least 160 mil

3D3V_S0

1D5V_S0

PM_LAN_ ENABLE (27) PLT_RST # (5,18,27,65,71)

PCIE_W AKE# (27)

USB3_PE GB_CLKREQ# (20)

+DC_IN

USB3.0 PCIE

LAN CLK

WWAN CLK

5V_USB FOR USB3.0 POWER at least 4A

1D05V_VTT FOR USB3.0 POWER at least ?A

3D3V_S5 FOR LAN POWER at least over 3pin amount.

1D5V_S0 FOR USB3.0 POWER at least ?A

NP4

D D

USB3_PW R_ON(27,62)

20101224 A00: Change R8210 to 0402 0 ohm pad. 20101228 A00: VGA_THRM change to USB_PWR_EN. 20101229 A00: Remove R2809 and R8210. Connect USB3_PWR_ON from KBC to IOBD1.61.

C C

USB3.0 CLK

WWAN USB

WWAN PCIE

WWAN SMBUS

LAN PCIE

CLK_PCIE_ USB3(20)

CLK_PCIE_ USB3#(20)

USB_PP4(18) USB_PN4(18)

PS_ID_R(38 )

PCIE_RXP3(20) PCIE_RXN3(20)

PCIE_TXP3(20) PCIE_TXN3(20)

PCH_SMB DATA(14,15,20 ,65,79)

PCH_SMB CLK(1 4,15,20,65,79)

1V_USB3 0_LDO_FB(6 2)

CLK_PCIE_ WWAN_ REQ#(20)

PCIE_CLK_ LAN_REQ#(20)

3G_EN(22) WW AN_LED#(68) USB30_S MI#(1 8)

PCIE_RXP2(20) PCIE_RXN2(20)

PCIE_TXP2(20) PCIE_TXN2(20)

1V_USB3 0

3D3V_S5

USB3_PW R_ON

ACES-CON N80C-GP-U

B B

Media Button Board Connector

5V_S5 5V_ S5

12

EC8201

EC8202

SCD1U10V2KX-5GP

A A

AFTP820 1AFTP 8201 AFTP820 2AFTP 8202 AFTP820 3AFTP 8203 AFTP820 4AFTP 8204 AFTP820 5AFTP 8205 AFTP820 6AFTP 8206 AFTP820 7AFTP 8207

MEDIA1_1

1

MEDIA1_2

1

MEDIA1_3

1

5V_S5

1

INSTANT_O N#

1

DATA_RE COVERY#

1

MEDIA_BTN 3#

1

5

MEDIA1

9

1

MEDIA1_1

2

MEDIA1_2

3

MEDIA1_3

4 5 6 7 8

10

ACES-CON 8-19-GP

20.K0320.008

20110103 A00: Change R8201~R8203 to 1k. 20110104 A00: Merge R8201~R8203 to RN8201 1k array resistor. 20110113 A00: Swap RN8201 base on swap report.

RN8201

1 2 3 4 5

4

RN8201

8 7 6

SRN1KJ-4 -GP

5V_S5

Low active

MEDIA_LED 1# (27)

MEDIA_LED 2# (27) MEDIA_LED 3# (27) INSTANT_O N# (27)

DATA_RE COVERY# (27)

MEDIA_BTN 3# (2 7)

MEDIA_LED 3# MEDIA_LED 2# MEDIA_LED 1#

8 7 6

5V_S5

RN8209

1 2

DY

3 45

SRN10KJ -6-GP

MEDIA1_1 MEDIA1_2 MEDIA1_3 INSTANT_O N# DATA_RE COVERY# MEDIA_BTN 3#

3

EC8204SCD1U10V2KX-5GP EC8204SCD1U10V2KX-5GP

EC8203SCD1U10V2KX-5GP EC8203SCD1U10V2KX-5GP

12

EC8207SCD1U10V2KX-5GP EC8207SCD1U10V2KX-5GP

EC8206SCD1U10V2KX-5GP EC8206SCD1U10V2KX-5GP

EC8205SCD1U10V2KX-5GP EC8205SCD1U10V2KX-5GP

12

EC8208SCD1U10V2KX-5GP EC8208SCD1U10V2KX-5GP

12

Title

IO Board Connector

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

2

Date: Sheet

IO Board Connector

Nirvana 13

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

82 1 03Tuesday, January 18, 2011

of

82 1 03Tuesday, January 18, 2011

of

82 1 03Tuesday, January 18, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document N umber Rev

A3

Date: Sheet of

Reserved

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

83 1 03Wednesday, December 22, 20 10

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

84 1 03Wednesday, December 22, 20 10

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

Date: Sheet

A3

Reserved

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

85 1 03Wednesday, December 22, 20 10

of

85 1 03Wednesday, December 22, 20 10

of

85 1 03Wednesday, December 22, 20 10

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

86 1 03Wednesday, December 22, 20 10

1

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Reserved

Nirvana 13 A00

Taipei Hsien 221, Taiwan, R.O.C.

87 1 03Wednesday, December 22, 20 10

1

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document N umber Rev

A3

Date: Sheet of

Reserved

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

88 1 03Wednesday, December 22, 20 10

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Reserved

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

89 1 03Wednesday, December 22, 20 10

of

89 1 03Wednesday, December 22, 20 10

of

89 1 03Wednesday, December 22, 20 10

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

90 1 03Wednesday, December 22, 20 10

of

90 1 03Wednesday, December 22, 20 10

of

90 1 03Wednesday, December 22, 20 10

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

91 1 03Wednesday, December 22, 20 10

of

91 1 03Wednesday, December 22, 20 10

of

91 1 03Wednesday, December 22, 20 10

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Reverved

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

92 1 03Wednesday, December 22, 20 10

of

92 1 03Wednesday, December 22, 20 10

of

92 1 03Wednesday, December 22, 20 10

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Reserved

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

93 1 03Wednesday, December 22, 20 10

of

93 1 03Wednesday, December 22, 20 10

of

93 1 03Wednesday, December 22, 20 10

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

Reserved

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

94 1 03Wednesday, December 22, 20 10

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

95 1 03Wednesday, December 22, 20 10

of

95 1 03Wednesday, December 22, 20 10

of

95 1 03Wednesday, December 22, 20 10

A00

5

D D

4

3

2

1

C C

B B

A A

(Blanking)

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

5

4

3

2

Date: Sheet

Reserved

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

96 1 03Wednesday, December 22, 20 10

of

96 1 03Wednesday, December 22, 20 10

of

96 1 03Wednesday, December 22, 20 10

1

A00

5

H2

H2 HOLE335 R115-GP

H1

H1 HT85B85 X925R29-S-GP

HT85B85 X925R29-S-GP

ZZ.00PAD.D01

1

D D

H13

H13 HOLE197 R166-1-GP

HOLE197 R166-1-GP

1

ZZ.00PAD.V71

HOLE335 R115-GP

1

H14

H14 HT85BE8 5R29-U-5-GP

HT85BE8 5R29-U-5-GP

ZZ.00PAD.D41

1

H3 STF276R16 0H209-1-GP

34.4ID01.001

1

H12

H12 HOLE197 R166-1-GP

HOLE197 R166-1-GP

1

ZZ.00PAD.V71

4

H5

H5 HOLE256 R115-GP

HOLE256 R115-GP

H15

H15 HOLE335 R115-GP

HOLE335 R115-GP

ZZ.00PAD.D01

1

ZZ.00PAD.D11

1

H16

H16 HT85B85 X925R29-S-GP

HT85B85 X925R29-S-GP

H6

H6 HT85BE8 5R29-U-5-GP

HT85BE8 5R29-U-5-GP

ZZ.00PAD.D41

1

H7

H7 HOLE256 R115-GP

HOLE256 R115-GP

1

H17

H17 HOLE276 R158-GP

HOLE276 R158-GP

1

ZZ.00PAD.U61

3

ZZ.00PAD.D11

H8

H8 HOLE256 R115-GP

HOLE256 R115-GP

1

H10

H10 HT85BE8 5R29-U-5-GP

HT85BE8 5R29-U-5-GP

1

2

H11

H11 HOLE197 R166-1-GP

HOLE197 R166-1-GP

1

ZZ.00PAD.V71

1

C C

SPR6

SPR1

SPR1 SPRING-51-GP

SPRING-51-GP

34.4F822.002DY

1

SPR2

SPRING-24-GP-U

DY

SPR3

DY

1

SPRING-24-GP-U

SPR6

SPRING-24-GP-U

DY

1

SPR4

SPR4 SPRING-24-GP -U

SPRING-24-GP -U

DY

1

34.45T31.001

SPR7

SPR7 SPRING-57-GP

SPRING-57-GP

DY

1

34.42T14.002

SPR8

SPR8 SPRING-51-GP

SPRING-51-GP

DY

1

34.4F822.002

RF RequestEMI Request

1D05V_V TT

EC9738 SCD1U10V2K X-5GP

EC9739 SCD1U10V2K X-5GP

EC9740 SCD1U10V2K X-5GP

EC9741 SCD1U10V2K X-5GP

EC9742 SCD1U10V2K X-5GP

EC9743 SCD1U10V2K X-5GP

EC9744 SCD1U10V2K X-5GP

EC9745 SCD1U10V2K X-5GP

EC9746 SCD1U10V2K X-5GP

EC9747 SCD1U10V2K X-5GP

EC9748 SCD1U10V2K X-5GP

4

DY

12

3

DY

EC9721

LVDS_DD C_CLK_RLVDS_DDC_DATA _R

12

DY

EC9722

SCD1U10V2KX-5GP

3D3V_S0 5V_ S5

5V_S0 3D3V_S0

5V_S5 +DC_IN

5V_S5 DCBATOU T

SCD1U10V2KX-5GP

5V_S5 5V_S0

1D05V_V TT 3D3V_S0

5V_S0 3D3V_S0

1D05V_V TT 3D3V_S0

3D3V_S0 5V_ S0

1D5V_S3 5V_ S5

5V_S0 3D3V_S0

DY

EC9719

DY

EC9723

DY

R9701

12

AUD_DMIC_CLK1

12

AUD_DMIC_ IN0

47R2J-2-GP

SCD1U10V2KX-5GP

5

DY

EC9720

DY

R9702

CLK_PCH _48M(20,32) AUD_DMIC_ CLK(29,49) AUD_DMIC_ IN0(29 ,49) LVDS_DD C_DATA_R(17,49) LVDS_DD C_CLK_R(17,49)

12

47R2J-2-GP

AUD_DMIC_IN01

12

SCD1U10V2KX-5GP

AUD_DMIC_ CLK

B B

CLK_PCH _48M

A A

1D05V_V TT

12

DY

EC9725

EC9724

SCD1U10V2KX-5GP

EC9727 SCD1U10V2K X-5GP

3D3V_S0

3D3V_S0 5V_ S0

12

DY

EC9734 SCD1U10V2K X-5GP

12

DY

EC9733 SCD1U10V2K X-5GP

12

DY

2

DY

EC9726

12

SCD1U10V2KX-5GP

1D05V_V TT

5V_S5

12

DY

EC9728

SCD1U10V2KX-5GP

Title

Size Document N umber Rev

A3

Date: Sheet of

5V_S05 V_S5

12

DY

EC9729

DY

EC9730

SCD1U10V2KX-5GP

UNUSED PARTS/EMI Capacitors

Nirvana 13

5V_S0

12

DY

EC9732

EC9731

SCD1U10V2KX-5GP

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

3D3V_S01D05V_V TT

3D3V_S0

12

DY

EC9735

EC9736

SCD1U10V2KX-5GP

97 1 03Tuesday, January 18, 2011

3D3V_S0

DY

EC9737

SCD1U10V2KX-5GP

12

SCD1U10V2KX-5GP

A00

5

4

3

2

1

Huron River Platform Power Sequence

(AC mode)

+RTC_VCC

RTC_RST#

Within logic high level and disable if

D D

it is less than the logic low level.

V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within

0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V.

Not floating.

Sense the power button status

This signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input.

C C

V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V.

DCBATOUT

3D3V_AUX_S5

S5_ENABLE

5V_S5

3D3V_S5

PM_RSMRST#(EC Delay 40ms) T6

PCH_SUSCLK_KBC

AC_PRESENT

AC

PM_SLP_S4#

PM_SLP_S3#

PM_LAN_ENABLE

1D5V_S3

DDR_VREF_S3(0.75V)

5V_S0

3D3V_S0

+5VS_PCH_VCC5REF

1D5V_S0

1D8V_S0

0D75V_S0

RUNPWROK

1D05V_VTT

1.05VTT_PWRGD

0D85V_S0

D85V_PWRGD

CPU SVID BUS

VCC_CORE

VCC_GFXCORE

IMVP_PWRGD

B B

This signal represents the Power Good for all the non-CORE and non-graphics power rails.

CLK_EXP_P

PWROK

VDDPWRGOOD

H_CPUPWRGD

SYS_PWROK

PLT_RST#

DMI

KBC_PWRBTN#

PM_PWRBTN#

AC

T1

>9ms

T2

3D3V_AUX_KBC

PM_PWRBTN#

T10

ALL_SYS_PWRGD=D85V_PWRGD

D85V_PWRGD

1D8V_S0

T3

T4

0D85V_S0

T5+5VA_PCH_VCC5REFSUS

>10ms

Press Power button

T11

>30us

T12

T13

T14

T15

T17

T18

T19

>99ms

T27

<650ms2ms<

T29

red word: KBC GPIO

>5ms

T8T7<90ms

0ms<

>16ms

T9

T16

T24

>0us

T28

KBC GPIO34 control power on by 3V_5V_EN

KBC GPIO43 to PCH

PCH to KBC GPIO00

KBC GPO84 to PCH

Platform to KBC PSL_IN2

KBC GPIO20 to PCH

PCH to KBC GPIO44

PCH to KBC GPIO01

KBC GPIO23 to LAN

Enable by PM_SLP_S4#

+5V_RUN & +3.3V_RUN need meet 0.7V difference

T20

T30 T31 T32

>1ms

>2ms

<650ms5ms<

T21

SetVID ACK

1ms<

T22

T33

T35

1D8V_S0 & 1D5V_S3 power ready

T23

TPS51461RGER PGOOD

50us< <2000us

T25

T26

ISL95831 PGOOD to system

<5ms

>0ms

<100ms

VT357FCX PGOOD

KBC GPIO77 to PCH

PCH to CPU

>1ms+60us

T34

PCH to all system

<200us

T36

(DC mode)

Sense the power button status

V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within

0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V.

V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V.

This signal represents the Power Good for all the non-CORE and non-graphics power rails.

+RTC_VCC

RTC_RST#

DCBATOUT

3D3V_AUX_S5

KBC_PWRBTN#

3D3V_AUX_KBC

S5_ENABLE

5V_S5

3D3V_S5

+5VA_PCH_VCC5REFSUS

PM_PWRBTN#

PM_RSMRST#

PCH_SUSCLK_KBC

DC

PM_SLP_S4#

PM_SLP_S3#

PM_LAN_ENABLE

1D5V_S3

DDR_VREF_S3(0.75V)

5V_S0

3D3V_S0

+5VS_PCH_VCC5REF

1D5V_S0

1D8V_S0

0D75V_S0

1D05V_VTT

1.05VTT_PWRGD

0D85V_S0

D85V_PWRGD

CPU SVID BUS

VCC_CORE

VCC_GFXCORE

IMVP_PWRGD

CLK_EXP_P

PWROK

VDDPWRGOOD

H_CPUPWRGD

SYS_PWROK

PLT_RST#

DMI

T1

PCH_RSMRST#

red word: KBC GPIO

>9ms

T2

Press Power button

T10

>30us

0D85V_S0

ALL_SYS_PWRGD=D85V_PWRGD

T27

D85V_PWRGD

1D8V_S0

Platform to KBC PSL_IN2

T3

T4

T5

T6

T11

T12

T13

T14

T15

T17

T18

T19

T24

>99ms

T28

<650ms2ms<

T29

EC_ENABLE#_1(GPIO31) keep low

KBC GPIO34 control power on by 3V_5V_EN

+5V_ALW & +3.3V_ALW need meet 0.7V difference

T7

>16ms

T8

>10ms

>5ms

T9

KBC GPIO20 to PCH

KBC GPIO43 to PCH

PCH to KBC GPIO00

+5V_RUN & +3.3V_RUN need meet 0.7V difference

T16

T20RUNPWROK

T21

>0us

>1ms

T30

>2ms

T31

<650ms5ms<

T32

PCH to KBC GPIO44

PCH to KBC GPIO01

KBC GPIO23 to LAN

Enable by PM_SLP_S4#

1D8V_S0 & 1D5V_S3 power ready

T22

T23

ACKSetVID

50us< <2000us

T25

T26

<5ms

>0ms

T33

1ms<

<100ms

T35

VT357FCX PGOOD

TPS51461RGER PGOOD

ISL95831 PGOOD to system

KBC GPIO77 to PCH

PCH to CPU

>1ms+60us

T34

PCH to all system

<200us

T36

Robson XT Power-Up/Down Sequence

DGPU_PWR_EN#(Discrete only)

3D3V_VGA_S0(Discrete only)

A A

8209A_EN/DEM_VGA(Discrete only)

VGA_CORE(Discrete only)

1V_VGA_S0(Discrete only)

9035_PGOOD_1V(Discrete only)

1D8V_VGA_S0(Discrete only)

DGPU_PWROK(Discrete only)

1D5V_VGA_S0(Discrete only)

3D3V_S0

Ta

>0ms

Tb

Tc

Td

>0ms

<20ms

For power-down, reversing the ramp-up sequence is recommende d.

5

4

PCH GPIO54 output

3D3V_VGA_S0 above VT357 VIH

RT9035 PGOOD

VT357 PGOOD

Title

Size Document Number Rev

A1

Wednesday, December 22, 2010

Date: Sheet

Wednesday, December 22, 2010

Date: Sheet

Wednesday, December 22, 2010

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Power Sequence

Nirvana 13

A00

98

of

103

5

4

3

2

1

Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM

AC

D D

DC

Battery

Page39

C C

B B

Adapter in

PWR_CHG_ACOK

BT+

Page38

5

RUNPWROK

AD+

SWITCH

Page40

BQ24745 Charger

Page40

ACOK

-1

Power Button

5V_S5 DCBATOUT

TPS51218DSCR

EN

5V_S5

-6.1

DCBATOUT

-4

AC_IN#

KBC_PWRBTN#

PM_SLP_S4#

PM_SLP_S3#

V5IN VIN

Page45

DCBATOUT

-3.1 -3.1 -3.1

3V_5V_EN

-3.3

15V_S5

PUMP

-5

-2

BJT

SLP_S4# SLP_S3#

RSMRST#

PWRBTN#

Cougar Point PCH

APWROK

PWROK

SYS_PWROK

3

4

DRAMPWRGD

PROCPWRGD

PLTRST#

PM_SLP_S4#

PM_SLP_S3#

1

PWR_5V3D3V_ENC

ENC

RT8223MGQW DC/DC (3V/5V)

VIN

-3

3D3V_AUX_KBC

GPIO70

KBC NPCE795P

GPIO6

GPIO44

GPIO01

GPIO34

GPIO43

GPIO20

Page27

GPIO77

LL1

LL2

VREG5

VREG3

PGOOD

Page41

-3.2

5V_S5

3D3V_S5

5V_AUX_S5

3D3V_AUX_S5

3V_5V_POK

-3.1

S5_ENABLE

-2.1

PM_RSMRST#

PM_PWRBTN#

S0_PWR_GOOD

SYS_PWROK

2

10

1D05_VTT

VOUT

PGOOD

1.05VTT_PWRGD

S0_PWR_GOOD

IMVP_PWRGD

AND GATE

A

B

Y

10

SYS_PWROK

5a

S5_ENABLE

11

12

13

PLT_RST#

SWITCH

Page37

SWITCH

Page37

SWITCH

Page37

5V_S0

3D3V_S0

1D5V_S0

0D75V_EN

PM_DRAM_PWRGD

H_CPUPWRGD

AND GATE

B

A

Y

VDDPWRGOOD

H_CPUPWRGD_R

BUF_CPU_RST#

SM_DRAMPWROK

UNCOREPWRGOOD

Sandy Bridge CPU

RSTIN#

SVID

3

PM_SLP_S4#

4

PM_SLP_S3#

SVID

8

-6

DCBATOUT5V_S5

VDDP VIN

EN

TPS51116RGER

Page46

5V_S5 3D3V_S5

VIN

VDD

TPS53311RGTR

EN

Page47

VOUT

REF

VTT

PGD

VOUT

PGD

1D5V_S3

DDR_VREF_S3

0D75V_S0

RUNPWROK

5

1D8V_S0

RUNPWROK

5

5a

1.05VTT_PWRGD

VDDP

RT8208BGQW

EN

Page48

VOUT

PGOOD

0D85_S0

D85V_PWRGD

-7

RTC_AUX_S5

VIN

6

DCBATOUT

8

A A

6

D85V_PWRGD

SVID

7

IMVP_VR_ON

VIN

VR

OUTPUT

SVID

ISL95831HRTZ

VR_ON

Page42 & 43 & 44

PGOOD

VCC_CORE

VCC_GFXCORE

IMVP_PWRGD

9

Power Up Sequence: -8 ~ 13

5

4

3

3D3V_AUX_S5

+RTC_VCC

RTC battery

2

-5

-8

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Nirvana 13

1

Taipei Hsie n 221, Taiwan, R.O.C.

99

A00

of

103

Title

Power Up Sequence Diagram

Size Documen t Number Rev

A2

Date: Sheet of

Wednesd ay, December 22, 2010

Date: Sheet

Wednesd ay, December 22, 2010

Date: Sheet

Wednesd ay, December 22, 2010

5

4

3

2

1

Adapter

D D

AO4407A

DCBATOUT

1D5V_S3

TPS51216

TPS51218

POLYSW

DCBATOUT_LCD

Charger

Battery

BQ24745

+PBATT

TPCA8062

1D5V_S0

0D75V_S0DDR_VREF_S3

1D05V_VTT

TPS51427

C C

15V_S5

3D3V_AUX_S5

5V_AUX_S5

VCC_CORE

VT1317VT1317

VCC_GFXCORE

5V_S5

G547F2P81

5V_USB1_S3

TPCA8062

5V_S0

TPS51461

0D85V_S0

AO4468

3D3V_S0

3D3V_S5

TPS51311

1D8V_S0

AO3403

3D3V_LAN_S5

B B

G5285T11

LCDVDD

RTS5138

3D3V_CARD_S0

Power Shape

A A

5

4

Regulator LDO Switch

3

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Block Diagram

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

2

Date: Sheet

Power Block Diagram

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

100 103W ednesday, December 22, 2010

of

100 103W ednesday, December 22, 2010

of

100 103W ednesday, December 22, 2010

1

A00

Wistron Nirvana 13 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual