Wistron Nirvana 13 Schematic

5

4

3

2

1

Nirvana 13 Discrete GDDR5 Schematics Document

D D

Sandy Bridge

Intel PCH

C C

2011-01-18 REV : A00

B B

DY :None Installed 10mW: External circuit for 10mW solution installed. GSENSOR_ADI: Stuff for ADI G-Sensor VCCSA_PWM: Stuff for VCCSA PWM solution. P2800A1: Stuff for P2800EA1

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Cover

Nirvana 13

of

1 104Tuesday, January 18, 2011

1

A00

5

Seymour:512M (64M*32b*2)

D D

GDDR5 VRAM

512MB

GDDR5 1.25GHZ

AMD Graphic

SEYMOUR-XT-S3

83,84,85,86,87 4,5,6,7,8,9,10,11,12,13

C C

HDMI

LCD

CRT

SD/MMC+/MS/ MS Pro/xD/SDXC

(8 in 1)

B B

51

49

50

Card Reader

RTS5138

74

Bluetooth V3.0

Finger Print

CAMERA w/ Digital MIC

HP

MIC IN

A A

1CH SPEAKER

5

HDMI

LVDS(Single Channel)

RGB CRT

32

63

64

49

4

88

USB 2.0 x 1

CODEC

IDT 92HD87B1

4

3

Nirvana 13 Block Diagram (Discrete 8 layers)

Project Code: 91.4ID01.001 PCB P/N : 10244 Revision : -1

Intel CPU

DDRIII 1066/1333 Channel A

PCIe x 16

(Discrete)

FDIx4x2

(HDMI V1.3)

USB2.0 x 4

HDA

Flash ROM

4MB

29

Touch PAD

4

Sandy Bridge

DMIx4

Intel

PCH Cougar Point

14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6)

PCIE ports (8)

LPC I/F

ACPI 1.1

17,18,19,20,21,22,23,24,25,26

SPI

SMBus

LPC Bus

60

KBC

NUVOTON

NPCE795PA

27

Int.

69 69

KB

ADC

DAC

DDRIII 1066/1333 Channel B

PCIE x 1

PCIE x 1,USB2.0 x 1

USB2.0 x 1

SATA x 1

SATA x 2

Free Fall Sensor

Thermal Sensor

Main:ENEP2800

FAN Controller

Main: G991P11U

3

25

79

28

DDRIII 1066/1333

10/100/1000 LOM

Realtek

RTL8111E-VB

USB3.0 Controller

NEC uPD720200F1

Mini-Card

WWAN

Mini-Card

802.11a/b/g

USB CHARGE

PI5USB14550

Fan

55

65

2

Slot 1

14

Slot 2

15

(On Daughter Board)

RJ45 CONN

USB3.0 x 2

SIM

ESATA/USB Combo

HDD

56

ODD

56

2

1

PCB LAYER

DIS

L1:Top L2:GND L3:Signal L4:Signal L5:VCC L6:Signal L7:GND L8:Bottom

CPU DC/DC

VT1316+VT1317

INPUTS

5V_S5

OUTPUTS

VCC_CORE

SYSTEM DC/DC

VT1316+VT1317

INPUTS

5V_S5

OUTPUTS

VCC_GFXCORE

SYSTEM DC/DC

TPS51461

INPUTS

5V_S5

OUTPUTS

0D85V_S0

VGA

5V_S0

VT357

OUTPUTS

VGA_CORE

INPUTS

SYSTEM DC/DC

VT358/RT9026

INPUTS

5V_S5/5V_S5

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

SYSTEM DC/DC

VT357

INPUTS

5V_S5

OUTPUTS

1D05V_VTT

TI CHARGER

BQ24745

INPUTS

+DC_IN_S5

+PBATT

OUTPUTS

DCBATOUT

SYSTEM DC/DC

TPS51427

82

5757

INPUTS

DCBATOUT 5V_S5

26

SYSTEM DC/DC

INPUTS

3D3V_S5

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5 15V_S5

TPS51311

OUTPUTS

1D8V_S0

SYSTEM DC/DC

G9731

INPUTS OUTPUTS

26

1D5V_S3 1V_VGA_S0

1D5V_S0 5V_S0 3D3V_S03D3V_S5

of

36,93

Switches

INPUTS OUTPUTS

1D5V_S3 5V_S5

1D8V_S0 1D8V_VGA_S0 1D5V_S3 1D5V_VGA_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Tuesday, January 04, 2011

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Nirvana 13

1

2 104

A00

42

44

48

92

46

45

40

41

47

93

5

4

3

2

1

PCH Strapping

Huron River Schematic Checklist Rev.1_0

Name Schematics Notes

SPKR

INIT3_3V# Weak internal pull-up. This signal should not be pulled low. Leave as "No Connect".

GNT3#/GPIO55

D D

GNT2#/GPIO53 GNT1#/GPIO51

INTVRMEN

DF_TVS

SATA1GP /GPIO19

C C

HDA_SDO

HDA_SYNC

GPIO15

DSWVRMEN

B B

GPIO28

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Enable when Pull-up.

No Reboot Mode with TCO Disabled:

GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail.

Integrated 1.05 V VRM Enable / Disable

Integrated 1.05 V VRMs is enabled when high. This signal should always be pulled high

DMI and FDI Tx/Rx Termination Voltage

Weak internal pull-down. It needs to be connected to PROC_SELECT with a 1K±5% pull-up resistor to PCH VCCPNAND rail and a 4.7K±5% series resistor.

Boot BIOS Strap bit 0

This Signal has a weak internal pull-up. Note: This field determines the destination of accesses to the BIOS memory range. This strap is used in conjunction with Boot BIOS Destination Selection 1 strap. Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI 0 0 LPC

Signal has a weak internal pull-down. Default: the security measures defined in the Flash Descriptor will be in effect. Pull-up: the Flash Descriptor Security will be overridden. This strap should only be asserted high via external pull-up in manufacturing or debug environments ONLY.

On-Die PLL Voltage Regulator Voltage Select

This signal has a weak internal pull-down. On Die PLL VR is supplied by 1.5 V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform.

TLS Confidentiality

Low - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality This signal has a weak internal pull-down.



NOTE: A strong pull-up may be needed for GPIO functionality

Deep S4/S5 Well On-Die Voltage Regulator Enable

This signal enables the internal Deep Sleep 1.05 V regulators. This signal must be always pulled-up to VccRTC.

On-Die PLL Voltage Regulator

This signal has a weak internal pull-up. The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled. If not used, 8.2-kȍ to 10-kȍ pull-up to +V3.3A power-rail.

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[2]

CFG[4]

CFG[6:5]

CFG[7]

POWER PLANE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5

3D3V_AUX_KBC

3D3V_AUX_S5

PCI-Express Static Lane Reversal

Display Port Presence strap

PCI-Express Port Bifurcation Straps

PEG DEFER TRAINING

VOLTAGE DESCRIPTION

5V

3.3V

1.8V

1.5V

1.05V

0.95 - 0.85V

0.75V

0.35V to 1.5V

0.4 to 1.25V

1.8V

3.3V 1V

5V

1.5V

0.75V

6V-14.1V 6V-14.1V 5V 5V

3.3V

3.3V3D3V_LAN_S5

3.3V

1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded Display Port.

Enabled - An external Display Port device is

0:

connectd to the Embedded Display Port

11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled

1:

PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

0:

Voltage Rails

ACTIVE IN

S0

S3

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

Huron River Schematic Checklist Rev.1_0

Default Value

0

1

11

1

CPU Core Rail Graphics Core Rail

AC Brick Mode only

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

USB Table

PCIE Routing

LANE1

LANE2

LANE3

LANE4 Mini Card1(WLAN)

A A

LANE5

LANE6

LANE7

X

LAN (I/O Board)

Mini Card2(WWAN)

USB3.0

X

SATA Table

SATA

Pair

0

1

2

3

4

5

Device

HDD1

N/A

ODD

ESATA

LANE8 X

5

Pair

0

1

2

3

4

5

6

7

8

9

10

11

12

13

4

Device

X

ESATA / USB COMBO

Fingerprint

BLUETOOTH

Mini Card2 (WWAN)

CARD READER

X

Mini Card1 (WLAN)

CAMERA

X

SMBus ADDRESSES

2

I C / SMBus Addresses

Device

EC SMBus 1 Battery Capacity Board

EC SMBus 2 PCH MXM LCD Thermal Sensor

PCH SMBus CK505 Clock Generator SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot

3

HURON RIVER ORB

Address Hex Bus Ref Des

KBC_SDA1/KBC_SCL1 KBC_SDA1/KBC_SCL1

KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2

PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

Nirvana 13

3 104Tuesday, January 04, 2011

1

of

A00

5

4

3

2

1

SSID = CPU

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

1 OF 9

CPU1A

D D

C C

B B

NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Lane reversal does not apply to FDI sideband signals.

1D05V_VTT

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

DMI_TXN[3:0](19)

DMI_TXP[3:0](19)

DMI_RXN[3:0](19)

DMI_RXP[3:0](19)

FDI_TXN[7:0](19)

FDI_TXP[7:0](19)

FDI_FSYNC0(19) FDI_FSYNC1(19)

FDI_ INT(19)

FDI_LSYNC0(19) FDI_LSYNC1(19)

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DP_COMP

B27 B25 A25 B24

B28 B26 A24 B23

G21 E22 F21 D21

G22 D22 F20 C21

A21 H19 E19 F18 B21 C20 D18 E17

A22 G19 E20 G18 B20 C19 D19 F17

H20

H17

A18 A17 B16

C15 D15

C17 F16 C16 G15

C18 E16 D16 F15

J18 J17

J19

SANDY

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI0_LSYNC FDI1_LSYNC

EDP_COMPIO EDP_ICOMPO EDP_HPD

EDP_AUX EDP_AUX#

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3

SANDY

DMI

Intel(R) FDI

eDP

1 OF 9

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11

PCI EXPRESS* - GRAPHICS

PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_IRCOMP_R

PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0

PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0

PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0

PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

1 2

PEG_RXN[0..15]

Reverse the Bus for Layout 6/28

PEG_RXP[0..15]

NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect

C401 SCD22U10V2KX-1GPC401 SCD22U10V2KX-1GP

1 2

C402 SCD22U10V2KX-1GPC402 SCD22U10V2KX-1GP

1 2

C403 SCD22U10V2KX-1GPC403 SCD22U10V2KX-1GP

1 2

C404 SCD22U10V2KX-1GPC404 SCD22U10V2KX-1GP

1 2

C405 SCD22U10V2KX-1GPC405 SCD22U10V2KX-1GP

1 2

C406 SCD22U10V2KX-1GPC406 SCD22U10V2KX-1GP

1 2

C407 SCD22U10V2KX-1GPC407 SCD22U10V2KX-1GP

1 2

C408 SCD22U10V2KX-1GPC408 SCD22U10V2KX-1GP

1 2

C409 SCD22U10V2KX-1GPC409 SCD22U10V2KX-1GP

1 2

C410 SCD22U10V2KX-1GPC410 SCD22U10V2KX-1GP

1 2

C411 SCD22U10V2KX-1GPC411 SCD22U10V2KX-1GP

1 2

C412 SCD22U10V2KX-1GPC412 SCD22U10V2KX-1GP

1 2

C413 SCD22U10V2KX-1GPC413 SCD22U10V2KX-1GP

1 2

C414 SCD22U10V2KX-1GPC414 SCD22U10V2KX-1GP

1 2

C415 SCD22U10V2KX-1GPC415 SCD22U10V2KX-1GP

1 2

C416 SCD22U10V2KX-1GPC416 SCD22U10V2KX-1GP

1 2

C417 SCD22U10V2KX-1GPC417 SCD22U10V2KX-1GP

1 2

C418 SCD22U10V2KX-1GPC418 SCD22U10V2KX-1GP

1 2

C419 SCD22U10V2KX-1GPC419 SCD22U10V2KX-1GP

1 2

C420 SCD22U10V2KX-1GPC420 SCD22U10V2KX-1GP

1 2

C421 SCD22U10V2KX-1GPC421 SCD22U10V2KX-1GP

1 2

C422 SCD22U10V2KX-1GPC422 SCD22U10V2KX-1GP

1 2

C423 SCD22U10V2KX-1GPC423 SCD22U10V2KX-1GP

1 2

C424 SCD22U10V2KX-1GPC424 SCD22U10V2KX-1GP

1 2

C425 SCD22U10V2KX-1GPC425 SCD22U10V2KX-1GP

1 2

C426 SCD22U10V2KX-1GPC426 SCD22U10V2KX-1GP

1 2

C427 SCD22U10V2KX-1GPC427 SCD22U10V2KX-1GP

1 2

C428 SCD22U10V2KX-1GPC428 SCD22U10V2KX-1GP

1 2

C429 SCD22U10V2KX-1GPC429 SCD22U10V2KX-1GP

1 2

C430 SCD22U10V2KX-1GPC430 SCD22U10V2KX-1GP

1 2

C431 SCD22U10V2KX-1GPC431 SCD22U10V2KX-1GP

1 2

C432 SCD22U10V2KX-1GPC432 SCD22U10V2KX-1GP

1 2

1D05V_VTT

PEG_RXN[0..15] (83)

PEG_RXP[0..15] (83)

PEG Static Lane Reversal

PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0

PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0

PEG_TXN[0..15]

PEG_TXP[0..15]

PEG_TXN[0..15] (83)

PEG_TXP[0..15] (83)

Stuff to disable internal graphics function for power saving.

A A

NOTE: Select a Fast FET similar to 2N7002E whose rise/ fall time is less tha n 6 ns. If HPD on eDP inte rfac e is disabled, connect it to CPU VCCIO via a 10-kȍ pull-U p resistor on the motherboard.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU 1/7(PEG/DMI/FDI/eDP)

Size Document Number Rev

Date: Sheet of

Date: Sheet

CPU 1/7(PEG/DMI/FDI/eDP)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

4 104Tuesday, January 18, 2011

A00

5

SSID = CPU

H_SNB_IVB#(18)

1D05V_VTT

R501

D D

R501

62R2J-GP

H_PROCHOT#

1 2

CRB : 47pf CEKLT:43pf

12

C502

C502 SC47P50V2JN-3GP

SC47P50V2JN-3GP

Connect EC to PROCHOT# through inverting OD buffer.

H_PECI(22,27)

H_PROCHOT#(27,40,42)

H_THERMTRIP#(22,36)

1

TP501TPAD14-GP TP501TPAD14-GP

1

TP502TPAD14-GP TP502TPAD14-GP

R513

1 2

56R2J-4-GP

4

SKTOCC#_R

H_CATERR#

H_PROCHOT#_R

AN34

AL33

AN33

AL32

AN32

C26

CPU1B

SNB_IVB#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

SANDY

3

2 OF 9

A28

BCLK

A27

BCLK#

MISCTHERMALPWR MANAGEMENT

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

DDR3

MISC

DDR3

MISC

A16 A15

R8

AK1 A5 A4

2

CLK_EXP_P (20)

RN502

CLK_DP_P_R CLK_DP_N_R

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils.

RN502

2 3 1

SRN1KJ-7-GP

R502

1 2

4K99R2F-L-GP

R506 140R2F-GPR506 140R2F-GP

1 2

R507 25D5R2F-GPR507 25D5R2F-GP

1 2

R508 200R2F-L-GPR508 200R2F-L-GP

1 2

CLK_EXP_N (20)

4

1D05V_VTT

20110104 A00: merge R512,R514 to RN502 1k array resistor. 20110113 A00: Swap RN502 base on swap report.

SM_DRAMRST# (37)

1

Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted.

10KR2J-3-GP

H_CPUPWRGD_R

R510

1 2

1K5R2F-2-GP

PM_DRAM_PWRGD(19,37)

VDDPWRGOOD(37)

12

H_PM_SYNC(19)

H_CPUPWRGD(22,36)

R509

R509 750R2F-GP

750R2F-GP

DY

1 2

12

R504

H_CPUPWRGD_R

0R0402-PAD

VDDPWRGOOD

R505

0R2J-2-GP

DY

BUF_CPU_RST#

C501

C501 SC220P50V2KX-3GP

SC220P50V2KX-3GP

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

SANDY

AP29

PRDY#

AP27

PREQ#

AR26

TCK

AR27

TMS

AP30

TRST#

AR28

TDI

AP26

TDO

AL35

DBR#

AT28

BPM#0

AR29

BPM#1

JTAG & BPM

BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

AR30 AT30 AP32 AR31 AT31 AR32

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_TDI XDP_TMS XDP_TDO XDP_TCLK

XDP_TRST#

XDP_DBRESET#

RN501

1

8

2

7

3

6

4 5

SRN51J-1-GP

R511 51R2J-2-GPR511 51R2J-2-GP

1 2

R516

1 2

10KR2J-3-GP

1D05V_VTT

3D3V_S0

R503

1 2

C C

PLT_RST#(18,27,65,71,82,83)

B B

Buffered reset to CPU

PLT_RST#(18,27,65,71,82,83)

U501

1

IN B

VCC

2

DY

IN A

GND3OUT Y

74VHC1G09DFT2G-GP

73.01G09.AAH

1D05V_VTT

DY

5

4

12

R518

R518 75R2J-1-GP

75R2J-1-GP

3D3V_S0

12

C503

DY

SCD1U10V2KX-5GP

1 2

DY

R517 43R2J-GP

DY

12

0R2J-2-GP

BUF_CPU_RST#BUFO_CPU_RST#

R515

XDP_DBRESET#

XDP_DBRESET# (19)

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU 2/7(THERMAL/CLOCK/PM )

Size Document Number Rev

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

5 104Tuesday, January 18, 2011

1

A00

5

4

3

2

1

SSID = CPU

4 OF 9

3 OF 9

CPU1C

SANDY

M_A_DQ[63:0](14)

D D

C C

B B

M_A_DQ[63:0]

M_A_BS0(14) M_A_BS1(14) M_A_BS2(14)

M_A_CAS#(14) M_A_RAS#(14) M_A_WE#(14)

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AK8

AK9 AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9 AF9

C5

SA_DQ0

D5

SA_DQ1

D3

SA_DQ2

D2

SA_DQ3

D6

SA_DQ4

C6

SA_DQ5

C2

SA_DQ6

C3

SA_DQ7

F10

SA_DQ8

F8

SA_DQ9 SA_DQ10

G9

SA_DQ11

F9

SA_DQ12

F7

SA_DQ13

G8

SA_DQ14

G7

SA_DQ15

K4

SA_DQ16

K5

SA_DQ17

K1

SA_DQ18

J1

SA_DQ19

J5

SA_DQ20

J4

SA_DQ21

J2

SA_DQ22

K2

SA_DQ23

M8

SA_DQ24 SA_DQ25

N8

SA_DQ26

N7

SA_DQ27 SA_DQ28

M9

SA_DQ29

N9

SA_DQ30

M7

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37

AJ5

SA_DQ38

AJ6

SA_DQ39

AJ8

SA_DQ40 SA_DQ41

AJ9

SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55

V6

SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

3 OF 9

SA_CLK0

SA_CLK#0

SA_CKE0

SA_CLK1

SA_CLK#1

SA_CKE1

SA_CLK2

SA_CLK#2

SA_CKE2

SA_CLK3

SA_CLK#3

SA_CKE3

SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3

SA_ODT0

SA_ODT1 SA_ODT2 SA_ODT3

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIM0_CLK_DDR0 (14) M_A_DIM0_CLK_DDR#0 (14) M_A_DIM0_CKE0 (14)

M_A_DIM0_CLK_DDR1 (14) M_A_DIM0_CLK_DDR#1 (14) M_A_DIM0_CKE1 (14)

M_A_DIM0_CS#0 (14) M_A_DIM0_CS#1 (14)

M_A_DIM0_ODT0 (14) M_A_DIM0_ODT1 (14)

M_A_DQS #[7:0] (1 4)

M_A_DQS[7:0] (14)

M_A_A[15:0] (14)

M_B_DQ[63:0](15)

M_B_DQ[63:0]

M_B_BS0(15) M_B_BS1(15) M_B_BS2(15)

M_B_CAS#(15) M_B_RAS#(15) M_B_WE#(15)

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA9 AA7

AA10

AB8 AB9

CPU1D

SANDY

C9

SB_DQ0

A7

SB_DQ1 SB_DQ2

C8

SB_DQ3

A9

SB_DQ4

A8

SB_DQ5

D9

SB_DQ6

D8

SB_DQ7

G4

SB_DQ8

F4

SB_DQ9

F1

SB_DQ10

G1

SB_DQ11

G5

SB_DQ12

F5

SB_DQ13

F2

SB_DQ14

G2

SB_DQ15

J7

SB_DQ16

J8

SB_DQ17 SB_DQ18

K9

SB_DQ19

J9

SB_DQ20

J10

SB_DQ21

K8

SB_DQ22

K7

SB_DQ23

M5

SB_DQ24

N4

SB_DQ25

N2

SB_DQ26

N1

SB_DQ27

M4

SB_DQ28

N5

SB_DQ29

M2

SB_DQ30

M1

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54

R6

SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

4 OF 9

SB_CLK0

SB_CLK#0

SB_CKE0

SB_CLK1

SB_CLK#1

SB_CKE1

SB_CLK2

SB_CLK#2

SB_CKE2

SB_CLK3

SB_CLK#3

SB_CKE3

SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIM0_CLK_DDR0 (15) M_B_DIM0_CLK_DDR#0 (15) M_B_DIM0_CKE0 (15)

M_B_DIM0_CLK_DDR1 (15) M_B_DIM0_CLK_DDR#1 (15) M_B_DIM0_CKE1 (15)

M_B_DIM0_CS#0 (15) M_B_DIM0_CS#1 (15)

M_B_DIM0_ODT0 (15) M_B_DIM0_ODT1 (15)

M_B_DQS#[7:0] (15)

M_B_DQS[7:0] (15)

M_B_A[15:0] (15)

SANDY

A A

5

4

3

SANDY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU 3/7(DDR)

Nirvana 13

1

A00

of

6 104Tuesday, January 18, 2011

A00

SSID = CPU

5

4

3

2

1

CFG7

1

TP713 TPAD14-GPTP713 TPAD14-GP

1

TP714 TPAD14-GPTP714 TPAD14-GP

CFG4

CFG2

DY

12

R701

DY

1KR2J-1-GP

12

DY

12

DY

12

R704

R705

R705 1KR2J-1-GP

1KR2J-1-GP

R702

R702 1KR2J-1-GP

1KR2J-1-GP

12

R703

R703 3K3R2F-2-GP

3K3R2F-2-GP

PEG Static Lane Reversal

CFG2

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

1KR2J-1-GP

CFG[6:5]

11: x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

PEG DEFER TRAINING

CFG7

1: PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

5 OF 9

CPU1E

AK28

CFG0

AK29

D D

TP712TPAD14-GP TP712TPAD14-GP

CFG2

CFG4 CFG5 CFG6 CFG7

CFG17

1

M3 - Processor Generated SO-DIMM VREF_DQ

C C

M_VREF_DQ_DIMM0 M_VREF_DQ_DIMM1

M_VREF_CA_DIMM0

M_VREF_CA_DIMM1

R707 0R2J-2-GP

R706 0R2J-2-GP

DY

R708 0R2J-2-GP

1 2

DY

R709 0R2J-2-GP

1 2

DY

1 2

DY

M_VREF_DQ_DIMM0_C M_VREF_DQ_DIMM1_C

R711

1KR2F-3-GP

20 mils

R710 0R2J-2-GP

1 2

DY

B B

B4:VREF_DQ CHA

D1:VREF_DQ CHB

12

R712

1KR2F-3-GP

H_VCCP_SEL

AL26 AL27

AK26

AL29

AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29

AJ31 AH31

AJ33 AH33

AJ26

F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29

B18 A19

B4 D1

J20

J15

CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

RSVD#AJ31 RSVD#AH31 RSVD#AJ33 RSVD#AH33

RSVD#AJ26

RSVD#B4 RSVD#D1

RSVD#F25 RSVD#F24 RSVD#F23 RSVD#D24 RSVD#G25 RSVD#G24 RSVD#E23 RSVD#D23 RSVD#C30 RSVD#A31 RSVD#B30 RSVD#B29 RSVD#D30 RSVD#B31 RSVD#A30 RSVD#C29

RSVD#J20 RSVD#B18 RSVD#A19

RSVD#J15

SANDY

RESERVED

5 OF 9

RSVD#L7 RSVD#AG7 RSVD#AE7 RSVD#AK2

RSVD#W8

RSVD#AT26

RSVD#AM33

RSVD#AJ27

RSVD#T8

RSVD#J16 RSVD#H16

RSVD#G16

RSVD#AR35

RSVD#AT34 RSVD#AT33

RSVD#AP35

RSVD#AR34

RSVD#B34 RSVD#A33 RSVD#A34 RSVD#B35 RSVD#C35

RSVD#AJ32

RSVD#AK32

RSVD#AH27

RSVD#AN35 RSVD#AM35

RSVD#AT2 RSVD#AT1 RSVD#AR1

L7 AG7 AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

AN35 AM35

AT2 AT1 AR1

RSVD#AN35 RSVD#AM35

CFG5

CFG6

SANDY

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU 4/7(RESERVED)

Size Document Number Rev

Date: Sheet of

Date: Sheet

CPU 4/7(RESERVED)

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

of

7 104Tuesday, January 04, 2011

1

A00

5

4

3

2

1

SSID = CPU

D D

POWER

CPU1F

SANDY

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

SANDY

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

SANDY

4

CORE SUPPLY

VCC_CORE

PROCESSOR CORE POWER

C C

B B

A A

VCC_CORE

20110118 A00: Reserve C846~C848 22uF (0805 size).

53A

12

DY

12

C802

C801

SC10U6D3V5KX-1GP

12

C819

C820

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

20110118 A00: Change C823, C824, C825 to 22uF from 10uF (0805 size).

12

C816

C821

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

12

C836

C837

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

VCC Output Decoupling Recommendation: 4 x 470 uF at Bottom Socket Edge 8 x 22 uF at Top Socket Cavity 8 x 22 uF at Top Socket Edge 8 x 22 uF at Bottom Socket Cavity

12

C846

C847

DY

SC22U6D3V5MX-2GP

5

12

C811

C803

SC10U6D3V5KX-1GP

C818

SC22U6D3V5MX-2GP

C822

SC10U6D3V5KX-1GP

C835

SC22U6D3V5MX-2GP

12

C811

C804

DY

SC22U6D3V5MX-2GP

12

C815

C817

SC10U6D3V5KX-1GP

12

C824

C823

SC22U6D3V5MX-2GP

12

C833

C834

SC10U6D3V5KX-1GP

C848

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

12

C825

C826

C827

SC22U6D3V5MX-2GP

12

C832

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

12

C828

C831

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

6 OF 9

AH13

VCCIO

AH10

VCCIO

AG10

VCCIO

AC10

VCCIO

Y10

VCCIO

U10

VCCIO

P10

VCCIO

L10

VCCIO

J14

VCCIO

J13

VCCIO

J12

VCCIO

J11

VCCIO

H14

VCCIO

H12

VCCIO

H11

VCCIO

G14

VCCIO

G13

VCCIO

G12

VCCIO

F14

VCCIO

F13

VCCIO

F12

VCCIO

F11

VCCIO

E14

VCCIO

E12

VCCIO

E11

VCCIO

D14

VCCIO

D13

VCCIO

D12

VCCIO

D11

VCCIO

C14

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSSIO_SENSE

C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

PEG AND DDR

SENSE LINES SVID

VCCIO Output Decoupling Recommendation: 2 x 330 uF (3 x 330 uF for 2012 capable designs) 5 x 22 uF & 5 x 0805 no-stuff at Bottom 7 x 22 uF & 2 x 0805 no-stuff at Top

12

C805

DY

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

20101231 A00: Merge R801,R802 to RN801 100 ohm array resistor. 20110113 A00: Change RN801 to 100 ohm 1% (66.10156.04L). 20110113 A00: Swap RN801 base on swap report.

VCC_CORE

12

C806

DY

SC10U6D3V3MX-GP

No-stuff sites outside the socket may be removed. No-stuff sites inside the socket cavity need to remain.

R803 43R2J-G PR803 43R2J-GP

1 2

RN801

2 3

R2

1

R1

SRN100F-1-GP

VCCIO_SENSE (45) VSSIO_SENSE (45)

3

12

C807

C808

DY

SC10U6D3V3MX-GP

12

C829

SC10U6D3V5KX-1GP

12

C809

SC10U6D3V5KX-1GP

12

C830

SC10U6D3V5KX-1GP

12

C838

C810

SC10U6D3V5KX-1GP

12

C843

C842

DY

SC4D7U6D3V5KX-3GP

These resistors need to close to power IC.

VR_SVID_ALERT#

H_CPU_SVIDCLK

H_CPU_SVIDDAT

VR_SVID_ALERT# (42)

H_CPU_SVIDCLK (42)

4

H_CPU_SVIDDAT (42)

R805 75R2J-1-GPR805 75R2J-1-GP

1 2

R806 54D9R2F-L1-GP

1 2

R804 130R2F-1-GPR804 130R2F-1-GP

1 2

VCCSENSE (42) VSSSENSE (42)

C839

SC4D7U6D3V5KX-3GP

1D05V_VTT

C844

SC10U6D3V5KX-1GP

DY

1D05V_VTT

12

C841

C840

SC10U6D3V5KX-1GP

12

C845

SC10U6D3V5KX-1GP

1D05V_VTT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

CPU 5/7(VCC_CORE)

Nirvana 13

1

8 104Tuesday, January 18, 2011

A00

of

5

VAXG Output Decoupling Recommendation:

SSID = CPU

VCC_GFXCORE

2 x 470 uF at Bottom Socket Edge 2 x 22 uF at Top Socket Cavity 4 x 22 uF at Top Socket Edge 2 x 22 uF at Bottom Socket Cavity 4 x 22 uF at Bottom Socket Edge

PROCESSOR VAXG: 33A

D D

DY

C C

Disabling Guidelines for External Graphics Designs: Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed. Can be left floating (Gfx VR keeps VAXG rail from floating)

B B

if the VR is stuffed

12

C901

SC10U6D3V5KX-1GP

DY

1D8V_S0

12

C902

SC4D7U6D3V5KX-3GP

12

C908

SC10U6D3V3MX-GP

12

C904

C903

SC4D7U6D3V5KX-3GP

DY

PROCESSOR VCCPLL: 1.2A

12

C923

SC10U6D3V5KX-1GP

12

C905

SC22U6D3V5MX-2GP

12

C920

DY

SC10U6D3V3MX-GP

12

C922

SC1U10V2KX-1GP

4

12

C906

SC4D7U6D3V5KX-3GP

12

C921

SC10U6D3V3MX-GP

12

C924

SC1U10V2KX-1GP

AT24 AT23 AT21 AT20 AT18

AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17

AM24 AM23 AM21 AM20 AM18 AM17

AL24

AL23

AL21

AL20

AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

3

POWER

CPU1G

VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG

B6

VCCPLL

A6

VCCPLL

A2

VCCPLL

SANDY

POWER

SANDY

GRAPHICS

1.8V RAIL

SENSE

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

7 OF 9

VAXG_SENSE

VSSAXG_SENSE

LINES

SM_VREF

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCSA_SENSE

FC_C22

VCCSA_VID1

AK35 AK34

Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation.

+V_SM_VREF_CNT should have 10 mil trace width

+V_SM_VREF_CNT

AL1

Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

PROCESSOR VDDQ: 10A

12

C909

DY

SC10U6D3V3MX-GP

PROCESSOR VCCSA: 6A

12

C916

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

VCCUSA_SENSE

H_FC_C22 VCCSA_SEL

SC10U6D3V5KX-1GP

1

23

2

VCC_AXG_SENSE (42) VSS_AXG_SENSE (42)

+V_SM_VREF_CNT (37)

12

C910

C911

DY

12

RN901

RN901 SRN1KJ -7-GP

SRN1KJ -7-GP

C911

DY

SC10U6D3V3MX-GP

0D85V_S0

12

C917

C915

SC10U6D3V5KX-1GP

VCCUSA_SENSE (48)

H_FC_C22 (48) VCCSA_SEL (48)

12

C912

SC10U6D3V5KX-1GP

SC10U6D3V3MX-GP

SC10U6D3V5KX-1GP

1

20101231 A00: Merge R906,R907 to RN902 100 ohm array resistor. 20110113 A00: Change RN801 to 100 ohm 1% (66.10156.04L).

RN902

R1

VCC_AXG_SENSE VSS_AXG_SENSE

1D5V_S0

12

C914

C913

SC10U6D3V5KX-1GP

VDDQ Output Decoupling Recommendation: 1 x 330 uF 6 x 10 uF

TC901

79.33719.20L

SC4D7U6D3V5KX-3GP

2nd = 77.C3371.13L

VCCSA Output Decoupling Recommendation: 1 x 330 uF 2 x 10 uF at Bottom Socket Cavity 1 x 10 uF at Bottom Socket Edge

1 2 3

SRN100F-1-GP

12

DY

ST330U2VDM-4-GP

C907

R1

4

R2

12

DY

C918

C919

SCD1U10V2KX-5GP

VCC_GFXCORE

12

DY

C925

SCD1U10V2KX-5GP

1D5V_S3

SCD1U10V2KX-5GP

4

VCCPLL Output Decoupling Recommendation: 1 x 330 uF 2 x 1 uF 1 x 10 uF

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU 6/7(VCC_GFX_CORE)

Size Document Number Rev

Date: Sheet of

Date: Sheet

CPU 6/7(VCC_GFX_CORE)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

9 104Tuesday, January 18, 2011

1

A00

5

4

3

2

1

SSID = CPU

9 OF 9

8 OF 9

CPU1H

AT35

VSS

AT32

VSS

AT29

VSS

AT27

VSS

AT25

VSS

D D

C C

B B

AT22 AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34

K35 K32 K29 K26

H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11

CPU1I

T35

VSS

T34

VSS

T33

VSS

T32

VSS

T31

VSS

T30

VSS

T29

VSS

T28

VSS

T27

VSS

T26

VSS

P9

VSS

P8

VSS

P6

VSS

P5

VSS

P3

VSS

P2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L33

VSS

L30

VSS

L27

VSS

L9

VSS

L8

VSS

L6

VSS

L5

VSS

L4

VSS

L3

VSS

L2

VSS

L1

VSS VSS VSS VSS VSS

J34

VSS

J31

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H9

VSS

H8

VSS

H7

VSS

H6

VSS

H5

VSS

H4

VSS

H3

VSS

H2

VSS

H1

VSS VSS VSS VSS VSS VSS VSS VSS VSS

F34

VSS

F31

VSS

F29

VSS

SANDY

VSS

9 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

SANDY

A A

5

4

3

SANDY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU 7/7(VSS)

Nirvana 13

1

A00

of

10 104Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

Remove the XDP connector for space saving 6/28

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

XDP

NIRVANA 13

Taipei Hsien 221, Taiwan, R.O.C.

of

11 104

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

of

12 104Tuesday, January 04, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

13 104Tuesday, January 04, 2011

A00

5

4

3

2

1

SSID = MEMORY

DM1

H=9.2mm

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-42-GP

62.10017.N61

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIM0

197

SA0

SA1_DIM0

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_A_RAS# (6) M_A_WE# (6) M_A_CAS# (6)

M_A_DIM0_CS#0 (6) M_A_DIM0_CS#1 (6)

M_A_DIM0_CKE0 (6) M_A_DIM0_CKE1 (6)

M_A_DIM0_CLK_DDR0 (6) M_A_DIM0_CLK_DDR#0 (6)

M_A_DIM0_CLK_DDR1 (6) M_A_DIM0_CLK_DDR#1 (6)

PCH_SMBDATA (15,20,65,79,82) PCH_SMBCLK (15,20,65,79,82)

TS#_DIMM0_1 (15)

Layout Note: Place these Caps near SO-DIMMA.

PART NUMBER

62.10017.N61

62.10017.U01

62.10017.T11

20101231 A00: Merge R1401,R1402 to RN1401 10k ohm array resistor. 20110104 A00: Change RN1401 to 0R short pad. 20110113 A00: Swap RN1401 base on swap report.

3D3V_S0

12

C1402

C1401

DY

SCD1U10V2KX-5GP

1D5V_S3

SC2D2U10V3KX-1GP

12

ST330U2VDM-4-GP

TC1401

DY

79.33719.20L

2nd = 77.C3371.13L

12

C1414

DY

SCD1U10V2KX-5GP

Height TYPE

9.2mm

SA0_DIM0

SA1_DIM0

23

SODIMM A DECO UPLING

12

C1403

C1404

C1405

DY

SC10U6D3V5KX-1GP

12

C1415

DY

SCD1U10V2KX-5GP

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

12

C1417

C1416

SCD1U10V2KX-5GP

1

RN1401

RN1401 0R4P2R-PAD

0R4P2R-PAD

RN

4

Thermal EVENT

TS#_DIMM0_1

12

C1407

C1406

DY

SC10U6D3V5KX-1GP

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

3D3V_S0

R1403

1 2

10KR2J-3-GP

12

C1409

C1408

SC10U10V5ZY-1GP

C1410

DY

SC10U6D3V5KX-1GP

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

12

DY

M_A_DQ[63:0](6)

12

C1422

DY

SC1U6D3V2KX-GP

M_A_DIM0_ODT0(6) M_A_DIM0_ODT1(6)

M_VREF_CA_DIMM0 M_VREF_DQ_DIMM0

DDR3_DRAMRST#(15,37)

M_A_A[15:0] (6)

M_A_BS2(6)

M_A_BS0(6) M_A_BS1(6)

C1418

SC10U6D3V5KX-1GP

M_A_DQS#[7:0] (6)

M_A_DQS[7:0] ( 6)

0D75V_S0

DDR_VREF_S3

R1405

R1405 0R0402-PAD

D D

20101224 A00: 0402 0R pad: R1404 R1405.

C C

B B

1 2

12

DDR_VREF_S3

1 2

12

0D75V_S0

0R0402-PAD

C1423

SCD1U10V2KX-5GP

R1404

R1404 0R0402-PAD

0R0402-PAD

C1411

SCD1U10V2KX-5GP

12

C1419

M_VREF_CA_DIMM0

12

C1425

DY

SC2D2U10V3KX-1GP

M_VREF_DQ_DIMM0

12

C1412

DY

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1420

DY

SC1U6D3V2KX-GP

12

C1424

SCD1U10V2KX-5GP

12

C1413

SCD1U10V2KX-5GP

12

C1421

SC1U6D3V2KX-GP

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

DDR3-DIMM1 SOCKET1

Nirvana 13

1

of

14 104Tuesday, January 18, 2011

A00

5

SSID = MEMORY

M_B_A[15:0] (6)

C1520

SC1U6D3V2KX-GP

M_B_BS2(6)

M_B_BS0(6) M_B_BS1(6)

M_B_DQ[63:0](6)

12

C1521

SC1U6D3V2KX-GP

M_B_DIM0_ODT0(6) M_B_DIM0_ODT1(6)

M_VREF_CA_DIMM1 M_VREF_DQ_DIMM1

DDR3_DRAMRST#(14,37)

M_B_DQS#[7:0] (6)

M_B_DQS[7:0] ( 6)

0D75V_S0

D D

DDR_VREF_S3

R1504

R1504 0R0402-PAD

0R0402-PAD

M_VREF_CA_DIMM1

1 2

12

C1523

SCD1U10V2KX-5GP

DDR_VREF_S3

R1503

R1503 0R0402-PAD

0R0402-PAD

C C

B B

1 2

12

C1515

SCD1U10V2KX-5GP

0D75V_S0

12

C1522

C1524

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

20101224 A00: 0402 0R pad: R1503 R1504.

M_VREF_DQ_DIMM1

12

C1516

C1517

12

DY

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1518

SC1U6D3V2KX-GP

C1517

SCD1U10V2KX-5GP

C1519

SC1U6D3V2KX-GP

DY

12

DY

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

H=5.2mm

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-48-GP

62.10017.P41

4

NP1

NP2

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIM1

197

SA0

SA1_DIM1

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_B_RAS# (6) M_B_WE# (6) M_B_CAS# (6)

M_B_DIM0_CS#0 (6) M_B_DIM0_CS#1 (6)

M_B_DIM0_CKE0 (6) M_B_DIM0_CKE1 (6)

M_B_DIM0_CLK_DDR0 (6) M_B_DIM0_CLK_DDR#0 (6)

M_B_DIM0_CLK_DDR1 (6) M_B_DIM0_CLK_DDR#1 (6)

PCH_SMBDATA (14,20,65,79,82) PCH_SMBCLK (14,20,65,79,82)

TS#_DIMM0_1 (14)

Layout Note: Place these Caps near SO-DIMMB.

PART NUMBER

62.10017.P41

62.10017.T91 5.2mm

62.10017.T01 5.2mm

3

12

C1502

C1501

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

Height TYPE

5.2mm

1D5V_S3

SA1_DIM1

SA0_DIM1

3D3V_S0

SODIMM B DECO UPLING

12

C1503

DY

12

C1511

DY

3D3V_S0

12

C1504

DY

SC10U10V5ZY-1GP

12

C1512

SCD1U10V2KX-5GP

R1501

R1501 10KR2J-3-GP

10KR2J-3-GP

R1502

R1502 0R0402-PAD

0R0402-PAD

20100104 A00: Change R1502 to 0R0402 short pad.

12

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

SO-DIMMB is placed f arther from the Processor than SO-DIMM A

12

C1507

C1505

SC10U6D3V5KX-1GP

C1513

C1507

C1506

SC10U6D3V5KX-1GP

12

C1514

SCD1U10V2KX-5GP

DY

SC4D7U6D3V5KX-3GP

2

12

C1508

C1509

C1510

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

1

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

DDR3-DIMM2 SOCKET2

Size Document Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

Nirvana 13

1

A00

of

15 104Tuesday, January 18, 2011

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

of

16 104Tuesday, January 04, 2011

1

A00

5

L_DDC_DATA(PAGE17):

D D

RN1702

1 2 3

SRN100KJ-6-GP

4

L_BKLT_EN LVDS_VDD_EN

This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display

Place near PCH

3D3V_S0

RN1703

1 2 3 4 5

SRN2K2J-2-GP

C C

SRN2K2J-2-GP

20110104 A00: Merge RN1701,RN1706 to RN1703 2.2k array resistor. 20110113 A00: Swap RN1703.7,RN1703.5; swap RN1703.8,RN1703.6.

8 7 6

PCH_HDMI_DATA PCH_HDMI_CLK L_CTRL_DATA L_CTRL_CLK

Impedance:90 ohm

Close to PCH side

CRT_GREEN

CRT_BLUE CRT_RED

678

RN1705

RN1705 SRN150F-1-GP

SRN150F-1-GP

123

4 5

B B

4

L_BKLT_EN(27)

LVDS_VDD_EN(49)

L_BKLT_CTRL(49)

LVDS_DDC_CLK_R(49,97) LVDS_DDC_DATA_R(49,97)

20101224 A00: Change RN1704 to 0402 0 ohm pad.

12

R1701

R1701 2K37R2F-GP

2K37R2F-GP

LVDSA_CLK#(49) LVDSA_CLK(49)

LVDSA_DATA0#(49) LVDSA_DATA1#(49) LVDSA_DATA2#(49)

LVDSA_DATA0(49) LVDSA_DATA1(49) LVDSA_DATA2(49)

0617 Modify: Joseph Removed LVDSB r elated net for single LVDS channel ba se on Dell updated spec.

CRT_BLUE(50) CRT_GREEN(50) CRT_RED(50)

CRT_DDC_CLK(50) CRT_DDC_DATA(50)

CRT_HSYNC(50) CRT_VSYNC(50)

Notes: 1K 0.5% 0402.

TP1701TPAD14-GP TP1701TPAD14-GP

RN1704

1 2 3

0R4P2R-PAD

R1702

1KR2D-1-GP

LVDS_DDC_CLK_R LVDS_DDC_DATA_R

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG

RN

LVDS_VBG

1

LVDS_VREFH

4

LVDS_VREFL

DAC_IREF_R

12

PCH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGAR-GP-U2-NF

3

4 OF 10

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

Cougar

Cougar Point

Point

LVDS

CRT

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

2

DDI Port B Detect:(SDVO_CTRL_ DATA) 1: Port B detected 0: Port B not detected

1

PCH_HDMI_CLK (51) PCH_HDMI_DATA (51)

HDMI_PCH_DET (51)

HDMI_DATA2_R# (51) HDMI_DATA2_R (51) HDMI_DATA1_R# (51) HDMI_DATA1_R (51) HDMI_DATA0_R# (51) HDMI_DATA0_R (51) HDMI_CLK_R# (51) HDMI_CLK_R (51)

Impedance:100 ohmImpedance:90 ohm

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

PCH 1/9(LVDS/CRT/DDI)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

17 104Tuesday, January 18, 2011

1

A00

5

SSID = PCH

RN1801

D D

3D3V_S0

INT_PIRQB# INT_PIRQF# INT_PIRQA#

R1801 4K7R2J-2-GP

A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3 Low = A16 swap

C C

RN1801

1 2 3 4 5 6

SRN8K2J-2-GP-U

12

DY

override/Top-Block Swap Override enabled High = Default

R1802

1 2

DY

1KR2J-1-GP

R1803

1 2

DY

1KR2J-1-GP

10

INT_PIRQD#

9

INT_PIRQE#

8

INT_PIRQC#

7

INT_PIRQG#

PCI_GNT3#

BBS_BIT1

BBS_BIT0

3D3V_S0

BBS_BIT0 (21)

BOOT BIOS Strap

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

0 0 LPC

0 1 Reserved

Reserved 01

B B

20101231 A00: Merge R1804,R1806 to RN1804 22 ohm array resistor. 20110113 A00: Swap RN1804 base on swap report.

A A

PLT_RST#(5,27,65,71,82,83)

11

12

DY

5

SPI(Default)

CLK_PCI_LPC(65,71,97) CLK_PCI_FB(20) CLK_PCI_KBC(27)

20101224 A00: 0402 0R pad: R1807.

0R0402-PAD

R1816

12

C1801

DY

SC220P50V2KX-3GP

100KR2J-1-GP

R1807

PCI_PLTRST#

12

HDD_FALL_INT1(79)

SATA_ODD_DA#(56)

KB_LED_BL_DET(69)

EC1801

1 2

DY

SC4D7P50V2CN-1GP

USB30_SMI#(82)

DGPU_HOLD_RST#(83)

DGPU_PWR_EN#(93)

TP1806TPAD14-GP TP1806TPAD14-GP

RN1804

2 3 1

SRN22-3-GP

EC1802

4

DGPU_HOLD_RST# DGPU_PWR_EN#

DGPU_PWM_SELECT#

1

4

R1805 22R2J-2-GPR1805 22R2J-2-GP

1 2

DY

SC4D7P50V2CN-1GP

1 2

4

1 2 3

SRN10KJ-5-GP

3D3V_S0

1 2

1

TP1807TPAD14-GP TP1807TPAD14-GP

1 2

DGPU_PWR_EN#

R1812 0R0402-PADR1812 0R0402-PAD

1 2

R1813 0R0402-PADR1813 0R0402-PAD

1 2

R1815 0R0402-PADR1815 0R0402-PAD

1 2

R1817 0R0402-PADR1817 0R0402-PAD

1 2

KBC CLK EMI

R1818 10KR2J-3-GPR1818 10KR2J-3-GP

FFS_INT2_R

RN1803

R1814

R1814 8K2R2J-3-GP

8K2R2J-3-GP

TP1801TPAD14-GP TP1801TPAD14-GP

TP1802TPAD14-GP TP1802TPAD14-GP

4

1

CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

DGPU_SELECT#

BBS_BIT1

PCI_GNT3#

INT_PIRQE# INT_ PIRQF# INT_PIRQG# INT_PIRQH#

PCI_PME#

PCI_PLTRST#

3D3V_S5

3

PCH1E

Cougar

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

H3

AH12

AM4 AM5

Y13 K24

L24 AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

K40 K38 H38

G38

C46 C44 E40

D47 E42 F46

G42 G40

C42 D44

K10

C6

H49 H43

J48 K42 H40

USB_OC#2_3

Cougar

TP1

Point

TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO 5

PME#

PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

COUGAR-GP-U2-NF

OC[3:0]# for Device 29 (Ports 0-7) OC[7:4]# for Device 26 (Ports 8-13)

3

NVRAM

RSVD

PCI

USB

RN1802

1 2 3 4 5 6

SRN8K2J-2-GP-U

5 OF 10

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD

DF_TVS

RSVD

RSVD RSVD

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

10

USB_OC#12_13

9

USB_OC#8_9USB_OC#6_7

8

USB_OC#10_11USB_OC#0_1

7

USB_OC#4_5

2

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

NV_ALE

AV5

NV_CLE

AY1

NV_RCOMP

AV10

AT8

AY5 BA2

AT12

USB Ext. port 1 (HS)

BF3

External debug port use on Huron river platform

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_RBIAS

C33

B33

USB_OC#0_1

A14

USB_OC#2_3

K20

USB_OC#4_5

B17

USB_OC#6_7

C16

USB_OC#8_9

L16

USB_OC#10_11

A16

USB_OC#12_13

D14 C14

3D3V_S5

TP1803 TPAD14-GPTP1803 TPAD14-GP

1

USB_PN1 (57) USB_PP1 (57) USB_PN2 (64) USB_PP2 (64) USB_PN3 (63) USB_PP3 (63) USB_PN4 (82) USB_PP4 (82) USB_PN5 (32) USB_PP5 (32)

USB_PN11 (65) USB_PP11 (65) USB_PN12 (49) USB_PP12 (49)

1 2

R1811

R1811 22D6R2F-L1-GP

22D6R2F-L1-GP

FFS_INT2_R (79)

2

NV_CLE

DMI & FDI Termination Voltage

NV_CLE

USB_OC#0_1 (61)

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

1D8V_S0

12

R1808

R1808 2K2R2J-2-GP

2K2R2J-2-GP

R1809

1 2

1KR2J-1-GP

H_SNB_IVB# (5)

Set to Vss when LOW

Set to Vcc when HIGH

Danbury Technology: Disabled when Low. Enable when High.

USB Table

Pair

X

0

E-SATA / USB Combo

1

Fingerprint

2

BLUETOOTH

3

Mini Card2 (WWAN)

4

CARD READER

5

X

6

X

7

X

8

X

9

X

10

Mini Card1 (WLAN)

11

CAMERA

12

X

13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH 2/9(PCI/USB/NVRAM)

Nirvana 13

1

NV_ALE

Device

1

1D8V_S0

12

R1810

R1810 1KR2J-1-GP

1KR2J-1-GP

DY

A00

of

18 104Tuesday, January 18, 2011

A00

5

4

3

2

1

1 2

1 2 3 45

12

12 12

12

DMI_RXN[3:0](4)

DMI_RXP[3:0](4 )

DMI_TXN[3:0](4)

DMI_TXP[3:0](4)

DMI_RXN0(4) DMI_RXN1(4) DMI_RXN2(4) DMI_RXN3(4)

DMI_RXP0(4) DMI_RXP1(4) DMI_RXP2(4) DMI_RXP3(4)

DMI_TXN0(4) DMI_TXN1(4) DMI_TXN2(4) DMI_TXN3(4)

DMI_TXP0(4 ) DMI_TXP1(4 ) DMI_TXP2(4 ) DMI_TXP3(4 )

1 2

R1903 0R0402-PADR1903 0R0402-PAD

1 2

R1925 0R0402-PADR1925 0R0402-PAD

1 2

DY

PWROK

R1907

1 2

0R2J-2-GP

DY

BATLOW# PM_RI# PCH_WAKE# SUS_PWR_ACK

AC_PRESENT

PM_PWRBTN# PM_SLP_LAN#

PM_RSMRST#

DMI_COMP_R

RBIAS_CPY

SUSACK#SUS_PWR_ACK

SYS_RESET#

R1905

10KR2J-3-GP

R1923

1 2

0R2J-2-GP

DY

R1906 0R0402-PADR1906 0R0402-PAD

1 2

MEPWROK

PM_RSMRST#

BATLOW#

PM_RI#

PCH1C

BC24

DMI0RXN

Cougar

BE20 BG18 BG20

BE24 BC20

BJ18

BJ20

AW24 AW20

BB18

AV18

AY24

AY20

AY18 AU18

BJ24

BG25

BH21

C12

K3

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

COUGAR-GP-U2-NF

4

Cougar

DMI1RXN

Point

DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPW RDNACK/GPIO30

PWRBTN#

ACPRESENT/GPIO31

BATLOW#/GPI O72

RI#

3 OF 10

BJ14

FDI_RXN0

AY14

FDI_RXN1

BE14

FDI_RXN2

BH13

FDI_RXN3

BC12

FDI_RXN4

BJ12

FDI_RXN5

BG10

FDI_RXN6

BG9

FDI_RXN7

BG14

FDI_RXP0

BB14

FDI_RXP1

BF14

FDI_RXP2

BG13

FDI_RXP3

BE12

FDI_RXP4

BG12

FDI_RXP5

BJ10

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#/GPIO29

BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

DSWODVREN

PCH_DPWROK

PM_SUS_STAT#

SUS_CLK

PM_SLP_S5#

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PM_SLP_LAN#

3

FDI_TXN[7:0] (4) FDI_TXP[7:0] (4)

FDI_TXN0 (4) FDI_TXN1 (4) FDI_TXN2 (4) FDI_TXN3 (4) FDI_TXN4 (4) FDI_TXN5 (4) FDI_TXN6 (4) FDI_TXN7 (4)

FDI_TXP0 (4) FDI_TXP1 (4) FDI_TXP2 (4) FDI_TXP3 (4) FDI_TXP4 (4) FDI_TXP5 (4) FDI_TXP6 (4) FDI_TXP7 (4)

FDI_ INT (4)

FDI_FSYNC0 (4)

FDI_FSYNC1 (4)

FDI_LSYNC0 (4)

FDI_LSYNC1 (4)

DY

1

PM_RSMRST#

R1910 0R0402-PADR1910 0R0402-PAD

1 2

R1911 10KR2J-3-GP

1 2

PCH_WAKE# (27)

PM_CLKRUN# (27)

TP1901 TPAD14-GPTP1901 TPAD14-GP

R1913 0R0402-PADR1913 0R0402-PAD

1 2

TP1902 TPAD14-GPTP1902 TPAD14-GP

TP1903TPAD14-GPTP1903TPAD14-GP

TP1904TPAD14-GPTP1904TPAD14-GP

H_PM_SYNC (5)

TP1905TPAD14-GPTP1905TPAD14-GP

R1912

1 2

0R0402-PAD

For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)

2.DPWROK and RSMRST# will rise at the same time (connected on board)

3.SLP_SUS# and SUSACK# are left as ‘no connect’

4.SUSWARN# used as SUSPWRDNACK/GPIO30

PM_RSMRST#

RSMRST#_KBC (27)

PCH_SUSCLK_KBC

EC1901

1 2

DY

SC4D7P50V2CN-1GP

RTC_AUX_S5

PCH_SUSCLK_KBC (27)

PM_SLP_S4# (27,46)

PM_SLP_S3# (27,36,37,46,47)

2

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1 2

DSWODVREN

PM_CLKRUN#

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Nirvana 13

R1918 330KR2J-L1-GP

1 2

DY

R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH 3/9(DM I/FDI/PM)

19 104Tuesday, January 18, 2011

1

RTC_AUX_S5

3D3V_S0

of

A00

SSID = PCH

D D

Signal Routing Guideline: DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

1D05V_VTT

R1901 49D9R2F-GPR1901 49D9R2F-GP

R1902 750R2F-GPR1902 750R2F-GP

SYS_PWROK

R1926

XDP_DBRESET#(5 )

S0_PWR_GOOD(27,36)

PM_PWRBTN#(27)

DY

SYS_PWROK(36)

RUNPWROK(45,46,47)

3D3V_S5

R1926

PWROK

R1904

3D3V_S0

1 2

R1924 0R0402-PADR1924 0R0402-PAD

RN1901

8 7 6

SRN10KJ-6-GP

R1921

100KR2J-1-GP

R1922 10KR2J-3-GP

DY

R1920 10KR2J-3-GP

DY

R1908

10KR2J-3-GP

5

C C

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

B B

A A

1 2

10KR2J-3-GP

1 2

100KR2J-1-GP

PM_DRAM_PWRGD(5,37)

SUS_PWR_ACK(27)

AC_PRESENT(27)

5

SSID = PCH

D D

C C

::$1&/.

:/$1&/.

B B

86%&/.

A A

PCIE_RXN2(82)

PCIE_RXP2(82) PCIE_TXN2(82) PCIE_TXP2(82)

PCIE_RXN3(82)

PCIE_RXP3(82) PCIE_TXN3(82) PCIE_TXP3(82)

PCIE_RXN4(65)

PCIE_RXP4(65) PCIE_TXN4(65) PCIE_TXP4(65)

PCIE_RXN5(82)

PCIE_RXP5(82) PCIE_TXN5(82) PCIE_TXP5(82)

CLK_PCIE_WWAN#(82) CLK_PCIE_WWAN(82)

CLK_PCIE_WWAN_REQ#(82)

CLK_PCIE_WLAN_REQ#(65)

CLK_PCIE_LAN#(82)

/$1&/.

3D3V_S0

PCIECLKRQ1# and PCIECLKRQ2#

CLK_PCIE_LAN(82)

PCIE_CLK_LAN_REQ#(82)

USB3_PEGB_CLKREQ#(82)

RN2018

1 2 3

SRN10KJ-5-GP

C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP

1 2

C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP

1 2

C2011 SCD1U10V2KX-5GPC2011 SCD1U10V2KX-5GP

1 2

C2012 SCD1U10V2KX-5GPC2012 SCD1U10V2KX-5GP

1 2

C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP

1 2

C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP

1 2

C2009 SCD1U10V2KX-5GPC2009 SCD1U10V2KX-5GP

1 2

C2010 SCD1U10V2KX-5GPC2010 SCD1U10V2KX-5GP

1 2

20101224 A00: Change RN2011~RN2014 to 0402 0 ohm pad.

CLK_PCIE_WLAN#(65) CLK_PCIE_WLAN(65)

CLK_PCIE_USB3#(82)

CLK_PCIE_USB3(82)

PCIE_CLK_RQ2#

4

CLK_PCIE_WLAN_REQ#

Support S0 power only

5

RN2011

1 2 3

0R4P2R-PAD

RN2012

2 3 1

0R4P2R-PAD

RN2014

2 3 1

0R4P2R-PAD

RN2013

1 2 3

0R4P2R-PAD

TP2005TPAD14-GP TP2005TPAD14-GP TP2006TPAD14-GP TP2006TPAD14-GP

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN3_C PCIE_TXP3_C

PCIE_TXN4_C PCIE_TXP4_C

PCIE_TXN5_C PCIE_TXP5_C

RN

CLK_PCH_SRC0_N

4

CLK_PCH_SRC0_P

CLK_PCH_SRC1_N

4

RN

PCIE_CLK_RQ2#

CLK_PCH_SRC3_N CLK_PCH_SRC3_P

4

RN

CLK_PCH_SRC4_N

4

CLK_PCH_SRC4_P

PCIE_CLK_REQ5#

PEG_B_CLKRQ#

PCIE_CLK_REQ6#

CLK_PCIE_NEW_REQ#

1 1

ITPXDP_N ITPXDP_P

4

PCH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1#/GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2#/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4#/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5#/GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

COUGAR-GP-U2-NF

4

3

2 OF 10

Cougar

Cougar Point

Point

LAN

W-WAN

WLAN

USB3.0

PCI-E*

Intel GBE LAN

Dock

SMBALERT#/GPIO11

SMBDATA

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPI O74

Link

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_DATA1

CL_RST1#

SMBCLK

SML0CLK

CL_CLK1

EC_SWI#

E12

SMB_CLK

H14

SMB_DATA

C9

DRAMRST_CNTRL_PCH

A12

SML0_CLK

C8

SML0_DATA

G12

PCH_GPIO74

C13

SML1_CLK

E14

SML1_DATA

M16

CL_CLK

M7

CL_DATA

T11

CL_RST#

P10

1

TP2001 TPAD14-GPTP2001 TPAD14-GP

1

TP2002 TPAD14-GPTP2002 TPAD14-GP

1

TP2003 TPAD14-GPTP2003 TPAD14-GP

NEW CARD

PEG_CLKREQ#_R

XTAL25_IN

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43

F47

H47

K49

3

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_PCLK_PCH_SRC1_P

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

CLK_BUF_REF14

CLK_PCI_FB

XTAL25_IN XTAL25_OUT

XCLK_RCOMP

JTAG_TCK

CLK_48_USB30

CLKOUTFLEX2

DGPU_PRSNT#

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLOCKS

– Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 – Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2 if more than 2 PCI clocks + PCI loopback are routed.

CLKOUT_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

FLEX CLOCKS

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

XTAL25_OUT

XCLK_RCOMP

1 2

DY

RN2016

1 2 3

0R4P2R-PAD

RN2010

2 3 1

0R4P2R-PAD

20101224 A00: Change RN2016,RN2010 to 0402 0 ohm pad.

RN2008 SRN10KJ-5-GPRN2008 SRN10KJ-5-GP

CLK_PCI_FB (18)

R2007

1 2

90D9R2F-1-GP

1

+VCCDIFFCLKN

R2001

1 2

DY

22R2J-2-GP

R2016

1 2

22R2J-2-GP

TP2007 TPAD14-GPTP2007 TPAD14-GP

2

PEG_CLKREQ# (85)

CLK_PCIE_VGA# (83) CLK_PCIE_VGA (83)

CLK_EXP_N (5) CLK_EXP_P (5)

4

PEG_CLKREQ#_R

SMB_DATA

SMB_CLK

20110112 A00: Change C2007,C2008 to 15pF from 12pF base on vendor's report.

EC_SWI# (27)

DRAMRST_CNTRL_PCH (37)

SML1_CLK (27,85)

SML1_DATA (27,85)

R2003

RN

0R2J-2-GP

4

RN

2 3 1

PL 10K FOR Integrated CLOCK GEN mode.

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_REF14

need very close to PCH

JTAG_TCK_VGA (83,85)

CLK_PCH_48M (32,97)

RN2020 SRN10KJ-5-GPRN2020 SRN10KJ-5-GP

1 2 3

RN2021

2 3 1

RN2019 SRN10KJ-5-GPRN2019 SRN10KJ-5-GP

1 2 3

R2008

1 2

10KR2J-3-GP

For RTS5138

For VGA_ 27M

2

3D3V_S5

DY

4

1

12

R2004

R2004 10KR2J-3-GP

10KR2J-3-GP

12

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

RN2007

2 3 1

SRN2K2J-1-GP

2nd = 84.DM601.03F

84.2N702.A3F

2N7002KDW-GP

6

5

Q2001

XTAL25_IN

XTAL25_OUT

3D3V_S0 3D3V_S0

12

R2012

12

R2010

DY

SRN10KJ-5-GP

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

SMB_CLK SMB_DATA

SML0_DATA SML0_CLK

SML1_CLK SML1_DATA

PCIE_CLK_REQ6# PCH_GPIO74

DRAMRST_CNTRL_PCH

4

1

2

34

R2006

R2006 1M1R2J-GP

1M1R2J-GP

2 3

1 2

12

R2013

DY

UMA_DIS# DGPU_PRSNT#

10KR2J-3-GP

12

R2011

10KR2J-3-GP

3D3V_S5

PCH 4/9(PCI-E/SMBUS/CLOCK/CL)

Nirvana 13

4

2 3 1

1 2 3

R2009

1 2

1KR2J-1-GP

PCH_SMBDATA (14,15,65,79,82)

PCH_SMBCLK (14,15,65,79,82)

X2001

XTAL-25MHZ-155-GP

82.30020.D41

2nd = 82.30020.G71

2nd = 82.30020.G71 3rd = 82.30020.G61

3rd = 82.30020.G61

UMA_DISCRETE# UMA: 1 1 DIS :0 1 SG(PX) : 0 0 ATI(Muxless) : 1 0

1 2 3 4 5

SC15P50V2JN-2-GP

41

SC15P50V2JN-2-GP

UMA_DIS# (22)

RN2001

8 7 6

SRN10KJ-6-GP

SRN10KJ-6-GP RN2002

RN2002

8 7 6

SRN10KJ-6-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

3D3V_S5

RN2003

1

SRN2K2J-1-GP

23

RN2004

23

SRN2K2J-1-GP

1

RN2005

RN2005 SRN2K2J-1-GP

SRN2K2J-1-GP

4

RN2006

4

SRN10KJ-5-GP

C2008

12

C2007

12

CLK_PCIE_WWAN_REQ#

PCIE_CLK_LAN_REQ# USB3_PEGB_CLKREQ#

EC_SWI# PCIE_CLK_REQ5# CLK_PCIE_NEW_REQ# PEG_B_CLKRQ#

of

20 104Tuesday, January 18, 2011

A00

5

SSID = PCH

RTC_X1

1 2

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

D D

C2101

SC15P50V2JN-2-GP

C C

X2101

1 4

12

X-32D768KHZ-67-GP

82.30001.A81

2nd = 82.30001.691

3rd = 82.30001.861

HDA_CODEC_SYNC(29) HDA_CODEC_SDOUT(29)

HDA_CODEC_RST#(29) HDA_CODEC_BITCLK(29)

32

RTC_X2

12

C2102

C2102 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

DY

RN2102

1 2 3

SRN33J -5-GP-U

R212233R2J-2-GP

12

R212333R2J-2-GP R212333R2J-2-GP

12

4

HDA_SYNC HDA_SDOUT

HDA_RST# HDA_BITCLK

RTC_AUX_S5

Flash Descriptor Security Overide

+3VS_+1.5VS_HDA_IO

DY

R2102 1KR2J-1-GP

1 2

3D3V_S0

B B

NO REBOOT STRAP

DY

R2106 1KR2J-1-GP

1 2

+3VS_+1.5VS_HDA_IO

This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310

1 2

HDA_SDO UT

HDA_SDOUT

HDA_SPKR

R2103 1KR2J-1-GPR2103 1KR2J-1-GP

Low = Default High = Enable

No Reboot Strap

Low = Default High = No Reboot

HDA_SYNC

PLL ODVR VOLTAGE

2N7002K-2-GP

G

S

Q2101

R2117

84.2N702.J31

100KR2J-1-GP

2ND = 84.2N702.031

Low = 1.8V (Default) High = 1.5V

D

5

R2124

33R2J-2-GP

HDA_SYNCHDA_SYNC_R

12

DY

HDA_SYNC

RUN_ENABLE

A A

1 2

4

RN2101

2 3 1

4

SRN20KJ-1-GP

C2104

SC1U6D3V2KX-GP

20110110 A00: Merge R2115,R2116 to RN2101. 20110113 A00: Swap RN2101 base on swap report.

12

C2103

C2103 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

21

G2101

12

GAP-OPEN

RTC_AUX_S5

INTVRMEN- Integrated SUS

1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs

1M1R2J-GP

R2104

12

1 2

R2105

330KR2F-L-GP

HDA_SPKR(29)

HDA_SDIN0(29)

3

RTC_X1

RTC_X2

RTC_RST#

SRTC_RST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BITCLK

HDA_SYNC

HDA_RST#

Notes: ME_UNLOCK (HDA_SDO) connect to EC. Make sure EC drive this pin "low" all the time.

R2107 1KR2J-1-GPR2107 1KR2J-1-GP

ME_UNLOCK(27)

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

HDA_CODEC_BITCLK

EC2102

1 2

SC4D7P50V2CN-1GP

4

HDA_CODEC_SDOUT

EC2103

1 2

DY

SC4D7P50V2CN-1GP

1 2

SPI_CLK_R(27,60)

SPI_CS0#_R(27,60)

SPI_SI_R(27,60)

SPI_SO_R(27,60)

SPI_CS0#_RHDA_CODEC_SYNC

EC2101

1 2

DY

HDA_SDOUT

CE(49)

TP2101TPAD14-GP TP2101TPAD14-GP

TP2102TPAD14-GP TP2102TPAD14-GP

TP2103TPAD14-GP TP2103TPAD14-GP

TP2104TPAD14-GP TP2104TPAD14-GP

1 2

R2108 33R2J-2-GPR2108 33R2J-2-GP

1 2

R2109 33R2J-2-GPR2109 33R2J-2-GP

1 2

R2110 33R2J-2-GPR2110 33R2J-2-GP

SC4D7P50V2CN-1GP

CE

PCH_JTAG_TCK_BUF

1

PCH_JTAG_TMS

1

PCH_JTAG_TDI

1

PCH_JTAG_TDO

1

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_SI

EC_SMI#(22,27)

3

A20

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34

G34

C34

A34

A36

C36

N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

S_GPIO(22)

FP_DET#(22) PSW_CLR#(22)

PCH1A

Cougar

RTCX1

Point

RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN#/GPIO33

HDA_DOCK_RST#/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

COUGAR-GP-U2-NF

SATA_DET#0 INT_ SERIRQ

EC_SMI#

1 2 3 4 5

4

RTCIHDA

JTAG

SPI

RN2103

8 7 6

SRN10KJ-6-GP

SRN10KJ-6-GP RN2104

RN2104

1 23

SRN10KJ-5-GP

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

3D3V_S0

2

C38 A38 B37 C37

D36

E36 K36

V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

SATA_DET#0

BBS_BIT0

1

LPC_AD [0..3]

LPC_FRAME# (27,65,71)

KB_DET# (69)

INT_ SERIRQ (27 )

SATA_COMP

SATA3_COMP

RBIAS_SATA3

R2112 37D4R2F-GPR2112 37D4R2F-GP

R2113 49D9R2F-GPR2113 49D9R2F-GP

R2114 750R2F-GPR2114 750R2F-GP

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

LPC_AD[0..3] (27,65,71)

SATA_RXN0 (56) SATA_RXP0 (56) SATA_TXN0 (56) SATA_TXP0 (56)

SATA_RXN4 (56) SATA_RXP4 (56) SATA_TXN4 (56) SATA_TXP4 (56)

SATA_RXN5 (57) SATA_RXP5 (57) SATA_TXN5 (57) SATA_TXP5 (57)

1D05V_VTT

1 2

SATA_LED# (68)

BBS_BIT0 (18)

PCH 5/9(SPI/RTC/LPC/SATA/IHDA)

1D05V_VTT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

1

21 104Tuesday, January 18, 2011

HDD1

HDD2

ODD

ESATA

of

A00

5

4

3

2

1

3D3V_S0

R2202

1 2

100KR2J-1-GP

3D3V_S0

RN2203

1

D D

SRN10KJ-5-GP

GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.

3D3V_S0

R2220

1 2

10KR2J-3-GP

PCH_TEMP_ALERT#

MFG_MODE

C C

EC_SCI#

DGPU_HPD_INTR#

DBC_EN

20100104 A00: Merge RN2215,R2216 to RN2201 10k array resistor.

RTC_DET# PCH_GPIO57

B B

PCH_GPIO15

3G_EN

2 3

PCH_GPIO48

SRN10KJ-5-GP

4

RN2202

1 2 3

RN2204

1 2 3

R2214 10KR2J-3-GP

1 2

DY

RN2201

1 2 3

SRN10KJ-5-GP

R2217

1 2

DY

10KR2J-3-GP

1 2

SATA_ODD_PRSNT#

H_A20GATE

H_RCIN#

20100104 A00: Merge RN2201,R2222,R2223 to 10k array resistor. 20110113 A00: Combine PCH_TEMP_ALERT#,MFG_MODE to RN2202. Combine EC_SCI#,DGPU_HPD_INTR# to RN2204

3D3V_S0

4

3D3V_S5

4

R2201

1KR2J-1-GP

R2221

10KR2J-3-GP

Note: For PCH debug with XDP, need to NO STUFF R2218

PSW_CLR#(21)

For thermal sensor detection.

3D3V_S0

12

R2224

R2224 10KR2J-3-GP

10KR2J-3-GP

DY

VRAM_SIZE1

A A

12

DY

5

R2225

R2225 10KR2J-3-GP

10KR2J-3-GP

SSID = PCH

S_GPIO GPIO0

EC_SMI#(21,27)

EC_SCI#(27)

RTC_DET#(60)

R2213 0R0402-PADR2213 0R0402-PAD

DGPU_PWROK(86,92,93)

DBC_EN(49)

3G_EN(82)

TP2203

PSW_CLR#

FP_DET#(21)

21

G2201

TP2206TPAD14-GP TP2206TPAD14-GP

TP2207TPAD14-GP TP2207TPAD14-GP

TP2208TPAD14-GP TP2208TPAD14-GP

TP2209TPAD14-GP TP2209TPAD14-GP

1 2

1

SATA_ODD_PRSNT#(56)

GAP-OPEN

4

S_GPIO(21)

TPAD14-GP

R2218

1 2

100R2J-2-GP

EC_SMI#

DGPU_HPD_INTR#

EC_SCI#

ICC_EN#

RTC_DET#

PCH_GPIO15

DGPU_PWROK

DBC_EN

3G_EN

PCH_GPIO27

1

PLL_ODVR_EN

DMI_OVRVLTG

FDI_OVRVLTG

MFG_MODE

GSENSOR_DET

PCH_GPIO48

PCH_TEMP_ALERT#

PCH_GPIO57

PCH_NCTF_1

PCH_NCTF_2

PCH_NCTF_3

PCH_NCTF_4

PCH_GPIO16

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/G PIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24/MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49

D6

GPIO57

A4

NCTF_VSS#A4

A44

NCTF_VSS#A44

A45

NCTF_VSS#A45

A46

NCTF_VSS#A46

A5

NCTF_VSS#A5

A6

NCTF_VSS#A6

B3

NCTF_VSS#B3

B47

NCTF_VSS#B47

BD1

NCTF_VSS#BD1

BD49

NCTF_VSS#BD49

BE1

NCTF_VSS#BE1

BE49

NCTF_VSS#BE49

BF1

NCTF_VSS#BF1

BF49

NCTF_VSS#BF49

COUGAR-GP-U2-NF

6 OF 10

A20GATE

PECI

RCIN#

INIT3_3V#

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

UMA_DIS#

VRAM_SIZE1

VRAM_SIZE2

TS_VSS

H_PECI_R

PCH_THERMTRIP_R

INIT3_3V#

3D3V_S0

ICC_EN#

R2219 0R0402-PADR2219 0R0402-PAD

Cougar

Cougar Point

Point

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49

BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

PROCPWRGD

GPIO

THRMTRIP#

CPU/MISC

NCTF_VSS#BG2

NCTF_VSS#BG48

NCTF_VSS#BH3

NCTF_VSS#BH47

NCTF_VSS#BJ4

NCTF_VSS#BJ44

NCTF_VSS#BJ45

NCTF_VSS#BJ46

NCTF_VSS#BJ5

NCTF

NCTF_VSS#BJ6

NCTF_VSS#C2

NCTF_VSS#C48

NCTF_VSS#D1

NCTF_VSS#D49

NCTF_VSS#E1

NCTF_VSS#E49

NCTF_VSS#F1

D1,D49,E1,E49,F1,F49

NCTF_VSS#F49

PLL ON DIE VR ENABLE



NOTE:This signal has a weak internal pull-up 20K ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED)

PLL_ODVR_EN

3

1 2

DY

R2212

1KR2J-1-GP

1

1 2

12

R2207

R2207 10KR2J-3-GP

10KR2J-3-GP

DY

FDI_OVRVLTG

12

R2208

R2208 10KR2J-3-GP

10KR2J-3-GP

12

R2209

R2209 10KR2J-3-GP

10KR2J-3-GP

DY

DMI_OVRVLTG

12

R2210

R2210 10KR2J-3-GP

10KR2J-3-GP

R2211

1 2

SATA_ODD_PWRGT (56)

UMA_DIS# (20)

TP2204

TPAD14-GP

TP2205

TPAD14-GP

H_A20GATE (27)

R2203

1 2

DY

H_RCIN# (27)

R2204 390R2J-1-GPR2204 390R2J-1-GP

TP2201

1

0R2J-2-GP

H_CPUPWRGD (5,36)

1 2

TPAD14-GP

TS Signal Disable Guideline: TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4 should not float on the motherboard. They should be tied to GND directly.

FDI TERMINATION VOLTAGE OVERRIDE

GPIO37 (FDI_OVRVLTG)

DMI TERMINATION VOLTAGE OVERRIDE

GPIO36 (DMI_OVRVLTG)

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

Integrated Clock Chip Enable

ICC_EN#

1KR2J-1-GP

GPIO8 has a weak[20K] internal pull up.

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

2

GSENSOR_ADI GSENSOR_ST

R2205 DY 10K

R2206 100K DY

3D3V_S0

12

R2205

10KR2J-3-GP

GSENSOR_DET

12

10KR2J-3-GP

R2206

100KR2J-1-GP

GSENSOR_ST

H_PECI (5,27)

H_THERMTRIP# (5,36)

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

GSENSOR_ADI

HIGH (R2211 DY)- DISABLED [DEFAULT]

LOW (R2211)- ENABLED

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

PCH 6/9(GPIO/CPU)

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

of

22 104Tuesday, January 18, 2011

1

A00

5

4

3

2

1

SSID = PCH

D D

C C

B B

VCCVRM(Internal PLL and VRMs): A.1.5V for Mobile B.1.8 V for Desktop

(1uFx3)

(10uFx1_0603)

(1uF x4)

0.159A(Totally current of VCCVRM)

6A

1D05V_VTT

2.925A(Total current of VCCIO)

12

C2305

0.266A (Totally VCC3_3 current)

0.042A (Totally current of VCCDMI)

1.3A

12

C2301

SC10U6D3V5KX-1GP

12

C2306

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

(0.1uF x1)

1D5V_S0

12

C2302

TP2301TPAD14-GP TP2301TPAD14-GP

12

C2307

TP2302TPAD14-GP TP2302TPAD14-GP

1D05V_VTT

12

C2303

SC1U6D3V2KX-GP

1D05V_VTT

1

12

3D3V_S0

1

SC1U6D3V2KX-GP

(10uF x1)

C2308

SC1U6D3V2KX-GP

12

C2304

SC1U6D3V2KX-GP

VCCAPLLEXP

12

C2309

SC1U6D3V2KX-GP

12

C2310

C2310 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

VCCFDIPLL

+1.05VS_VCC_DMI

PCH1G

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO

BJ22

VCCAPLLEXP

AN16

VCCIO

AN17

VCCIO

AN21

VCCIO

AN26

VCCIO

AN27

VCCIO

AP21

VCCIO

AP23

VCCIO

AP24

VCCIO

AP26

VCCIO

AT24

VCCIO

AN33

VCCIO

AN34

VCCIO

BH29

VCC3_3

AP16

VCCVRM

BG6

VCCAFDIPLL

AP17

VCCIO

AU20

VCCDMI

COUGAR-GP-U2-NF

POWER

Cougar

Cougar Point

Point

VCC CORE

VCCIO

FDI

CRTLVDS

DMI

NAND / SPI HVCMOS

7 OF 10

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS

VCC3_3

VCCVRM

VCCDMI

VCCCLKDMI

VccDFTERM

VCCSPI

0.001A

U48

U47

0.001A

+3VS_VCCA_LVDS

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

0.16A

AT16

0.042A

+1.05VS_VCC_DMI

AT20

AB36

0.02A

+1.05VS_VCC_DMI_CCI

AG16

AG17

AJ16

AJ17

V1

20101228 A00: 0402 0R pad: R2301.

(0.1uF/0.01uF x1) (10uF x1_0603)

+VCCA_DAC_1_2

12

C2313

0.06A

+1.8VS_VCCTX_LVDS

0.266A

12

0.19A

12

C2322

C2322 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

0.02A

12

C2314

SCD01U16V2KX-3GP

12

C2316

(0.1uFx1)

C2319

C2319 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

VCCVRM

R2306

0R0402-PAD

0.02A

0R0402-PAD

R2307

0R0402-PAD

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2321

C2321 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

3D3V_DAC_S0

12

R2301

R2301 0R0402-PAD

0R0402-PAD

12

C2315

0.001A

SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

0.06A

12

C2317

SCD01U16V2KX-3GP

R2308

0R0402-PAD

12

SCD01U16V2KX-3GP

3D3V_S0

1D05V_VTT

(1uFx1) (10uFx1)

SCD01U16V2KX-3GP

0.19A

0.02A

(1uFx1)

3D3V_S0

L2301

1 2

DY

HCB1608KF-181-GP

68.00214.051

2nd = 68.00206.041

3rd = 68.00335.081

R2304

1 2

0R0603-PAD

R2305

1 2

0R0805-PAD

12

C2318

12

0R0805-PAD

(0.01uF x2) (22uF x1)

SC10U6D3V5KX-1GP

20101224 A00: 0402 0R pad: R2301,R2306,R2307,R2308.

1D5V_S0

(1uF x1)

1D8V_S0

(0.1uFx1)

3D3V_S5

3D3V_S0

1D8V_S0

3.3V CRT LDO

5V_S5 3D3V_DAC_S0

3D3V_S0

U2301

1

VIN

2

A A

5

12

C2311

SC1U10V2KX-1GP

4

GND EN3NC#4

G9091-330T11U-GP

74.09091.J3F

2nd = 74.09198.G7F

3rd = 74.07716.A7F

VOUT

5

4

Current Limit=360mA

12

C2312

SC1U6D3V2KX-GP

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

PCH 7/9(POWER1)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

A00

of

23 104Tuesday, January 04, 2011

1

A00

5

SSID = PCH

0.002A

3D3V_S0

(10uFx1)

D D

C C

1D05V_VTT

B B

1D05V_VTT

A A

L2401

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

L2402

L2403

R2404

12

0R0402-PAD

R2405

12

0R0402-PAD

0.08A

C2443

DY

0.08A

C2444

DY

5

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

20101224 A00: 0402 0R pad: R2404,R2405.

+1.05VS_VCCA_A_DPL

12

+1.05VS_VCCA_B_DPL

12

+VCCDIFFCLK

12

SC1U6D3V2KX-GP

+V1.05S_SSCVCC

12

SC1U6D3V2KX-GP

(1uFx1)

+V3.3S_VCC_CLKF33

C2401

12

(22uFx2_0603) (1uFx3)

(1uFx1) (220uFx1)

12

SC10U6D3V3MX-GP

12

SC10U6D3V3MX-GP

C2412

C2413

12

C2402

C2402 SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC10U6D3V5KX-1GP

1D05V_VTT

C2409

C2409 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

(1uFx1) (220uFx1)

C2410

C2410 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

1D05V_VTT

(1uFx1)

3D3V_S5

(0.1uFx1)

C2403

12

SC10U6D3V5KX-1GP

12

C2411

R2406

1 2

0R0603-PAD

SC1U6D3V2KX-GP

(0.1uFx1)

(1uFx1)

1D05V_VTT

0.001A

(0.1uFx2) (4.7uFx1_0603)

SC4D7U6D3V3KX-GP

RTC_AUX_S5

6uA

(0.1uFx2) (1uFx1)

1.01A (Total current of VCCASW)

C2404

SC10U6D3V5KX-1GP

+VCCRTCEXT

(0.1uFx1)

+VCCDIFFCLKN

C2414

C2417

4

1

TP2405TPAD14-GP TP2405TPAD14-GP

1

(10uFx1)

1

12

VCCACLK

+VCCPDSW

DCPSUSBYP

1

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

+VCCSUS1

12

C2407

C2408

SC1U6D3V2KX-GP

TP2401TPAD14-GP TP2401TPAD14-GP

R2403

1 2

0R0603-PAD

TP2404TPAD14-GP TP2404TPAD14-GP

1D05V_VTT

TP2402TPAD14-GP TP2402TPAD14-GP

12

C2406

SC1U6D3V2KX-GP

0.16A (Totally current of VCCVRM

1D5V_S0

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

+VCCDIFFCLK

0.055A

12

(1uFx1)

0.095A

SCD1U10V2KX-5GP

4

+V1.05S_SSCVCC

C2415

+VCCSST

12

TP2406TPAD14-GP TP2406TPAD14-GP

12

C2418

SCD1U10V2KX-5GP

12

C2421

SCD1U10V2KX-5GP

(1uFx1)

1

12

C2422

DCPSUS

SCD1U10V2KX-5GP

PCH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3

BH23

VCCAPLLDMI2

AL29

VCCIO

AL24

DCPSUS

AA19

VCCASW

AA21

VCCASW

AA24

VCCASW

AA26

VCCASW

AA27

VCCASW

AA29

VCCASW

AA31

VCCASW

AC26

VCCASW

AC27

VCCASW

AC29

VCCASW

AC31

VCCASW

AD29

VCCASW

AD31

VCCASW

W21

VCCASW

W23

VCCASW

W24

VCCASW

W26

VCCASW

W29

VCCASW

W31

VCCASW

W33

VCCASW

N16

DCPRTC

Y49

VCCVRM

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO

AF33

VCCDIFFCLKN

AF34

VCCDIFFCLKN

AG34

VCCDIFFCLKN

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS

V19

DCPSUS

BJ8

V_PROC_IO

A22

VCCRTC

COUGAR-GP-U2-NF

3

10 OF 10

POWER

Cougar

Cougar Point

Point

Clock and Miscellaneous

PCI/GPIO/LPCMISC

SATA USB

CPURTC

HDA

3

10 OF 10

VCCIO

VCCSUS3_3

VCCIO

V5REF_SUS

DCPSUS

VCCSUS3_3

V5REF

VCCSUS3_3

VCC3_3

VCCIO

VCCAPLLSATA

VCCVRM

VCCIO

VCCASW

VCCSUSHDA

N26

P26

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

2

12

(1uFx1)

C2423

C2423 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

0.097A (Totally current of VCCSUS3_3)

(0.1uFx1)

12

C2424

C2424 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

(0.1uFx1)

C2425

C2425 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

TP2403 TPAD14-GPTP2403 TPAD14-GP

1

C2437

C2437 SC1U10V2KX-1GP

SC1U10V2KX-1GP

0.001A

(1uFx1)

12

R2411

1 2

DY

C2434

0R3J-0-U -GP

DY

(1uFx1)

SC10U6D3V5KX-1GP

1D05V_VTT

+5VA_PCH_VCC5REFSUS

+VCCA_USBSUS

+5VS_PCH_VCC5REF

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

+V1.05S_VCCAPLL_SATA3

1D5V_S0

1D05V_VTT

SC1U6D3V2KX-GP

3D3V_S5

C2428

C2430

C2429

C2432

C2435

12

DY

12

+3VS_+1.5VS_HDA_IO

0.01A

(0.1uFx1)

12

C2433

SCD1U10V2KX-5GP

C2433

2

1D05V_VTT

3D3V_S5

2nd = 83.R2004.B8F

3D3V_S5

0.001A

2nd = 83.R2004.B8F

3D3V_S5

3D3V_S0

(0.1uFx2)

C2431

C2431 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

(0.1uFx1)

1D05V_VTT

(1uFx1)

1D05V_VTT

(10uFx1)

1D05V_VTT

1

3D3V_S5

21

D2401

D2401 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

R2408

1 2

10R2J-2-GP

12

C2426

C2426 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

21

D2402

D2402 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

1 2

10R2J-2-GP

12

C2427

C2427 SC1U10V2KX-1GP

SC1U10V2KX-1GP

+3VS_+1.5VS_HDA_IO

R2409

1 2

0R0603-PAD

Title

PCH 8/9(POWER2)

Size Document Number Rev

Date: Sheet of

Date: Sheet

PCH 8/9(POWER2)

Nirvana 13

5V_S5

(0.1uFx1)

5V_S0

R2407

(1uFx1)

3D3V_S5

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

24 104Tuesday, January 04, 2011

1

A00

5

4

3

2

1

SSID = PCHSSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS

AA17

VSS

AA2

VSS

AA3

VSS

AA33

VSS

AA34

VSS

AB11

VSS

AB14

VSS

AB39

VSS

AB4

VSS

AB43

VSS

AB5

VSS

AB7

VSS

AC19

VSS

AC2

VSS

AC21

VSS

AC24

VSS

AC33

VSS

AC34

VSS

AC48

VSS

AD10

VSS

AD11

VSS

AD12

VSS

AD13

VSS

AD19

VSS

AD24

VSS

AD26

VSS

AD27

VSS

AD33

VSS

AD34

VSS

AD36

VSS

AD37

VSS

AD38

VSS

AD39

VSS

AD4

VSS

AD40

VSS

AD42

VSS

AD43

VSS

AD45

VSS

AD46

VSS

AD8

VSS

AE2

VSS

AE3

VSS

AF10

VSS

AF12

VSS

AD14

VSS

AD16

VSS

AF16

VSS

AF19

VSS

AF24

VSS

AF26

VSS

AF27

VSS

AF29

VSS

AF31

VSS

AF38

VSS

AF4

VSS

AF42

VSS

AF46

VSS

AF5

VSS

AF7

VSS

AF8

VSS

AG19

VSS

AG2

VSS

AG31

VSS

AG48

VSS

AH11

VSS

AH3

VSS

AH36

VSS

AH39

VSS

AH40

VSS

AH42

VSS

AH46

VSS

AH7

VSS

AJ19

VSS

AJ21

VSS

AJ24

VSS

AJ33

VSS

AJ34

VSS

AK12

VSS

AK3

VSS

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

8 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS

AY42

VSS

AY46

VSS

AY8

VSS

B11

VSS

B15

VSS

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

F45

VSS

BB12

VSS

BB16

VSS

BB20

VSS

BB22

VSS

BB24

VSS

BB28

VSS

BB30

VSS

BB38

VSS

BB4

VSS

BB46

VSS

BC14

VSS

BC18

VSS

BC2

VSS

BC22

VSS

BC26

VSS

BC32

VSS

BC34

VSS

BC36

VSS

BC40

VSS

BC42

VSS

BC48

VSS

BD46

VSS

BD5

VSS

BE22

VSS

BE26

VSS

BE40

VSS

BF10

VSS

BF12

VSS

BF16

VSS

BF20

VSS

BF22

VSS

BF24

VSS

BF26

VSS

BF28

VSS

BD3

VSS

BF30

VSS

BF38

VSS

BF40

VSS

BF8

VSS

BG17

VSS

BG21

VSS

BG33

VSS

BG44

VSS

BG8

VSS

BH11

VSS

BH15

VSS

BH17

VSS

BH19

VSS

H10

VSS

BH27

VSS

BH31

VSS

BH33

VSS

BH35

VSS

BH39

VSS

BH43

VSS

BH7

VSS

D3

VSS

D12

VSS

D16

VSS

D18

VSS

D22

VSS

D24

VSS

D26

VSS

D30

VSS

D32

VSS

D34

VSS

D38

VSS

D42

VSS

D8

VSS

E18

VSS

E26

VSS

G18

VSS

G20

VSS

G26

VSS

G28

VSS

G36

VSS

G48

VSS

H12

VSS

H18

VSS

H22

VSS

H24

VSS

H26

VSS

H30

VSS

H32

VSS

H34

VSS

F3

VSS

COUGAR-GP-U2-NF

3

Cougar

Cougar Point

Point

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

PCH 9/9(VSS)

Nirvana 13

1

A00

of

25 104Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

26 104Tuesday, January 04, 2011

A00

5

SSID = KBC

3D3V_AUX_KBC

R2771

R2771 2D2R3-1-U-GP

2D2R3-1-U-GP

1 2

12

D D

20101228 A00: VGA_THRM change to USB_PWR_EN. 20101229 A00: Rename USB_PWR_EN to USB3_PWR_ON.

C C

AFTP2701AFTP2701 AFTP2702AFTP2702 AFTP2703AFTP2703

C2701

R2702

1 2

0R0603-PAD

12

C2704

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

USB_PWR_EN#

1

AC_PRESENT

1

E51_TxD

1

C2705

SCD1U10V2KX-5GP

EC_AGND

12

C2706

AC_PRESENT(19)

12

C2707

SCD1U10V2KX-5GP

AD_IA(40)

C2714 SCD1U10V2KX-5GPC2714 SCD1U10V2KX-5GP

1 2

PSID_EC(38)

CPU_THRM(28)

FAN1_DAC(28)

LCD_TST(49)

SUS_PWR_ACK(19)

USBCHARGER_CB0(57)

USB3_PWR_ON(62,82) SYS_THRM(28)

BATT_WHITE_LED#(68)

CAP_LED(69)

S5_ENABLE(36)

MEDIA_BTN3#(82)

BAT_IN#(39)

LID_CLOSE#(70)

RSMRST#_KBC(19)

PM_SLP_S4#(19,46)

ME_UNLOCK(21)

RCID(38)

WIFI_RF_EN(65) BLUETOOTH_EN(63,65) S0_PWR_GOOD(19,36)

TP_LOCK_LED#(68)

USB_PWR_EN#(61)

IMVP_PWRGD(36,42)

C2708

SCD1U10V2KX-5GP

12

EC_AGND

MEDIA_BTN2#

KBC_VCORF

12

C2712

C2712 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

12

C2710

C2709

SC2D2U10V3KX-1GP

PCB_VER_AD

USB3_PWR_ON

PSL_IN2 MODEL_ID_DET

ECSMI#_KBC

PSL_IN1 PSL_OUT EC_GPIO72

SCD1U10V2KX-5GP

3D3V_AUX_KBC_VCC

U2701A

104

VREF

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

79

GPIO2

95

GPIO3/AD6

96

GPIO4/AD5

108

GPIO5/AD4

93

PSL_IN2#_GPIO6

94

GPIO7/AD7

114

GPIO16

6

GPIO24

109

GPIO30

14

GPIO34/CIRRXL

15

GPIO36

80

GPIO41

17

GPIO42/TCK

20

GPIO43/TMS

21

GPIO44/TDI

23

GPIO46/CIRRXM/TRST#

26

GPIO51

73

PSL_IN1_GPIO70

74

PSL_OUT_GPIO71

75

VBKUP

82

GPIO75

83

GPO76/SHBM

84

GPIO77

91

GPIO81

110

GPO82/IOX_LDSH/TEST#

112

GPIO84/IOX_SCLK/XORTR#

107

GPIO97

44

VCORF

NPCE795PA0DX-GP-U

VBAT

VCC19VCC46VCC76VCC88VCC

GND18GND45GND78GND89GND

115

GND

5

116

ROSA Multi GPIO setting

R2711 0R0402-PADR2711 0R0402-PAD

C2719 SCD1U10V2KX-5GP

CPU_THRM

USB3_PWR_ON

SYS_THRM

L_BKLT_EN(17)

B B

KBC_PWRBTN#(68)

A A

12

DY

C2720 SCD1U10V2KX-5GP

12

DY

C2721 SCD1U10V2KX-5GP

12

DY

EC_AGND

PANEL_BLEN

1 2

R2761 0R0402-PADR2761 0R0402-PAD

BAT54CPT-GP

1

3

2ND = 83.00054.Q81

2

D2702

2ND = 83.00054.Q81

83.R2003.E81

AC_IN#_KBC

5

PSL_IN2

83.R2003.E81

KBC_ON#

D2703

2

10mW

1

BAT54CPT-GP

R2704

1 2

3

EC_GPIO72

330KR2J-L1-GP

KBC_ON#_R

AC_IN# (40)

EC_SWI#(20)

EC_SCI#( 22)

RN2706

4

SRN10KJ-5-GP

EC_SWI#(20)

EC_SCI#(22)

3D3V_AUX_S5

1

KBC_ON#_GATE

23

SCD1U10V2KX-5GP

D2701

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

D2704

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

20101224 A00: 0402 0R pad: R2758,R2759.

C2722

1 2

SCD1U10V2KX-5GP

12

C2713

DY

2N7002K-2-GP

G

S

Q2706

84.2N702.J31

2ND = 84.2N702.031

G

102

AVCC

GPIO11/CLKRUN#

GPIO10/LPCPD#

GPIO67/PWUREQ#

KBRST#/GPIO86

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO27/PSDAT2

GPIO35/PSDAT1

F_SDIO/F_SDIO0

1 2

ECSWI#_KBC

3

ECSCI#_KBC

3

ECSWI#_KBC

R2758

12

0R0402-PAD

ECSCI#_KBC

R2759

12

0R0402-PAD

3D3V_AUX_S5

S

G

D

3D3V_AUX_KBC

S5_ENABLE

D

4

SCD1U10V2KX-5GP

4

1 OF 2

VDD

LRESET#

LCLK

LFRAME#

LAD3 LAD2 LAD1 LAD0

SERIRQ

GPIO65/SMI#

ECSCI#/GPIO54

GPIO85/GA20

GPIO26/PSCLK2

GPIO37/PSCLK1

GPIO17/SCL1

GPIO22/SDA1

GPIO73/SCL2

GPIO74/SDA2

GPIO23/SCL3

GPIO31/SDA3

GPIO47/SCL4

GPIO53/SDA4

F_CS0#

F_SCK

F_SDI/F_SDIO1

AGND

103

EC_AGND

Q2703

Q2703 DMP2130L-7-GP

DMP2130L-7-GP

2ND = 84.03413.A31

84.02130.031

4

3

3D3V_AUX_KBC

20101224 A00 Modify:

3D3V_S0

12

C2703

C2702

7 2 3 1 128 127 126 125 8 9 29 124 123 121 122

27 25 11 10 71 72

70 69 67 68 119 120 24 28

90 92 86 87

C2703

DY

SC2D2U10V3KX-1GP

C2711

DY

1 2

SC220P50V2KX-3GP

PLT_RST#_EC

R2735

12

0R0402-PAD

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

PANEL_BLEN

ECSCI#_KBC

ECSWI#_KBC

AD_IA_HW2

MEDIA_BTN1#

EC_ENABLE#_1

PROCHOT_EC

EC_SPI_CS#_C EC_SPI_CLK_C EC_SPI_DI_C EC_SPI_DO_C

NOTE: Locate resistors R2719 and R2722 close to the NPCE791L.

NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connect ion.

CLK_PCI_KBC (18)

PM_LAN_ENABLE (82)

LCD_TST_EN (49)

R2737 0R0402-PADR2737 0R0402-PAD R2722 33R2J-2-GPR2722 33R2J-2-GP

EC_GPIO47 High Active

PROCHOT_EC

12

R2732

2ND = 84.2N702.031

100KR2J-1-GP

Change R2724 to 47K from 33K.

PCB_VER_AD

SCD1U10V2KX-5GP

PLT_RST# (5,18,65,71,82,83)

LPC_FRAME# (21,65,71)

LPC_AD[0..3] (21,65,71)

INT_SERIRQ (21) PM_CLKRUN# (19)

HDMI_ IN# (5 1)

H_A20GATE (22) H_RCIN# (22)

BLON_OUT (49)

AD_IA_HW2 (40)

PCH_WAKE# ( 19)

TPDATA (69) TPCLK (69)

<------ TP

BAT_SCL (39,40) BAT_SDA (39,40) SML1_CLK (20,85) SML1_DATA (20,85)

33R2J-2-GPR2736 33R 2J-2-GPR2736

12

33R2J-2-GPR2719 33R 2J-2-GPR2719

12 12 12

Q2702

G

S

2N7002K-2-GP

84.2N702.J31

12

C2717

1 2

EC_AGND

<------ BATTERY / CHARGER <------PCH / eDP

20101224 A00: 0402 0R pad: R2737,R2735.

SPI_CS0#_R (21,60) SPI_CLK_R (21,60) SPI_SO_R (21,60)

SPI_SI_R (21,60)

12

H_PROCHOT#_EC

D

PSL SOLUTION

R2756

EC_GPIO72

1 2

0R0402-PAD

AC_OK

DY

R2767

1 2

G

DY

S

2N7002K-2-GP

84.2N702.J31

1 2

DY

AC_OK(40)

PSL_OUT

2ND = 84.2N702.031

NOTES: Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD.

R2768

0R2J-2-GP

0R2J-2-GP Q2705

Q2705

D

KBC_ON#_R

PSL_IN1

DY

12

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

R2724

R2724 47KR2F-GP

47KR2F-GP

R2726

R2726 100KR2F-L1-GP

100KR2F-L1-GP

X01

X02

A00

Reserved

Reserved 1.65V

Reserved 100.0K 215.0K 1.048V

NOTES: The NPCE795P GPIO/PWM outputs that are connected to LEDs have high drive buffers (20mA) and can be connected directly to the LEDs.

FAN_TACH1(28)

PM_PWRBTN#(19)

PCIE_WAKE#(82) PM_SLP_S3#(19,36,37,46,47)

CHG_AMBER_LED#(68)

KBC_BEEP(29)

MEDIA_LED1#( 82)

KB_BL_CTRL(69)

AD_IA_HW(40) MEDIA_LED3#( 82) MEDIA_LED2#( 82)

PWRLED#(68)

E51_RxD(65)

AMP_MUTE#(29)

PCH_SUSCLK_KBC(19)

H_PECI(5,22)

1D05V_VTT

EC_SPI_DI_C

R2773

R2773 100KR2J-1-GP

100KR2J-1-GP

1 2

R2733 0R0402-PADR2733 0R0402-PAD

H_PROCHOT # (5,40,42)

Need very close to EC

PURE_HW_SHUTDOWN#(28,36,85)

10mW SOLUTION

R2769

R2769 100KR2J-1-GP

100KR2J-1-GP

3D3V_AUX_KBC

3D3V_AUX_KBCRTC_AUX_S5

R2734

1 2

DY

R2763

AC_IN#_KBC

1 2

0R0402-PAD

EC_ENABLE#_1

2ND = 84.2N702.031

20101228 A00: Change R2756,R2763,R2766 to 0R short pad.

3

G

S

2N7002K-2-GP

84.2N702.J31

R2766

1 2

0R0402-PAD

VBACKUP

EC_GPIO72

0R2J-2-GP

PSL_IN1

Q2704

10mW

PSL_IN1

PSL_OUT

KBC_ON#

D

KBC_ON#_RKBC_ON#

100.0KX00

100.0K

ECRST#

E51_TxD(65)

R2721 43R 2J-GPR 2721 43R2J-GP

1 2 1 2

R2720 0R0402-PADR2720 0R0402-PAD

3D3V_AUX_S5

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.204V

U2701B

31

GPIO56/TA1

117

GPIO20/TA2

63

GPIO14/TB1

64

GPIO01/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

81

GPIO66/G_PWM

66

GPIO33/H_PWM

22

GPIO45/E_PWM

16

GPIO40/F_PWM

85

VCC_POR#

113

GPIO87/CIRRXM/SIN_CR

111

GPIO83/SOUT_CR/TRIST#

30

GPIO55/CLKOUT/IOX_DIN_DIO

77

GPIO00/EXTCLK

13

PECI

12

VTT

NPCE795PA0DX-GP- U

E

B

Q2701

C

2nd = 84.03906.F11

KBSOUT15/GPIO61/XOR_OUT

12

MMBT3906-4-GP

DY

84.T3906.A11

C2716

12

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

143.0K100.0K 1.358VReserved

174.0KReserved 100.0K

PECI

EC_VTT

12

SCD1U16V2KX-3GP

R2705

R2705 10KR2J-3-GP

10KR2J-3-GP

EC GPIO standard PH/PL

BAT_SCL BAT_SDA

BAT_IN# AC_IN#_KBC

S5_ENABLE ECRST#

EC_ENABLE#_1

FAN_TACH1(28)

FAN_TACH1

E51_RxD

BLUETOOTH_EN

2

C2718

KBSOUT9/SDP_VIS# KBSOUT10/P80_CLK KBSOUT11/P80_DAT

ECRST#

C2715

RN2701

4

SRN4K7J-8-GP

RN2703

4

SRN100KJ-6-GP

RN2705

8 7 6

SRN10KJ-6-GP

1 2

R2712 10KR2J-3-GPR2712 10KR2J-3-GP

DY

1 2

R2708 10KR2J-3-GP

DY

1 2

R2709 10KR2J-3-GP

2

3D3V_AUX_KBC

MODEL_ID_DET

1 2

EC_AGND

SCD1U10V2KX-5GP

2 OF 2

KBSOUT0/JENK#

KBSOUT1/TCK KBSOUT2/TMS

KBSOUT3/TDI

KBSOUT4/JEN0#

KBSOUT5/TDO

KBSOUT6/RDY#

KBSOUT7 KBSOUT8

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

GPIO60/KBSOUT16 GPIO57/KBSOUT17

KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7

SC1U6D3V2KX-GP

23 1

1 23

1 2 3 45

12

R2710

R2710 174KR2F-GP

174KR2F-GP

12

R2739

R2739 100KR2F-L1-GP

100KR2F-L1-GP

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

54 55 56 57 58 59 60 61

3D3V_AUX_KBC

3D3V_S0

1

MODEL_ID_DET(GPIO07)

DQ15_ATI

DQ15_NVIDIA

DN15_UMA

DN15_ATI

Reserved

DN13_UMA

DN13_ATI

DQ15_Ventura 100.0K 215.0K 1.048V

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

100.0KDQ15_UMA 3.0V

100.0K

10.0K(64.10025.6DL)

20.0K(64.20025.6DL)

33.0K

47.0K(64.47025.6DL)

64.9K(64.64925.6DL)

76.8K

100.0K

143.0K100.0K 1.358V

174.0K100.0K

Notes: The total SPI interface signal between EC and PCH can’t not exceed 6500mil. The mismatch between SPI signal must be within 500mil

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16

USB_DET#

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

KCOL[0..16] (69)

KROW[0..7] ( 69)

D2705

EC_SMI#(21,22)

EC_SMI# ECSMI#_KBC

1

2

BAS16-6-GP

2ND = 83.00016.F11

20101224 A00: 0402 0R pad: R2760.

R2760

12

0R0402-PAD

3

DY

83.00016.K11

ECSMI#_KBC

MEDIA BUTTON CONTROL

USB_DET#

MEDIA_BTN1#

MEDIA_BTN2#

MEDIA_BTN3#

PCIE_WAKE#

INSTANT_ON#(82)

USBDET_CON#(57)

DATA_RECOVERY#(82)

Title

KBC Nuvoton NPCE785P

Size Document Number Rev

A2

Date: Sheet

INSTANT_ON#

USBDET_CON#

DATA_RECOVERY#

Nirvana 13

1 2

R2772 100KR2J-1-GPR2772 100KR2J-1-GP

1 2

R2770 100KR2J-1-GPR2770 100KR2J-1-GP

1 2

R2774 100KR2J-1-GPR2774 100KR2J-1-GP

1 2

R2775 100KR2J-1-GPR2775 100KR2J-1-GP

1 2

R2776 100KR2J-1-GPR2776 100KR2J-1-GP

BAT54CPT-GP

1

3

2ND = 83.00054.Q81

2

D2706

BAT54CPT-GP

1

3

2ND = 83.00054.Q81

2

D2707

BAT54CPT-GP

1

3

2ND = 83.00054.Q81

2

D2708

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

27 104T uesday, January 18, 2011

1

27 104T uesday, January 18, 2011

3D3V_AUX_KBC

MEDIA_BTN1#

83.R2003.E81

KBC_ON#_R

USB_DET#

83.R2003.E81

KBC_ON#_R

MEDIA_BTN2#

83.R2003.E81

KBC_ON#_R

of

2.75V100.0K

2.48V100.0K

2.24V

2.0V

1.87V

1.65V

1.204V

A00

5

4

3

2

1

SSID = Thermal

D D

C C

B B

3D3V_DAC_S0

12

DY

R2808

R2808 NTC-100K-8-GP

NTC-100K-8-GP

12

C2802

SCD1U10V2KX-5GP

P2800_DXP

12

C2806

C2806 SC470P50V3JN-2GP

SC470P50V3JN-2GP

P2800_DXN

SCD1U10V2KX-5GP

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

2ND = 84.03904.P11

3

84.03904.L06

Q2801

1

PMBS3904-1-GP

2

2.System Sensor, Put on palm rest

Thermal sensor P2800

3D3V_DAC_S0

12

R2803

R2803 107KR2F-GP

P2800A1

R2804

R2804 226KR2F-GP

226KR2F-GP

P2800A1

12

C2807

C2807 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

THERM_SYS_SHDN#_OTZ ADJ

107KR2F-GP

ADJ

12

87.1 Degree

12

C2805

P2800A1

SCD1U10V2KX-5GP

P2800EA1-GP

5

VCC

6 7 8

1.H/W T8 Shutdown

TDR

DXP

TDL

DXN

GND

OTZ

ADJ

U2801

74.02800.A71

4 3 2 1

20101224 A00 Modify: If stuff P2800EA1 then must stuff R2803,R2804 C2805 but if stuff P28003B0 should be un-stuff.

SYS_THRM (27) CPU_THRM (27)

PURE_HW_SHUTDOW N#(27,36,85)

FAN_TACH1(27)

AFTP2801AFTP2801

AFTP2802AFTP2802

1 2

R2807 0R0402-PADR2807 0R0402-PAD

FAN_TACH1_C

1

FAN_VCC

1

THERM_SYS_SHDN#_OTZ

12

C2811

DY

RSET = 0.0012T 2 — 0.9308T + 96.147 T=87 ; RSET=24.25ohm

THERM_SYS_SHDN#

R2806

24K3R2F-1-GP

1 2

DY

1 2

R2812 0R2J-2-GP

DY

Fan controller

R2802 0R2J-2-GP

1 2

DY

5V_S0

FAN1_DAC(27)

For linear FAN

SCD1U10V2KX-5GP

1 2

U2805_3

FAN_VCC

*Layout* 10 mil

FAN_TACH1_C

*Layout* 15 mil

12

C2808

DY

SCD1U16V2KX-3GP

R2805

1 2

0R2J-2-GP

Q2802

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

U2805

SET GND OUT#3HYST

G709T1UF-GP

74.00709.A7F

DY

VCC

U2802

FON#

1

FON#

2 3 4

21

D2802

12

D2802

C2809

CH551H-30PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

SC4D7U6D3V3KX-GP

THERM_SYS_SHDN#

S

G

20101228 A00 Modify: Un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805 at X-Build.

U2805_5U2805_1

5

12

C2817

4

DY

U2805_4

R2811

DY

0R2J-2-GP

GND

VIN

GND

VO

GND

VSET

GND

G991P11U-GP

74.00991.031

2nd = 74.02793.A31

3rd = 74.05606.A71

FAN_VCC

12

C2810

DY

3D3V_S0

12

3D3V_S0

R2801

DY

150R2F-1-GP

SCD1U10V2KX-5GP

R2810

DY

0R2J-2-GP

12

8 7 6 5

3 2

1

SC2200P50V2KX-2GP

R2809

R2809 100KR2J-1-GP

100KR2J-1-GP

3D3V_DAC_S0

12

3D3V_DAC_S0

12

5V_S0

12

C2804

C2803

SC4D7U6D3V3KX-GP

FAN1

5

4

ACES-CON3-11-GP

20.F0772.003

2nd = 20.F1841.003

SCD1U10V2KX-5GP

Hysterisis is 10°C for HYST = VCC, 2°C for HYST = GND.

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

THERMAL P2800 / Fan control

Size Document Number Rev

A3

Date: Sheet

5

4

3

2

Date: Sheet

THERMAL P2800 / Fan control

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

A00

28 104Tuesday, January 18, 2011

of

1

of

A00

5

SSID = AUDIO

D D

3D3V_S0

Close to codec

12

C2902

C2904

C2903

SC1U6D3V2KX-GP

C C

1 2

SCD1U10V2KX-5GP

1 2

SCD1U10V2KX-5GP

AUD_DMIC_CLK(49,97)

AUD_DMIC_IN0(49,97) HDA_CODEC_SDOUT(21) HDA_CODEC_BITCLK(21)

HDA_SDIN0(21)

HDA_CODEC_SYNC(21) HDA_CODEC_RST#(21)

4

AMP_MUTE#(27)

AMP_MUTE#

Close to codec

AUD_DVDDCORE

12

C2901

C2901 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1 2 3 4 5 6 7 8 9

10

R2901

1 2

33R2J-2-GP

AUD_DMIC_CLK AUD_DMIC_IN0 HDA_CODEC_SDOUT HDA_CODEC_BITCLK HDA_CODEC_SDIN0

HDA_CODEC_SYNC HDA_CODEC_RST# AUD_PC_BEEP

2010/06/30 Change to 92HD87 (71.92H87.A03)

U2901

DVDD_LV DMIC_CLK/GPIO_1 DMIC_0/GPIO_2 SDATA_OUT BITCLK SDATA_IN DVDD SYNC RESET# PCBEEP

3

AUD_SPK_LAUD_SPK_L+

+AVDD+PVDD

AUD_VREG

35

41

THERMAL_PAD

92HD87B1A5NDGXTBX8-GP

34

36

40

37

38

33

39

PVSS

EAPD

PVDD

71.92H87.A03

SENSE_A11SENSE_B12PORTF_L13PORTF_R14PORTC_L15PORTC_R16VREFFILT17CAP218VREFOUT_A19VREFOUT_C

PVDD

PORTD_-L

PORTD_-R

PORTD_+L

PORTD_+R

31

32

AVDD2

20

VREG/+2_5V

CAP+

CAP-

AVSS2

PORTB_R

PORTB_L

AVSS2

PORTA_R

PORTA_L

AVDD1

V-

AUD_SPK_L- (58)

AUD_SPK_L+ (58)

30 29 28 27 26 25 24 23 22 21

2

R2902

1 2

0R0603-PAD

C2906

SC1U10V2KX-1GP

1 2 1 2

12 12

0R0603-PAD

12

C2914

C2914 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

C2922 SC1U10V3KX-3GPC2922 SC1U10V3KX-3GP C2921 SC1U10V3KX-3GPC2921 SC1U10V3KX-3GP

C2905

1 2

PUMP_CAPP

PUMP_CAPN AUD_V_B

AUD_HP1_JACK_R AUD_HP1_JACK_L

AUD_EXT_MIC_R AUD_EXT_MIC_L

+AVDD

SCD1U10V2KX-5GP

1 2

R2906 60D4R2F-GPR2906 60D4R2F-GP R2905 60D4R2F-GPR2905 60D4R2F-GP

Put C2921 and C2922 close to codec

5V_S0 +PVDD

12

C2908

1 2

SCD1U10V2KX-5GP

AUD_HP1_JACK_R2 (58)

AUD_HP1_JACK_L2 (58)

MIC_IN_R (58) MIC_IN_L (58)

C2909

SC1U10V2KX-1GP

C2910

SC10U6D3V5MX-3GP

1

1 2

R2903

R2903 0R0603-PAD

0R0603-PAD

R2904

R2904 0R0603-PAD

0R0603-PAD

5V_S0

3D3V_S0

AUD_SENSE_A

AUD_SENSE_B

AUD_PC_BEEP

AUD_CAP2

AUD_VREFFLT

12

R2908

R2908 10KR2J-3-GP

10KR2J-3-GP

AMP_MUTE#

AUD_VREFOUT_B

HDA_CODEC_BITCLK_1

12

C2907

C2923

SC1U10V2KX-1GP

B B

C2907

DY

SC4D7P50V2CN-1GP

R2907

1 2

DY

47R2J-2-GP

HDA_CODEC_BITCLK

AUD_PC_BEEP Trace width>15 mils

AUD_PC_BEEP

C2912 SCD1U10V2KX-5GPC2912 SCD1U10V2KX-5GP

C2913 SCD1U10V2KX-5GPC2913 SCD1U10V2KX-5GP

G2901

G2901 DUMMY-C2

DUMMY-C2

1 2

12

SB_SPKR_R

KBC_BEEP_R

AUD_VREFOUT_B

120KR2J-L-GP

R2909

1 2

R2910

470KR2J-2-GP

From PCH

HDA_SPKR (21)

KBC_BEEP (27)

From EC

$]DOLD,)(0,

HDA_CODEC_SDOUT

12

R2912

R2912 47R2J-2-GP

47R2J-2-GP

DY

PCH_AZ_CODEC_SDOUT1

A A

12

C2920

DY

SCD1U10V2KX-5GP

5

AUD_SENSE_A

+AVDD

12

R2915

R2915 2K49R2F-GP

2K49R2F-GP

12

C2919

C2919 SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

Close to Pin13

4

R2913

1 2

20KR2F-L-GP

R2919

39K2R2F-L-GP

AUD_HP1_JD# (58)

AUD_SENSE_B

12

EXT_MIC_JD# (58)

Close to Pin14

3

+AVDD

12

AUD_CAP2

AUD_VREFFLT

AUD_V_B

AUD_VREG

R2916

R2916 2K49R2F-GP

2K49R2F-GP

R2918

R2918 20KR2F-L-GP

20KR2F-L-GP

12

C2918

C2917

C2918

SC4D7U6D3V3KX-GP

SC10U6D3V5MX-3GP

Close to codec

AUD_VREFOUT_B

RN2901

SRN4K7J-8-GP

MIC_IN_L(58) MIC_IN_R(58)

2

12

C2915

C2916

SC1U6D3V2KX-GP

SC10U6D3V5MX-3GP

23

SC1U6D3V2KX-GP

1

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Audio Codec 92HD87B1

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

29 104Tuesday, January 18, 2011

1

A00

of

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

30 104Tuesday, January 04, 2011

A00