Wistron Nirvana 13 Schematic

5

4

3

2

1

Nirvana 13 Discrete GDDR5 Schematics Document

D D

Sandy Bridge

Intel PCH

C C

2011-01-18 REV : A00

B B

DY :None Installed 10mW: External circuit for 10mW solution installed. GSENSOR_ADI: Stuff for ADI G-Sensor VCCSA_PWM: Stuff for VCCSA PWM solution. P2800A1: Stuff for P2800EA1

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Cover

Nirvana 13

of

1 104Tuesday, January 18, 2011

1

A00

5

Seymour:512M (64M*32b*2)

D D

GDDR5 VRAM

512MB

GDDR5 1.25GHZ

AMD Graphic

SEYMOUR-XT-S3

83,84,85,86,87 4,5,6,7,8,9,10,11,12,13

C C

HDMI

LCD

CRT

SD/MMC+/MS/ MS Pro/xD/SDXC

(8 in 1)

B B

51

49

50

Card Reader

RTS5138

74

Bluetooth V3.0

Finger Print

CAMERA w/ Digital MIC

HP

MIC IN

A A

1CH SPEAKER

5

HDMI

LVDS(Single Channel)

RGB CRT

32

63

64

49

4

88

USB 2.0 x 1

CODEC

IDT 92HD87B1

4

3

Nirvana 13 Block Diagram (Discrete 8 layers)

Project Code: 91.4ID01.001 PCB P/N : 10244 Revision : -1

Intel CPU

DDRIII 1066/1333 Channel A

PCIe x 16

(Discrete)

FDIx4x2

(HDMI V1.3)

USB2.0 x 4

HDA

Flash ROM

4MB

29

Touch PAD

4

Sandy Bridge

DMIx4

Intel

PCH Cougar Point

14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6)

PCIE ports (8)

LPC I/F

ACPI 1.1

17,18,19,20,21,22,23,24,25,26

SPI

SMBus

LPC Bus

60

KBC

NUVOTON

NPCE795PA

27

Int.

69 69

KB

ADC

DAC

DDRIII 1066/1333 Channel B

PCIE x 1

PCIE x 1,USB2.0 x 1

USB2.0 x 1

SATA x 1

SATA x 2

Free Fall Sensor

Thermal Sensor

Main:ENEP2800

FAN Controller

Main: G991P11U

3

25

79

28

DDRIII 1066/1333

10/100/1000 LOM

Realtek

RTL8111E-VB

USB3.0 Controller

NEC uPD720200F1

Mini-Card

WWAN

Mini-Card

802.11a/b/g

USB CHARGE

PI5USB14550

Fan

55

65

2

Slot 1

14

Slot 2

15

(On Daughter Board)

RJ45 CONN

USB3.0 x 2

SIM

ESATA/USB Combo

HDD

56

ODD

56

2

1

PCB LAYER

DIS

L1:Top L2:GND L3:Signal L4:Signal L5:VCC L6:Signal L7:GND L8:Bottom

CPU DC/DC

VT1316+VT1317

INPUTS

5V_S5

OUTPUTS

VCC_CORE

SYSTEM DC/DC

VT1316+VT1317

INPUTS

5V_S5

OUTPUTS

VCC_GFXCORE

SYSTEM DC/DC

TPS51461

INPUTS

5V_S5

OUTPUTS

0D85V_S0

VGA

5V_S0

VT357

OUTPUTS

VGA_CORE

INPUTS

SYSTEM DC/DC

VT358/RT9026

INPUTS

5V_S5/5V_S5

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

SYSTEM DC/DC

VT357

INPUTS

5V_S5

OUTPUTS

1D05V_VTT

TI CHARGER

BQ24745

INPUTS

+DC_IN_S5

+PBATT

OUTPUTS

DCBATOUT

SYSTEM DC/DC

TPS51427

82

5757

INPUTS

DCBATOUT 5V_S5

26

SYSTEM DC/DC

INPUTS

3D3V_S5

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5 15V_S5

TPS51311

OUTPUTS

1D8V_S0

SYSTEM DC/DC

G9731

INPUTS OUTPUTS

26

1D5V_S3 1V_VGA_S0

1D5V_S0 5V_S0 3D3V_S03D3V_S5

of

36,93

Switches

INPUTS OUTPUTS

1D5V_S3 5V_S5

1D8V_S0 1D8V_VGA_S0 1D5V_S3 1D5V_VGA_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Tuesday, January 04, 2011

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Nirvana 13

1

2 104

A00

42

44

48

92

46

45

40

41

47

93

5

4

3

2

1

PCH Strapping

Huron River Schematic Checklist Rev.1_0

Name Schematics Notes

SPKR

INIT3_3V# Weak internal pull-up. This signal should not be pulled low. Leave as "No Connect".

GNT3#/GPIO55

D D

GNT2#/GPIO53 GNT1#/GPIO51

INTVRMEN

DF_TVS

SATA1GP /GPIO19

C C

HDA_SDO

HDA_SYNC

GPIO15

DSWVRMEN

B B

GPIO28

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Enable when Pull-up.

No Reboot Mode with TCO Disabled:

GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail.

Integrated 1.05 V VRM Enable / Disable

Integrated 1.05 V VRMs is enabled when high. This signal should always be pulled high

DMI and FDI Tx/Rx Termination Voltage

Weak internal pull-down. It needs to be connected to PROC_SELECT with a 1K±5% pull-up resistor to PCH VCCPNAND rail and a 4.7K±5% series resistor.

Boot BIOS Strap bit 0

This Signal has a weak internal pull-up. Note: This field determines the destination of accesses to the BIOS memory range. This strap is used in conjunction with Boot BIOS Destination Selection 1 strap. Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI 0 0 LPC

Signal has a weak internal pull-down. Default: the security measures defined in the Flash Descriptor will be in effect. Pull-up: the Flash Descriptor Security will be overridden. This strap should only be asserted high via external pull-up in manufacturing or debug environments ONLY.

On-Die PLL Voltage Regulator Voltage Select

This signal has a weak internal pull-down. On Die PLL VR is supplied by 1.5 V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform.

TLS Confidentiality

Low - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality This signal has a weak internal pull-down.



NOTE: A strong pull-up may be needed for GPIO functionality

Deep S4/S5 Well On-Die Voltage Regulator Enable

This signal enables the internal Deep Sleep 1.05 V regulators. This signal must be always pulled-up to VccRTC.

On-Die PLL Voltage Regulator

This signal has a weak internal pull-up. The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled. If not used, 8.2-kȍ to 10-kȍ pull-up to +V3.3A power-rail.

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[2]

CFG[4]

CFG[6:5]

CFG[7]

POWER PLANE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5

3D3V_AUX_KBC

3D3V_AUX_S5

PCI-Express Static Lane Reversal

Display Port Presence strap

PCI-Express Port Bifurcation Straps

PEG DEFER TRAINING

VOLTAGE DESCRIPTION

5V

3.3V

1.8V

1.5V

1.05V

0.95 - 0.85V

0.75V

0.35V to 1.5V

0.4 to 1.25V

1.8V

3.3V 1V

5V

1.5V

0.75V

6V-14.1V 6V-14.1V 5V 5V

3.3V

3.3V3D3V_LAN_S5

3.3V

1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded Display Port.

Enabled - An external Display Port device is

0:

connectd to the Embedded Display Port

11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled

1:

PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

0:

Voltage Rails

ACTIVE IN

S0

S3

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

Huron River Schematic Checklist Rev.1_0

Default Value

0

1

11

1

CPU Core Rail Graphics Core Rail

AC Brick Mode only

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

USB Table

PCIE Routing

LANE1

LANE2

LANE3

LANE4 Mini Card1(WLAN)

A A

LANE5

LANE6

LANE7

X

LAN (I/O Board)

Mini Card2(WWAN)

USB3.0

X

SATA Table

SATA

Pair

0

1

2

3

4

5

Device

HDD1

N/A

ODD

ESATA

LANE8 X

5

Pair

0

1

2

3

4

5

6

7

8

9

10

11

12

13

4

Device

X

ESATA / USB COMBO

Fingerprint

BLUETOOTH

Mini Card2 (WWAN)

CARD READER

X

Mini Card1 (WLAN)

CAMERA

X

SMBus ADDRESSES

2

I C / SMBus Addresses

Device

EC SMBus 1 Battery Capacity Board

EC SMBus 2 PCH MXM LCD Thermal Sensor

PCH SMBus CK505 Clock Generator SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot

3

HURON RIVER ORB

Address Hex Bus Ref Des

KBC_SDA1/KBC_SCL1 KBC_SDA1/KBC_SCL1

KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2

PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

Nirvana 13

3 104Tuesday, January 04, 2011

1

of

A00

5

4

3

2

1

SSID = CPU

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

1 OF 9

CPU1A

D D

C C

B B

NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Lane reversal does not apply to FDI sideband signals.

1D05V_VTT

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

DMI_TXN[3:0](19)

DMI_TXP[3:0](19)

DMI_RXN[3:0](19)

DMI_RXP[3:0](19)

FDI_TXN[7:0](19)

FDI_TXP[7:0](19)

FDI_FSYNC0(19) FDI_FSYNC1(19)

FDI_ INT(19)

FDI_LSYNC0(19) FDI_LSYNC1(19)

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DP_COMP

B27 B25 A25 B24

B28 B26 A24 B23

G21 E22 F21 D21

G22 D22 F20 C21

A21 H19 E19 F18 B21 C20 D18 E17

A22 G19 E20 G18 B20 C19 D19 F17

H20

H17

A18 A17 B16

C15 D15

C17 F16 C16 G15

C18 E16 D16 F15

J18 J17

J19

SANDY

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI0_LSYNC FDI1_LSYNC

EDP_COMPIO EDP_ICOMPO EDP_HPD

EDP_AUX EDP_AUX#

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3

SANDY

DMI

Intel(R) FDI

eDP

1 OF 9

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11

PCI EXPRESS* - GRAPHICS

PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_IRCOMP_R

PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0

PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0

PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0

PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

1 2

PEG_RXN[0..15]

Reverse the Bus for Layout 6/28

PEG_RXP[0..15]

NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect

C401 SCD22U10V2KX-1GPC401 SCD22U10V2KX-1GP

1 2

C402 SCD22U10V2KX-1GPC402 SCD22U10V2KX-1GP

1 2

C403 SCD22U10V2KX-1GPC403 SCD22U10V2KX-1GP

1 2

C404 SCD22U10V2KX-1GPC404 SCD22U10V2KX-1GP

1 2

C405 SCD22U10V2KX-1GPC405 SCD22U10V2KX-1GP

1 2

C406 SCD22U10V2KX-1GPC406 SCD22U10V2KX-1GP

1 2

C407 SCD22U10V2KX-1GPC407 SCD22U10V2KX-1GP

1 2

C408 SCD22U10V2KX-1GPC408 SCD22U10V2KX-1GP

1 2

C409 SCD22U10V2KX-1GPC409 SCD22U10V2KX-1GP

1 2

C410 SCD22U10V2KX-1GPC410 SCD22U10V2KX-1GP

1 2

C411 SCD22U10V2KX-1GPC411 SCD22U10V2KX-1GP

1 2

C412 SCD22U10V2KX-1GPC412 SCD22U10V2KX-1GP

1 2

C413 SCD22U10V2KX-1GPC413 SCD22U10V2KX-1GP

1 2

C414 SCD22U10V2KX-1GPC414 SCD22U10V2KX-1GP

1 2

C415 SCD22U10V2KX-1GPC415 SCD22U10V2KX-1GP

1 2

C416 SCD22U10V2KX-1GPC416 SCD22U10V2KX-1GP

1 2

C417 SCD22U10V2KX-1GPC417 SCD22U10V2KX-1GP

1 2

C418 SCD22U10V2KX-1GPC418 SCD22U10V2KX-1GP

1 2

C419 SCD22U10V2KX-1GPC419 SCD22U10V2KX-1GP

1 2

C420 SCD22U10V2KX-1GPC420 SCD22U10V2KX-1GP

1 2

C421 SCD22U10V2KX-1GPC421 SCD22U10V2KX-1GP

1 2

C422 SCD22U10V2KX-1GPC422 SCD22U10V2KX-1GP

1 2

C423 SCD22U10V2KX-1GPC423 SCD22U10V2KX-1GP

1 2

C424 SCD22U10V2KX-1GPC424 SCD22U10V2KX-1GP

1 2

C425 SCD22U10V2KX-1GPC425 SCD22U10V2KX-1GP

1 2

C426 SCD22U10V2KX-1GPC426 SCD22U10V2KX-1GP

1 2

C427 SCD22U10V2KX-1GPC427 SCD22U10V2KX-1GP

1 2

C428 SCD22U10V2KX-1GPC428 SCD22U10V2KX-1GP

1 2

C429 SCD22U10V2KX-1GPC429 SCD22U10V2KX-1GP

1 2

C430 SCD22U10V2KX-1GPC430 SCD22U10V2KX-1GP

1 2

C431 SCD22U10V2KX-1GPC431 SCD22U10V2KX-1GP

1 2

C432 SCD22U10V2KX-1GPC432 SCD22U10V2KX-1GP

1 2

1D05V_VTT

PEG_RXN[0..15] (83)

PEG_RXP[0..15] (83)

PEG Static Lane Reversal

PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0

PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0

PEG_TXN[0..15]

PEG_TXP[0..15]

PEG_TXN[0..15] (83)

PEG_TXP[0..15] (83)

Stuff to disable internal graphics function for power saving.

A A

NOTE: Select a Fast FET similar to 2N7002E whose rise/ fall time is less tha n 6 ns. If HPD on eDP inte rfac e is disabled, connect it to CPU VCCIO via a 10-kȍ pull-U p resistor on the motherboard.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU 1/7(PEG/DMI/FDI/eDP)

Size Document Number Rev

Date: Sheet of

Date: Sheet

CPU 1/7(PEG/DMI/FDI/eDP)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

4 104Tuesday, January 18, 2011

A00

5

SSID = CPU

H_SNB_IVB#(18)

1D05V_VTT

R501

D D

R501

62R2J-GP

H_PROCHOT#

1 2

CRB : 47pf CEKLT:43pf

12

C502

C502 SC47P50V2JN-3GP

SC47P50V2JN-3GP

Connect EC to PROCHOT# through inverting OD buffer.

H_PECI(22,27)

H_PROCHOT#(27,40,42)

H_THERMTRIP#(22,36)

1

TP501TPAD14-GP TP501TPAD14-GP

1

TP502TPAD14-GP TP502TPAD14-GP

R513

1 2

56R2J-4-GP

4

SKTOCC#_R

H_CATERR#

H_PROCHOT#_R

AN34

AL33

AN33

AL32

AN32

C26

CPU1B

SNB_IVB#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

SANDY

3

2 OF 9

A28

BCLK

A27

BCLK#

MISCTHERMALPWR MANAGEMENT

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

DDR3

MISC

DDR3

MISC

A16 A15

R8

AK1 A5 A4

2

CLK_EXP_P (20)

RN502

CLK_DP_P_R CLK_DP_N_R

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils.

RN502

2 3 1

SRN1KJ-7-GP

R502

1 2

4K99R2F-L-GP

R506 140R2F-GPR506 140R2F-GP

1 2

R507 25D5R2F-GPR507 25D5R2F-GP

1 2

R508 200R2F-L-GPR508 200R2F-L-GP

1 2

CLK_EXP_N (20)

4

1D05V_VTT

20110104 A00: merge R512,R514 to RN502 1k array resistor. 20110113 A00: Swap RN502 base on swap report.

SM_DRAMRST# (37)

1

Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted.

10KR2J-3-GP

H_CPUPWRGD_R

R510

1 2

1K5R2F-2-GP

PM_DRAM_PWRGD(19,37)

VDDPWRGOOD(37)

12

H_PM_SYNC(19)

H_CPUPWRGD(22,36)

R509

R509 750R2F-GP

750R2F-GP

DY

1 2

12

R504

H_CPUPWRGD_R

0R0402-PAD

VDDPWRGOOD

R505

0R2J-2-GP

DY

BUF_CPU_RST#

C501

C501 SC220P50V2KX-3GP

SC220P50V2KX-3GP

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

SANDY

AP29

PRDY#

AP27

PREQ#

AR26

TCK

AR27

TMS

AP30

TRST#

AR28

TDI

AP26

TDO

AL35

DBR#

AT28

BPM#0

AR29

BPM#1

JTAG & BPM

BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

AR30 AT30 AP32 AR31 AT31 AR32

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_TDI XDP_TMS XDP_TDO XDP_TCLK

XDP_TRST#

XDP_DBRESET#

RN501

1

8

2

7

3

6

4 5

SRN51J-1-GP

R511 51R2J-2-GPR511 51R2J-2-GP

1 2

R516

1 2

10KR2J-3-GP

1D05V_VTT

3D3V_S0

R503

1 2

C C

PLT_RST#(18,27,65,71,82,83)

B B

Buffered reset to CPU

PLT_RST#(18,27,65,71,82,83)

U501

1

IN B

VCC

2

DY

IN A

GND3OUT Y

74VHC1G09DFT2G-GP

73.01G09.AAH

1D05V_VTT

DY

5

4

12

R518

R518 75R2J-1-GP

75R2J-1-GP

3D3V_S0

12

C503

DY

SCD1U10V2KX-5GP

1 2

DY

R517 43R2J-GP

DY

12

0R2J-2-GP

BUF_CPU_RST#BUFO_CPU_RST#

R515

XDP_DBRESET#

XDP_DBRESET# (19)

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU 2/7(THERMAL/CLOCK/PM )

Size Document Number Rev

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

5 104Tuesday, January 18, 2011

1

A00

5

4

3

2

1

SSID = CPU

4 OF 9

3 OF 9

CPU1C

SANDY

M_A_DQ[63:0](14)

D D

C C

B B

M_A_DQ[63:0]

M_A_BS0(14) M_A_BS1(14) M_A_BS2(14)

M_A_CAS#(14) M_A_RAS#(14) M_A_WE#(14)

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AK8

AK9 AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9 AF9

C5

SA_DQ0

D5

SA_DQ1

D3

SA_DQ2

D2

SA_DQ3

D6

SA_DQ4

C6

SA_DQ5

C2

SA_DQ6

C3

SA_DQ7

F10

SA_DQ8

F8

SA_DQ9 SA_DQ10

G9

SA_DQ11

F9

SA_DQ12

F7

SA_DQ13

G8

SA_DQ14

G7

SA_DQ15

K4

SA_DQ16

K5

SA_DQ17

K1

SA_DQ18

J1

SA_DQ19

J5

SA_DQ20

J4

SA_DQ21

J2

SA_DQ22

K2

SA_DQ23

M8

SA_DQ24 SA_DQ25

N8

SA_DQ26

N7

SA_DQ27 SA_DQ28

M9

SA_DQ29

N9

SA_DQ30

M7

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37

AJ5

SA_DQ38

AJ6

SA_DQ39

AJ8

SA_DQ40 SA_DQ41

AJ9

SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55

V6

SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

3 OF 9

SA_CLK0

SA_CLK#0

SA_CKE0

SA_CLK1

SA_CLK#1

SA_CKE1

SA_CLK2

SA_CLK#2

SA_CKE2

SA_CLK3

SA_CLK#3

SA_CKE3

SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3

SA_ODT0

SA_ODT1 SA_ODT2 SA_ODT3

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIM0_CLK_DDR0 (14) M_A_DIM0_CLK_DDR#0 (14) M_A_DIM0_CKE0 (14)

M_A_DIM0_CLK_DDR1 (14) M_A_DIM0_CLK_DDR#1 (14) M_A_DIM0_CKE1 (14)

M_A_DIM0_CS#0 (14) M_A_DIM0_CS#1 (14)

M_A_DIM0_ODT0 (14) M_A_DIM0_ODT1 (14)

M_A_DQS #[7:0] (1 4)

M_A_DQS[7:0] (14)

M_A_A[15:0] (14)

M_B_DQ[63:0](15)

M_B_DQ[63:0]

M_B_BS0(15) M_B_BS1(15) M_B_BS2(15)

M_B_CAS#(15) M_B_RAS#(15) M_B_WE#(15)

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA9 AA7

AA10

AB8 AB9

CPU1D

SANDY

C9

SB_DQ0

A7

SB_DQ1 SB_DQ2

C8

SB_DQ3

A9

SB_DQ4

A8

SB_DQ5

D9

SB_DQ6

D8

SB_DQ7

G4

SB_DQ8

F4

SB_DQ9

F1

SB_DQ10

G1

SB_DQ11

G5

SB_DQ12

F5

SB_DQ13

F2

SB_DQ14

G2

SB_DQ15

J7

SB_DQ16

J8

SB_DQ17 SB_DQ18

K9

SB_DQ19

J9

SB_DQ20

J10

SB_DQ21

K8

SB_DQ22

K7

SB_DQ23

M5

SB_DQ24

N4

SB_DQ25

N2

SB_DQ26

N1

SB_DQ27

M4

SB_DQ28

N5

SB_DQ29

M2

SB_DQ30

M1

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54

R6

SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

4 OF 9

SB_CLK0

SB_CLK#0

SB_CKE0

SB_CLK1

SB_CLK#1

SB_CKE1

SB_CLK2

SB_CLK#2

SB_CKE2

SB_CLK3

SB_CLK#3

SB_CKE3

SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIM0_CLK_DDR0 (15) M_B_DIM0_CLK_DDR#0 (15) M_B_DIM0_CKE0 (15)

M_B_DIM0_CLK_DDR1 (15) M_B_DIM0_CLK_DDR#1 (15) M_B_DIM0_CKE1 (15)

M_B_DIM0_CS#0 (15) M_B_DIM0_CS#1 (15)

M_B_DIM0_ODT0 (15) M_B_DIM0_ODT1 (15)

M_B_DQS#[7:0] (15)

M_B_DQS[7:0] (15)

M_B_A[15:0] (15)

SANDY

A A

5

4

3

SANDY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU 3/7(DDR)

Nirvana 13

1

A00

of

6 104Tuesday, January 18, 2011

A00

SSID = CPU

5

4

3

2

1

CFG7

1

TP713 TPAD14-GPTP713 TPAD14-GP

1

TP714 TPAD14-GPTP714 TPAD14-GP

CFG4

CFG2

DY

12

R701

DY

1KR2J-1-GP

12

DY

12

DY

12

R704

R705

R705 1KR2J-1-GP

1KR2J-1-GP

R702

R702 1KR2J-1-GP

1KR2J-1-GP

12

R703

R703 3K3R2F-2-GP

3K3R2F-2-GP

PEG Static Lane Reversal

CFG2

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

1KR2J-1-GP

CFG[6:5]

11: x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

PEG DEFER TRAINING

CFG7

1: PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

5 OF 9

CPU1E

AK28

CFG0

AK29

D D

TP712TPAD14-GP TP712TPAD14-GP

CFG2

CFG4 CFG5 CFG6 CFG7

CFG17

1

M3 - Processor Generated SO-DIMM VREF_DQ

C C

M_VREF_DQ_DIMM0 M_VREF_DQ_DIMM1

M_VREF_CA_DIMM0

M_VREF_CA_DIMM1

R707 0R2J-2-GP

R706 0R2J-2-GP

DY

R708 0R2J-2-GP

1 2

DY

R709 0R2J-2-GP

1 2

DY

1 2

DY

M_VREF_DQ_DIMM0_C M_VREF_DQ_DIMM1_C

R711

1KR2F-3-GP

20 mils

R710 0R2J-2-GP

1 2

DY

B B

B4:VREF_DQ CHA

D1:VREF_DQ CHB

12

R712

1KR2F-3-GP

H_VCCP_SEL

AL26 AL27

AK26

AL29

AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29

AJ31 AH31

AJ33 AH33

AJ26

F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29

B18 A19

B4 D1

J20

J15

CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

RSVD#AJ31 RSVD#AH31 RSVD#AJ33 RSVD#AH33

RSVD#AJ26

RSVD#B4 RSVD#D1

RSVD#F25 RSVD#F24 RSVD#F23 RSVD#D24 RSVD#G25 RSVD#G24 RSVD#E23 RSVD#D23 RSVD#C30 RSVD#A31 RSVD#B30 RSVD#B29 RSVD#D30 RSVD#B31 RSVD#A30 RSVD#C29

RSVD#J20 RSVD#B18 RSVD#A19

RSVD#J15

SANDY

RESERVED

5 OF 9

RSVD#L7 RSVD#AG7 RSVD#AE7 RSVD#AK2

RSVD#W8

RSVD#AT26

RSVD#AM33

RSVD#AJ27

RSVD#T8

RSVD#J16 RSVD#H16

RSVD#G16

RSVD#AR35

RSVD#AT34 RSVD#AT33

RSVD#AP35

RSVD#AR34

RSVD#B34 RSVD#A33 RSVD#A34 RSVD#B35 RSVD#C35

RSVD#AJ32

RSVD#AK32

RSVD#AH27

RSVD#AN35 RSVD#AM35

RSVD#AT2 RSVD#AT1 RSVD#AR1

L7 AG7 AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

AN35 AM35

AT2 AT1 AR1

RSVD#AN35 RSVD#AM35

CFG5

CFG6

SANDY

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU 4/7(RESERVED)

Size Document Number Rev

Date: Sheet of

Date: Sheet

CPU 4/7(RESERVED)

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

of

7 104Tuesday, January 04, 2011

1

A00

5

4

3

2

1

SSID = CPU

D D

POWER

CPU1F

SANDY

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

SANDY

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

SANDY

4

CORE SUPPLY

VCC_CORE

PROCESSOR CORE POWER

C C

B B

A A

VCC_CORE

20110118 A00: Reserve C846~C848 22uF (0805 size).

53A

12

DY

12

C802

C801

SC10U6D3V5KX-1GP

12

C819

C820

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

20110118 A00: Change C823, C824, C825 to 22uF from 10uF (0805 size).

12

C816

C821

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

12

C836

C837

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

VCC Output Decoupling Recommendation: 4 x 470 uF at Bottom Socket Edge 8 x 22 uF at Top Socket Cavity 8 x 22 uF at Top Socket Edge 8 x 22 uF at Bottom Socket Cavity

12

C846

C847

DY

SC22U6D3V5MX-2GP

5

12

C811

C803

SC10U6D3V5KX-1GP

C818

SC22U6D3V5MX-2GP

C822

SC10U6D3V5KX-1GP

C835

SC22U6D3V5MX-2GP

12

C811

C804

DY

SC22U6D3V5MX-2GP

12

C815

C817

SC10U6D3V5KX-1GP

12

C824

C823

SC22U6D3V5MX-2GP

12

C833

C834

SC10U6D3V5KX-1GP

C848

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

12

C825

C826

C827

SC22U6D3V5MX-2GP

12

C832

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

12

C828

C831

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

6 OF 9

AH13

VCCIO

AH10

VCCIO

AG10

VCCIO

AC10

VCCIO

Y10

VCCIO

U10

VCCIO

P10

VCCIO

L10

VCCIO

J14

VCCIO

J13

VCCIO

J12

VCCIO

J11

VCCIO

H14

VCCIO

H12

VCCIO

H11

VCCIO

G14

VCCIO

G13

VCCIO

G12

VCCIO

F14

VCCIO

F13

VCCIO

F12

VCCIO

F11

VCCIO

E14

VCCIO

E12

VCCIO

E11

VCCIO

D14

VCCIO

D13

VCCIO

D12

VCCIO

D11

VCCIO

C14

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSSIO_SENSE

C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

PEG AND DDR

SENSE LINES SVID

VCCIO Output Decoupling Recommendation: 2 x 330 uF (3 x 330 uF for 2012 capable designs) 5 x 22 uF & 5 x 0805 no-stuff at Bottom 7 x 22 uF & 2 x 0805 no-stuff at Top

12

C805

DY

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

20101231 A00: Merge R801,R802 to RN801 100 ohm array resistor. 20110113 A00: Change RN801 to 100 ohm 1% (66.10156.04L). 20110113 A00: Swap RN801 base on swap report.

VCC_CORE

12

C806

DY

SC10U6D3V3MX-GP

No-stuff sites outside the socket may be removed. No-stuff sites inside the socket cavity need to remain.

R803 43R2J-G PR803 43R2J-GP

1 2

RN801

2 3

R2

1

R1

SRN100F-1-GP

VCCIO_SENSE (45) VSSIO_SENSE (45)

3

12

C807

C808

DY

SC10U6D3V3MX-GP

12

C829

SC10U6D3V5KX-1GP

12

C809

SC10U6D3V5KX-1GP

12

C830

SC10U6D3V5KX-1GP

12

C838

C810

SC10U6D3V5KX-1GP

12

C843

C842

DY

SC4D7U6D3V5KX-3GP

These resistors need to close to power IC.

VR_SVID_ALERT#

H_CPU_SVIDCLK

H_CPU_SVIDDAT

VR_SVID_ALERT# (42)

H_CPU_SVIDCLK (42)

4

H_CPU_SVIDDAT (42)

R805 75R2J-1-GPR805 75R2J-1-GP

1 2

R806 54D9R2F-L1-GP

1 2

R804 130R2F-1-GPR804 130R2F-1-GP

1 2

VCCSENSE (42) VSSSENSE (42)

C839

SC4D7U6D3V5KX-3GP

1D05V_VTT

C844

SC10U6D3V5KX-1GP

DY

1D05V_VTT

12

C841

C840

SC10U6D3V5KX-1GP

12

C845

SC10U6D3V5KX-1GP

1D05V_VTT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

CPU 5/7(VCC_CORE)

Nirvana 13

1

8 104Tuesday, January 18, 2011

A00

of

5

VAXG Output Decoupling Recommendation:

SSID = CPU

VCC_GFXCORE

2 x 470 uF at Bottom Socket Edge 2 x 22 uF at Top Socket Cavity 4 x 22 uF at Top Socket Edge 2 x 22 uF at Bottom Socket Cavity 4 x 22 uF at Bottom Socket Edge

PROCESSOR VAXG: 33A

D D

DY

C C

Disabling Guidelines for External Graphics Designs: Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed. Can be left floating (Gfx VR keeps VAXG rail from floating)

B B

if the VR is stuffed

12

C901

SC10U6D3V5KX-1GP

DY

1D8V_S0

12

C902

SC4D7U6D3V5KX-3GP

12

C908

SC10U6D3V3MX-GP

12

C904

C903

SC4D7U6D3V5KX-3GP

DY

PROCESSOR VCCPLL: 1.2A

12

C923

SC10U6D3V5KX-1GP

12

C905

SC22U6D3V5MX-2GP

12

C920

DY

SC10U6D3V3MX-GP

12

C922

SC1U10V2KX-1GP

4

12

C906

SC4D7U6D3V5KX-3GP

12

C921

SC10U6D3V3MX-GP

12

C924

SC1U10V2KX-1GP

AT24 AT23 AT21 AT20 AT18

AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17

AM24 AM23 AM21 AM20 AM18 AM17

AL24

AL23

AL21

AL20

AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

3

POWER

CPU1G

VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG

B6

VCCPLL

A6

VCCPLL

A2

VCCPLL

SANDY

POWER

SANDY

GRAPHICS

1.8V RAIL

SENSE

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

7 OF 9

VAXG_SENSE

VSSAXG_SENSE

LINES

SM_VREF

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCSA_SENSE

FC_C22

VCCSA_VID1

AK35 AK34

Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation.

+V_SM_VREF_CNT should have 10 mil trace width

+V_SM_VREF_CNT

AL1

Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

PROCESSOR VDDQ: 10A

12

C909

DY

SC10U6D3V3MX-GP

PROCESSOR VCCSA: 6A

12

C916

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

VCCUSA_SENSE

H_FC_C22 VCCSA_SEL

SC10U6D3V5KX-1GP

1

23

2

VCC_AXG_SENSE (42) VSS_AXG_SENSE (42)

+V_SM_VREF_CNT (37)

12

C910

C911

DY

12

RN901

RN901 SRN1KJ -7-GP

SRN1KJ -7-GP

C911

DY

SC10U6D3V3MX-GP

0D85V_S0

12

C917

C915

SC10U6D3V5KX-1GP

VCCUSA_SENSE (48)

H_FC_C22 (48) VCCSA_SEL (48)

12

C912

SC10U6D3V5KX-1GP

SC10U6D3V3MX-GP

SC10U6D3V5KX-1GP

1

20101231 A00: Merge R906,R907 to RN902 100 ohm array resistor. 20110113 A00: Change RN801 to 100 ohm 1% (66.10156.04L).

RN902

R1

VCC_AXG_SENSE VSS_AXG_SENSE

1D5V_S0

12

C914

C913

SC10U6D3V5KX-1GP

VDDQ Output Decoupling Recommendation: 1 x 330 uF 6 x 10 uF

TC901

79.33719.20L

SC4D7U6D3V5KX-3GP

2nd = 77.C3371.13L

VCCSA Output Decoupling Recommendation: 1 x 330 uF 2 x 10 uF at Bottom Socket Cavity 1 x 10 uF at Bottom Socket Edge

1 2 3

SRN100F-1-GP

12

DY

ST330U2VDM-4-GP

C907

R1

4

R2

12

DY

C918

C919

SCD1U10V2KX-5GP

VCC_GFXCORE

12

DY

C925

SCD1U10V2KX-5GP

1D5V_S3

SCD1U10V2KX-5GP

4

VCCPLL Output Decoupling Recommendation: 1 x 330 uF 2 x 1 uF 1 x 10 uF

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU 6/7(VCC_GFX_CORE)

Size Document Number Rev

Date: Sheet of

Date: Sheet

CPU 6/7(VCC_GFX_CORE)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

9 104Tuesday, January 18, 2011

1

A00

5

4

3

2

1

SSID = CPU

9 OF 9

8 OF 9

CPU1H

AT35

VSS

AT32

VSS

AT29

VSS

AT27

VSS

AT25

VSS

D D

C C

B B

AT22 AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34

K35 K32 K29 K26

H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11

CPU1I

T35

VSS

T34

VSS

T33

VSS

T32

VSS

T31

VSS

T30

VSS

T29

VSS

T28

VSS

T27

VSS

T26

VSS

P9

VSS

P8

VSS

P6

VSS

P5

VSS

P3

VSS

P2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L33

VSS

L30

VSS

L27

VSS

L9

VSS

L8

VSS

L6

VSS

L5

VSS

L4

VSS

L3

VSS

L2

VSS

L1

VSS VSS VSS VSS VSS

J34

VSS

J31

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H9

VSS

H8

VSS

H7

VSS

H6

VSS

H5

VSS

H4

VSS

H3

VSS

H2

VSS

H1

VSS VSS VSS VSS VSS VSS VSS VSS VSS

F34

VSS

F31

VSS

F29

VSS

SANDY

VSS

9 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

SANDY

A A

5

4

3

SANDY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU 7/7(VSS)

Nirvana 13

1

A00

of

10 104Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

Remove the XDP connector for space saving 6/28

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 04, 2011

Date: Sheet

XDP

NIRVANA 13

Taipei Hsien 221, Taiwan, R.O.C.

of

11 104

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

of

12 104Tuesday, January 04, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

13 104Tuesday, January 04, 2011

A00

5

4

3

2

1

SSID = MEMORY

DM1

H=9.2mm

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-42-GP

62.10017.N61

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIM0

197

SA0

SA1_DIM0

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_A_RAS# (6) M_A_WE# (6) M_A_CAS# (6)

M_A_DIM0_CS#0 (6) M_A_DIM0_CS#1 (6)

M_A_DIM0_CKE0 (6) M_A_DIM0_CKE1 (6)

M_A_DIM0_CLK_DDR0 (6) M_A_DIM0_CLK_DDR#0 (6)

M_A_DIM0_CLK_DDR1 (6) M_A_DIM0_CLK_DDR#1 (6)

PCH_SMBDATA (15,20,65,79,82) PCH_SMBCLK (15,20,65,79,82)

TS#_DIMM0_1 (15)

Layout Note: Place these Caps near SO-DIMMA.

PART NUMBER

62.10017.N61

62.10017.U01

62.10017.T11

20101231 A00: Merge R1401,R1402 to RN1401 10k ohm array resistor. 20110104 A00: Change RN1401 to 0R short pad. 20110113 A00: Swap RN1401 base on swap report.

3D3V_S0

12

C1402

C1401

DY

SCD1U10V2KX-5GP

1D5V_S3

SC2D2U10V3KX-1GP

12

ST330U2VDM-4-GP

TC1401

DY

79.33719.20L

2nd = 77.C3371.13L

12

C1414

DY

SCD1U10V2KX-5GP

Height TYPE

9.2mm

SA0_DIM0

SA1_DIM0

23

SODIMM A DECO UPLING

12

C1403

C1404

C1405

DY

SC10U6D3V5KX-1GP

12

C1415

DY

SCD1U10V2KX-5GP

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

12

C1417

C1416

SCD1U10V2KX-5GP

1

RN1401

RN1401 0R4P2R-PAD

0R4P2R-PAD

RN

4

Thermal EVENT

TS#_DIMM0_1

12

C1407

C1406

DY

SC10U6D3V5KX-1GP

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

3D3V_S0

R1403

1 2

10KR2J-3-GP

12

C1409

C1408

SC10U10V5ZY-1GP

C1410

DY

SC10U6D3V5KX-1GP

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

12

DY

M_A_DQ[63:0](6)

12

C1422

DY

SC1U6D3V2KX-GP

M_A_DIM0_ODT0(6) M_A_DIM0_ODT1(6)

M_VREF_CA_DIMM0 M_VREF_DQ_DIMM0

DDR3_DRAMRST#(15,37)

M_A_A[15:0] (6)

M_A_BS2(6)

M_A_BS0(6) M_A_BS1(6)

C1418

SC10U6D3V5KX-1GP

M_A_DQS#[7:0] (6)

M_A_DQS[7:0] ( 6)

0D75V_S0

DDR_VREF_S3

R1405

R1405 0R0402-PAD

D D

20101224 A00: 0402 0R pad: R1404 R1405.

C C

B B

1 2

12

DDR_VREF_S3

1 2

12

0D75V_S0

0R0402-PAD

C1423

SCD1U10V2KX-5GP

R1404

R1404 0R0402-PAD

0R0402-PAD

C1411

SCD1U10V2KX-5GP

12

C1419

M_VREF_CA_DIMM0

12

C1425

DY

SC2D2U10V3KX-1GP

M_VREF_DQ_DIMM0

12

C1412

DY

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1420

DY

SC1U6D3V2KX-GP

12

C1424

SCD1U10V2KX-5GP

12

C1413

SCD1U10V2KX-5GP

12

C1421

SC1U6D3V2KX-GP

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

DDR3-DIMM1 SOCKET1

Nirvana 13

1

of

14 104Tuesday, January 18, 2011

A00

5

SSID = MEMORY

M_B_A[15:0] (6)

C1520

SC1U6D3V2KX-GP

M_B_BS2(6)

M_B_BS0(6) M_B_BS1(6)

M_B_DQ[63:0](6)

12

C1521

SC1U6D3V2KX-GP

M_B_DIM0_ODT0(6) M_B_DIM0_ODT1(6)

M_VREF_CA_DIMM1 M_VREF_DQ_DIMM1

DDR3_DRAMRST#(14,37)

M_B_DQS#[7:0] (6)

M_B_DQS[7:0] ( 6)

0D75V_S0

D D

DDR_VREF_S3

R1504

R1504 0R0402-PAD

0R0402-PAD

M_VREF_CA_DIMM1

1 2

12

C1523

SCD1U10V2KX-5GP

DDR_VREF_S3

R1503

R1503 0R0402-PAD

0R0402-PAD

C C

B B

1 2

12

C1515

SCD1U10V2KX-5GP

0D75V_S0

12

C1522

C1524

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

20101224 A00: 0402 0R pad: R1503 R1504.

M_VREF_DQ_DIMM1

12

C1516

C1517

12

DY

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1518

SC1U6D3V2KX-GP

C1517

SCD1U10V2KX-5GP

C1519

SC1U6D3V2KX-GP

DY

12

DY

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

H=5.2mm

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-48-GP

62.10017.P41

4

NP1

NP2

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIM1

197

SA0

SA1_DIM1

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_B_RAS# (6) M_B_WE# (6) M_B_CAS# (6)

M_B_DIM0_CS#0 (6) M_B_DIM0_CS#1 (6)

M_B_DIM0_CKE0 (6) M_B_DIM0_CKE1 (6)

M_B_DIM0_CLK_DDR0 (6) M_B_DIM0_CLK_DDR#0 (6)

M_B_DIM0_CLK_DDR1 (6) M_B_DIM0_CLK_DDR#1 (6)

PCH_SMBDATA (14,20,65,79,82) PCH_SMBCLK (14,20,65,79,82)

TS#_DIMM0_1 (14)

Layout Note: Place these Caps near SO-DIMMB.

PART NUMBER

62.10017.P41

62.10017.T91 5.2mm

62.10017.T01 5.2mm

3

12

C1502

C1501

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

Height TYPE

5.2mm

1D5V_S3

SA1_DIM1

SA0_DIM1

3D3V_S0

SODIMM B DECO UPLING

12

C1503

DY

12

C1511

DY

3D3V_S0

12

C1504

DY

SC10U10V5ZY-1GP

12

C1512

SCD1U10V2KX-5GP

R1501

R1501 10KR2J-3-GP

10KR2J-3-GP

R1502

R1502 0R0402-PAD

0R0402-PAD

20100104 A00: Change R1502 to 0R0402 short pad.

12

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

SO-DIMMB is placed f arther from the Processor than SO-DIMM A

12

C1507

C1505

SC10U6D3V5KX-1GP

C1513

C1507

C1506

SC10U6D3V5KX-1GP

12

C1514

SCD1U10V2KX-5GP

DY

SC4D7U6D3V5KX-3GP

2

12

C1508

C1509

C1510

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

1

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

DDR3-DIMM2 SOCKET2

Size Document Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

Nirvana 13

1

A00

of

15 104Tuesday, January 18, 2011

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

of

16 104Tuesday, January 04, 2011

1

A00

5

L_DDC_DATA(PAGE17):

D D

RN1702

1 2 3

SRN100KJ-6-GP

4

L_BKLT_EN LVDS_VDD_EN

This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display

Place near PCH

3D3V_S0

RN1703

1 2 3 4 5

SRN2K2J-2-GP

C C

SRN2K2J-2-GP

20110104 A00: Merge RN1701,RN1706 to RN1703 2.2k array resistor. 20110113 A00: Swap RN1703.7,RN1703.5; swap RN1703.8,RN1703.6.

8 7 6

PCH_HDMI_DATA PCH_HDMI_CLK L_CTRL_DATA L_CTRL_CLK

Impedance:90 ohm

Close to PCH side

CRT_GREEN

CRT_BLUE CRT_RED

678

RN1705

RN1705 SRN150F-1-GP

SRN150F-1-GP

123

4 5

B B

4

L_BKLT_EN(27)

LVDS_VDD_EN(49)

L_BKLT_CTRL(49)

LVDS_DDC_CLK_R(49,97) LVDS_DDC_DATA_R(49,97)

20101224 A00: Change RN1704 to 0402 0 ohm pad.

12

R1701

R1701 2K37R2F-GP

2K37R2F-GP

LVDSA_CLK#(49) LVDSA_CLK(49)

LVDSA_DATA0#(49) LVDSA_DATA1#(49) LVDSA_DATA2#(49)

LVDSA_DATA0(49) LVDSA_DATA1(49) LVDSA_DATA2(49)

0617 Modify: Joseph Removed LVDSB r elated net for single LVDS channel ba se on Dell updated spec.

CRT_BLUE(50) CRT_GREEN(50) CRT_RED(50)

CRT_DDC_CLK(50) CRT_DDC_DATA(50)

CRT_HSYNC(50) CRT_VSYNC(50)

Notes: 1K 0.5% 0402.

TP1701TPAD14-GP TP1701TPAD14-GP

RN1704

1 2 3

0R4P2R-PAD

R1702

1KR2D-1-GP

LVDS_DDC_CLK_R LVDS_DDC_DATA_R

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG

RN

LVDS_VBG

1

LVDS_VREFH

4

LVDS_VREFL

DAC_IREF_R

12

PCH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGAR-GP-U2-NF

3

4 OF 10

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

Cougar

Cougar Point

Point

LVDS

CRT

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

2

DDI Port B Detect:(SDVO_CTRL_ DATA) 1: Port B detected 0: Port B not detected

1

PCH_HDMI_CLK (51) PCH_HDMI_DATA (51)

HDMI_PCH_DET (51)

HDMI_DATA2_R# (51) HDMI_DATA2_R (51) HDMI_DATA1_R# (51) HDMI_DATA1_R (51) HDMI_DATA0_R# (51) HDMI_DATA0_R (51) HDMI_CLK_R# (51) HDMI_CLK_R (51)

Impedance:100 ohmImpedance:90 ohm

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

PCH 1/9(LVDS/CRT/DDI)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

17 104Tuesday, January 18, 2011

1

A00

5

SSID = PCH

RN1801

D D

3D3V_S0

INT_PIRQB# INT_PIRQF# INT_PIRQA#

R1801 4K7R2J-2-GP

A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3 Low = A16 swap

C C

RN1801

1 2 3 4 5 6

SRN8K2J-2-GP-U

12

DY

override/Top-Block Swap Override enabled High = Default

R1802

1 2

DY

1KR2J-1-GP

R1803

1 2

DY

1KR2J-1-GP

10

INT_PIRQD#

9

INT_PIRQE#

8

INT_PIRQC#

7

INT_PIRQG#

PCI_GNT3#

BBS_BIT1

BBS_BIT0

3D3V_S0

BBS_BIT0 (21)

BOOT BIOS Strap

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

0 0 LPC

0 1 Reserved

Reserved 01

B B

20101231 A00: Merge R1804,R1806 to RN1804 22 ohm array resistor. 20110113 A00: Swap RN1804 base on swap report.

A A

PLT_RST#(5,27,65,71,82,83)

11

12

DY

5

SPI(Default)

CLK_PCI_LPC(65,71,97) CLK_PCI_FB(20) CLK_PCI_KBC(27)

20101224 A00: 0402 0R pad: R1807.

0R0402-PAD

R1816

12

C1801

DY

SC220P50V2KX-3GP

100KR2J-1-GP

R1807

PCI_PLTRST#

12

HDD_FALL_INT1(79)

SATA_ODD_DA#(56)

KB_LED_BL_DET(69)

EC1801

1 2

DY

SC4D7P50V2CN-1GP

USB30_SMI#(82)

DGPU_HOLD_RST#(83)

DGPU_PWR_EN#(93)

TP1806TPAD14-GP TP1806TPAD14-GP

RN1804

2 3 1

SRN22-3-GP

EC1802

4

DGPU_HOLD_RST# DGPU_PWR_EN#

DGPU_PWM_SELECT#

1

4

R1805 22R2J-2-GPR1805 22R2J-2-GP

1 2

DY

SC4D7P50V2CN-1GP

1 2

4

1 2 3

SRN10KJ-5-GP

3D3V_S0

1 2

1

TP1807TPAD14-GP TP1807TPAD14-GP

1 2

DGPU_PWR_EN#

R1812 0R0402-PADR1812 0R0402-PAD

1 2

R1813 0R0402-PADR1813 0R0402-PAD

1 2

R1815 0R0402-PADR1815 0R0402-PAD

1 2

R1817 0R0402-PADR1817 0R0402-PAD

1 2

KBC CLK EMI

R1818 10KR2J-3-GPR1818 10KR2J-3-GP

FFS_INT2_R

RN1803

R1814

R1814 8K2R2J-3-GP

8K2R2J-3-GP

TP1801TPAD14-GP TP1801TPAD14-GP

TP1802TPAD14-GP TP1802TPAD14-GP

4

1

CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

DGPU_SELECT#

BBS_BIT1

PCI_GNT3#

INT_PIRQE# INT_ PIRQF# INT_PIRQG# INT_PIRQH#

PCI_PME#

PCI_PLTRST#

3D3V_S5

3

PCH1E

Cougar

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

H3

AH12

AM4 AM5

Y13 K24

L24 AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

K40 K38 H38

G38

C46 C44 E40

D47 E42 F46

G42 G40

C42 D44

K10

C6

H49 H43

J48 K42 H40

USB_OC#2_3

Cougar

TP1

Point

TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO 5

PME#

PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

COUGAR-GP-U2-NF

OC[3:0]# for Device 29 (Ports 0-7) OC[7:4]# for Device 26 (Ports 8-13)

3

NVRAM

RSVD

PCI

USB

RN1802

1 2 3 4 5 6

SRN8K2J-2-GP-U

5 OF 10

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD

DF_TVS

RSVD

RSVD RSVD

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

10

USB_OC#12_13

9

USB_OC#8_9USB_OC#6_7

8

USB_OC#10_11USB_OC#0_1

7

USB_OC#4_5

2

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

NV_ALE

AV5

NV_CLE

AY1

NV_RCOMP

AV10

AT8

AY5 BA2

AT12

USB Ext. port 1 (HS)

BF3

External debug port use on Huron river platform

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_RBIAS

C33

B33

USB_OC#0_1

A14

USB_OC#2_3

K20

USB_OC#4_5

B17

USB_OC#6_7

C16

USB_OC#8_9

L16

USB_OC#10_11

A16

USB_OC#12_13

D14 C14

3D3V_S5

TP1803 TPAD14-GPTP1803 TPAD14-GP

1

USB_PN1 (57) USB_PP1 (57) USB_PN2 (64) USB_PP2 (64) USB_PN3 (63) USB_PP3 (63) USB_PN4 (82) USB_PP4 (82) USB_PN5 (32) USB_PP5 (32)

USB_PN11 (65) USB_PP11 (65) USB_PN12 (49) USB_PP12 (49)

1 2

R1811

R1811 22D6R2F-L1-GP

22D6R2F-L1-GP

FFS_INT2_R (79)

2

NV_CLE

DMI & FDI Termination Voltage

NV_CLE

USB_OC#0_1 (61)

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

1D8V_S0

12

R1808

R1808 2K2R2J-2-GP

2K2R2J-2-GP

R1809

1 2

1KR2J-1-GP

H_SNB_IVB# (5)

Set to Vss when LOW

Set to Vcc when HIGH

Danbury Technology: Disabled when Low. Enable when High.

USB Table

Pair

X

0

E-SATA / USB Combo

1

Fingerprint

2

BLUETOOTH

3

Mini Card2 (WWAN)

4

CARD READER

5

X

6

X

7

X

8

X

9

X

10

Mini Card1 (WLAN)

11

CAMERA

12

X

13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH 2/9(PCI/USB/NVRAM)

Nirvana 13

1

NV_ALE

Device

1

1D8V_S0

12

R1810

R1810 1KR2J-1-GP

1KR2J-1-GP

DY

A00

of

18 104Tuesday, January 18, 2011

A00

5

4

3

2

1

1 2

1 2 3 45

12

12 12

12

DMI_RXN[3:0](4)

DMI_RXP[3:0](4 )

DMI_TXN[3:0](4)

DMI_TXP[3:0](4)

DMI_RXN0(4) DMI_RXN1(4) DMI_RXN2(4) DMI_RXN3(4)

DMI_RXP0(4) DMI_RXP1(4) DMI_RXP2(4) DMI_RXP3(4)

DMI_TXN0(4) DMI_TXN1(4) DMI_TXN2(4) DMI_TXN3(4)

DMI_TXP0(4 ) DMI_TXP1(4 ) DMI_TXP2(4 ) DMI_TXP3(4 )

1 2

R1903 0R0402-PADR1903 0R0402-PAD

1 2

R1925 0R0402-PADR1925 0R0402-PAD

1 2

DY

PWROK

R1907

1 2

0R2J-2-GP

DY

BATLOW# PM_RI# PCH_WAKE# SUS_PWR_ACK

AC_PRESENT

PM_PWRBTN# PM_SLP_LAN#

PM_RSMRST#

DMI_COMP_R

RBIAS_CPY

SUSACK#SUS_PWR_ACK

SYS_RESET#

R1905

10KR2J-3-GP

R1923

1 2

0R2J-2-GP

DY

R1906 0R0402-PADR1906 0R0402-PAD

1 2

MEPWROK

PM_RSMRST#

BATLOW#

PM_RI#

PCH1C

BC24

DMI0RXN

Cougar

BE20 BG18 BG20

BE24 BC20

BJ18

BJ20

AW24 AW20

BB18

AV18

AY24

AY20

AY18 AU18

BJ24

BG25

BH21

C12

K3

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

COUGAR-GP-U2-NF

4

Cougar

DMI1RXN

Point

DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPW RDNACK/GPIO30

PWRBTN#

ACPRESENT/GPIO31

BATLOW#/GPI O72

RI#

3 OF 10

BJ14

FDI_RXN0

AY14

FDI_RXN1

BE14

FDI_RXN2

BH13

FDI_RXN3

BC12

FDI_RXN4

BJ12

FDI_RXN5

BG10

FDI_RXN6

BG9

FDI_RXN7

BG14

FDI_RXP0

BB14

FDI_RXP1

BF14

FDI_RXP2

BG13

FDI_RXP3

BE12

FDI_RXP4

BG12

FDI_RXP5

BJ10

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#/GPIO29

BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

DSWODVREN

PCH_DPWROK

PM_SUS_STAT#

SUS_CLK

PM_SLP_S5#

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PM_SLP_LAN#

3

FDI_TXN[7:0] (4) FDI_TXP[7:0] (4)

FDI_TXN0 (4) FDI_TXN1 (4) FDI_TXN2 (4) FDI_TXN3 (4) FDI_TXN4 (4) FDI_TXN5 (4) FDI_TXN6 (4) FDI_TXN7 (4)

FDI_TXP0 (4) FDI_TXP1 (4) FDI_TXP2 (4) FDI_TXP3 (4) FDI_TXP4 (4) FDI_TXP5 (4) FDI_TXP6 (4) FDI_TXP7 (4)

FDI_ INT (4)

FDI_FSYNC0 (4)

FDI_FSYNC1 (4)

FDI_LSYNC0 (4)

FDI_LSYNC1 (4)

DY

1

PM_RSMRST#

R1910 0R0402-PADR1910 0R0402-PAD

1 2

R1911 10KR2J-3-GP

1 2

PCH_WAKE# (27)

PM_CLKRUN# (27)

TP1901 TPAD14-GPTP1901 TPAD14-GP

R1913 0R0402-PADR1913 0R0402-PAD

1 2

TP1902 TPAD14-GPTP1902 TPAD14-GP

TP1903TPAD14-GPTP1903TPAD14-GP

TP1904TPAD14-GPTP1904TPAD14-GP

H_PM_SYNC (5)

TP1905TPAD14-GPTP1905TPAD14-GP

R1912

1 2

0R0402-PAD

For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)

2.DPWROK and RSMRST# will rise at the same time (connected on board)

3.SLP_SUS# and SUSACK# are left as ‘no connect’

4.SUSWARN# used as SUSPWRDNACK/GPIO30

PM_RSMRST#

RSMRST#_KBC (27)

PCH_SUSCLK_KBC

EC1901

1 2

DY

SC4D7P50V2CN-1GP

RTC_AUX_S5

PCH_SUSCLK_KBC (27)

PM_SLP_S4# (27,46)

PM_SLP_S3# (27,36,37,46,47)

2

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1 2

DSWODVREN

PM_CLKRUN#

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Nirvana 13

R1918 330KR2J-L1-GP

1 2

DY

R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH 3/9(DM I/FDI/PM)

19 104Tuesday, January 18, 2011

1

RTC_AUX_S5

3D3V_S0

of

A00

SSID = PCH

D D

Signal Routing Guideline: DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

1D05V_VTT

R1901 49D9R2F-GPR1901 49D9R2F-GP

R1902 750R2F-GPR1902 750R2F-GP

SYS_PWROK

R1926

XDP_DBRESET#(5 )

S0_PWR_GOOD(27,36)

PM_PWRBTN#(27)

DY

SYS_PWROK(36)

RUNPWROK(45,46,47)

3D3V_S5

R1926

PWROK

R1904

3D3V_S0

1 2

R1924 0R0402-PADR1924 0R0402-PAD

RN1901

8 7 6

SRN10KJ-6-GP

R1921

100KR2J-1-GP

R1922 10KR2J-3-GP

DY

R1920 10KR2J-3-GP

DY

R1908

10KR2J-3-GP

5

C C

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

B B

A A

1 2

10KR2J-3-GP

1 2

100KR2J-1-GP

PM_DRAM_PWRGD(5,37)

SUS_PWR_ACK(27)

AC_PRESENT(27)

5

SSID = PCH

D D

C C

::$1&/.

:/$1&/.

B B

86%&/.

A A

PCIE_RXN2(82)

PCIE_RXP2(82) PCIE_TXN2(82) PCIE_TXP2(82)

PCIE_RXN3(82)

PCIE_RXP3(82) PCIE_TXN3(82) PCIE_TXP3(82)

PCIE_RXN4(65)

PCIE_RXP4(65) PCIE_TXN4(65) PCIE_TXP4(65)

PCIE_RXN5(82)

PCIE_RXP5(82) PCIE_TXN5(82) PCIE_TXP5(82)

CLK_PCIE_WWAN#(82) CLK_PCIE_WWAN(82)

CLK_PCIE_WWAN_REQ#(82)

CLK_PCIE_WLAN_REQ#(65)

CLK_PCIE_LAN#(82)

/$1&/.

3D3V_S0

PCIECLKRQ1# and PCIECLKRQ2#

CLK_PCIE_LAN(82)

PCIE_CLK_LAN_REQ#(82)

USB3_PEGB_CLKREQ#(82)

RN2018

1 2 3

SRN10KJ-5-GP

C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP

1 2

C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP

1 2

C2011 SCD1U10V2KX-5GPC2011 SCD1U10V2KX-5GP

1 2

C2012 SCD1U10V2KX-5GPC2012 SCD1U10V2KX-5GP

1 2

C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP

1 2

C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP

1 2

C2009 SCD1U10V2KX-5GPC2009 SCD1U10V2KX-5GP

1 2

C2010 SCD1U10V2KX-5GPC2010 SCD1U10V2KX-5GP

1 2

20101224 A00: Change RN2011~RN2014 to 0402 0 ohm pad.

CLK_PCIE_WLAN#(65) CLK_PCIE_WLAN(65)

CLK_PCIE_USB3#(82)

CLK_PCIE_USB3(82)

PCIE_CLK_RQ2#

4

CLK_PCIE_WLAN_REQ#

Support S0 power only

5

RN2011

1 2 3

0R4P2R-PAD

RN2012

2 3 1

0R4P2R-PAD

RN2014

2 3 1

0R4P2R-PAD

RN2013

1 2 3

0R4P2R-PAD

TP2005TPAD14-GP TP2005TPAD14-GP TP2006TPAD14-GP TP2006TPAD14-GP

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN3_C PCIE_TXP3_C

PCIE_TXN4_C PCIE_TXP4_C

PCIE_TXN5_C PCIE_TXP5_C

RN

CLK_PCH_SRC0_N

4

CLK_PCH_SRC0_P

CLK_PCH_SRC1_N

4

RN

PCIE_CLK_RQ2#

CLK_PCH_SRC3_N CLK_PCH_SRC3_P

4

RN

CLK_PCH_SRC4_N

4

CLK_PCH_SRC4_P

PCIE_CLK_REQ5#

PEG_B_CLKRQ#

PCIE_CLK_REQ6#

CLK_PCIE_NEW_REQ#

1 1

ITPXDP_N ITPXDP_P

4

PCH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1#/GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2#/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4#/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5#/GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

COUGAR-GP-U2-NF

4

3

2 OF 10

Cougar

Cougar Point

Point

LAN

W-WAN

WLAN

USB3.0

PCI-E*

Intel GBE LAN

Dock

SMBALERT#/GPIO11

SMBDATA

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPI O74

Link

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_DATA1

CL_RST1#

SMBCLK

SML0CLK

CL_CLK1

EC_SWI#

E12

SMB_CLK

H14

SMB_DATA

C9

DRAMRST_CNTRL_PCH

A12

SML0_CLK

C8

SML0_DATA

G12

PCH_GPIO74

C13

SML1_CLK

E14

SML1_DATA

M16

CL_CLK

M7

CL_DATA

T11

CL_RST#

P10

1

TP2001 TPAD14-GPTP2001 TPAD14-GP

1

TP2002 TPAD14-GPTP2002 TPAD14-GP

1

TP2003 TPAD14-GPTP2003 TPAD14-GP

NEW CARD

PEG_CLKREQ#_R

XTAL25_IN

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43

F47

H47

K49

3

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_PCLK_PCH_SRC1_P

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

CLK_BUF_REF14

CLK_PCI_FB

XTAL25_IN XTAL25_OUT

XCLK_RCOMP

JTAG_TCK

CLK_48_USB30

CLKOUTFLEX2

DGPU_PRSNT#

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLOCKS

– Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 – Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2 if more than 2 PCI clocks + PCI loopback are routed.

CLKOUT_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

FLEX CLOCKS

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

XTAL25_OUT

XCLK_RCOMP

1 2

DY

RN2016

1 2 3

0R4P2R-PAD

RN2010

2 3 1

0R4P2R-PAD

20101224 A00: Change RN2016,RN2010 to 0402 0 ohm pad.

RN2008 SRN10KJ-5-GPRN2008 SRN10KJ-5-GP

CLK_PCI_FB (18)

R2007

1 2

90D9R2F-1-GP

1

+VCCDIFFCLKN

R2001

1 2

DY

22R2J-2-GP

R2016

1 2

22R2J-2-GP

TP2007 TPAD14-GPTP2007 TPAD14-GP

2

PEG_CLKREQ# (85)

CLK_PCIE_VGA# (83) CLK_PCIE_VGA (83)

CLK_EXP_N (5) CLK_EXP_P (5)

4

PEG_CLKREQ#_R

SMB_DATA

SMB_CLK

20110112 A00: Change C2007,C2008 to 15pF from 12pF base on vendor's report.

EC_SWI# (27)

DRAMRST_CNTRL_PCH (37)

SML1_CLK (27,85)

SML1_DATA (27,85)

R2003

RN

0R2J-2-GP

4

RN

2 3 1

PL 10K FOR Integrated CLOCK GEN mode.

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_REF14

need very close to PCH

JTAG_TCK_VGA (83,85)

CLK_PCH_48M (32,97)

RN2020 SRN10KJ-5-GPRN2020 SRN10KJ-5-GP

1 2 3

RN2021

2 3 1

RN2019 SRN10KJ-5-GPRN2019 SRN10KJ-5-GP

1 2 3

R2008

1 2

10KR2J-3-GP

For RTS5138

For VGA_ 27M

2

3D3V_S5

DY

4

1

12

R2004

R2004 10KR2J-3-GP

10KR2J-3-GP

12

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

RN2007

2 3 1

SRN2K2J-1-GP

2nd = 84.DM601.03F

84.2N702.A3F

2N7002KDW-GP

6

5

Q2001

XTAL25_IN

XTAL25_OUT

3D3V_S0 3D3V_S0

12

R2012

12

R2010

DY

SRN10KJ-5-GP

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

SMB_CLK SMB_DATA

SML0_DATA SML0_CLK

SML1_CLK SML1_DATA

PCIE_CLK_REQ6# PCH_GPIO74

DRAMRST_CNTRL_PCH

4

1

2

34

R2006

R2006 1M1R2J-GP

1M1R2J-GP

2 3

1 2

12

R2013

DY

UMA_DIS# DGPU_PRSNT#

10KR2J-3-GP

12

R2011

10KR2J-3-GP

3D3V_S5

PCH 4/9(PCI-E/SMBUS/CLOCK/CL)

Nirvana 13

4

2 3 1

1 2 3

R2009

1 2

1KR2J-1-GP

PCH_SMBDATA (14,15,65,79,82)

PCH_SMBCLK (14,15,65,79,82)

X2001

XTAL-25MHZ-155-GP

82.30020.D41

2nd = 82.30020.G71

2nd = 82.30020.G71 3rd = 82.30020.G61

3rd = 82.30020.G61

UMA_DISCRETE# UMA: 1 1 DIS :0 1 SG(PX) : 0 0 ATI(Muxless) : 1 0

1 2 3 4 5

SC15P50V2JN-2-GP

41

SC15P50V2JN-2-GP

UMA_DIS# (22)

RN2001

8 7 6

SRN10KJ-6-GP

SRN10KJ-6-GP RN2002

RN2002

8 7 6

SRN10KJ-6-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

3D3V_S5

RN2003

1

SRN2K2J-1-GP

23

RN2004

23

SRN2K2J-1-GP

1

RN2005

RN2005 SRN2K2J-1-GP

SRN2K2J-1-GP

4

RN2006

4

SRN10KJ-5-GP

C2008

12

C2007

12

CLK_PCIE_WWAN_REQ#

PCIE_CLK_LAN_REQ# USB3_PEGB_CLKREQ#

EC_SWI# PCIE_CLK_REQ5# CLK_PCIE_NEW_REQ# PEG_B_CLKRQ#

of

20 104Tuesday, January 18, 2011

A00

5

SSID = PCH

RTC_X1

1 2

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

D D

C2101

SC15P50V2JN-2-GP

C C

X2101

1 4

12

X-32D768KHZ-67-GP

82.30001.A81

2nd = 82.30001.691

3rd = 82.30001.861

HDA_CODEC_SYNC(29) HDA_CODEC_SDOUT(29)

HDA_CODEC_RST#(29) HDA_CODEC_BITCLK(29)

32

RTC_X2

12

C2102

C2102 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

DY

RN2102

1 2 3

SRN33J -5-GP-U

R212233R2J-2-GP

12

R212333R2J-2-GP R212333R2J-2-GP

12

4

HDA_SYNC HDA_SDOUT

HDA_RST# HDA_BITCLK

RTC_AUX_S5

Flash Descriptor Security Overide

+3VS_+1.5VS_HDA_IO

DY

R2102 1KR2J-1-GP

1 2

3D3V_S0

B B

NO REBOOT STRAP

DY

R2106 1KR2J-1-GP

1 2

+3VS_+1.5VS_HDA_IO

This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310

1 2

HDA_SDO UT

HDA_SDOUT

HDA_SPKR

R2103 1KR2J-1-GPR2103 1KR2J-1-GP

Low = Default High = Enable

No Reboot Strap

Low = Default High = No Reboot

HDA_SYNC

PLL ODVR VOLTAGE

2N7002K-2-GP

G

S

Q2101

R2117

84.2N702.J31

100KR2J-1-GP

2ND = 84.2N702.031

Low = 1.8V (Default) High = 1.5V

D

5

R2124

33R2J-2-GP

HDA_SYNCHDA_SYNC_R

12

DY

HDA_SYNC

RUN_ENABLE

A A

1 2

4

RN2101

2 3 1

4

SRN20KJ-1-GP

C2104

SC1U6D3V2KX-GP

20110110 A00: Merge R2115,R2116 to RN2101. 20110113 A00: Swap RN2101 base on swap report.

12

C2103

C2103 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

21

G2101

12

GAP-OPEN

RTC_AUX_S5

INTVRMEN- Integrated SUS

1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs

1M1R2J-GP

R2104

12

1 2

R2105

330KR2F-L-GP

HDA_SPKR(29)

HDA_SDIN0(29)

3

RTC_X1

RTC_X2

RTC_RST#

SRTC_RST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BITCLK

HDA_SYNC

HDA_RST#

Notes: ME_UNLOCK (HDA_SDO) connect to EC. Make sure EC drive this pin "low" all the time.

R2107 1KR2J-1-GPR2107 1KR2J-1-GP

ME_UNLOCK(27)

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

HDA_CODEC_BITCLK

EC2102

1 2

SC4D7P50V2CN-1GP

4

HDA_CODEC_SDOUT

EC2103

1 2

DY

SC4D7P50V2CN-1GP

1 2

SPI_CLK_R(27,60)

SPI_CS0#_R(27,60)

SPI_SI_R(27,60)

SPI_SO_R(27,60)

SPI_CS0#_RHDA_CODEC_SYNC

EC2101

1 2

DY

HDA_SDOUT

CE(49)

TP2101TPAD14-GP TP2101TPAD14-GP

TP2102TPAD14-GP TP2102TPAD14-GP

TP2103TPAD14-GP TP2103TPAD14-GP

TP2104TPAD14-GP TP2104TPAD14-GP

1 2

R2108 33R2J-2-GPR2108 33R2J-2-GP

1 2

R2109 33R2J-2-GPR2109 33R2J-2-GP

1 2

R2110 33R2J-2-GPR2110 33R2J-2-GP

SC4D7P50V2CN-1GP

CE

PCH_JTAG_TCK_BUF

1

PCH_JTAG_TMS

1

PCH_JTAG_TDI

1

PCH_JTAG_TDO

1

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_SI

EC_SMI#(22,27)

3

A20

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34

G34

C34

A34

A36

C36

N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

S_GPIO(22)

FP_DET#(22) PSW_CLR#(22)

PCH1A

Cougar

RTCX1

Point

RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN#/GPIO33

HDA_DOCK_RST#/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

COUGAR-GP-U2-NF

SATA_DET#0 INT_ SERIRQ

EC_SMI#

1 2 3 4 5

4

RTCIHDA

JTAG

SPI

RN2103

8 7 6

SRN10KJ-6-GP

SRN10KJ-6-GP RN2104

RN2104

1 23

SRN10KJ-5-GP

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

3D3V_S0

2

C38 A38 B37 C37

D36

E36 K36

V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

SATA_DET#0

BBS_BIT0

1

LPC_AD [0..3]

LPC_FRAME# (27,65,71)

KB_DET# (69)

INT_ SERIRQ (27 )

SATA_COMP

SATA3_COMP

RBIAS_SATA3

R2112 37D4R2F-GPR2112 37D4R2F-GP

R2113 49D9R2F-GPR2113 49D9R2F-GP

R2114 750R2F-GPR2114 750R2F-GP

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

LPC_AD[0..3] (27,65,71)

SATA_RXN0 (56) SATA_RXP0 (56) SATA_TXN0 (56) SATA_TXP0 (56)

SATA_RXN4 (56) SATA_RXP4 (56) SATA_TXN4 (56) SATA_TXP4 (56)

SATA_RXN5 (57) SATA_RXP5 (57) SATA_TXN5 (57) SATA_TXP5 (57)

1D05V_VTT

1 2

SATA_LED# (68)

BBS_BIT0 (18)

PCH 5/9(SPI/RTC/LPC/SATA/IHDA)

1D05V_VTT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

1

21 104Tuesday, January 18, 2011

HDD1

HDD2

ODD

ESATA

of

A00

5

4

3

2

1

3D3V_S0

R2202

1 2

100KR2J-1-GP

3D3V_S0

RN2203

1

D D

SRN10KJ-5-GP

GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.

3D3V_S0

R2220

1 2

10KR2J-3-GP

PCH_TEMP_ALERT#

MFG_MODE

C C

EC_SCI#

DGPU_HPD_INTR#

DBC_EN

20100104 A00: Merge RN2215,R2216 to RN2201 10k array resistor.

RTC_DET# PCH_GPIO57

B B

PCH_GPIO15

3G_EN

2 3

PCH_GPIO48

SRN10KJ-5-GP

4

RN2202

1 2 3

RN2204

1 2 3

R2214 10KR2J-3-GP

1 2

DY

RN2201

1 2 3

SRN10KJ-5-GP

R2217

1 2

DY

10KR2J-3-GP

1 2

SATA_ODD_PRSNT#

H_A20GATE

H_RCIN#

20100104 A00: Merge RN2201,R2222,R2223 to 10k array resistor. 20110113 A00: Combine PCH_TEMP_ALERT#,MFG_MODE to RN2202. Combine EC_SCI#,DGPU_HPD_INTR# to RN2204

3D3V_S0

4

3D3V_S5

4

R2201

1KR2J-1-GP

R2221

10KR2J-3-GP

Note: For PCH debug with XDP, need to NO STUFF R2218

PSW_CLR#(21)

For thermal sensor detection.

3D3V_S0

12

R2224

R2224 10KR2J-3-GP

10KR2J-3-GP

DY

VRAM_SIZE1

A A

12

DY

5

R2225

R2225 10KR2J-3-GP

10KR2J-3-GP

SSID = PCH

S_GPIO GPIO0

EC_SMI#(21,27)

EC_SCI#(27)

RTC_DET#(60)

R2213 0R0402-PADR2213 0R0402-PAD

DGPU_PWROK(86,92,93)

DBC_EN(49)

3G_EN(82)

TP2203

PSW_CLR#

FP_DET#(21)

21

G2201

TP2206TPAD14-GP TP2206TPAD14-GP

TP2207TPAD14-GP TP2207TPAD14-GP

TP2208TPAD14-GP TP2208TPAD14-GP

TP2209TPAD14-GP TP2209TPAD14-GP

1 2

1

SATA_ODD_PRSNT#(56)

GAP-OPEN

4

S_GPIO(21)

TPAD14-GP

R2218

1 2

100R2J-2-GP

EC_SMI#

DGPU_HPD_INTR#

EC_SCI#

ICC_EN#

RTC_DET#

PCH_GPIO15

DGPU_PWROK

DBC_EN

3G_EN

PCH_GPIO27

1

PLL_ODVR_EN

DMI_OVRVLTG

FDI_OVRVLTG

MFG_MODE

GSENSOR_DET

PCH_GPIO48

PCH_TEMP_ALERT#

PCH_GPIO57

PCH_NCTF_1

PCH_NCTF_2

PCH_NCTF_3

PCH_NCTF_4

PCH_GPIO16

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/G PIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24/MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49

D6

GPIO57

A4

NCTF_VSS#A4

A44

NCTF_VSS#A44

A45

NCTF_VSS#A45

A46

NCTF_VSS#A46

A5

NCTF_VSS#A5

A6

NCTF_VSS#A6

B3

NCTF_VSS#B3

B47

NCTF_VSS#B47

BD1

NCTF_VSS#BD1

BD49

NCTF_VSS#BD49

BE1

NCTF_VSS#BE1

BE49

NCTF_VSS#BE49

BF1

NCTF_VSS#BF1

BF49

NCTF_VSS#BF49

COUGAR-GP-U2-NF

6 OF 10

A20GATE

PECI

RCIN#

INIT3_3V#

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

UMA_DIS#

VRAM_SIZE1

VRAM_SIZE2

TS_VSS

H_PECI_R

PCH_THERMTRIP_R

INIT3_3V#

3D3V_S0

ICC_EN#

R2219 0R0402-PADR2219 0R0402-PAD

Cougar

Cougar Point

Point

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49

BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

PROCPWRGD

GPIO

THRMTRIP#

CPU/MISC

NCTF_VSS#BG2

NCTF_VSS#BG48

NCTF_VSS#BH3

NCTF_VSS#BH47

NCTF_VSS#BJ4

NCTF_VSS#BJ44

NCTF_VSS#BJ45

NCTF_VSS#BJ46

NCTF_VSS#BJ5

NCTF

NCTF_VSS#BJ6

NCTF_VSS#C2

NCTF_VSS#C48

NCTF_VSS#D1

NCTF_VSS#D49

NCTF_VSS#E1

NCTF_VSS#E49

NCTF_VSS#F1

D1,D49,E1,E49,F1,F49

NCTF_VSS#F49

PLL ON DIE VR ENABLE



NOTE:This signal has a weak internal pull-up 20K ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED)

PLL_ODVR_EN

3

1 2

DY

R2212

1KR2J-1-GP

1

1 2

12

R2207

R2207 10KR2J-3-GP

10KR2J-3-GP

DY

FDI_OVRVLTG

12

R2208

R2208 10KR2J-3-GP

10KR2J-3-GP

12

R2209

R2209 10KR2J-3-GP

10KR2J-3-GP

DY

DMI_OVRVLTG

12

R2210

R2210 10KR2J-3-GP

10KR2J-3-GP

R2211

1 2

SATA_ODD_PWRGT (56)

UMA_DIS# (20)

TP2204

TPAD14-GP

TP2205

TPAD14-GP

H_A20GATE (27)

R2203

1 2

DY

H_RCIN# (27)

R2204 390R2J-1-GPR2204 390R2J-1-GP

TP2201

1

0R2J-2-GP

H_CPUPWRGD (5,36)

1 2

TPAD14-GP

TS Signal Disable Guideline: TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4 should not float on the motherboard. They should be tied to GND directly.

FDI TERMINATION VOLTAGE OVERRIDE

GPIO37 (FDI_OVRVLTG)

DMI TERMINATION VOLTAGE OVERRIDE

GPIO36 (DMI_OVRVLTG)

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

Integrated Clock Chip Enable

ICC_EN#

1KR2J-1-GP

GPIO8 has a weak[20K] internal pull up.

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

2

GSENSOR_ADI GSENSOR_ST

R2205 DY 10K

R2206 100K DY

3D3V_S0

12

R2205

10KR2J-3-GP

GSENSOR_DET

12

10KR2J-3-GP

R2206

100KR2J-1-GP

GSENSOR_ST

H_PECI (5,27)

H_THERMTRIP# (5,36)

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

GSENSOR_ADI

HIGH (R2211 DY)- DISABLED [DEFAULT]

LOW (R2211)- ENABLED

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

PCH 6/9(GPIO/CPU)

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

of

22 104Tuesday, January 18, 2011

1

A00

5

4

3

2

1

SSID = PCH

D D

C C

B B

VCCVRM(Internal PLL and VRMs): A.1.5V for Mobile B.1.8 V for Desktop

(1uFx3)

(10uFx1_0603)

(1uF x4)

0.159A(Totally current of VCCVRM)

6A

1D05V_VTT

2.925A(Total current of VCCIO)

12

C2305

0.266A (Totally VCC3_3 current)

0.042A (Totally current of VCCDMI)

1.3A

12

C2301

SC10U6D3V5KX-1GP

12

C2306

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

(0.1uF x1)

1D5V_S0

12

C2302

TP2301TPAD14-GP TP2301TPAD14-GP

12

C2307

TP2302TPAD14-GP TP2302TPAD14-GP

1D05V_VTT

12

C2303

SC1U6D3V2KX-GP

1D05V_VTT

1

12

3D3V_S0

1

SC1U6D3V2KX-GP

(10uF x1)

C2308

SC1U6D3V2KX-GP

12

C2304

SC1U6D3V2KX-GP

VCCAPLLEXP

12

C2309

SC1U6D3V2KX-GP

12

C2310

C2310 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

VCCFDIPLL

+1.05VS_VCC_DMI

PCH1G

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO

BJ22

VCCAPLLEXP

AN16

VCCIO

AN17

VCCIO

AN21

VCCIO

AN26

VCCIO

AN27

VCCIO

AP21

VCCIO

AP23

VCCIO

AP24

VCCIO

AP26

VCCIO

AT24

VCCIO

AN33

VCCIO

AN34

VCCIO

BH29

VCC3_3

AP16

VCCVRM

BG6

VCCAFDIPLL

AP17

VCCIO

AU20

VCCDMI

COUGAR-GP-U2-NF

POWER

Cougar

Cougar Point

Point

VCC CORE

VCCIO

FDI

CRTLVDS

DMI

NAND / SPI HVCMOS

7 OF 10

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS

VCC3_3

VCCVRM

VCCDMI

VCCCLKDMI

VccDFTERM

VCCSPI

0.001A

U48

U47

0.001A

+3VS_VCCA_LVDS

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

0.16A

AT16

0.042A

+1.05VS_VCC_DMI

AT20

AB36

0.02A

+1.05VS_VCC_DMI_CCI

AG16

AG17

AJ16

AJ17

V1

20101228 A00: 0402 0R pad: R2301.

(0.1uF/0.01uF x1) (10uF x1_0603)

+VCCA_DAC_1_2

12

C2313

0.06A

+1.8VS_VCCTX_LVDS

0.266A

12

0.19A

12

C2322

C2322 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

0.02A

12

C2314

SCD01U16V2KX-3GP

12

C2316

(0.1uFx1)

C2319

C2319 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

VCCVRM

R2306

0R0402-PAD

0.02A

0R0402-PAD

R2307

0R0402-PAD

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2321

C2321 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

3D3V_DAC_S0

12

R2301

R2301 0R0402-PAD

0R0402-PAD

12

C2315

0.001A

SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

0.06A

12

C2317

SCD01U16V2KX-3GP

R2308

0R0402-PAD

12

SCD01U16V2KX-3GP

3D3V_S0

1D05V_VTT

(1uFx1) (10uFx1)

SCD01U16V2KX-3GP

0.19A

0.02A

(1uFx1)

3D3V_S0

L2301

1 2

DY

HCB1608KF-181-GP

68.00214.051

2nd = 68.00206.041

3rd = 68.00335.081

R2304

1 2

0R0603-PAD

R2305

1 2

0R0805-PAD

12

C2318

12

0R0805-PAD

(0.01uF x2) (22uF x1)

SC10U6D3V5KX-1GP

20101224 A00: 0402 0R pad: R2301,R2306,R2307,R2308.

1D5V_S0

(1uF x1)

1D8V_S0

(0.1uFx1)

3D3V_S5

3D3V_S0

1D8V_S0

3.3V CRT LDO

5V_S5 3D3V_DAC_S0

3D3V_S0

U2301

1

VIN

2

A A

5

12

C2311

SC1U10V2KX-1GP

4

GND EN3NC#4

G9091-330T11U-GP

74.09091.J3F

2nd = 74.09198.G7F

3rd = 74.07716.A7F

VOUT

5

4

Current Limit=360mA

12

C2312

SC1U6D3V2KX-GP

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

PCH 7/9(POWER1)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

A00

of

23 104Tuesday, January 04, 2011

1

A00

5

SSID = PCH

0.002A

3D3V_S0

(10uFx1)

D D

C C

1D05V_VTT

B B

1D05V_VTT

A A

L2401

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

L2402

L2403

R2404

12

0R0402-PAD

R2405

12

0R0402-PAD

0.08A

C2443

DY

0.08A

C2444

DY

5

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

20101224 A00: 0402 0R pad: R2404,R2405.

+1.05VS_VCCA_A_DPL

12

+1.05VS_VCCA_B_DPL

12

+VCCDIFFCLK

12

SC1U6D3V2KX-GP

+V1.05S_SSCVCC

12

SC1U6D3V2KX-GP

(1uFx1)

+V3.3S_VCC_CLKF33

C2401

12

(22uFx2_0603) (1uFx3)

(1uFx1) (220uFx1)

12

SC10U6D3V3MX-GP

12

SC10U6D3V3MX-GP

C2412

C2413

12

C2402

C2402 SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC10U6D3V5KX-1GP

1D05V_VTT

C2409

C2409 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

(1uFx1) (220uFx1)

C2410

C2410 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

1D05V_VTT

(1uFx1)

3D3V_S5

(0.1uFx1)

C2403

12

SC10U6D3V5KX-1GP

12

C2411

R2406

1 2

0R0603-PAD

SC1U6D3V2KX-GP

(0.1uFx1)

(1uFx1)

1D05V_VTT

0.001A

(0.1uFx2) (4.7uFx1_0603)

SC4D7U6D3V3KX-GP

RTC_AUX_S5

6uA

(0.1uFx2) (1uFx1)

1.01A (Total current of VCCASW)

C2404

SC10U6D3V5KX-1GP

+VCCRTCEXT

(0.1uFx1)

+VCCDIFFCLKN

C2414

C2417

4

1

TP2405TPAD14-GP TP2405TPAD14-GP

1

(10uFx1)

1

12

VCCACLK

+VCCPDSW

DCPSUSBYP

1

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

+VCCSUS1

12

C2407

C2408

SC1U6D3V2KX-GP

TP2401TPAD14-GP TP2401TPAD14-GP

R2403

1 2

0R0603-PAD

TP2404TPAD14-GP TP2404TPAD14-GP

1D05V_VTT

TP2402TPAD14-GP TP2402TPAD14-GP

12

C2406

SC1U6D3V2KX-GP

0.16A (Totally current of VCCVRM

1D5V_S0

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

+VCCDIFFCLK

0.055A

12

(1uFx1)

0.095A

SCD1U10V2KX-5GP

4

+V1.05S_SSCVCC

C2415

+VCCSST

12

TP2406TPAD14-GP TP2406TPAD14-GP

12

C2418

SCD1U10V2KX-5GP

12

C2421

SCD1U10V2KX-5GP

(1uFx1)

1

12

C2422

DCPSUS

SCD1U10V2KX-5GP

PCH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3

BH23

VCCAPLLDMI2

AL29

VCCIO

AL24

DCPSUS

AA19

VCCASW

AA21

VCCASW

AA24

VCCASW

AA26

VCCASW

AA27

VCCASW

AA29

VCCASW

AA31

VCCASW

AC26

VCCASW

AC27

VCCASW

AC29

VCCASW

AC31

VCCASW

AD29

VCCASW

AD31

VCCASW

W21

VCCASW

W23

VCCASW

W24

VCCASW

W26

VCCASW

W29

VCCASW

W31

VCCASW

W33

VCCASW

N16

DCPRTC

Y49

VCCVRM

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO

AF33

VCCDIFFCLKN

AF34

VCCDIFFCLKN

AG34

VCCDIFFCLKN

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS

V19

DCPSUS

BJ8

V_PROC_IO

A22

VCCRTC

COUGAR-GP-U2-NF

3

10 OF 10

POWER

Cougar

Cougar Point

Point

Clock and Miscellaneous

PCI/GPIO/LPCMISC

SATA USB

CPURTC

HDA

3

10 OF 10

VCCIO

VCCSUS3_3

VCCIO

V5REF_SUS

DCPSUS

VCCSUS3_3

V5REF

VCCSUS3_3

VCC3_3

VCCIO

VCCAPLLSATA

VCCVRM

VCCIO

VCCASW

VCCSUSHDA

N26

P26

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

2

12

(1uFx1)

C2423

C2423 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

0.097A (Totally current of VCCSUS3_3)

(0.1uFx1)

12

C2424

C2424 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

(0.1uFx1)

C2425

C2425 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

TP2403 TPAD14-GPTP2403 TPAD14-GP

1

C2437

C2437 SC1U10V2KX-1GP

SC1U10V2KX-1GP

0.001A

(1uFx1)

12

R2411

1 2

DY

C2434

0R3J-0-U -GP

DY

(1uFx1)

SC10U6D3V5KX-1GP

1D05V_VTT

+5VA_PCH_VCC5REFSUS

+VCCA_USBSUS

+5VS_PCH_VCC5REF

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

+V1.05S_VCCAPLL_SATA3

1D5V_S0

1D05V_VTT

SC1U6D3V2KX-GP

3D3V_S5

C2428

C2430

C2429

C2432

C2435

12

DY

12

+3VS_+1.5VS_HDA_IO

0.01A

(0.1uFx1)

12

C2433

SCD1U10V2KX-5GP

C2433

2

1D05V_VTT

3D3V_S5

2nd = 83.R2004.B8F

3D3V_S5

0.001A

2nd = 83.R2004.B8F

3D3V_S5

3D3V_S0

(0.1uFx2)

C2431

C2431 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

(0.1uFx1)

1D05V_VTT

(1uFx1)

1D05V_VTT

(10uFx1)

1D05V_VTT

1

3D3V_S5

21

D2401

D2401 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

R2408

1 2

10R2J-2-GP

12

C2426

C2426 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

21

D2402

D2402 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

1 2

10R2J-2-GP

12

C2427

C2427 SC1U10V2KX-1GP

SC1U10V2KX-1GP

+3VS_+1.5VS_HDA_IO

R2409

1 2

0R0603-PAD

Title

PCH 8/9(POWER2)

Size Document Number Rev

Date: Sheet of

Date: Sheet

PCH 8/9(POWER2)

Nirvana 13

5V_S5

(0.1uFx1)

5V_S0

R2407

(1uFx1)

3D3V_S5

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

24 104Tuesday, January 04, 2011

1

A00

5

4

3

2

1

SSID = PCHSSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS

AA17

VSS

AA2

VSS

AA3

VSS

AA33

VSS

AA34

VSS

AB11

VSS

AB14

VSS

AB39

VSS

AB4

VSS

AB43

VSS

AB5

VSS

AB7

VSS

AC19

VSS

AC2

VSS

AC21

VSS

AC24

VSS

AC33

VSS

AC34

VSS

AC48

VSS

AD10

VSS

AD11

VSS

AD12

VSS

AD13

VSS

AD19

VSS

AD24

VSS

AD26

VSS

AD27

VSS

AD33

VSS

AD34

VSS

AD36

VSS

AD37

VSS

AD38

VSS

AD39

VSS

AD4

VSS

AD40

VSS

AD42

VSS

AD43

VSS

AD45

VSS

AD46

VSS

AD8

VSS

AE2

VSS

AE3

VSS

AF10

VSS

AF12

VSS

AD14

VSS

AD16

VSS

AF16

VSS

AF19

VSS

AF24

VSS

AF26

VSS

AF27

VSS

AF29

VSS

AF31

VSS

AF38

VSS

AF4

VSS

AF42

VSS

AF46

VSS

AF5

VSS

AF7

VSS

AF8

VSS

AG19

VSS

AG2

VSS

AG31

VSS

AG48

VSS

AH11

VSS

AH3

VSS

AH36

VSS

AH39

VSS

AH40

VSS

AH42

VSS

AH46

VSS

AH7

VSS

AJ19

VSS

AJ21

VSS

AJ24

VSS

AJ33

VSS

AJ34

VSS

AK12

VSS

AK3

VSS

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

8 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS

AY42

VSS

AY46

VSS

AY8

VSS

B11

VSS

B15

VSS

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

F45

VSS

BB12

VSS

BB16

VSS

BB20

VSS

BB22

VSS

BB24

VSS

BB28

VSS

BB30

VSS

BB38

VSS

BB4

VSS

BB46

VSS

BC14

VSS

BC18

VSS

BC2

VSS

BC22

VSS

BC26

VSS

BC32

VSS

BC34

VSS

BC36

VSS

BC40

VSS

BC42

VSS

BC48

VSS

BD46

VSS

BD5

VSS

BE22

VSS

BE26

VSS

BE40

VSS

BF10

VSS

BF12

VSS

BF16

VSS

BF20

VSS

BF22

VSS

BF24

VSS

BF26

VSS

BF28

VSS

BD3

VSS

BF30

VSS

BF38

VSS

BF40

VSS

BF8

VSS

BG17

VSS

BG21

VSS

BG33

VSS

BG44

VSS

BG8

VSS

BH11

VSS

BH15

VSS

BH17

VSS

BH19

VSS

H10

VSS

BH27

VSS

BH31

VSS

BH33

VSS

BH35

VSS

BH39

VSS

BH43

VSS

BH7

VSS

D3

VSS

D12

VSS

D16

VSS

D18

VSS

D22

VSS

D24

VSS

D26

VSS

D30

VSS

D32

VSS

D34

VSS

D38

VSS

D42

VSS

D8

VSS

E18

VSS

E26

VSS

G18

VSS

G20

VSS

G26

VSS

G28

VSS

G36

VSS

G48

VSS

H12

VSS

H18

VSS

H22

VSS

H24

VSS

H26

VSS

H30

VSS

H32

VSS

H34

VSS

F3

VSS

COUGAR-GP-U2-NF

3

Cougar

Cougar Point

Point

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

PCH 9/9(VSS)

Nirvana 13

1

A00

of

25 104Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

26 104Tuesday, January 04, 2011

A00

5

SSID = KBC

3D3V_AUX_KBC

R2771

R2771 2D2R3-1-U-GP

2D2R3-1-U-GP

1 2

12

D D

20101228 A00: VGA_THRM change to USB_PWR_EN. 20101229 A00: Rename USB_PWR_EN to USB3_PWR_ON.

C C

AFTP2701AFTP2701 AFTP2702AFTP2702 AFTP2703AFTP2703

C2701

R2702

1 2

0R0603-PAD

12

C2704

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

USB_PWR_EN#

1

AC_PRESENT

1

E51_TxD

1

C2705

SCD1U10V2KX-5GP

EC_AGND

12

C2706

AC_PRESENT(19)

12

C2707

SCD1U10V2KX-5GP

AD_IA(40)

C2714 SCD1U10V2KX-5GPC2714 SCD1U10V2KX-5GP

1 2

PSID_EC(38)

CPU_THRM(28)

FAN1_DAC(28)

LCD_TST(49)

SUS_PWR_ACK(19)

USBCHARGER_CB0(57)

USB3_PWR_ON(62,82) SYS_THRM(28)

BATT_WHITE_LED#(68)

CAP_LED(69)

S5_ENABLE(36)

MEDIA_BTN3#(82)

BAT_IN#(39)

LID_CLOSE#(70)

RSMRST#_KBC(19)

PM_SLP_S4#(19,46)

ME_UNLOCK(21)

RCID(38)

WIFI_RF_EN(65) BLUETOOTH_EN(63,65) S0_PWR_GOOD(19,36)

TP_LOCK_LED#(68)

USB_PWR_EN#(61)

IMVP_PWRGD(36,42)

C2708

SCD1U10V2KX-5GP

12

EC_AGND

MEDIA_BTN2#

KBC_VCORF

12

C2712

C2712 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

12

C2710

C2709

SC2D2U10V3KX-1GP

PCB_VER_AD

USB3_PWR_ON

PSL_IN2 MODEL_ID_DET

ECSMI#_KBC

PSL_IN1 PSL_OUT EC_GPIO72

SCD1U10V2KX-5GP

3D3V_AUX_KBC_VCC

U2701A

104

VREF

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

79

GPIO2

95

GPIO3/AD6

96

GPIO4/AD5

108

GPIO5/AD4

93

PSL_IN2#_GPIO6

94

GPIO7/AD7

114

GPIO16

6

GPIO24

109

GPIO30

14

GPIO34/CIRRXL

15

GPIO36

80

GPIO41

17

GPIO42/TCK

20

GPIO43/TMS

21

GPIO44/TDI

23

GPIO46/CIRRXM/TRST#

26

GPIO51

73

PSL_IN1_GPIO70

74

PSL_OUT_GPIO71

75

VBKUP

82

GPIO75

83

GPO76/SHBM

84

GPIO77

91

GPIO81

110

GPO82/IOX_LDSH/TEST#

112

GPIO84/IOX_SCLK/XORTR#

107

GPIO97

44

VCORF

NPCE795PA0DX-GP-U

VBAT

VCC19VCC46VCC76VCC88VCC

GND18GND45GND78GND89GND

115

GND

5

116

ROSA Multi GPIO setting

R2711 0R0402-PADR2711 0R0402-PAD

C2719 SCD1U10V2KX-5GP

CPU_THRM

USB3_PWR_ON

SYS_THRM

L_BKLT_EN(17)

B B

KBC_PWRBTN#(68)

A A

12

DY

C2720 SCD1U10V2KX-5GP

12

DY

C2721 SCD1U10V2KX-5GP

12

DY

EC_AGND

PANEL_BLEN

1 2

R2761 0R0402-PADR2761 0R0402-PAD

BAT54CPT-GP

1

3

2ND = 83.00054.Q81

2

D2702

2ND = 83.00054.Q81

83.R2003.E81

AC_IN#_KBC

5

PSL_IN2

83.R2003.E81

KBC_ON#

D2703

2

10mW

1

BAT54CPT-GP

R2704

1 2

3

EC_GPIO72

330KR2J-L1-GP

KBC_ON#_R

AC_IN# (40)

EC_SWI#(20)

EC_SCI#( 22)

RN2706

4

SRN10KJ-5-GP

EC_SWI#(20)

EC_SCI#(22)

3D3V_AUX_S5

1

KBC_ON#_GATE

23

SCD1U10V2KX-5GP

D2701

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

D2704

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

20101224 A00: 0402 0R pad: R2758,R2759.

C2722

1 2

SCD1U10V2KX-5GP

12

C2713

DY

2N7002K-2-GP

G

S

Q2706

84.2N702.J31

2ND = 84.2N702.031

G

102

AVCC

GPIO11/CLKRUN#

GPIO10/LPCPD#

GPIO67/PWUREQ#

KBRST#/GPIO86

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO27/PSDAT2

GPIO35/PSDAT1

F_SDIO/F_SDIO0

1 2

ECSWI#_KBC

3

ECSCI#_KBC

3

ECSWI#_KBC

R2758

12

0R0402-PAD

ECSCI#_KBC

R2759

12

0R0402-PAD

3D3V_AUX_S5

S

G

D

3D3V_AUX_KBC

S5_ENABLE

D

4

SCD1U10V2KX-5GP

4

1 OF 2

VDD

LRESET#

LCLK

LFRAME#

LAD3 LAD2 LAD1 LAD0

SERIRQ

GPIO65/SMI#

ECSCI#/GPIO54

GPIO85/GA20

GPIO26/PSCLK2

GPIO37/PSCLK1

GPIO17/SCL1

GPIO22/SDA1

GPIO73/SCL2

GPIO74/SDA2

GPIO23/SCL3

GPIO31/SDA3

GPIO47/SCL4

GPIO53/SDA4

F_CS0#

F_SCK

F_SDI/F_SDIO1

AGND

103

EC_AGND

Q2703

Q2703 DMP2130L-7-GP

DMP2130L-7-GP

2ND = 84.03413.A31

84.02130.031

4

3

3D3V_AUX_KBC

20101224 A00 Modify:

3D3V_S0

12

C2703

C2702

7 2 3 1 128 127 126 125 8 9 29 124 123 121 122

27 25 11 10 71 72

70 69 67 68 119 120 24 28

90 92 86 87

C2703

DY

SC2D2U10V3KX-1GP

C2711

DY

1 2

SC220P50V2KX-3GP

PLT_RST#_EC

R2735

12

0R0402-PAD

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

PANEL_BLEN

ECSCI#_KBC

ECSWI#_KBC

AD_IA_HW2

MEDIA_BTN1#

EC_ENABLE#_1

PROCHOT_EC

EC_SPI_CS#_C EC_SPI_CLK_C EC_SPI_DI_C EC_SPI_DO_C

NOTE: Locate resistors R2719 and R2722 close to the NPCE791L.

NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connect ion.

CLK_PCI_KBC (18)

PM_LAN_ENABLE (82)

LCD_TST_EN (49)

R2737 0R0402-PADR2737 0R0402-PAD R2722 33R2J-2-GPR2722 33R2J-2-GP

EC_GPIO47 High Active

PROCHOT_EC

12

R2732

2ND = 84.2N702.031

100KR2J-1-GP

Change R2724 to 47K from 33K.

PCB_VER_AD

SCD1U10V2KX-5GP

PLT_RST# (5,18,65,71,82,83)

LPC_FRAME# (21,65,71)

LPC_AD[0..3] (21,65,71)

INT_SERIRQ (21) PM_CLKRUN# (19)

HDMI_ IN# (5 1)

H_A20GATE (22) H_RCIN# (22)

BLON_OUT (49)

AD_IA_HW2 (40)

PCH_WAKE# ( 19)

TPDATA (69) TPCLK (69)

<------ TP

BAT_SCL (39,40) BAT_SDA (39,40) SML1_CLK (20,85) SML1_DATA (20,85)

33R2J-2-GPR2736 33R 2J-2-GPR2736

12

33R2J-2-GPR2719 33R 2J-2-GPR2719

12 12 12

Q2702

G

S

2N7002K-2-GP

84.2N702.J31

12

C2717

1 2

EC_AGND

<------ BATTERY / CHARGER <------PCH / eDP

20101224 A00: 0402 0R pad: R2737,R2735.

SPI_CS0#_R (21,60) SPI_CLK_R (21,60) SPI_SO_R (21,60)

SPI_SI_R (21,60)

12

H_PROCHOT#_EC

D

PSL SOLUTION

R2756

EC_GPIO72

1 2

0R0402-PAD

AC_OK

DY

R2767

1 2

G

DY

S

2N7002K-2-GP

84.2N702.J31

1 2

DY

AC_OK(40)

PSL_OUT

2ND = 84.2N702.031

NOTES: Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD.

R2768

0R2J-2-GP

0R2J-2-GP Q2705

Q2705

D

KBC_ON#_R

PSL_IN1

DY

12

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

R2724

R2724 47KR2F-GP

47KR2F-GP

R2726

R2726 100KR2F-L1-GP

100KR2F-L1-GP

X01

X02

A00

Reserved

Reserved 1.65V

Reserved 100.0K 215.0K 1.048V

NOTES: The NPCE795P GPIO/PWM outputs that are connected to LEDs have high drive buffers (20mA) and can be connected directly to the LEDs.

FAN_TACH1(28)

PM_PWRBTN#(19)

PCIE_WAKE#(82) PM_SLP_S3#(19,36,37,46,47)

CHG_AMBER_LED#(68)

KBC_BEEP(29)

MEDIA_LED1#( 82)

KB_BL_CTRL(69)

AD_IA_HW(40) MEDIA_LED3#( 82) MEDIA_LED2#( 82)

PWRLED#(68)

E51_RxD(65)

AMP_MUTE#(29)

PCH_SUSCLK_KBC(19)

H_PECI(5,22)

1D05V_VTT

EC_SPI_DI_C

R2773

R2773 100KR2J-1-GP

100KR2J-1-GP

1 2

R2733 0R0402-PADR2733 0R0402-PAD

H_PROCHOT # (5,40,42)

Need very close to EC

PURE_HW_SHUTDOWN#(28,36,85)

10mW SOLUTION

R2769

R2769 100KR2J-1-GP

100KR2J-1-GP

3D3V_AUX_KBC

3D3V_AUX_KBCRTC_AUX_S5

R2734

1 2

DY

R2763

AC_IN#_KBC

1 2

0R0402-PAD

EC_ENABLE#_1

2ND = 84.2N702.031

20101228 A00: Change R2756,R2763,R2766 to 0R short pad.

3

G

S

2N7002K-2-GP

84.2N702.J31

R2766

1 2

0R0402-PAD

VBACKUP

EC_GPIO72

0R2J-2-GP

PSL_IN1

Q2704

10mW

PSL_IN1

PSL_OUT

KBC_ON#

D

KBC_ON#_RKBC_ON#

100.0KX00

100.0K

ECRST#

E51_TxD(65)

R2721 43R 2J-GPR 2721 43R2J-GP

1 2 1 2

R2720 0R0402-PADR2720 0R0402-PAD

3D3V_AUX_S5

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.204V

U2701B

31

GPIO56/TA1

117

GPIO20/TA2

63

GPIO14/TB1

64

GPIO01/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

81

GPIO66/G_PWM

66

GPIO33/H_PWM

22

GPIO45/E_PWM

16

GPIO40/F_PWM

85

VCC_POR#

113

GPIO87/CIRRXM/SIN_CR

111

GPIO83/SOUT_CR/TRIST#

30

GPIO55/CLKOUT/IOX_DIN_DIO

77

GPIO00/EXTCLK

13

PECI

12

VTT

NPCE795PA0DX-GP- U

E

B

Q2701

C

2nd = 84.03906.F11

KBSOUT15/GPIO61/XOR_OUT

12

MMBT3906-4-GP

DY

84.T3906.A11

C2716

12

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

143.0K100.0K 1.358VReserved

174.0KReserved 100.0K

PECI

EC_VTT

12

SCD1U16V2KX-3GP

R2705

R2705 10KR2J-3-GP

10KR2J-3-GP

EC GPIO standard PH/PL

BAT_SCL BAT_SDA

BAT_IN# AC_IN#_KBC

S5_ENABLE ECRST#

EC_ENABLE#_1

FAN_TACH1(28)

FAN_TACH1

E51_RxD

BLUETOOTH_EN

2

C2718

KBSOUT9/SDP_VIS# KBSOUT10/P80_CLK KBSOUT11/P80_DAT

ECRST#

C2715

RN2701

4

SRN4K7J-8-GP

RN2703

4

SRN100KJ-6-GP

RN2705

8 7 6

SRN10KJ-6-GP

1 2

R2712 10KR2J-3-GPR2712 10KR2J-3-GP

DY

1 2

R2708 10KR2J-3-GP

DY

1 2

R2709 10KR2J-3-GP

2

3D3V_AUX_KBC

MODEL_ID_DET

1 2

EC_AGND

SCD1U10V2KX-5GP

2 OF 2

KBSOUT0/JENK#

KBSOUT1/TCK KBSOUT2/TMS

KBSOUT3/TDI

KBSOUT4/JEN0#

KBSOUT5/TDO

KBSOUT6/RDY#

KBSOUT7 KBSOUT8

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

GPIO60/KBSOUT16 GPIO57/KBSOUT17

KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7

SC1U6D3V2KX-GP

23 1

1 23

1 2 3 45

12

R2710

R2710 174KR2F-GP

174KR2F-GP

12

R2739

R2739 100KR2F-L1-GP

100KR2F-L1-GP

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

54 55 56 57 58 59 60 61

3D3V_AUX_KBC

3D3V_S0

1

MODEL_ID_DET(GPIO07)

DQ15_ATI

DQ15_NVIDIA

DN15_UMA

DN15_ATI

Reserved

DN13_UMA

DN13_ATI

DQ15_Ventura 100.0K 215.0K 1.048V

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

100.0KDQ15_UMA 3.0V

100.0K

10.0K(64.10025.6DL)

20.0K(64.20025.6DL)

33.0K

47.0K(64.47025.6DL)

64.9K(64.64925.6DL)

76.8K

100.0K

143.0K100.0K 1.358V

174.0K100.0K

Notes: The total SPI interface signal between EC and PCH can’t not exceed 6500mil. The mismatch between SPI signal must be within 500mil

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16

USB_DET#

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

KCOL[0..16] (69)

KROW[0..7] ( 69)

D2705

EC_SMI#(21,22)

EC_SMI# ECSMI#_KBC

1

2

BAS16-6-GP

2ND = 83.00016.F11

20101224 A00: 0402 0R pad: R2760.

R2760

12

0R0402-PAD

3

DY

83.00016.K11

ECSMI#_KBC

MEDIA BUTTON CONTROL

USB_DET#

MEDIA_BTN1#

MEDIA_BTN2#

MEDIA_BTN3#

PCIE_WAKE#

INSTANT_ON#(82)

USBDET_CON#(57)

DATA_RECOVERY#(82)

Title

KBC Nuvoton NPCE785P

Size Document Number Rev

A2

Date: Sheet

INSTANT_ON#

USBDET_CON#

DATA_RECOVERY#

Nirvana 13

1 2

R2772 100KR2J-1-GPR2772 100KR2J-1-GP

1 2

R2770 100KR2J-1-GPR2770 100KR2J-1-GP

1 2

R2774 100KR2J-1-GPR2774 100KR2J-1-GP

1 2

R2775 100KR2J-1-GPR2775 100KR2J-1-GP

1 2

R2776 100KR2J-1-GPR2776 100KR2J-1-GP

BAT54CPT-GP

1

3

2ND = 83.00054.Q81

2

D2706

BAT54CPT-GP

1

3

2ND = 83.00054.Q81

2

D2707

BAT54CPT-GP

1

3

2ND = 83.00054.Q81

2

D2708

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

27 104T uesday, January 18, 2011

1

27 104T uesday, January 18, 2011

3D3V_AUX_KBC

MEDIA_BTN1#

83.R2003.E81

KBC_ON#_R

USB_DET#

83.R2003.E81

KBC_ON#_R

MEDIA_BTN2#

83.R2003.E81

KBC_ON#_R

of

2.75V100.0K

2.48V100.0K

2.24V

2.0V

1.87V

1.65V

1.204V

A00

5

4

3

2

1

SSID = Thermal

D D

C C

B B

3D3V_DAC_S0

12

DY

R2808

R2808 NTC-100K-8-GP

NTC-100K-8-GP

12

C2802

SCD1U10V2KX-5GP

P2800_DXP

12

C2806

C2806 SC470P50V3JN-2GP

SC470P50V3JN-2GP

P2800_DXN

SCD1U10V2KX-5GP

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

2ND = 84.03904.P11

3

84.03904.L06

Q2801

1

PMBS3904-1-GP

2

2.System Sensor, Put on palm rest

Thermal sensor P2800

3D3V_DAC_S0

12

R2803

R2803 107KR2F-GP

P2800A1

R2804

R2804 226KR2F-GP

226KR2F-GP

P2800A1

12

C2807

C2807 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

THERM_SYS_SHDN#_OTZ ADJ

107KR2F-GP

ADJ

12

87.1 Degree

12

C2805

P2800A1

SCD1U10V2KX-5GP

P2800EA1-GP

5

VCC

6 7 8

1.H/W T8 Shutdown

TDR

DXP

TDL

DXN

GND

OTZ

ADJ

U2801

74.02800.A71

4 3 2 1

20101224 A00 Modify: If stuff P2800EA1 then must stuff R2803,R2804 C2805 but if stuff P28003B0 should be un-stuff.

SYS_THRM (27) CPU_THRM (27)

PURE_HW_SHUTDOW N#(27,36,85)

FAN_TACH1(27)

AFTP2801AFTP2801

AFTP2802AFTP2802

1 2

R2807 0R0402-PADR2807 0R0402-PAD

FAN_TACH1_C

1

FAN_VCC

1

THERM_SYS_SHDN#_OTZ

12

C2811

DY

RSET = 0.0012T 2 — 0.9308T + 96.147 T=87 ; RSET=24.25ohm

THERM_SYS_SHDN#

R2806

24K3R2F-1-GP

1 2

DY

1 2

R2812 0R2J-2-GP

DY

Fan controller

R2802 0R2J-2-GP

1 2

DY

5V_S0

FAN1_DAC(27)

For linear FAN

SCD1U10V2KX-5GP

1 2

U2805_3

FAN_VCC

*Layout* 10 mil

FAN_TACH1_C

*Layout* 15 mil

12

C2808

DY

SCD1U16V2KX-3GP

R2805

1 2

0R2J-2-GP

Q2802

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

U2805

SET GND OUT#3HYST

G709T1UF-GP

74.00709.A7F

DY

VCC

U2802

FON#

1

FON#

2 3 4

21

D2802

12

D2802

C2809

CH551H-30PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

SC4D7U6D3V3KX-GP

THERM_SYS_SHDN#

S

G

20101228 A00 Modify: Un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805 at X-Build.

U2805_5U2805_1

5

12

C2817

4

DY

U2805_4

R2811

DY

0R2J-2-GP

GND

VIN

GND

VO

GND

VSET

GND

G991P11U-GP

74.00991.031

2nd = 74.02793.A31

3rd = 74.05606.A71

FAN_VCC

12

C2810

DY

3D3V_S0

12

3D3V_S0

R2801

DY

150R2F-1-GP

SCD1U10V2KX-5GP

R2810

DY

0R2J-2-GP

12

8 7 6 5

3 2

1

SC2200P50V2KX-2GP

R2809

R2809 100KR2J-1-GP

100KR2J-1-GP

3D3V_DAC_S0

12

3D3V_DAC_S0

12

5V_S0

12

C2804

C2803

SC4D7U6D3V3KX-GP

FAN1

5

4

ACES-CON3-11-GP

20.F0772.003

2nd = 20.F1841.003

SCD1U10V2KX-5GP

Hysterisis is 10°C for HYST = VCC, 2°C for HYST = GND.

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

THERMAL P2800 / Fan control

Size Document Number Rev

A3

Date: Sheet

5

4

3

2

Date: Sheet

THERMAL P2800 / Fan control

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

A00

28 104Tuesday, January 18, 2011

of

1

of

A00

5

SSID = AUDIO

D D

3D3V_S0

Close to codec

12

C2902

C2904

C2903

SC1U6D3V2KX-GP

C C

1 2

SCD1U10V2KX-5GP

1 2

SCD1U10V2KX-5GP

AUD_DMIC_CLK(49,97)

AUD_DMIC_IN0(49,97) HDA_CODEC_SDOUT(21) HDA_CODEC_BITCLK(21)

HDA_SDIN0(21)

HDA_CODEC_SYNC(21) HDA_CODEC_RST#(21)

4

AMP_MUTE#(27)

AMP_MUTE#

Close to codec

AUD_DVDDCORE

12

C2901

C2901 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1 2 3 4 5 6 7 8 9

10

R2901

1 2

33R2J-2-GP

AUD_DMIC_CLK AUD_DMIC_IN0 HDA_CODEC_SDOUT HDA_CODEC_BITCLK HDA_CODEC_SDIN0

HDA_CODEC_SYNC HDA_CODEC_RST# AUD_PC_BEEP

2010/06/30 Change to 92HD87 (71.92H87.A03)

U2901

DVDD_LV DMIC_CLK/GPIO_1 DMIC_0/GPIO_2 SDATA_OUT BITCLK SDATA_IN DVDD SYNC RESET# PCBEEP

3

AUD_SPK_LAUD_SPK_L+

+AVDD+PVDD

AUD_VREG

35

41

THERMAL_PAD

92HD87B1A5NDGXTBX8-GP

34

36

40

37

38

33

39

PVSS

EAPD

PVDD

71.92H87.A03

SENSE_A11SENSE_B12PORTF_L13PORTF_R14PORTC_L15PORTC_R16VREFFILT17CAP218VREFOUT_A19VREFOUT_C

PVDD

PORTD_-L

PORTD_-R

PORTD_+L

PORTD_+R

31

32

AVDD2

20

VREG/+2_5V

CAP+

CAP-

AVSS2

PORTB_R

PORTB_L

AVSS2

PORTA_R

PORTA_L

AVDD1

V-

AUD_SPK_L- (58)

AUD_SPK_L+ (58)

30 29 28 27 26 25 24 23 22 21

2

R2902

1 2

0R0603-PAD

C2906

SC1U10V2KX-1GP

1 2 1 2

12 12

0R0603-PAD

12

C2914

C2914 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

C2922 SC1U10V3KX-3GPC2922 SC1U10V3KX-3GP C2921 SC1U10V3KX-3GPC2921 SC1U10V3KX-3GP

C2905

1 2

PUMP_CAPP

PUMP_CAPN AUD_V_B

AUD_HP1_JACK_R AUD_HP1_JACK_L

AUD_EXT_MIC_R AUD_EXT_MIC_L

+AVDD

SCD1U10V2KX-5GP

1 2

R2906 60D4R2F-GPR2906 60D4R2F-GP R2905 60D4R2F-GPR2905 60D4R2F-GP

Put C2921 and C2922 close to codec

5V_S0 +PVDD

12

C2908

1 2

SCD1U10V2KX-5GP

AUD_HP1_JACK_R2 (58)

AUD_HP1_JACK_L2 (58)

MIC_IN_R (58) MIC_IN_L (58)

C2909

SC1U10V2KX-1GP

C2910

SC10U6D3V5MX-3GP

1

1 2

R2903

R2903 0R0603-PAD

0R0603-PAD

R2904

R2904 0R0603-PAD

0R0603-PAD

5V_S0

3D3V_S0

AUD_SENSE_A

AUD_SENSE_B

AUD_PC_BEEP

AUD_CAP2

AUD_VREFFLT

12

R2908

R2908 10KR2J-3-GP

10KR2J-3-GP

AMP_MUTE#

AUD_VREFOUT_B

HDA_CODEC_BITCLK_1

12

C2907

C2923

SC1U10V2KX-1GP

B B

C2907

DY

SC4D7P50V2CN-1GP

R2907

1 2

DY

47R2J-2-GP

HDA_CODEC_BITCLK

AUD_PC_BEEP Trace width>15 mils

AUD_PC_BEEP

C2912 SCD1U10V2KX-5GPC2912 SCD1U10V2KX-5GP

C2913 SCD1U10V2KX-5GPC2913 SCD1U10V2KX-5GP

G2901

G2901 DUMMY-C2

DUMMY-C2

1 2

12

SB_SPKR_R

KBC_BEEP_R

AUD_VREFOUT_B

120KR2J-L-GP

R2909

1 2

R2910

470KR2J-2-GP

From PCH

HDA_SPKR (21)

KBC_BEEP (27)

From EC

$]DOLD,)(0,

HDA_CODEC_SDOUT

12

R2912

R2912 47R2J-2-GP

47R2J-2-GP

DY

PCH_AZ_CODEC_SDOUT1

A A

12

C2920

DY

SCD1U10V2KX-5GP

5

AUD_SENSE_A

+AVDD

12

R2915

R2915 2K49R2F-GP

2K49R2F-GP

12

C2919

C2919 SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

Close to Pin13

4

R2913

1 2

20KR2F-L-GP

R2919

39K2R2F-L-GP

AUD_HP1_JD# (58)

AUD_SENSE_B

12

EXT_MIC_JD# (58)

Close to Pin14

3

+AVDD

12

AUD_CAP2

AUD_VREFFLT

AUD_V_B

AUD_VREG

R2916

R2916 2K49R2F-GP

2K49R2F-GP

R2918

R2918 20KR2F-L-GP

20KR2F-L-GP

12

C2918

C2917

C2918

SC4D7U6D3V3KX-GP

SC10U6D3V5MX-3GP

Close to codec

AUD_VREFOUT_B

RN2901

SRN4K7J-8-GP

MIC_IN_L(58) MIC_IN_R(58)

2

12

C2915

C2916

SC1U6D3V2KX-GP

SC10U6D3V5MX-3GP

23

SC1U6D3V2KX-GP

1

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Audio Codec 92HD87B1

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

29 104Tuesday, January 18, 2011

1

A00

of

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

30 104Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document Number Rev

A3

Date: Sheet

Reserved

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

of

31 104Tuesday, January 04, 2011

1

A00

5

SSID = SDIO

4

3

2

1

D D

48MHz clock input trace of characteristic impedance (Zo) must be 50



±15%.

3D3V_CARD_S0

CLK_PCH_48M(20,97)

XD_D7 SP14 SP13 SP12

C3201

RREF

1 2

DY

3D3V_S0

MAX 0.4A

3D3V_CARD_S0

12

DY

C3204

C3203

SCD1U10V2KX-4GP

C C

SCD1U10V2KX-4GP

1 2

C3204 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

DY

SC100P50V2JN-3GP

R3201

1 2

6K2R2F-GP

USB_PN5_R USB_PP5_R

V18

12

C3202

C3202 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2 3 4 5 6

25

RREF DM DP 3V3_IN CARD_3V3 V18

GND

24

23

CLK_IN

XD_CD#7SP18SP29SP310SP411SP5

SP11

U3201

U3201 RTS5138-GR-GP

RTS5138-GR-GP

22

SP1119SP1220SP1321SP14

SP10

XD_D7

GPIO0

SP9 SP8 SP7 SP6

71.05138.003

12

SP5 SP4 SP3 SP2 SP1 XD_CD#

XD_D7 (74) SP14 (74) SP13 (74) SP12 (74) SP11 (74)

18 17 16 15 14 13

SP10

SP9 SP8 SP7 SP6

SP5 (74) SP4 (74) SP3 (74) SP2 (74) SP1 (74) XD_CD# (74)

SP10 (74)

SP9 (74) SP8 (74) SP7 (74) SP6 (74)

12

C3206

C3206 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

Close to chip

12

C3207

C3207 SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

The maximum range of the PMOS output current

1. xD-Picture Card: 250mA

B B

2. SD/MMC Card: 250mA

3. MS/MSPRO/Duo-HG: 250mA

The pin2 / pin3 (DM/DP) of RTS5138 chip trace layout with differential characteristic impedance (Zdiff) is 90ȍ± 10%

POWER TRACE

1.RTS5138: pin 4 (3V3_IN) trace fixed width is 30 mils (minimum).

2.RTS5138: pin 5 (CARD_3V3) trace fixed width is 30 mils (minimum).

R3211

USB_PP5(18)

1 2

0R0402-PAD

USB_PP5_R

3.RTS5138: pin 6 (V18) trace fixed width is 12 mils (minimum). Keep the trace routing lengths as short as possible.

4.RTS5138: pin 1(RREF) trace fixed width is 12 mils (minimum).

5.RTS5138: pin 1(RREF) trace must far away 48MHz clock trace.

6.De-coupling and Bulk capacitor should place near to RT5138 chip and Combo Socket.

7.It is recommended that use of ferrites bead on power trace.

8.Via size: Pad>=32 mils, Finished hole>=16 mils.

R3210

USB_PN5(18)

1 2

0R0402-PAD

USB_PN5_R

A A

5

4

3

20101227 A00: Change R3210,R3211 to 0R 0402 pad. 20100104 A00: Remove TR3201.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

2

Date: Sheet

Card Reader RTS5138

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

A00

of

32 104Tuesday, January 18, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

33 104Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

34 104Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

of

35 104Tuesday, January 04, 2011

1

A00

5

PS_S3CNTRL

IMVP_PWRGD(27,42)

Q3603

G

S

2N7002K-2-GP

D

2

3

1

D3602

D3602 BAS16-6-GP

BAS16-6-GP

83.00016.K11

2ND = 83.00016.F11

SSID = Reset.Suspend

D D

S0_PWR_GOOD(19,27)

4

20101224 A00: 0402 0R pad: R3614.

R3614

0R0402-PAD

12

C3612

SCD01U50V2KX-1GP

SYS_PWROK

Power Sequence

12

DY

SYS_PWROK (19)

3

R3622

1D05V_VTT

H_PWRGD_R

R3601

H_CPUPWRGD(5,22)

3V_5V_EN(41)

1 2

1KR2J-1-GP

DY

12

DY

R3602

200KR2J-L1-GP

SCD1U10V2KX-5GP

2ND = 83.00016.F11

BAS16-6-GP

2

1

1 2

R3603 1KR2J-1-GPR3603 1KR2J-1-GP

56R2J-4-GP

C3602

83.00016.K11

3

D3601

12

E

B

DY

Q3601

12

CHT2222APT-GP

C

DY

2

H_THERMTRIP# (5,22)

PURE_HW _SHUTDOWN # (27,28,85)

S5_ENABLE (27)

1

SSID = Reset.Suspend

AO4468 MAX 9A

Rds(on) = 18.5mOhm

2nd = 84.08882.037

84.04468.037

5V_S5 5V_S0

AO4468-GP

6

D

7

D

8

D

12

C3608

C3608 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

Rds(on) = 18.5mOhm AO4468 MAX 11.6A

2nd = 84.08882.037

84.04468.037

3D3V_S5

AO4468-GP

6

D

7

D

8

D

U3602

12

C3605

C3605 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

U3602

45

GD

3

S

2

S

1

S

U3601

3D3V_S0

45

GD

3

S

2

S

1

S

12

+5V_RUN

+5V_RUN Comsumption Peak current 7.73A

12

C3603

C3603 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

+3.3V_RUN

+3.3V_RUN Comsumption Peak current 8.14A

C3604

C3604 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

PS_S3CNTRL (37)

15V_S5

R3604

R3604 100KR2J-1-GP

100KR2J-1-GP

1 2

R3605

1 2

R3607

1 2

10KR2J-3-GP

3.3V_RUN_ENABLE

10KR2J-3-GP

5V_RUN_ENABLE

Run Power

C C

3D3V_AUX_S5

PS_S3CNTRL

R3606

1 2

100KR2J-1-GP

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

PM_SLP_S3#(19,27,37,46,47)

RUN_ENABLE

Q3602

5

6

123 4

GGDDSS

1

+1.5V_RUN_CPU Comsumption Peak current 10A

B B

+1.5V_RUN for Mini-Card Comsumption Peak current 1A

1 2

1D5V_S3 1D5V_S0

TPCA8062-H-GP MAX 28A Rds(on) = 4.1~5.4m OHM

U3606

S

D

S

D

8

S

D

S

D

7

S

D

S

D

6

GD

TPCA8062-H-GP

R3630

10KR2J-3-GP

SCD01U50V2KX-1GP

1.5V_RUN_ENABLE

C3610

12

TPCA8062-H-GP

84.08062.037

2nd = 84.00460.037

3rd = 84.00312.037

1 2 3 45

1D5V_S0

MAX Current ? mA Design Current ? mA

Total= 11.39A

12

C3609

C3609 SC4D7U6D3V5KX-3G P

SC4D7U6D3V5KX-3G P

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

A2

Nirvana 13

Date: Sheet

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

Power Plane Enable

36 104Tuesday, January 18, 2011

1

36 104Tuesday, January 18, 2011

A00

of

5

Close to CPU

D D

S3 Power Reduction Circuit Processor VREF_DQ Implementation

M_VREF_DQ_DIMM0

R3708 0R0402-PADR3708 0R0402-PAD

1 2

4

+V_SM_VREF

R3707

R3707 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q3708

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

S

G

RUN_ENABLE

R3705

R3705 100KR2J-1-GP

100KR2J-1-GP

1 2

3

+V_SM_VREF_CNT (9)

2

Close to DIMM S3 Power Reduction Circuit SM_DRAMPWROK

1D5V_S00D75V_S0

12

R3703

R3703 22R2J-2-GP

22R2J-2-GP

Q3701_D

D

S

G

PS_S3CNTRL(36)

2

Q3701

Q3701 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

PS_S3CNTRL

G

12

DY

Q3702_D

D

DY

R3704

R3704 220R2J-L2-GP

220R2J-L2-GP

S

Q3702

Q3702 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

1

C C

S3 Power Reduction

5

PS_S3CNTRL(36)

B B

3D3V_S0

12

R3713

200R2F-L-GP

PM_DRAM_PWRGD(5,19)

A A

R3717

1 2

DY

PM_DRAM_PWRGD(5,19)

SM_DRAMPWROK must have a maximum of 15ns rise or fall time over VDDQ * 0.55± 200mV and the edge must be monotonic

5

DY

0R2J-2-GP

0D75V_EN

VDDPWRGOOD_R

2N7002K-2-GP

G

S

Q3704

84.2N702.J31

2ND = 84.2N702.031

PM_SLP_S3#(19,27,36,46,47)

U3701

1

2

3

TC7SZ08FU-2-GP

73.7SZ08.EAH

2ND = 73.01G08.L04

3rd = 73.7SZ08.DAH

5

4

0D75V_EN

D

1 2

DY

R3716 22R2J-2-GP

DY

Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK

1D5V_S03D3V_S0

CEKLT V1.0: PCH to 1K,CUP to 200R

12

R3702

200R2F-L-GP

DY

VDDPWRGOOD_R

PS_S3CNTRL

4

R3721

39R2J-L-GP

12

DY

D

G

1.05VTT_PWRGD (45,48)

12

R3710

R3710 0R0402-PAD

0R0402-PAD

12

C3705

C3705 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R3719

1 2

910R2F-GP

Q3707_D

Q3707

DY

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

S

20101224 A00: 0402 0R pad: R3710.

0D75V_EN (46)

VDDPWRGOOD (5)

12

R3720

R3720 750R2F-GP

750R2F-GP

3

SM_DRAMRST#(5)

Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK

R3709

1 2

DY

2ND = 84.2N702.031

84.2N702.J31

Q3703

S

G

2N7002K-2-GP

SCD047U16V2KX-1-GP

2

1D5V_S3

12

R3706

R3706 1KR2J-1-GP

1KR2J-1-GP

0R2J-2-GP

SM_DRAMRST#_D

D

12

C3703

DRAMRST_CNTRL_PCH

12

Title

Size Document Number Rev

A3

Date: Sheet

S3 Power Reduction Circuit SM_DRAMRST#

R3718

1 2

1KR2J-1-GP

C3702

C3702 SC100P50V2JN-3GP

SC100P50V2JN-3GP

DRAMRST_CNTRL_PCH (20)

S3 Power Reduction

Nirvana 13

DDR3_DRAMRST# (14,15)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

37 104Tuesday, January 18, 2011

1

A00

5

4

3

2

1

84.03904.L06

PQ3802

PMBS3904-1-GP

1 2

PQ3802_1

1 2

FDV301N-NL-GP

D

84.03904.L06

2nd = 84.03904.P11

3rd = 84.03904.T11

2

1

3

G

PQ3801

PR3808

1 2

DY

33R2J-2-GP

12

DY

D D

PR3801

15KR2J-1-GP

PR3803

100KR2J-1-GP

PR3804

PS_ID_R PS_ID_1

PS_ID_R(82)

C C

Place close to BTB connector

B B

AFTP3801AFTP3801 AFTP3802AFTP3802 AFTP3803AFTP3803

1 1 1

PS_ID_R +DC_IN +DC_IN

1 2

0R0402-PAD

PD3804

DY

B240A-13-GP

2 1

+DC_IN AD+

280mils or Copper Shape

KA

PD3801

PD3801 1SMB22AT3G-GP-U

1SMB22AT3G-GP-U

83.22R03.03G

2ND = 83.P6SBM.AAG

5V_S5

12

PR3802

PR3802 10KR2J-3-GP

10KR2J-3-GP

PSID_DISABLE#_R

SD

This cap should be used only as last resort for EMI suppression.

PC3801

PC3801 SCD1U50V3KX-GP

SCD1U50V3KX-GP

PS_ID

PR3807

1 2

33R2J-2-GP

RCID(27)

12

PC3804

SC1U25V5KX-1GP

12

PR3810

PU3801_G

PR3811

PR3811 47KR3J-L-GP

47KR3J-L-GP

1 2

PR3812

PR3812 100KR2J-1-GP

100KR2J-1-GP

DY

1 2

1 2 3 4 5

240KR3-GP

Id=-12A Qg=-25nC Rdson=10~38mohm

83.00099.T11

2nd = 83.00099.K11

3rd = 83.BAV99.D11

2N7002K-2-GP

G

S

PQ3803

84.2N702.J31

2ND = 84.2N702.031

PU3801

S

D

S

D

S

S S

S GD

GD

AO4407A-GP

8

D

7

D

6

DY

3D3V_S5

12

PC3805

1

2

PD3803

PD3803 BAV99-5-GP-U

BAV99-5-GP-U

3

D

12

PC3802

DY

SCD01U50V2KX-1GP

3D3V_S5

12

PC3803

SCD01U50V2KX-1GP

PR3806

PR3806 2K2R2J-2-GP

2K2R2J-2-GP

12

PC3806

SC10U25V6KX-1GP

PSID_EC (27)

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

DCIN Jack

Nirvana 13

of

38 104Tuesday, January 18, 2011

1

A00

5

4

3

2

1

BT+

D D

C C

BATT_SENSE(40)

BAT_IN#(27)

BAT_SDA(27,40) BAT_SCL(27,40)

G3901

GAP-CLOSE-PWR-3-GP

12

20101224 A00: Rename PRN3901 to PN3901.

C3902

SCD1U50V3KX-GP

C3902

PN3901

1 2 3 4 5

SRN33J -7-GP

AFTP3902AFTP3902 AFTP3903AFTP3903 AFTP3904AFTP3904 AFTP3905AFTP3905

8 7 6

12

EC3901

DY

12

C3901

C3901 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

AFTP3901AFTP3901

EC3902

12

DY

SC10P50V2JN-4GP

1 1 1 1

PBAT_PRES1# PBAT_SMBDAT1 PBAT_SMBCLK1 BT+

KA

DY

PD3902

PBAT_SMBCLK1 PBAT_SMBDAT1 PBAT_PRES1#

BAT_ALERT

1

1SMA18AT3G-GP

400mils or Copper Shape

Batt Connecter

BATT1

10

1

2 3 4 5 6 7 8 9

11

TCN-CON9-3-GP

20.81327.009

For actual location, need to be swap all pin

Placement: Close to Batt Connector

B B

A A

5

BAT_IN#

3

D3902

D3902 BAV99-5-GP-U

BAV99-5-GP-U

1

2

83.00099.T11

2nd = 83.00099.K11

3rd = 83.BAV99.D11

BAT_SDA

3

D3903

D3903 BAV99-5-GP-U

BAV99-5-GP-U

1

2

83.00099.T11

2nd = 83.00099.K11

3rd = 83.BAV99.D11

4

BAT_SCL

3

D3901

D3901 BAV99-5-GP-U

BAV99-5-GP-U

1

2

83.00099.T11

2nd = 83.00099.K11

3rd = 83.BAV99.D11

3D3V_AUX_KBC

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

BATT CONN

Nirvana 13

1

A00

of

39 104Tuesday, January 18, 2011

A00

5

4

3

2

1

SSID = Charger

AD+

Id=-12A Qg=-25nC Rdson=10~38mohm

D D

AD+

1 2

DC_IN_D

12

PWR_CHG_ACOK

PR4009

316KR3F-2-GP

PR4009

316KR3F-2-GP

PWR_CHG_REF

12

PC4010

PR4016

10KR2F-2-GP

PR4014 49K9R2F-L-GPPR4014 49K9R2F-L-GP

SCD01U50V2KX-1GP

CHG_AGND

C C

B B

1 2

AD_IA(27)

PR4025

This Resistor must be 1% tolerance.

PR4001

20KR2J-L2-GP

12

8K45R2F-2-GPDYPR4025

8K45R2F-2-GP

DY

12

SC220P50V2JN-3GP

PC4024

PC4026

AC_IN#(27)

SCD1U10V2KX-5GP

280mils or Copper Shape

PU4002

S

D

S

D

1

8

S

D

S

D

2

7

S

D

S

D

3

6

GD

45

AO4407A-GP

84.04407.F37

2nd = 84.P1403.B37

84.2N702.A3F

PR4004

2nd = 84.DM601.03F

10KR2J-3-GP

3 4

2

1

PR4033

20R5F-1GP

AC_OK

12

PR4021

PR4021 4K7R2J-2-GP

4K7R2J-2-GP

1 2

PC4021

PC4021 SC150P50V2JN-3GP

SC150P50V2JN-3GP

PWR_CHG_FBO1

12

DY

SCD1U50V3KX-GP

PC4033

AD+_G_2

AD+_G_1

5

6

1 2

3D3V_AUX_KBC

BAT_SCL(27,39)

BAT_SDA(27,39)

200KR2F-L-GP

PC4022

SC2200P50V2KX-2GP

12

DY

PC4027

SCD01U50V2KX-1GP

12

2N7002K-2-GP

DY

84.2N702.J31

1 2

12

PR4022

1 2

PR4526_01

12

PC4025

SC56P50V2JN-2GP

SCD01U50V2KX-1GP

PQ4002

PQ4001

2N7002KDW-GP

2ND = 84.2N702.031

PC4001

PC4001 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

CHG_AGND

1 2

20101222 A00 Power/Brian: Change PR4047 to 174k ohm from 121k ohm.

12

Change PR4035 to 300k from 49.9k. Change PR4031 to 150k from 0 ohm.

PR4003

100KR2J-1-GP

2N7002K-2-GP

PR4005

10KR2F-2-GP

PR4026

PR4026 7K5R2F-1-GP

7K5R2F-1-GP

2N7002K-2-GP

2ND = 84.2N702.031

1 2

AD_IA_HW(27)

1 2

PC4003

SCD47U50V5KX-1GP

PR4012

1 2

0R0402-PAD

12

PG4007 GAP-C LOSE-PWR-3-GPPG4007 G AP-CLOSE-PWR-3-GP

12

PG4008 GAP-C LOSE-PWR-3-GPPG4008 G AP-CLOSE-PWR-3-GP

12

PR4027

1 2

0R0402-PAD

12

PC4029

DY

PC4028

D

S

G

AC_OK

PQ4003

84.2N702.J31

PR4034

0R0402-PAD

PWR_CHG_DCIN

PWR_CHG_ACIN

PWR_CHG_ACOK

PWR_CHG_SCL

PWR_CHG_SDA

CHG_AGND

PWR_CHG_VICM PWR_CHG_FBO

PWR_CHG_EAI PWR_CHG_EAO PWR_CHG_REF

12

DY

SC1U6D3V2KX-GP

AC_OK (27)

G

PQ4003_G

CHG_AGND

PWR_CHG_CE

PC4030

SCD1U10V2KX-5GP

PQ4003_D

D

22

11

13

10

14

12

S

2

9

8

6 5 4 3 7

PWR_CHG_REF

12

PR4035

PR4035 300KR2F-L-GP

300KR2F-L-GP

PR4031

PR4031 150KR2F-L-GP

150KR2F-L-GP

1 2

CHG_AGND

PU4001

DCIN

ACIN

VDDSMB

ACOK

SCL

SDA

NC#14

VICM

FBO EAI EAO VREF CE GND

BQ24745RHDR-GP

GAP-CLOSE-PWR-3-GP

12

PR4047

PR4047 174KR2F-GP

174KR2F-GP

ICREF

1

ICREF

GND

29

1 2

CHG_AGND

AD+_TO_SYS

D01R2512F-4-GP

12

PG4002

PR4533_02

12

PR4008

PR4008 0R0402-PAD

0R0402-PAD

1 2

PC4002

PC4002 SCD1U50V3KX-GP

SCD1U50V3KX-GP

CHG_AGND

PWR_CHG_CSSP

28

CSSP

CSSN

ICOUT

BOOT VDDP

UGATE

PHASE

LGATE

PGND

CSOP

CSON

NC#16

VFB

PR4029

PR4029 0R0402-PAD

0R0402-PAD

SCD1U50V3KX-GP

PWR_CHG_CSSN

27

PWR_CHG_ICOUT

26

PWR_CHG_BOOT PWR_CHG_BST1

25

PWR_CHG_VDDP

21

PWR_CHG_UGATE

24

PWR_CHG_PHASE

23

PWR_CHG_LGATE

20

19

PWR_CHG_CSOP

18

PWR_CHG_CSON

17

16

15

PWR_CHG_VFB

CHG_AGND

3D3V_AUX_S5

PR4040

10KR2J-3-GP

AD_IA_HW2(27)

20101222 A00 Power/Brian: Change PR4036 to 0 ohm pad. Stuff PQ4004. Change PR4037 to 76.8k ohm from 49.9k ohm.

PR4002

1 2

12

PR4524_03

12

DY

PR4007

PR4007 0R2J-2-GP

0R2J-2-GP

12

PR4010

PR4010 0R0402-PAD

0R0402-PAD

PC4005

1 2

PR4017

1 2

0R0603-PAD

PR4018

1 2

0R0603-PAD

PR4028

1 2

0R0402-PAD

12

DY

PC4032

SCD1U25V2ZY-1GP

12

84.2N702.J31

2ND = 84.2N702.031

DY

1 2

DCBATOUT

PG4003

GAP-CLOSE-PWR-3-GP

20101222 A00 Power/Brian: Change PR4032 to 0 ohm pad.

H_PROCHOT#(5,27,42)

PC4004

1 2

SCD1U50V3KX-GP

CHG_AGND

K A

SD103AWS-1-GP

83.1R504.A8F

2nd = 83.1R504.B8F

PC4012

PC4012 SCD1U50V3KX-GP

SCD1U50V3KX-GP

1 2

DY

PC4014

PC4014 SC220P50V2JN-3GP

SC220P50V2JN-3GP

CHG_AGND

12

DY

PR4030

1K8R6J-GP

CHG_AGND

PQ4004

2N7002K-2-GP

PQ4004_G

PR4036

0R0402-PAD

PR4013

DY

33R3J-2-GP

33R3J-2-GP PD4001

PD4001

1 2

PC4020

SCD1U50V3KX-GP

1 2

BATT_SENSE (39)

PQ4004_D

D

S

G

CHG_AGND

1 2

12

1 2

PC4011

PC4011 SCD1U50V3KX-GP

SCD1U50V3KX-GP

PC4023

PC4023 SCD1U50V3KX-GP

SCD1U50V3KX-GP

12

PG4001

PR4032

0R0402-PAD

12

DY

CHG_AGND

DY

PR4037

PR4037 76K8R2F-GP

76K8R2F-GP

ICREF

400mils or Copper Shape

1 2

GAP-CLOSE-PWR-3-GP

PG4005

PG4004

PG4006

GAP-CLOSE-PWR-3-GP

1 2

160mils or Copper Shape

678

DDD

PC4006

SC1U6D3V2KX-GP

12

PC4013

PC4013 SC3300P50V3KX-1GP

SC3300P50V3KX-1GP

PWR_CHG_LX1

84.00412.037

PR4023

1 2

0R0402-PAD

CHG_AGND

PU4004 Id=12A

SSS

GD

SSS

GD

PU4004

Qg=3.8nC

123

4 5

Rdson=24~30mohm

SIS412DN-T1-GE3-GP

678

PU4005

DDD

SIS412DN-T1-GE3-GP

PU4005

SSS

GD

SSS

GD

Id=16A

123

4 5

Qg=7.3nC Rdson=13.5~16.5mohm

PR4020

1 2

0R0402-PAD

1 2

IND-5D6UH-48-GP-U1

PL4001 Id=7.5A DCR=23mohm(Max) Size=10*10

470KR2J-2-GP

PWR_DCBATOUT_CHG

12

PC4007

SC10U25V6KX-1GP

PL4001

PWR_CHG_CSOP_1

PU4003

S

D

S

D

1

8

S

D

S

D

2

7

S

D

S

AD+

12

PR4006

12

PC4009

PC4008

SCD1U50V3KX-GP

SC10U25V6KX-1GP

Charger Current=1.4~3.6A

BT+_R

PR4019

1 2

D01R2512F-4-GP

1 2

PG4010

PG4009

GAP-CLOSE-PWR-3-GP

3

GD

4 5

AO4407A-GP

84.04407.F37

2nd = 84.P1403.B37

12

EC4001

DY

12

1 2

SC10U25V6KX-1GP

PC4015

GAP-CLOSE-PWR-3-GP

PG4009_1

PR4024

PR4024 0R0402-PAD

0R0402-PAD

1 2

DY

1 2

PC4031

SCD1U50V3KX-GP

CHG_AGND

D

6

12

EC4002

DY

SC2200P50V2KX-2GP

12

SC10U25V6KX-1GP

PC4016

BT+

SCD1U25V2ZY-1GP

BT+

12

SC10U25V6KX-1GP

PC4017

Id=-12A Qg=-25nC Rdson=10~38mohm

240mils or Copper Shape

12

PC4034

SC10U25V6KX-1GP

SCD1U50V3KX-GP

PC4019

PC4018

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

CHARGER BQ24745

Nirvana 13

1

40 104T uesday, January 18, 2011

A00

of

5

20110110 A00: Change PG4110,PG4112,PG4114~PG4119,PG4122,PG4126,PG4129,PG4131,PG4133,PG4135~PG4138,PG4140,PG4142 to ZZ.CLOSE.001.

5V_S5

D D

C C

Connect VFB1 to GND for fixe 5V opteration

B B

5V_PWR

PG4110 GAP- CLOSE-PWR-3-GPPG4110 GAP-CLOSE-PWR-3-GP

1 2

PG4112 GAP- CLOSE-PWR-3-GPPG4112 GAP-CLOSE-PWR-3-GP

1 2

PG4114 GAP- CLOSE-PWR-3-GPPG4114 GAP-CLOSE-PWR-3-GP

1 2

PG4115 GAP- CLOSE-PWR-3-GPPG4115 GAP-CLOSE-PWR-3-GP

1 2

PG4116 GAP- CLOSE-PWR-3-GPPG4116 GAP-CLOSE-PWR-3-GP

1 2

PG4117 GAP- CLOSE-PWR-3-GPPG4117 GAP-CLOSE-PWR-3-GP

1 2

PG4119 GAP- CLOSE-PWR-3-GPPG4119 GAP-CLOSE-PWR-3-GP

1 2

PG4122 GAP- CLOSE-PWR-3-GPPG4122 GAP-CLOSE-PWR-3-GP

1 2

PG4124 GAP- CLOSE-PWR-3-GPPG4124 GAP-CLOSE-PWR-3-GP

1 2

PG4126 GAP- CLOSE-PWR-3-GPPG4126 GAP-CLOSE-PWR-3-GP

1 2

PG4129 GAP- CLOSE-PWR-3-GPPG4129 GAP-CLOSE-PWR-3-GP

1 2

PG4131 GAP- CLOSE-PWR-3-GPPG4131 GAP-CLOSE-PWR-3-GP

1 2

PG4133 GAP- CLOSE-PWR-3-GPPG4133 GAP-CLOSE-PWR-3-GP

1 2

PG4135 GAP- CLOSE-PWR-3-GPPG4135 GAP-CLOSE-PWR-3-GP

1 2

PG4136 GAP- CLOSE-PWR-3-GPPG4136 GAP-CLOSE-PWR-3-GP

1 2

PG4137 GAP- CLOSE-PWR-3-GPPG4137 GAP-CLOSE-PWR-3-GP

1 2

PG4138 GAP- CLOSE-PWR-3-GPPG4138 GAP-CLOSE-PWR-3-GP

1 2

PG4140 GAP- CLOSE-PWR-3-GPPG4140 GAP-CLOSE-PWR-3-GP

1 2

PG4142 GAP- CLOSE-PWR-3-GPPG4142 GAP-CLOSE-PWR-3-GP

1 2

20101224 A00: Rename PTC4101~PTC4103 to PT4101~PT4103.

Vout(5V)=VFB1*(1+R1/R2)

12

PC4112

SC1KP50V2KX-1GP

Design Current = 16A

25.1A<OCP< 29.3A

5V_PWR

20101224 A00: Rename PTC4101~PTC4103 to PT4101~PT4103.

12

PT4101

PT4102

ST220U6D3VDM-20GP

20101230 A00: Change PR4119 to 0R short pad.

12

PC4114

PC4113

SCD1U50V3KX-GP

SC10U25V6KX-1GP

1 2

IND-1D5UH-34-GP

68.1R510.10J

12

68.1R510.10J

PC4119

PG4125

12

SCD1U10V2KX-4GP

GAP-CLOSE-PWR-3-GP

PWR_5V_VOUT1

12

PR4117

PR4117 0R2J-2-GP

0R2J-2-GP

DY

12

PR4119

0R0402-PAD

PWR_5V3D3_AGN D

15V_S5

20110110 A00: Change PG4139,PG4141 to ZZ.CLOSE.001.

PC4115

PL4102

PG4139GAP-CLOSE-PWR-3-GP PG4139GAP-CLOSE-PWR-3-GP

PG4141GAP-CLOSE-PWR-3-GP PG4141GAP-CLOSE-PWR-3-GP

SC10U25V6KX-1GP

12

15V_PWR

12

PC4129

SC10U25V6KX-1GP

PWR_5V_SNUB

SCD1U25V2ZY-1GP

PC4116

SC10U25V6KX-1GP

12

DY

PC4120

12

SC680P50V2KX-2GP

DY

PR4113

2D2R6J-3-GP

PR4119_2

PC4126

1 2

PR4124

PR4124 24D9R3F-GP

24D9R3F-GP

SCD1U25V2ZY-1GP

4

20101230 A00: Change PR4103,PR4104 to 0R0805 short pad.

PWR_DCBATOUT _5V3D3V

678

DDD

DY

84.00172.037

SSS

PU4102

123

D

PU4108

SSS

123

12

PC4128

DDD

84.00172.037

GD

SSS

PU4101

4 5

123

SIR172DP-T1-GE3-GP

678

D

DDD

PU4106

SSS

G

123

4 5

SIR460DP-T1-GE3-GP

PD4102

1

2

10V_C

BAT54SW-2-GP

PD4103

1

15V_C

2

BAT54SW-2-GP

1 2

PR4125

PR4125 200KR2J-L1-GP

200KR2J-L1-GP

12

GD

4 5

DDD

G

4 5

15V_C_1

PWR_5V3D3_AGN D

SIR172DP-T1-GE3-GP

SIR460DP-T1-GE3-GP

5V_C_1

3

PC4125

PC4125 SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

5V_C_2

3

PC4127

PC4127 SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

12

PR4127

PR4127 39KR2J-GP

39KR2J-GP

5V_AUX_S5

1 2

PR4102 10R3J-3-GPPR4102 10R3J-3- GP

12

PC4102

SC4D7U10V5KX-1GP

DCBATOUT

12

PC4104

SCD1U25V3KX-GP

PWR_5V3D3_AGN D

CLOSE TO PIN 10

12

PC4117

SCD1U25V3KX-GP

PWR_5V_TRIP1

1 2

3V/5V_POK

PR4111

PWR_5V3D3V_EN

105KR2F-1-GP

PWR_5V_DRVH1 PWR_5V_LL1

12

PC4121

20101230 A00: Change PR4115 to 0R0603 short pad.

SCD1U25V3KX-GP

PWR_5V__VBST1_1 PWR_3D3V_VBST2

1 2

123

SKIPSEL GND FLOAT/VREF 2 V5IN Mode Auto Skip OOA. PWM Only

PC4103

1 2

PR4104

PR4103

0R0805-PAD

SC1U25V3KX-1-GP

12

PWR_5V3D3V_VIN

6

7

4

5

8

PU4103

VIN

LDO

GND

VSW VOUT1 VFB1 TRIP1 PGOOD1 EN1 DRVH1 LL1

VREF3

LDOREFIN

TPS51427RHBR-GP

VBST117DRVL118V5DRV19NC#2020GND21PGND22DRVL223VBST2

PWR_5V3D3_AGN D

12

PC4101

SC1U25V3KX-1-GP

33

9 10 11 12 13 14 15 16

PR4115

PWR_5V__VBST1 PWR_3D3V_VBST2_1

1 2

0R0603-PAD

PWR_5V__DRVL1

5V_AUX_S5

PD4101

PD4101 BAT54-7-F-GP

BAT54-7-F-GP

3

+5V_VCC1

PWR_5V3D3V_VR EF2

+5V_VCC1

12

PR4107

PR4107 0R2J-2-GP

0R2J-2-GP

DY

PR4108 0R2J-2-GP

PWR_5V3D3V_TONSEL

2

3

1

V5FILT

TONSEL

EN_LDO

24

PWR_3D3V_D RVL2

PG4143 GAP- CLOSE-PWR-3-GPPG4143 GAP-CLOSE-PWR-3-GP

1 2

12

1 2

DY

PC4106

1 2

SC1U25V3KX-1-GP

VREF2

PWR_5V3D3V_R EFIN2

32

REFIN2

PWR_3D3V_TR IP2

31

TRIP2

PWR_3D3V_VOU T2

30

VOUT2

PWR_5V3D3V_SKIPSEL

29

SKIPSEL

3V/5V_POK

28

PGOOD2

PWR_5V3D3V_EN

27

EN2

PWR_3D3V_D VRH2

26

DVRH2

PWR_3D3V_LL2

25

LL2

20101230 A00: Change PR4116 to 0R0603 short pad.

PR4116

1 2

0R0603-PAD

20110110 A00: Change PG4143 to ZZ.CLOSE.001.

PWR_5V3D3V_EN

PR4122

200KR2J-L1-GP

DY

1 2

PC4105

SC1U25V3KX-1-GP

DY

1 2

PWR_5V3D3_AGN D

PC4122

SCD1U25V3KX-GP

12

3V/5V_POK

+5V_VCC1PWR_5V3D3V_VR EF3

12

PR4106

PR4106 0R0603-PAD

0R0603-PAD

PR4105

0R2J-2-GP

PR4109

0R2J-2-GP

PR4101 187KR2F-GPPR 4101 187K R2F-GP

1 2

DY

PR4110

0R2J-2-GP

12

PWR_5V3D3_AGN D

PR4120 2KR2J-1-GPPR 4120 2KR2J-1-GP

3D3V_S5

12

PR4123

PR4123 100KR2J-1-GP

100KR2J-1-GP

5V_AUX_S5

1 2

12

PC4131

SC1U10V3KX-3GP

20110103 A00: Change PR4106 to 0R0603 short pad.

PWR_DCB ATOUT_5V3D3V

PU4104

AON7410-GP

678

DDD

84.07410.A37

SSS

GD

SSS

GD

123

4 5

678

DDD

PU4107

AON7702-GP

84.07702.037

SSS

GD

SSS

GD

123

4 5

12

CLOSE TO PIN 30

PC4123

PC4123 SCD1U25V3KX-GP

SCD1U25V3KX-GP

1 2

PU4105

G9091-330T11U-GP

74.09091.J3F

2nd = 74.09198.G7F

3rd = 74.07716.A7F

3V_5V_EN (36)

VIN

VOUT GND EN3NC#4

12

PC4107

SC10U25V6KX-1GP

12

DY

PC4118

PC4118 SC680P50V2KX-2GP

SC680P50V2KX-2GP

PWR_3D3V_SN UB

12

PR4112

DY

2D2R6J-3-GP

5

4

12

PC4108

PL4101

1 2

IND-2D2UH-46-GP-U

68.2R210.20B

2

20110110 A00:

3D3V_AUX_S5

12

PC4132

SC1U10V3KX-3GP

12

SC10U25V6KX-1GP

PG4121

PWR_5V3D3_AGN D

V_REFIN2=VREF2*PR4109/(PR4109+PR4105) Vout(3.3V)=V_REFIN2*(1+R1/R2)

12

PC4109

PC4110

SC1KP50V2KX-1GP

SCD1U50V3KX-GP

12

GAP-CLOSE-PWR-3-GP

PG4121_2

PR4114

PR4114 0R0402-PAD

0R0402-PAD

1 2

20101230 A00: Change PR4114 to 0R short pad.

PR4118

DY

0R2J-2-GP

1 2

Change PG4102~PG4109,PG4111,PG4113 to ZZ.CLOSE.001.

DCBATOUT

PC4111

SCD1U50V3KX-GP

12

PC4124

SCD1U10V2KX-4GP

77.22271.27L

PWR_DCBATOUT_5V3D3V

PG4102 GAP-C LOSE-PWR-3-GPPG4102 GAP-CLOSE-PWR-3-GP

1 2

PG4103 GAP-C LOSE-PWR-3-GPPG4103 GAP-CLOSE-PWR-3-GP

1 2

PG4104 GAP-C LOSE-PWR-3-GPPG4104 GAP-CLOSE-PWR-3-GP

1 2

PG4105 GAP-C LOSE-PWR-3-GPPG4105 GAP-CLOSE-PWR-3-GP

1 2

PG4106GAP-CLOSE-PW R-3-GP PG4106GAP-CLOSE-PWR-3-GP

12

PG4107GAP-CLOSE-PWR-3-GP PG4107GAP-CLOSE-PWR-3-GP

12

PG4108GAP-CLOSE-PWR-3-GP PG4108GAP-CLOSE-PWR-3-GP

12

PG4109GAP-CLOSE-PWR-3-GP PG4109GAP-CLOSE-PWR-3-GP

12

PG4111GAP-CLOSE-PWR-3-GP PG4111GAP-CLOSE-PWR-3-GP

12

PG4113GAP-CLOSE-PWR-3-GP PG4113GAP-CLOSE-PWR-3-GP

12

Design Current = 7.4A

11.6A<OCP< 13.7A

12

3D3V_PWR

PT4103

PG4118

GAP-CLOSE-PWR-3-GP

PG4120

GAP-CLOSE-PWR-3-GP

PG4123

GAP-CLOSE-PWR-3-GP

PG4101

GAP-CLOSE-PWR-3-GP

ST220U6D3VDM-20GP

PG4127

GAP-CLOSE-PWR-3-GP

PG4130

GAP-CLOSE-PWR-3-GP

PG4132

GAP-CLOSE-PWR-3-GP

PG4134

GAP-CLOSE-PWR-3-GP

3D3V_S5

20110110 A00: Change PG4118,PG4120,PG4123,PG4101,PG4127,PG4130,PG4132,PG4134 to ZZ.CLOSE.001.

12

Connect REFIN2 to V5FILT for fixed 3.3V operation

1

TONSEL GND VREF2 or Float V5FILT Ch1 400 kHz 400 kHz 200 kHz Ch2 500 kHz 300 kHz 300 kHz

A A

5

1A= 40mils

0.5A= 20mils

0.375A= 15mils

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

A2

Nirvana 13

Date: Sheet

4

3

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

TPS51427_5V/3D3V

41 104T uesday, January 18, 2011

1

41 104T uesday, January 18, 2011

A00

of

5

SSID = CPU.Regulator

4

3

2

1

12

PR4204

PR4204 1R2F-GP

1R2F-GP

SCD1U25V3KX-GP

GND_1316

PWR_VCORE_DB0(43) PWR_VCORE_DB1(43) PWR_VCORE_DB2(43)

1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2

PQ4201_D

PQ4201

5V_S5

12

PR4205

PR4205 1R2F-GP

1R2F-GP

12

PC4213

SCD1U25V3KX-GP

GND_1316

PWR_VCORE_VDD5

PWR_VCORE_VDD3 PWR_VCORE_VDD3

PWR_VCORE_IMON1 PWR_VCORE_IMON2

DB0_GFX(44) DB1_GFX(44) DB2_GFX(44)

PWR_VCORE_R_OSC PWR_VCORE_R_REF1 PWR_VCORE_R_REF2

PWR_VCORE_R_SEL0 PWR_VCORE_R_SEL1 PWR_VCORE_R_SEL2 PWR_VCORE_R_SEL3 PWR_VCORE_R_SEL4 PWR_VCORE_R_SEL5 PWR_VCORE_R_SEL6

5V_S5

12

PR4253

PR4253 1KR2F-3-GP

1KR2F-3-GP

DY

DS

DY

12

PC4201

PU4201

12

VDD5

43

VDD3

42

VDD3

21

IMON1

25

IMON2

37

DB10

36

DB11

35

DB12

33

DB20

32

DB21

31

DB22

24

IDES1_N

23

IDES1_P

27

IDES2_N

28

IDES2_P

41

R_OSC

22

R_REF1

26

R_REF2

2

R_SEL0

1

R_SEL1

48

R_SEL2

47

R_SEL3

46

R_SEL4

45

R_SEL5

44

R_SEL6

VT1316MAFQX-041-GP

74.01316.F33

20101223 A00: Power/Brian: Change PU4201 to 74.01316.F33.

PR4240

PQ4201_G

G

12

DY

0R2J-2-GP

PC4211

PC4211 SC220P50V2JN-3GP

SC220P50V2JN-3GP

5V_S5

12

PR4207

PR4207 100R2F-L1-GP-U

100R2F-L1-GP-U

DY

AO7401-GP

PQ4203_G

PC4428

12

SC4700P50V2KX-1GP

DY

12

DCMDRP1 DCMDRP2

SENSE1-

SENSE1+

SENSE2-

SENSE2+

TEMP_SENSE1 TEMP_SENSE2

SPHASE1_0 SPHASE1_1 SPHASE1_2

SPHASE2

VCLK VDIO

VR_ENABLE

VR_TT# VR1_READY VR2_READY

ALERT#

NC#17 NC#20

GND GND GND

PQ4203

G

3

18 19

PWR_VCORE_SENSE1-

14

PWR_VCORE_SENSE1+

13

PWR_VCORE_SENSE2-

15

PWR_VCORE_SENSE2+

16

PWR_VCORE_TEMP_SENSE1

29 30

40 39 38 34

5 4

6 10 8

PWR_VCORE_VR2_DELAY

9

7

17 20

49 11 3

DY

D S

GND_1316

12

SCD047U25V2KX-GP

3D3V_S01D05V_VTT

PR4210130R2F-1-GP PR4210130R2F-1-GP

PR420854D9R2F-L1-GP PR420854D9R2F-L1-GP

1

1 2

5K76R2F-2-GP

12

PC4219

4

PR4233

23

12

PC4218

SCD047U25V2KX-GP

PWR_VCORE_DB1 (43)

D85V_PWRGD (48)

20101231 A00: Change PR4209,PR4212 to PN4201 10k array resistor. 20110117 A00: Swap PN4201 base on the swap report.

PN4201

PN4201 SRN10KJ-5-GP

SRN10KJ-5-GP

PWR_VCORE_DCMDRP1 PWR_VCORE_DCMDRP2

PR4217 0R0402-PADPR4217 0R0402-PAD

1 2

PR4218 0R0402-PADPR4218 0R0402-PAD

1 2

PR4219 0R0402-PADPR4219 0R0402-PAD

1 2

PR4220 0R0402-PADPR4220 0R0402-PAD

1 2

TEMP_SENSE_GFX

PWR_VCORE_SPHASE_0 PWR_VCORE_SPHASE_1

PWR_VCORE_TEMP_SENSE1_R

12

PR4238

43K2R2F-L-GP

1 2

PR4223 100KR2F-L1-GPPR4223 100KR2F-L1-GP

12

PR4239

PR4239 NTC-220K-2-GP

NTC-220K-2-GP

2

NTCG104QH224HT

VSSSENSE (8) VCCSENSE (8) VSS_AXG_SENSE (9) VCC_AXG_SENSE (9)

PR4254

1 2

0R0402-PAD

PWR_VCORE_SPHASE_0 (43) PWR_VCORE_SPHASE_1 (43)

1D05V_PWR

12

GND_1316

0R0402-PAD

SPHASE_GFX (44)

H_CPU_SVIDCLK (8)

H_CPU_SVIDDAT (8)

D85V_PWRGD (48)

H_PROCHOT# (5,27,40)

IMVP_PWRGD (27,36)

VR_SVID_ALERT# (8)

H_PROCHOT#

PR4243

PR4243 48K7R3F-1-GP

48K7R3F-1-GP

PR4249

PR4249 1K54R2F-GP

1K54R2F-GP

Title

Size Document Number Rev

A3

Date: Sheet

20101227 A00: Change PR4217~PR4220,PR4254 to 0R 0402 pad.

PR4255

61K9R2F-GP

TEMP_SENSE_GFX_R

12

1 2

PR4224 100KR2F-L1-GPPR4224 100KR2F-L1-GP

12

PR4256

PR4256 NTC-220K-2-GP

NTC-220K-2-GP

NTCG104QH224HT

1D05V_PWR

PWR_VCORE_DB1

20101012

12

PR4244

PR4244 221KR2F-GP

221KR2F-GP

PWR_VCORE_DCMDRP1

12

20101012

PC4228

PC4228 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

VT1316+1317_CPU_CORE(1/3)

12

PR4245

PR4245 158KR2F-GP

158KR2F-GP

12

PR4250

PR4250 5K11R2F-L1-GP

5K11R2F-L1-GP

GND_1316

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

12

1

H_PROCHOT#

DB1_GFX

PR4246

PR4246 475KR3F-GP

475KR3F-GP

PWR_VCORE_DCMDRP2

PC4229

PC4229 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

of

42 104Tuesday, January 18, 2011

A00

3D3V_PWR

D D

1D05V_PWR

12

PR4215

DY

100R2F-L1-GP-U

C C

12

PR4221

PR4221 6K98R2-GP

6K98R2-GP

B B

A A

PC4214

SCD022U16V2KX-3GP

GND_1316

12

DY

12

PC4231

SCD022U16V2KX-3GP

1 2

PG4203

PG4203 GAP-CLOSE-PWR

GAP-CLOSE-PWR

5

PR4216

PR4216 100R2F-L1-GP-U

100R2F-L1-GP-U

GND_1316

12

PR4222

PR4222 8K87R2F-2-GP

8K87R2F-2-GP

1KR2F-3-GP

DMN601K-7-GP

PWR_VCORE_IDES1_N(43) PWR_VCORE_IDES1_P(43)

IDES_N_GFX(44) IDES_P_GFX(44)

PR4251

DY

PQ4202

12

DY

GND_1316

PQ4202_DPWR_VCORE_IDES1_P

DS

PWR_VCORE_IDES1_N PWR_VCORE_IDES1_P

PR4225130KR2F-GP PR4225130KR2F-GP PR422644K2R2D-GP PR422644K2R2D-GP PR422944K2R2D-GP PR422944K2R2D-GP

PR423123K7R2F-GP PR423123K7R2F-GP PR423239K2R2F-L-GP PR423239K2R2F-L-GP PR423439K2R2F-L-GP PR423439K2R2F-L-GP PR423532K4R2F-1-GP PR423532K4R2F-1-GP PR423627K4R2F-GP PR423627K4R2F-GP PR423739K2R2F-L-GP PR423739K2R2F-L-GP PR42013K74R2F-GP PR42013K74R2F-GP

G

DMN601K-7-GP

4

5

PR4202

1 2

6K19R2F-GP

1 2

PC4202 SC1KP50V2KX-1GPPC4202 SC1KP50V2KX-1GP

4

PR4203

1 2

11K3R2F-2-GP

PWR_VCORE_IDES1_N_2

12

PC4203

PC4203 SC4700P50V2KX-1GP

SC4700P50V2KX-1GP

3

5V_S5

12

PC4208

PC4204

2

12

PC4209

PC4205

PC4206

12

PC4210

12

PC4207

1

D D

PR4213

1 2

6K19R2F-GP

PC4212

PWR_VCORE_IDES0_P_1

1 2

SC1KP50V2KX-1GP

PWR_VCORE_SPHASE_0(42)

C C

PWR_VCORE_IDES1_N(42)

PWR_VCORE_IDES1_P(42)

B B

PWR_VCORE_IDES1_P

SC1KP50V2KX-1GP

PR4230

1 2

6K19R2F-GP

1 2

PC4216 SC1KP50V2KX-1GPPC4216 SC1KP50V2KX-1GP

PWR_VCORE0_IDES_P_1

PR4206

3K09R2F-1-GP

PR4214

1 2

11K3R2F-2-GP

1 2

PWR_VCORE_IDES1_N_1PWR_VCORE_IDES1_N

PWR_VCORE1_IDES_P_1

3K09R2F-1-GP

12

PWR_VCORE0_IDES_N PWR_VCORE0_IDES_P

5V_S5

PR4227

11K3R2F-2-GP

PR4241

PR4211

1 2

10R2J-2-GP

12

PC4217

PC4217 SC4700P50V2KX-1GP

SC4700P50V2KX-1GP

12

PWR_VCORE_DB0(42) PWR_VCORE_DB1(42) PWR_VCORE_DB2(42)

PC4215

SCD1U25V3KX-GP

PU4202_AVDD

12

PU4202

A5

IDES_N

A4

IDES_P

A6

DB0

A1

DB1

B1

DB2

B6

SPHASE

A3

AVDD

B3

AGND

B4

AGND

B5

AGND

VT1317SFCX-001-GP

A2

B2

GND_1317S_1

C6

E6

VDDHC4VDDHC5VDDH

VDDHE4VDDHE5VDDH

74.01317.B3Z

GNDC1GNDC2GND

GNDE1GNDE2GND

E3

C3

PG4201

1 2

GAP-CLOSE-PWR

G6

VDDHG4VDDHG5VDDH

GNDJ1GNDJ2GND

J3

SC10U6D3V3MX-GP

J6

VX#H1

VDDHJ4VDDHJ5VDDH

VX#H2 VX#H3 VX#H4 VX#H5 VX#H6 VX#D1 VX#D2 VX#D3 VX#D4 VX#D5 VX#D6 VX#F6 VX#F5 VX#F4 VX#F3 VX#F2 VX#F1

GNDG1GNDG2GND

G3

5V_S5

12

PC4220

SC10U6D3V3MX-GP

H1 H2 H3 H4 H5 H6 D1 D2 D3 D4 D5 D6 F6 F5 F4 F3 F2 F1

12

PC4222

PC4221

SC10U6D3V3MX-GP

PWR_VCORE_VX0

12

PC4223

SC10U6D3V3MX-GP

SC1U10V2KX-1GP

SCD1U25V3KX-GP

12

SCD1U25V3KX-GP

68.2415N.101

12

PC4226

SCD1U25V3KX-GP

4

3

PL4201

PL4201 IND-240NH-GP

IND-240NH-GP

1

2

SC10U6D3V3MX-GP

20101231 A00: Power/Brian: change PL4201 to 68.2415N.101 from 68.10110.10G.

12

PC4224

PC4225

SC1U10V2KX-1GP

VCC_CORE

C6

E6

G6

VDDHG4VDDHG5VDDH

J3

VDDHJ4VDDHJ5VDDH

GNDJ1GNDJ2GND

G3

J6

PWR_VCORE_VX1

H1

VX#H1

H2

VX#H2

H3

VX#H3

H4

VX#H4

H5

VX#H5

H6

VX#H6

D1

VX#D1

D2

VX#D2

D3

VX#D3

D4

VX#D4

D5

VX#D5

D6

VX#D6

F6

VX#F6

F5

VX#F5

F4

VX#F4

F3

VX#F3

F2

VX#F2

F1

VX#F1

GNDG1GNDG2GND

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

VT1316+1317_CPU_CORE(2/3)

Size Document Number Rev

A3

Date: Sheet

VT1316+1317_CPU_CORE(2/3)

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

43 104Tuesday, January 18, 2011

1

A00

PU4203

PR4248

PR4247

1 2

6K19R2F-GP

PC4227

SC1KP50V2KX-1GP

PWR_VCORE_SPHASE_1(42)

A A

5

PWR_VCORE_IDES1_P_1

1 2

4

PR4248

1 2

11K3R2F-2-GP

5V_S5

PWR_VCORE1_IDES_N PWR_VCORE1_IDES_P

PWR_VCORE_DB0(42) PWR_VCORE_DB1(42) PWR_VCORE_DB2(42)

PR4242

1 2

10R2J-2-GP

PC4230

SCD1U25V3KX-GP

PU4203_AVDD

12

PU4203

A5

IDES_N

A4

IDES_P

A6

DB0

A1

DB1

B1

DB2

B6

SPHASE

A3

AVDD

B3

AGND

B4

AGND

B5

AGND

VT1317SFCX-001-GP

A2

B2

GND_1317S_2

3

VDDHC4VDDHC5VDDH

VDDHE4VDDHE5VDDH

74.01317.B3Z

GNDC1GNDC2GND

GNDE1GNDE2GND

E3

C3

PG4202

1 2

GAP-CLOSE-PWR

5

D D

PR4402

20101012

IDES_N_GFX(42)

C C

IDES_P_GFX(42)

B B

1 2

3K24R2F-GP

PC4413

1 2

SC2700P50V2KX-1-GP

PC4422

1 2

SC2700P50V2KX-1-GP

PR4406

1 2

20101012

3K24R2F-GP

PR4403

1 2

11KR2F-L-GP

IDES_N_GFX_1

IDES_P_GFX_1

PR4405

1 2

11KR2F-L-GP

SPHASE_GFX(42)

4

PC4414

12

SC4700P50V2KX-1GP

PWR_AXG_IDES_P_1

12

PR4404

3K09R2F-1-GP

DB0_GFX(42) DB1_GFX(42) DB2_GFX(42)

SCD1U25V3KX-GP

5V_S5

12

PWR_AXG_IDES_P

PWR_AXG_AVDD

12

PC4427

PR4401

PR4401 10R2J-2-GP

10R2J-2-GP

A5 A4

A6 A1 B1

B6

A3 B3 B4 B5

PU4401

IDES_N IDES_P

DB0 DB1 DB2

SPHASE

AVDD AGND AGND AGND

AGND

A2

GND_1317S_3

C6

VDDHC4VDDHC5VDDH

74.01317.B3Z

AGND

GNDE1GNDE2GND

B2

E3

1 2

PG4401

PG4401 GAP-CLOSE-PWR

GAP-CLOSE-PWR

E6

VDDHE4VDDHE5VDDH

VDDHG4VDDHG5VDDH

GNDC1GNDC2GND

J3

C3

3

G6

VDDHJ4VDDHJ5VDDH

GNDJ1GNDJ2GND

G3

320mils or Copper Shape

5V_S5

12

PC4415

SC10U6D3V3MX-GP

J6

H1

VX#H1

H2

VX#H2

H3

VX#H3

H4

VX#H4

H5

VX#H5

H6

VX#H6

D1

VX#D1

D2

VX#D2

D3

VX#D3

D4

VX#D4

D5

VX#D5

D6

VX#D6

F6

VX#F6

F5

VX#F5

F4

VX#F4

F3

VX#F3

F2

VX#F2

F1

VX#F1

GNDG1GNDG2GND

VT1317SFCX-001-GP

12

PC4416

PC4417

SC10U6D3V3MX-GP

PWR_AXG_VXPWR_AXG_IDES_N

12

PC4418

SC10U6D3V3MX-GP

PL4401

1 2

IND-D1UH-26-GP

68.R1010.10T

2

12

PC4420

PC4419

SC1U10V2KX-1GP

8+a8+

8+a8+8+a8+

12

PC4423

PC4401

SC22U6D3V5MX-2GP

12

PC4402

12

PC4404

PC4403

DY

SC22U6D3V5MX-2GP

12

PC4421

SCD1U25V3KX-GP

2120mils or Copper Shape

12

PC4424

SC22U6D3V5MX-2GP

12

PC4425

PC4426

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

2120mils or Copper Shape

12

PC4405

12

PC4406

SC22U6D3V5MX-2GP

12

PC4408

PC4407

SC22U6D3V5MX-2GP

12

PC4409

PC4410

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

1

VCC_GFXCORE

12

PC4412

PC4411

SC22U6D3V5MX-2GP

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

VT1316+1317_AXG_CORE(3/3)

Size Document Number Rev

A3

Date: Sheet

VT1316+1317_AXG_CORE(3/3)

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

of

44 104Tuesday, January 18, 2011

1

A00

5

D D

3D3V_S0

12

PR4502

100KR2J-1-GP

C C

RUNPWROK(19,46,47)

1.05VTT_PWRGD(37,48)

20101227 A00: Change PR4503,PR4505,PR4504,PR4509 to 0R 0402 pad.

100KR2J-1-GP

PR4503 0R0402-PADPR4503 0R0402-PAD

1 2

PR4505 0R0402-PADPR4505 0R0402-PAD

1 2

12

PC4507

12

PR4501

34K8R2F-1-GP

PR4501

34K8R2F-1-GP

PR4506

44K2R2D-GP

4

PC4524

SCD22U10V3KX-2GP

AGND_1R05B_VTT

PWR_1D05V_IRIPL

PWR_1D05V_BIAS

PWR_1D05V_R_SEL/LOAD

PWR_1D05V_OE

12

PR4507

PR4507 6K49R2F-1-GP

6K49R2F-1-GP

5V_S5

12

PR4512

PR4512 10R2J-2-GP

10R2J-2-GP

12

PWR_1D05V_AVDD

PU4501

B2 B4 A1 A2

A5 B5

B3

AVDD

IRIPL TEMP BIAS R_SEL/ILOAD

VT357FCX-ADJ-007-GP

OE STAT

GNDC1GNDC2GND

C3

C5

VDDC4VDD

VDDE4VDD

GNDE1GNDE2GND

E3

3

140mils or Copper Shape

12

PC4502

SC22U6D3V5MX-2GP

E5

PWR_1D05V_VX

D1

VX#D1

D2

VX#D2

D3

VX#D3

D4

VX#D4

D5

VX#D5

A4

VSENSE+

VDES

AGND

B1

PWR_1D05V_VDESPWR_1D05V_STAT

A3

12

PC4503

SC22U6D3V5MX-2GP

PL4501

1 2

COIL-D20UH-GP

68.R2010.201

2

5V_S5

12

PC4504

SCD1U10V2KX-4GP

PC4501

SCD1U10V2KX-4GP

12

PC4505

VREF=1.21V

SC1U10V2KX-1GP

Vout=VREF*(Rdes/Rbios)

Design Current = 9.4A<OCP<A

400mils or Copper Shape

12

PC4508

SC22U6D3V5MX-2GP

12

PC4509

PC4510

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

12

PC4511

PC4512

SC22U6D3V5MX-2GP

22u * 12PCS

12

PC4513

SC22U6D3V5MX-2GP

ˢˢˢˢ

1D05V_PWR

12

PC4514

SC6800P25V2KX-1GP

1

1D05V_PWR

1 2

PG4501

PG4501 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4502

PG4502 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4503

PG4503 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4504

PG4504 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4505

PG4505 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4506

PG4506 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4507

PG4507 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4508

PG4508 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4509

PG4509 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4510

PG4510 GAP-CLOSE-PWR

GAP-CLOSE-PWR

12

PC4515

SCD1U10V2KX-4GP

1D05V_VTT

SCD01U25V2KX-3GP

AGND_1R05B_VTT

B B

PG4511

PG4511 GAP-CLOSE-PWR

GAP-CLOSE-PWR

AGND_1R05B_VTT

1 2

12

PC4516

SC22U6D3V5MX-2GP

12

PC4517

SC22U6D3V5MX-2GP

1D05V_PWR

PWR_1D05V_VSENSE+

12

PC4518

SC22U6D3V5MX-2GP

1 2

close output MLCC

PC4519

SC22U6D3V5MX-2GP

PR4513

PR4513 100R2F-L1-GP-U

100R2F-L1-GP-U

12

PC4521

PC4520

PC4521

DY

SC22U6D3V5MX-2GP

PR4504

1 2

0R0402-PAD

12

DY

SC22U6D3V5MX-2GP

VCCIO_SENSE (8)

VSENSE-TRACE

12

PR4508

1MR2F-GP

DY

12

PR4511

PR4511 38K3R2D-GP

38K3R2D-GP

12

PC4522

PC4522 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

PWR_1D05V_VSENSE-

0.5A= 20mils

A A

5

4

3

2

ROUTED DIFFERENTIALLY PARALLEL TO VSENSE+

PR4509

close output MLCC

PR4514

PR4514 100R2F-L1-GP-U

100R2F-L1-GP-U

1 2

Title

Size Document Number Rev

A3

Date: Sheet

1 2

0R0402-PAD

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

VT357_+1.05V_VTT

Nirvana 13

VSSIO_SENSE (8)

45 104Tuesday, January 18, 2011

1

A00

of

A00

5

4

3

2

1

SSID = PWR.Plane.Regulator_1p5v0p75v

180mils or Copper Shape

12

PU4602

D D

C C

B B

20101227 A00: Change PR4605,PR4607,PR4611,PR4602 to 0R 0402 pad.

PM_SLP_S4#(19,27)

RUNPWROK(19,45,47)

1 2

PR4607 0R0402-PADPR4607 0R0402-PAD

1 2

PR4605 0R0402-PADPR4605 0R0402-PAD

AGND_1D5V_PWR

12

PR4604

PC4614

44K2R2D-GP

SCD01U25V2KX-3GP

1 2

PG4618

PG4618 GAP-CLOSE-PWR

GAP-CLOSE-PWR

12

PR4610

5K9R2F-GP

AGND_1D5V_PWR

PWR_1D5V_BIAS PWR_1D5V_R_SEL/ILOAD

PWR_1D5V_OE PWR_1D5V_STAT

PWR_1D5V_IRIPL

12

PR4603

34K8R2F-1-GP

12

PR4601

DY

1MR2F-GP

A1 A2 A3 A4 A5 B5 B4 B2

B1

C1 C2 C3 E1 E2

E3 G1 G2 G3

74.00358.A3Z

PWR_1D5V_VDES

12

PR4608

56K2R2F-2-GP

BIAS R_SEL/ILOAD VDES VSENSE+ OE STAT TEMP IRIPL

AGND

GND GND GND GND GND GND GND GND GND

VT358FCX-ADJ-007-GP

PU4602

VDD VDD VDD VDD VDD VDD

AVDD

VX#D1 VX#D2 VX#D3 VX#D4 VX#D5 VX#F1 VX#F2 VX#F3 VX#F4 VX#F5

12

PC4626

SC2200P50V2KX-2GP

PR4606

C4 C5 E5 G4 E4 G5

B3

D1 D2 D3 D4 D5 F1 F2 F3 F4 F5

PR4606

10R2J-2-GP

PWR_1D5V_AVDD

PWR_1D5V_VX

PWR_1D5V_VSENSE+

PWR_1D5V_VSENSE-

12

PC4628

SC22U6D3V5MX-2GP

1 2

68.R2010.201

close output MLCC

12

PC4607

SC22U6D3V5MX-2GP

PC4625

PC4625 SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

12

PL4601

COIL-D20UH-GP

1 2

PG4619

PG4619 GAP-CLOSE-PWR

GAP-CLOSE-PWR

close output MLCC

VSENSE-TRACE ROUTED DIFFERENTIALLY PARALLEL TO VSENSE+

1 2

PG4620

PG4620 GAP-CLOSE-PWR

GAP-CLOSE-PWR

12

PC4617

SCD1U10V2KX-4GP

AGND_1D5V_PWR

12

PC4610

SC22U6D3V5MX-2GP

PC4618

PC4623

PC4622

5V_S5

VREF=1.21V Vout=VREF*(Rdes/Rbios)

12

SCD1U10V2KX-4GP

12

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

1D5V_PWR

12

PC4611

SC1U10V2KX-1GP

720mils or Copper Shape

12

PC4608

PC4619

SC22U6D3V5MX-2GP

12

PC4613

PC4620

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

22u * 12PCS

12

SC22U6D3V5MX-2GP

12

PC4621

SC22U6D3V5MX-2GP

12

PC4616

SC22U6D3V5MX-2GP

Design Current = 13.7A

21.6A<OCP< 25.4A

1D5V_PWR

12

PC4624

SC22U6D3V5MX-2GP

12

DY

PC4615

SC22U6D3V5MX-2GP

12

PC4627

PC4612

PC4609

SC6800P25V2KX-1GP

12

DY

SC22U6D3V5MX-2GP

12

SCD1U10V2KX-4GP

ˢˢˢˢ

1D5V_PWR

1 2

PG4617

PG4617 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4604

PG4604 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4606

PG4606 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4605

PG4605 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4608

PG4608 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4607

PG4607 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4614

PG4614 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4609

PG4609 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4611

PG4611 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4610

PG4610 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4613

PG4613 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4612

PG4612 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4616

PG4616 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4615

PG4615 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1D5V_S3

RT9026 for 0D75V_S0

1 2

12

PC4604

SC10U6D3V3MX-GP

3

1D5V_S3

0D75V_PWR

12

PC4601

1 2

PG4601

PG4601 GAP-CLOSE-PWR

GAP-CLOSE-PWR

1 2

PG4602

PG4602 GAP-CLOSE-PWR

GAP-CLOSE-PWR

SC10U6D3V3MX-GP

0.75V_PWR Design Current: 0.7A

0D75V_S0

1A= 40mils

0.5A= 20mils

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

VT358_+1.5V_SUS/+0.75V_SUS

Size Document Number Rev

A3

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

A00

of

46 104Tuesday, January 18, 2011

1

A00

5V_S5

12

PC4606

SC10U6D3V3MX-GP

VDDQSNS

VLDOIN

VTT

PGND

VTTSNS

GND

RT9026PFP-GP

11

0D75V_PWR_VLDOIN

12

PC4605

SCD1U10V2KX-4GP

1 2 3 4 5

PG4603

PG4603 GAP-CLOSE-PWR

GAP-CLOSE-PWR

Please near U34/Pin10

SC4D7U10V5KX-1GP

A A

PM_SLP_S3#(19,27,36,37,47)

0D75V_EN(37)

PM_SLP_S4#(19,27)

1 2

DY

PR4613 0R2J-2-GP

1 2

PR4602 0R0402-PADPR4602 0R0402-PAD

5

1 2

PR4611 0R0402-PADPR4611 0R0402-PAD

12

PC4629

DY

SCD1U10V2KX-4GP

DDR_VREF_S3

12

PC4630

DY

SCD1U10V2KX-4GP

PC4603

0D75V_PWR_S5

0D75V_PWR_S3

PC4602

4

12

PU4601

10

VIN

9

S5

8

GND

7

S3

6

12

VTTREF

5

4

SSID = PWR.Plane.Regulator_1p8v

3

2

1

D D

1A= 40mils

1.5A= 60mils

0.5A= 20mils

3D3V_S5

SCD1U25V3KX-GP

PU4701

12

C C

12

DY

PR4717

PR4717 57K6R2F-GP

57K6R2F-GP

B B

PC4702 SC100P50V2JN-3GPPC4702 SC100P50V2JN-3GP

1 2

PR4705

PWR_1D8V_FB_1

1 2

5K9R2F-GP

3D3V_S0

RUNPWROK(19,45,46)

PM_SLP_S3#(19,27,36,37,46)

1 2

PC4718 SC2200P50V2KX-2GPPC4718 SC2200P50V2KX-2GP

PWR_1D8V_PS

PR4707 20KR2J-L2-GPPR4707 20KR2J-L2-GP

1 2

PR4715 10KR2J-3-GPPR4715 10KR2J-3-GP

PWR_1D8V_FB

PWR_1D8V_COMP

1 2

12

1D8V_EN

PC4703

PC4703 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

VDD

11

AGND

17

PGND

10

FB

9

COMP

2

RES

8

MODE

3

PGOOD

1

EN

TPS51311RGTR-GP

74.51311.073

PGND PGND

VBST

SW#5 SW#6 SW#7

13

VIN

14

VIN

15 16

PWR_1D8V_VBST PWR_1D8V_VBST_1

4

PWR_1D8V_SW

5 6 7

PR4706

1 2

0R0603-PAD

SCD1U25V3KX-GP

PC4708

SCD1U25V3KX-GP

12

PC4716

68.2R210.20B

PWR_1D8V_VIN

12

PC4715

PC4715 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

PL4701

IND-2D2UH-46-GP-U

1 2

PC4717

SC2200P50V2KX-2GP

PC4717

PR4718

PR4718 40D2R2F-GP

40D2R2F-GP

12

PR4702

20KR2F-L-GP

PWR_1D8V_FB_2

12

PWR_1D8V_FB

12

PR4716

PR4716 10KR2F-2-GP

10KR2F-2-GP

1 2

PG4701

GAP-CLOSE-PWR

1 2

PG4702

GAP-CLOSE-PWR

PC4721

PC4721 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

PWR_1D8V_RUN 1D8V_S0

12

PC4719

DY

SC10U6D3V5MX-3GP

PC4720

12

PC4707

SCD1U25V3KX-GP

3D3V_S5

PG4704

1 2

GAP-CLOSE-PWR

PG4705

1 2

GAP-CLOSE-PWR

PG4706

1 2

GAP-CLOSE-PWR

SC22U6D3V5MX-2GP

PG4707

1 2

GAP-CLOSE-PWR

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51311_ +1.8V_RUN

Size Document Number Rev

A3

Date: Sheet

TPS51311_ +1.8V_RUN

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

47 104Tuesday, January 18, 2011

1

A00

5

4

3

2

1

TPS51461 for VCCSA

D D

PR4806

PR4806 1R2F-GP

1R2F-GP

C C

5V_S5

12

PC4803

SCD1U25V3KX-GP

B B

VID0 VCCSA

L

12

PC4815

PC4813

SC4D7U25V5KX-GP

VID1

L

H

12

SC4D7U25V5KX-GP

H

5V_S5

12

PC4816

SC2D2U10V3KX-1GP

12

PC4819

SC4D7U25V5KX-GP

0.9V

0.8V

0.725VL

0.675V

12

PC4814

SC1U10V2KX-1GP

PWR_VCCSA_V5DRV

3D3V_S0

12

PR4809

PR4809 4K7R2J-2-GP

4K7R2J-2-GP

PR4808

1 2

0R0402-PAD

PWR_VCCSA_VID1

PWR_VCCSA_VID0

PWR_VCCSA_EN

16

13

17

18

15

EN

VID014VID1

V5FILT

V5DRV PGND PGND PGND VIN VIN VIN GND

PGOOD

SW#11 SW#10

SW#9 SW#8 SW#7

GND1VREF2COMP3SLEW4VOUT5MODE

6

PWR_VCCSA_VREF

PWR_VCCSA_VOUT

PWR_VCCSA_SLEW

12

PR4802

PR4802 4K99R2F-L-GP

4K99R2F-L-GP

PWR_VCCSA_COMP_1PWR_VCCSA_COMPPWR_VCCSA_PGOOD

12

PC4817

PC4817 SC3300P50V3KX-1GP

SC3300P50V3KX-1GP

19 20 21 22 23 24 25

U4801

TPS51461RGER-GP

12

BST

11 10 9 8 7

74.51461.043

D85V_PWRGD (42)

PR4804

1 2

0R0402-PAD

0R0402-PAD PR4805

PR4805

1 2

0R0402-PAD

1 2

12

DY

PC4804

SC1U6D3V2KX-GP

PWR_VCCSA_BST

PWR_VCCSA_SW

PC4806

PC4806 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

1 2

PR4812

1 2

DY

1KR2F-3-GP

PR4801

PR4801 0R0402-PAD

0R0402-PAD

PR4807

1 2

0R0603-PAD

PR4811

1 2

100R2F-L1-GP-U

PR4810

1 2

0R0402-PAD

VCCSA_SEL (9)

H_FC_C22 (9)

PWR_VCCSA_BST_R

0D85V_S0

VCCUSA_SENSE (9)

1.05VTT_PWRGD (37,45)

PC4805

SCD1U25V3KX-GP

1 2

12

PR4803

PR4803 2D2R5F-2-GP

2D2R5F-2-GP

DY

68.R4710.10M

PWR_VCCSA_SNUB

12

PC4818

PC4818 SC560P50V-GP

SC560P50V-GP

PL4801

1 2

IND-D47UH-22-GP

PC4808

PC4809

SC22U6D3V5MX-2GP

12

DY

PC4809

12

SC22U6D3V5MX-2GP

PC4810

PC4807

SC22U6D3V5MX-2GP

12

Design Current = 4.2A

6.6A<OCP< 7.8A

0D85V_S0

PC4811

PC4801

SC22U6D3V5MX-2GP

12

PC4812

SCD1U25V3KX-GP

DY

PC4802

PC4802 SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

1 2

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

APL5916_VCCSA

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

48 104Tuesday, January 18, 2011

1

A00

SSID = VIDEO

DBC_EN_C

LVDS CONNECTOR

LCD1

31

NP1

NP2

32

PS-CON30-GP

20.F1816.030

CAMERA and DIGITAL MIC PIN DEFINE!

DCBATOUT_LCD

1

2 3 4 5 6 7 8 9 10 11 12

LVDSA_CLK_R

13

LVDSA_CLK#_R

14

CE_C

15

LVDSA_DATA2_R

16

LVDSA_DATA2#_R

17 18

LVDSA_DATA1_R

19

LVDSA_DATA1#_R

20 21

LVDSA_DATA0_R

22

LVDSA_DATA0#_R

23 24 25

LCD_TST_C

26 27 28 29 30

BLON_OUT_C_1 LCD_BRIGHTNESS DBC_EN_C

USB_CAMERA# USB_CAMERA

12

SD103AWS-1-GP

1

TP4904TPAD14-GPTP4904TPAD14-GP

LCDVDD

C4901

SCD1U10V2KX-5GP

R4901

33R2J-2-GP

12

R4906

R4906 10KR2J-3-GP

10KR2J-3-GP

DY

83.1R504.A8F

2nd = 83.1R504.B8F

PD4901

K A

3D3V_CAMERA_S0

1 2

R49080R2J-2-GP R49080R2J-2-GP

1 2

R49090R2J-2-GP R49090R2J-2-GP

AUD_DMIC_CLK (29,97)

AUD_DMIC_IN0 (29,97)

TP4903TPAD14-GPTP4903TPAD14-GP

LVDS_DDC_DATA_R_1 LVDS_DDC_CLK_R_1

C4902

SC1U6D3V2KX-GP

1 2

BLON_OUT_C

R4902

R4902 33R2J-2-GP

33R2J-2-GP

3D3V_S0

12

DBC_EN (22)

USB_PN12 (18) USB_PP12 (18)

20101227 A00: Change R4908,R4909,R4919,R4920,R4903,R4910,R4913~R4916 R4917,R4918 to 0R 0402 pad. 20110111 A00: Change R4908,R4909,R4903,R4910,R4913~R4916 R4917,R4918 to 0R 0402 reisstors.

1 2 1 2

R49190R2J-2-GP R49190R2J-2-GP R49200R2J-2-GP R49200R2J-2-GP

LVDSA_DATA2_R LVDSA_DATA2#_R

LVDSA_DATA1_R LVDSA_DATA1#_R

LVDSA_DATA0_R LVDSA_DATA0#_R

LVDSA_DATA2_R LVDSA_DATA2#_R

LVDSA_DATA1_R LVDSA_DATA1#_R

LVDSA_DATA0_R LVDSA_DATA0#_R

LVDSA_CLK_R LVDSA_CLK#_R

CE_C

12

DY

LVDS_DDC_DATA_R (17,97) LVDS_DDC_CLK_R (17,97)

R4903 0R2J-2-GPR4903 0R2J-2-GP

1 2

R4910 0R2J-2-GPR4910 0R2J-2-GP

1 2

R4913 0R2J-2-GPR4913 0R2J-2-GP

1 2

R4914 0R2J-2-GPR4914 0R2J-2-GP

1 2

R4915 0R2J-2-GPR4915 0R2J-2-GP

1 2

R4916 0R2J-2-GPR4916 0R2J-2-GP

1 2

EC4906 SC10P50V2JN-4GP

1 2

DY

EC4907 SC10P50V2JN-4GP

1 2

DY

EC4908 SC10P50V2JN-4GP

1 2

DY

EC4909 SC10P50V2JN-4GP

1 2

DY

EC4910 SC10P50V2JN-4GP

1 2

DY

EC4911 SC10P50V2JN-4GP

1 2

DY

R4917 0R2J-2-GPR4917 0R2J-2-GP

1 2

R4918 0R2J-2-GPR4918 0R2J-2-GP

1 2

R4911

33R2J-2-GP

R4912

R4912 10KR2J-3-GP

10KR2J-3-GP

L_BKLT_CTRL (17)

12

SRN2K2J-1-GP

RN9403

LVDS_DDC_CLK_R LVDS_DDC_DATA_R

LVDSA_DATA2 (17) LVDSA_DATA2# (17)

LVDSA_DATA1 (17) LVDSA_DATA1# (17)

LVDSA_DATA0 (17) LVDSA_DATA0# (17)

LVDSA_CLK (17) LVDSA_CLK# (17)

CE (21)

3D3V_S0

1

23

4

SSID = VIDEO

LCD POWER for ROSA

BAT54CPT-GP

LVDS_VDD_EN(17)

LCD_TST_EN(27)

LVDS_VDD_EN

R4951

100KR2J-1-GP

12

1

2

D4901

83.R2003.E81

2ND = 83.00054.Q81

BLON_OUT_C_1

3

1 2

BLON_OUT_C LCD_TST_C

R4921

1 2

100KR2J-1-GP

R4907

DY

12

R4905

100KR2J-1-GP

R4904

1 2

0R0402-PAD

49K9R2F-L-GP

RN4901

1 2 3

SRN100J-3-GP

ENVDDLCDVDD_EN

SCD1U10V2KX-5GP

12

DY

4

C4908

U4901

1

EN

IN#5

2

GND OUT3IN#4

G5285T11U-GP

74.05285.07F

2nd = 74.09724.09F

BLON_OUT (27)

LCD_TST (27)

3D3V_S0LCDVDD

5

4

12

C4907

SC1U10V3KX-3GP

DCBATOUT_LCD DCBATOUT

F4901

12

C4905

C4904

20110107 A00: Change F4902 to 0603 0 ohm.

C4905

1 2

SCD1U50V3KX-GP

SC1KP50V2KX-1GP

Camera Power

F4902

1 2

0R3J-0-U -GP

EC4903

SCD1U10V2KX-5GP

12

POLYSW-1D1A24V-GP-U

69.50007.A31

2nd = 69.50007.A41

3D3V_CAMERA_S03D3V_S0

12

C4903

DY

SC10U6D3V5KX-1GP

For EMI request

Close to LVDS connector

LCD_BRIGHTNESS LCD_TST_C

LVDSA_CLK# LVDSA_CLK

EC4904

SC5D6P50V2CN-1GP

DY

12

EC4905

12

DY

SC5D6P50V2CN-1GP

12

EC4902

EC4901

DY

SC33P50V2JN-3GP

20100104 A00: Remove TR4902.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

LCD/Inverter Connector

Size Document Number Rev

A3

Date: Sheet

LCD/Inverter Connector

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

49 104Tuesday, January 18, 2011

of

A00

5

Reserve for ATI to debug

R5007 0R2J-2-GP

1 2

DY

D D

CRT_RED(17)

CRT_GREEN(17)

CRT_BLUE(17)

C C

VGA_CRT_RED(85) VGA_CRT_GREEN(85) VGA_CRT_BLUE(85)

R5010 0R0402-PADR5010 0R0402-PAD

R5011 0R0402-PADR5011 0R0402-PAD

R5012 0R0402-PADR5012 0R0402-PAD

20101224 A00: Change R5010~R5012 to 0402 0 ohm pad.

DY

R5008 0R2J-2-GP

1 2

DY

R5009 0R2J-2-GP

1 2

DY

CRT_RED_R

12

CRT_GREEN_R

12

CRT_BLUE_R

12

R5001

R5002

150R2F-1-GP

12

R5003

150R2F-1-GP

Reduce layout branch trace. Keep reserved component near main signal

4

12

C5001

C5002

DY

SC10P50V2JN-4GP

12

C5003

DY

SC10P50V2JN-4GP

L5001

1 2

FCM1608CF-220T05-GP

L5002

1 2

FCM1608CF-220T05-GP

L5003

1 2

FCM1608CF-220T05-GP

12

C5004

C5005

SC10P50V2JN-4GP

12

C5006

SC10P50V2JN-4GP

CRT_R

CRT_G

CRT_B

12

3

5V_S0

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

500mA

5V_CRT_S0 5V_CRT_S0_R

D5001

21

CH551H-30PT-GP

CRT_B

3

D5004

D5004 BAV99PT-GP-U

BAV99PT-GP-U

DY

1

2

Place closer

F5001

1 2

FUSE-1D1A6V-4GP-U

69.50007.691

69.50007.691 2nd = 69.50007.771

2nd = 69.50007.771

R5006

1 2

DY

0R3J-0-U -GP

CRT_G

3

D5003

D5003 BAV99PT-GP-U

BAV99PT-GP-U

DY

1

2

CRT_R

5V_CRT_S0_R

C5013

SCD01U16V2KX-3GP

CRT_R

3

D5002

D5002 BAV99PT-GP-U

BAV99PT-GP-U

DY

1

2

C5013

3D3V_S0

CRT_G

CRT_B

12

CRT_DDCDATA_CON

CRT_HSYNC_CON

CRT_VSYNC_CON

CRT_DDCCLK_CON

C5011

CRT1

16

6 1

7 2 8 3 9 4

10

5

17

D-SUB-15-81-GP

12

DY

1

C5010

DY

11

12

13

14

15

12

CRT_DDCDATA_CON

CRT_HSYNC_CON

CRT_VSYNC_CON

CRT_DDCCLK_CON

12

DY

C5008

C5009

SC18P50V2JN-1-GP

SC100P50V2JN-3GP

CRT Hsync & Vsync level shift

SC100P50V2JN-3GP

CRT DDCDATA & DDCCLK level shift

B B

RN5001

SRN0J-6-GP

1

VGA_CRT_HSYNC(83,85) VGA_CRT_VSYNC(83,85)

CRT_HSYNC(17) CRT_VSYNC(17)

20101227 A00: Change R5013~R5016 to 0R 0402 pad.

A A

5

12

R5013 0R0402-PADR5013 0R0402-PAD

12

R5014 0R0402-PADR5014 0R0402-PAD

DY

2 3

CRT_HSYNC_R CRT_VSYNC_R

4

RN5004

1

4

2 3

SRN33J -5-GP-U

20101231 A00: Change R5004,R5005 to RN5001 33 ohm array resistor.

SRN33J -5-GP-U

4

CRT_HSYNC_CON CRT_VSYNC_CON

VGA_CRT_DDCDATA(85) VGA_CRT_DDCCLK(85)

3

Reserve for ATI to debug

CRT_DDC_DATA(17)

CRT_DDC_CLK(17)

RN5002

SRN0J-6-GP

1

4

2 3

DY

R5015 0R0402-PADR5015 0R0402-PAD

R5016 0R0402-PADR5016 0R0402-PAD

12

RN5007

SRN2K2J-1-GP

CRT_DDC_DATA_R

CRT_DDC_CLK_R

3D3V_S0

2

5V_CRT_S0

1

23

4

3D3V_S0

Q5001

34

2

5

1

6

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

Title

CRT Connector

Size Document Number Rev

A3

Date: Sheet

CRT Connector

Nirvana 13

1

23

RN5003

RN5003 SRN2K2J-1-GP

SRN2K2J-1-GP

4

CRT_DDCDATA_CON

CRT_DDCCLK_CON

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

50 104Tuesday, January 18, 2011

1

A00

5

4

3

2

1

SSID = VIDEO

D D

HDMI_CLK#(85) HDMI_CLK(85)

HDMI_DATA0#(85) HDMI_DATA0(85)

C C

HDMI_DATA1#(85) HDMI_DATA1(85)

HDMI_DATA2#(85) HDMI_DATA2(85)

HDMI_CLK_R#(17) HDMI_CLK_R(17)

HDMI_DATA0_R#(17) HDMI_DATA0_R(17)

HDMI_DATA1_R#(17) HDMI_DATA1_R(17)

B B

HDMI_DATA2_R#(17) HDMI_DATA2_R(17)

20100106 A00: Remove RN5112~RN5115. 20110111 A00: Change RN5112~RN5115 to 0R array resistors.

A A

2N7002K-2-GP

HPD_HDMI_CON

Removed LEVEL SHIFTER base on DELL feedback spec. (No support 220MHZ deep color mode, so can be removed HDMI LEVEL SHIFTER circuit.

Close to GPU

HDMI_CLK# HDMI_CLK

HDMI_DATA0# HDMI_DATA0

HDMI_DATA1# HDMI_DATA1

HDMI_DATA2# HDMI_DATA2

Close to PCH

RN5112 SRN0J-6-GPRN5112 SRN0J-6-GP

2 3 1

4

2 3 1

4

2 3 1

4

2 3 1

4

HDMI_OE#

1 2

84.2N702.J31

2ND = 84.2N702.031

Q5101

RN5113 SRN0J-6-GPRN5113 SRN0J-6-GP

RN5115 SRN0J-6-GPRN5115 SRN0J-6-GP

RN5114 SRN0J-6-GPRN5114 SRN0J-6-GP

3D3V_S0

12

DY

D

DY

G

5

R5109

R5109 20KR2J-L2-GP

20KR2J-L2-GP

S

HDMI Level Shifter & CONNECTOR

HDMI_PLL_GND

D

G

RN5108

1 2 3

RN5109

RN5110

1 2 3

RN5111

HDMI_CLK_R#_1 HDMI_CLK_R_1

HDMI_DATA0_R#_1 HDMI_DATA0_R_1

HDMI_DATA1_R#_1 HDMI_DATA1_R_1

HDMI_DATA2_R#_1 HDMI_DATA2_R_1

GPU_HDMI_CLK(85)

GPU_HDMI_DATA(85)

DY

0R2J-2-GP

HDMI_CLK_R#_1

4

HDMI_CLK_R_1

HDMI_DATA0_R#_1 HDMI_DATA0_R_1

HDMI_DATA1_R#_1 HDMI_DATA1_R_1

HDMI_DATA2_R#_1 HDMI_DATA2_R_1

DY

SRN0J-6-GP

DY

SRN0J-6-GP

SRN0J-6-GP SRN0J-6-GP

SRN0J-6-GP

DY

Close to HDMI Connector

ATI GPU has 5V Tolerance

RN5105

2 3 1

DY

SRN0J-6-GP

R5127

HDM I_IN# (2 7)

C5103 SCD1U10V2KX-5GPC5103 SCD1U10V2KX-5GP

1 2

C5104 SCD1U10V2KX-5GPC5104 SCD1U10V2KX-5GP

1 2

C5105 SCD1U10V2KX-5GPC5105 SCD1U10V2KX-5GP

1 2

C5106 SCD1U10V2KX-5GPC5106 SCD1U10V2KX-5GP

1 2

C5110 SCD1U10V2KX-5GPC5110 SCD1U10V2KX-5GP

1 2

C5107 SCD1U10V2KX-5GPC5107 SCD1U10V2KX-5GP

1 2

C5108 SCD1U10V2KX-5GPC5108 SCD1U10V2KX-5GP

1 2

C5109 SCD1U10V2KX-5GPC5109 SCD1U10V2KX-5GP

1 2

HDMI_PLL_GND

DDC_CLK_HDMI DDC_DATA_HDMI

4

Q5103

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

5V_S0

12

R5113

R5113 100KR2J-1-GP

100KR2J-1-GP

DY

678

RN5106

RN5106 SRN680J-GP

SRN680J-GP

123

4 5

Already PH on PCH side.(RN1706)

PCH_HDMI_CLK(17)

PCH_HDMI_DATA(17)

Routing Guidelines: CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm). The total delay on CTRLDATA should be longer than CTRLCLK.

123

S

678

HDMI_CLK_R_C# HDMI_CLK_R_C

HDMI_DATA0_R_C# HDMI_DATA0_R_C

HDMI_DATA1_R_C# HDMI_DATA1_R_C

HDMI_DATA2_R_C# HDMI_DATA2_R_C

RN5107

RN5107 SRN680J-GP

SRN680J-GP

4 5

3

HDMI CONN

HDMI1

R5123

0R2J-2-GP

DY

1 2

SKT-HDMI23-GP

22.10296.341

200KR2J-L1-GP

20101224 A00: Change RN5117,RN5112~RN5115 to 0402 0 ohm pad. 20110111 A00: Change RN5117 to 0 ohm resistor. 20110118 A00: Remove RN5117 for PCH_HDMI_CLK and PCH_HDMI_DATA.

PCH_HDMI_CLK PCH_HDMI_DATA

23 21 1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22

R5110

Removed HDMI_IN# CIRCUIT connect to KBC GPIO.

HDMI_DATA2_R_C

HDMI_DATA2_R_C# HDMI_DATA1_R_C

HDMI_DATA1_R_C# HDMI_DATA0_R_C

HDMI_DATA0_R_C# HDMI_CLK_R_C

HDMI_CLK_R_C#

DDC_CLK_HDMI DDC_DATA_HDMI

HPD_HDMI_CON

1 2

R5111 150KR2J-L1-GPR5111 150KR2J-L1-GP

12

2nd = 84.03904.P11

2nd = 84.03904.P11 3rd = 84.03904.T11

DY

3rd = 84.03904.T11

PCH_HDMI_DATA

2

12

C5102

C5102 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

HDMI_HPD_B

84.03904.L06

5V_CRT_S0_R

3D3V_S0

3

Q5102

1

PMBS3904-1-GP

2

HDMI_HPD_E

12

R5112

R5112 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

Q5104

34

2

5

1

6

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

Title

HDMI Level Shifter/Connector

Size Document Number Rev

A3

Date: Sheet

R5124

1 2

DY

1 2

R5125 0R0402-PADR5125 0R0402-PAD

RN5101

RN5101 SRN2K2J-1-GP

SRN2K2J-1-GP

DDC_CLK_HDMIPCH_HDMI_CLK

DDC_DATA_HDMI

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

0R2J-2-GP

5V_CRT_S0_R

4

1

2 3

1

HDMI_HPD_DET (85)

HDMI_PCH_DET (17)

of

51 104Tuesday, January 18, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

52 104Tuesday, January 04, 2011

A00

5

D D

4

3

2

1

(Blanking)

C C

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

LVDS_Switch

53 104Tuesday, January 04, 2011

1

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

54 104Tuesday, January 04, 2011

A00

5

SSID = User.Interface

4

3

2

1

ITP Connector

D D

CPU

TCK(PIN AC5)

C C

B B

H_CPURST# use pull-up Resistor close ITP connector 500 mil ( max ), others place near CPU side.

ITP Connector

TCK(PIN 5)

FBO(PIN 11)

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ITP

Size Document Number Rev

A3

Date: Sheet

ITP

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

55 104Tuesday, January 04, 2011

1

A00

SSID = SATA

3D3V_S0 5V_S0

12

C5604

SATA_TXP0(21)

SATA_TXN0(21)

SATA_RXN0(21)

SATA_RXP0(21)

12

C5601

SC56P50V2JN-2GP

C5616 SCD01U16V2KX-3GPC5616 SCD01U16V2KX-3GP C5615 SCD01U16V2KX-3GPC5615 SCD01U16V2KX-3GP

12

C5605

SC10U10V5ZY-1GP

1 2 1 2

12

C5606

SCD1U10V2KX-5GP

C5614SCD01U16V2KX-3GP C5614SCD01U16V2KX-3GP

12

C5613SCD01U16V2KX-3GP C5613SCD01U16V2KX-3GP

12

SATA_TXP0_C SATA_TXN0_C

SATA_RXN0_C SATA_RXP0_C

SATA HDD Connector

HDD1

19

SATA_TXN0_C

SATA_RXN0_C

3D3V_S0

5V_S0

FFS_INT2(79)

TP5602TPAD14-GP TP5602TPAD14-GP

HDD1_21 HDD1_22

1

3

5

7

9

11

13

15

17

MLX-CONN18A-S1GP

20.K0229.018

HDD1_20

20

SATA_TXP0_C

2

4

SATA_RXP0_C

6

8

10

12

14

16

18 2221

TP5601 TPAD14-GPTP5601 TPAD14-GP

1

3D3V_S0

5V_S0

1

TP5603 TPAD14-GPTP5603 TPAD14-GP

ODD Connector

ODD1

8

S1

SATA_TXP4_C

S2

SATA_TXN4_C

S3 S4

SATA_RX4-_C

S5

SATA_RX4+_C

S6 S7

P1 P2 P3 P4 P5 P6

9

SKT-SATA7P+6P-50-GP

62.10065.651

62.10065.651 2nd = 62.10065.221

2nd = 62.10065.221

SATA_RX- and SATA_RX+ Trace Length match within 20 mil

Mars: Exchange ODD and ESATA differential pair each other.

C5612 SCD01U16V2KX-3GPC5612 SCD01U16V2KX-3GP

1 2

C5611 SCD01U16V2KX-3GPC5611 SCD01U16V2KX-3GP

1 2

C5607 SCD01U16V2KX-3GPC5607 SCD01U16V2KX-3GP

1 2

C5608 SCD01U16V2KX-3GPC5608 SCD01U16V2KX-3GP

1 2

SATA_ODD_PRSNT# (22)

SATA_ODD_DA#_C

12

R5604

R5604 10KR2J-3-GP

10KR2J-3-GP

DY

AFTP5601AFTP5601

SATA_TXP4 (21)

SATA_TXN4 (21)

SATA_RXN4 (21) SATA_RXP4 (21)

ODD_PWR_5V

R56020R2J-2-GP

SATA_ODD_PWRGT SATA_ODD_DA#

DY

12

RN5601

4

SRN10KJ-5-GP

SATA_ODD_DA# (18)

3D3V_S0

1 23

SUPPORT ZERO SATA ODD

1

FFS_INT2

When the drive is powered on, the FET to the MD/DA pin drive is OFF. When the drive is powered off, the FET to the MD/DA pin is ON

5V_S0

R5605

R5605 100KR2J-1-GP

100KR2J-1-GP

1 2

ODD_PWRGT#

SATA_ODD_DA#_C

5

6

Q5601

SATA_ODD_PWRGT SATA_ODD_DA#

123 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

SATA Zero Power ODD

SATA_ODD_PWRGT(22)

U5601

U5601 G547F1P81U-GP

5V_S0

12

C5609

C5609 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

Title

Size Document Number Rev

A3

Date: Sheet

G547F1P81U-GP

EN/EN#4OC#

3

IN#3

2

IN#2

1

GND

74.00547.C79

2ND = 74.02191.079

ƵƌƌĞŶƚůŝŵŝƚ ĐƚŝǀĞ,ŝŐŚ ƚǇƉсхϮ

HDD/ODD

Nirvana 13

5

ODD_PWR_5V

6

OUT#6

7

OUT#7

8

OUT#8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

56 104Tuesday, January 18, 2011

A00

5

4

3

2

1

SSID = ESATA

D D

USB CHARGER

U5702

1

S0

2

USB_PN1_R

S0 S1

C C

0 0 001 1 1

1

D+

3

D-

4

GND

5

A+

PI5USB14550AZEE-GP

73.5USB1.003

Auto

D+/- connects to Y+/-

GND

VDD

11 10

S1

9

Y+

8

Y-

7 6

A-

CBUSB_PP1_R

C5701

1 2

R5721

0R0402-PAD

1 2

USB_PP1 (18)

USB_PN1 (18)

5V_S5

SCD1U10V2KX-4GP

USBCHARGER_CB0 (27)

0809

Switch Control Bit: CB=0 (AM):auto detection charger identification active. CB=1 (PM):connect DP/DM to TDP/TDM.

ESATA CONN

20100104 A00: Remove R5718,R5719

B B

USB_PP1_R USB_PP1_C

TR5701

1

WCM2012F2S-GP-U2

2

69.10084.081

USB_PN1_CUSB_PN1_R

34

SATA_TXP5(21) SATA_TXN5(21)

SATA_RXP5(21) SATA_RXN5(21)

C5707 SCD01U16V2KX-3GPC5707 SCD01U16V2KX-3GP

1 2

C5708 SCD01U16V2KX-3GPC5708 SCD01U16V2KX-3GP

1 2

C5705 SCD01U16V2KX-3GPC5705 SCD01U16V2KX-3GP

1 2

C5702 SCD01U16V2KX-3GPC5702 SCD01U16V2KX-3GP

1 2

USB_PP1_C USB_PN1_C

close to ESATA1

3

1 1 1

5V_USB1_S3 USB_PN1_C USB_PP1_C

AFTP5716 AFTE14P-GPAFTP5716 AFTE14P-GP

AFTP5715

AFTP5715 AFTP5703

AFTP5703

A A

5

4

AFTE14P-GP

AFTE14P-GP AFTE14P-GP

AFTE14P-GP

5V_USB1_S3

SATA_TXP5_C SATA_TXN5_C

SATA_RXP5_C SATA_RXN5_C

SKT-ESATA-USB-11P-6-GP-U

2

ESATA1

1

VBUS

DT1

6 7

9

3 2

DT2

GND

A+

GND

A-

GND B+10GND B-

GND

GND D+

GND D-

GND

22.10321.W11

2nd = 22.10339.261

ESATA1_D1

12 13

4 5 8 11 14 15 16 17

Title

Size Document Number Rev

A3

Date: Sheet

1 2

R5722 0R0402-PADR5722 0R0402-PAD

1

AFTP5714

AFTP5714 AFTE14P-GP

AFTE14P-GP

USB/ESATA

Nirvana 13

1

USBDET_CON# (27)

of

57 104Tuesday, January 18, 2011

1 2

DY

EC5701 SC5P50V2CN-2GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

5

4

3

2

1

SSID = AUDIO

6SHDNHU

/,1(287

&RQQHFWRU

D D

20101224 A00: Change R5803,R5804 to 0603 0 ohm pad.

SPK1

AUD_SPK_L-(29)

AUD_SPK_L+(29)

40 mils

12

DY

EC5801

MLVG0402220NV05BP-GP-U

12

DY

EC5802

MLVG0402220NV05BP-GP-U

1 2

R5803 0R0603-PADR5803 0R0603-PAD

1 2

R5804 0R0603-PADR5804 0R0603-PAD

AUD_SPK_L-_C

AUD_SPK_L+_C

JST-CON2-33-GP

21.D0300.102

3

1

2

4

1

AFTP5805AFTP5805

AUD_HP1_JACK_L2(29)

AUD_HP1_JACK_R2(29)

AUD_HP1_JD#(29)

AUD_HP1_JACK_L2 AUD_HP1_JACK_L2_R

AUD_HP1_JACK_R2

EC5805

SC1KP50V2KX-1GP

20101224 A00: 0402 0R pad: R5805,R5806.

1 2

R58050R0402-PAD R58050R0402-PAD

1 2

R58060R0402-PAD R58060R0402-PAD

12

EC5806

EC5806 SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

AUD_HP1_JACK_R2_R

L5801

1 2

BLM18BD601SN1D-GP

L5802

1 2

BLM18BD601SN1D-GP

EC5803

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1

AUD_HP1_JD#

12

EC5804

SCD01U16V2KX-3GP

20101224 A00: Rename LINEOUT1 to LOUT1.

1

AFTP5810AFTP5810

LOUT1

8 7 3 1 4

2 5 6

PHONE-JK383-GP-U

22.10133.K31

C C

AFTP5811AFTP5811

AFTP5803AFTP5803

AFTP5801AFTP5801 AFTP5802AFTP5802

AUD_SPK_L-_C

1

AUD_SPK_L+_C

1

AFTP5804AFTP5804

06/28

AUD_HP1_JD#

1

AUD_HP1_JACK_L1

1

AUD_HP1_JACK_R1

1

06/28

0,&,1

B B

600ohm 100MHz

MIC_IN_L(29)

MIC_IN_R(29)

MIC_IN_L

MIC_IN_R

200mA 0.5ohm DC

1 2

R5801 BLM18BD601SN1D-GPR5801 BLM18BD601SN1D-GP

1 2

R5802 BLM18BD601SN1D-GPR5802 BLM18BD601SN1D-GP

EXT_MIC_JD#(29)

06/28

AFTP5806AFTP5806

AFTP5807AFTP5807

AFTP5809AFTP5809

A A

MIC_IN_L_C

1

MIC_IN_R_C

1

EXT_MIC_JD#

1

DY

EC5807

12

MIC_IN_L_C

MIC_IN_R_C

EC5808

12

DY

SC100P50V2JN-3GP

1

MICIN1

8 7 3 1 4

2 5 6

PHONE-JK383-GP-U

22.10133.K31

AFTP5808AFTP5808

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Audio Jack

Nirvana 13

1

A00

of

58 104Tuesday, January 18, 2011

A00

5

D D

4

3

2

1

C C

B B

A A

(Blanking)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

A00

of

59 104Tuesday, January 04, 2011

1

A00

5

SSID = Flash.ROM

4

3

2

1

SPI FLASH ROM (4M byte) for PCH

3D3V_S5

D D

678

RN6001

RN6001 SRN4K7J-10-GP

SRN4K7J-10-GP

123

4 5

SPI_CS0#_R(21,27)

SPI_SO_R(21,27)

C C

1 2

R6001 33R2J-2-GPR6001 33R2J-2-GP

EC6002

SC4D7P50V2CN-1GP

EC6002

DY

SPI_SO

SPI_WP#

12

SPI_HOLD_0#

U6001

1

CS#

2

DO WP# VSS

HOLD#

3 4

W25Q32BVSSIG-1-GP

72.25Q32.A01

2nd = 72.25320.C01

2nd = 72.25320.C01 3rd = 72.25P32.C01

3rd = 72.25P32.C01

VCC

CLK

3D3V_S5

8 7 6 5

DI

EC6003

12

DY

EC6001

SC4D7P50V2CN-1GP

DY

12

C6001

3D3V_S5

12

C6002

SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP

SPI_CLK_R (21,27) SPI_SI_R (21,27)

Notes: The total SPI interface signal between EC and PCH can’t not exceed 6500mil. The mismatch between SPI signal must be within 500mil

Priority Wistron P/N Manufacturer Vendor P/N

1

2

3

72.25Q32.A01

72.25320.C01

72.25P32.C01

WINDBOND

MXIC

NUMONYX

W25Q32BVSSIG

MX25L3206EM2I-12G

M25PX32-VMW6F

B B

SSID = RBATT

RTC_AUX_S5

C6003

SC1U6D3V2KX-GP

R6004

1 2

DY

100R2J-2-GP

A A

RTC_PWRRTC_PWR

12

R6003

R6003 10MR2J-L-GP

10MR2J-L-GP

100R2J-2-GP

2N7002K-2-GP

G

D

S

Q6002

84.2N702.J31

2ND = 84.2N702.031

5

SC1U6D3V2KX-GP

RTC_DET# (22)

Q6001

3

CH715FPT-GP

1 2

83.R0304.B81

2nd = 83.00040.E81

Width=20mils

3D3V_AUX_S5

2

RTC_PWR

1

4

1 2

TP6002TPAD14-GP TP6002TPAD14-GP

+RTC_VCC

R6002

1KR2J-1-GP

TP6001TPAD14-GP TP6001TPAD14-GP

+RTC_VCC

1

NP1 NP2

1

BAT-060003HA002M213ZL-GP

RTC1

1

PWR

2

GND NP1 NP2

62.70014.001

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Flash/RTC

Nirvana 13

A00

of

60 104Tuesday, January 18, 2011

1

A00

5

SSID = USB

4

3

2

1

Close to ESATA Combo connector

Support 2A

U6101

USB POWER SW

D D

Main G547F2P81U-GP P/N:74.00547.A79

12

C6103

C6101

SCD1U10V2KX-5GP

C C

12

at least 80 mil

USB_PWR_EN#(27)

U6101

1

GND

2 3 4

OUT#8

IN#2

OUT#7

IN#3

OUT#6

EN/EN#

G547F2P81U-GP

74.00547.A79

2nd = 74.00547.079

OC#

8 7 6 5

at least 80 mil

SC1U10V2KX-1GP

USB_OC#0_1 (18)

C6102

5V_USB1_S35V_S5

12

TC6101

TC6101 ST100U6D3VAM-3-GP

ST100U6D3VAM-3-GP

80.10715.B1L

2nd = 77.C1071.20L

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

USB2.0 Power SW

61 104Tuesday, January 18, 2011

1

of

A00

5

4

3

2

1

1V_USB30 LDO

20101227 A00: Change R6205 to 0R 0402 pad. 20101228 A00: VGA_THRM change to USB_PWR_EN. 20101229 A00: Remove R6205,R6201 and rename USB3_PWR_ON from USB_PWR_EN.

D D

USB3.0 Host

TI 11.8k ohm (64.11825.6DL) 30.9k ohm (64.30925.6DL)

RT (R6202) RB (R6203)

2.37k ohm (64.23715.6DL) 7.5k ohm (64.75015.6DL)NEC

VOUT

1.05V

1.1V

USB3_PWR_ON(27,82)

3D3V_S5

12

C6202

SC1U10V2KX-1GP

SC10U10V5ZY-1GP

C C

B B

C6203

5V_S5

12

U6201

1

POK

2 3 4

2nd = 74.09025.03D

GND

VEN

GND

VIN

ADJ

VPP

VO

NC#5

G9661-25ADJF11U-GP

74.09661.07D

R6203

R6203 7K5R2F-1-GP

7K5R2F-1-GP

DY

RB

9 8 7 6 5

RT

DY

1 2

R6202

R6202 2K37R2F-GP

2K37R2F-GP

1V_USB30_LDO_FB (82)

1V_USB30

0.6A

Vo = 0.8 * ( 1 + ( RT / RB ) )

12

C6201

SC10U10V5ZY-1GP

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

USB 3.0 Port

Nirvana 13

1

of

62 104Tuesday, January 18, 2011

A00

5

4

SSID = User.Interface

3

Bluetooth Module

2

1

D D

AFTP6301AFTP6301

AFTP6302AFTP6302

AFTP6304AFTP6304 AFTP6305AFTP6305 AFTP6307AFTP6307

C C

USB_PP3(18)

USB_PN3(18)

BT_ACT(65)

BLUETOOTH_EN(27,65)

WLAN_ACT(65)

B B

BLUETOOTH_DET#

1

WLAN_ACT BDC_ON

1

BLUETOOTH_EN BT_LED

1

BLUETOOTH_GPIO3

1

BLUETOOTH_GPIO5

1

12

R6301

DY

BT_ACT BLUETOOTH_EN WLAN_ACT

EC6301

12

DY

100KR2J-1-GP

BT1

1

3 5 7

BT

9 11 13

ACES-CONN14D-GP

20.F1500.014

12

R6302

BT

10KR2J-3-GP

SC220P50V2KX-3GP

15 NP1 2

4 6 8 10 12 14 NP2 16

BT_ACT

USB_PP3 USB_PN3

1

AFTP6309AFTP6309 AFTP6310AFTP6310 AFTP6308AFTP6308 AFTP6311AFTP6311 AFTP6312AFTP6312 AFTP6313AFTP6313

AFTP6306AFTP6306

WLAN_ACT

1

BLUETOOTH_EN

1

BT_ACT

1

3D3V_S0

1

USB_PP3

1

USB_PN3

1

3D3V_S0

12

BT

C6301

SC2D2U6D3V3KX-GP

R6303

1 2

DY

0R2J-2-GP

Q6301

BT_LED

A A

G

BT

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

5

D

WLAN_WWAN_LED#

WLAN_WWAN_LED# (68)

4

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Bluetooth

Size Document Number Rev

A4

Date: Sheet

2

Bluetooth

Nirvana 13

of

63 104Tuesday, January 18, 2011

1

A00

5

D D

4

3D3V_S0

12

C6401

C6401 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

3

Biometric_USBPP Biometric_USBPN

AFTP40AFTP40

2

FP1

7

1

2 3 4 5 6

8

1

ACES-CON6-7GP

1

20101227 A00: Change R6403,R6404 to 0R 0402 pad. 20100104 A00: Remove TR6401.

R6403

C C

USB_PN2(18)

USB_PP2(18)

B B

R6403

1 2

0R0402-PAD

R6404

1 2

0R0402-PAD

Biometric_USBPN

Biometric_USBPP

AFTP42AFTP42 AFTP43AFTP43 AFTP44AFTP44

1 1 1

3D3V_S0 Biometric_USBPN Biometric_USBPP

20.K0256.006

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet

5

4

3

Date: Sheet

2

Finger Printer Conn

Nirvana 13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

of

64 104Tuesday, January 18, 2011

1

5

4

3

2

1

SSID = Wireless

Mini Card Connector(802.11a/b/g/n)

D D

3D3V_S0 1D5V_S0

12

5V_S5

12

C C

B B

12

C6502

SCD1U16V2KX-3GP

C6501

SCD1U16V2KX-3GP

12

C6503

C6504

SC10U6D3V5KX-1GP

WLAN_ACT

12

C6508

DY

SC220P50V2KX-3GP

E51_RXD(27) E51_TXD(27)

SCD1U16V2KX-3GP

DY

0R2J-2-GP

1 2 1 2

DY

0R2J-2-GP

12

C6505

SC10U6D3V5KX-1GP

R6501

R6502

WLAN_LED#(68) WPAN_LED#(68)

12

CLK_PCI_LPC(18,71,97)

C6507

C6506

SCD1U16V2KX-3GP

WLAN_ACT(63)

BT_ACT(63) LPC_AD0(21,27,71) LPC_AD1(21,27,71) LPC_AD2(21,27,71) LPC_AD3(21,27,71)

LPC_FRAME#(21,27,71)

WIFI_RF_EN(27)

BLUETOOTH_EN(27,63)

20101227 A00: Change R6510 to 0R 0603 pad.

R6505 0R2J-2-GP

1 2

DY

R6504 0R2J-2-GP

1 2

DY

R6507 0R2J-2-GP

1 2

DY

R6506 0R2J-2-GP

1 2

DY

R6509 0R2J-2-GP

1 2

DY

E51_RXD_R E51_TXD_R

3D3V_S0

1 2

R6510 0R0603-PADR6510 0R0603-PAD

5V_S5

WPAN_LED#

20101227 A00: Change R6511 to 0R 0402 pad.

1 2

R6503

1 2

R6511 0R0402-PADR6511 0R0402-PAD

1 2

DY

R6508 0R2J-2-GP

DY

0R3J-0-U -GP

1D5V_S03D3V_S0

LPC_AD0_C LPC_AD1_C LPC_AD2_C LPC_AD3_C LPC_FRAME#_C

+5V_MINI_DEBUG

WPAN_LED#_R

WLAN1

6

1.5V

2

3.3V

28

+1.5V

48

+1.5V

52

+3.3V

24

+3.3VAUX

3

RESERVED#3

5

RESERVED#5

8

RESERVED#8

10

RESERVED#10

12

RESERVED#12

14

RESERVED#14

16

RESERVED#16

17

RESERVED#17

19

RESERVED#19

20

RESERVED#20

37

RESERVED#37

39

RESERVED#39

41

RESERVED#41

43

RESERVED#43

45

RESERVED#45

47

RESERVED#47

49

RESERVED#49

51

RESERVED#51

42

LED_WW AN#

44

LED_WLAN#

46

LED_WPAN#

SKT-MINI52P-42-GP-U1

62.10043.831

REFCLK+

REFCLK-

PERN0

USB_D-

USB_D+

SMB_CLK

SMB_DATA

WAKE#

CLKREQ#

PERST#

NP1

NP2

NP1

NP2

PERP0

PETN0 PETP0

GND GND GND GND GND GND GND GND GND GND GND GND GND GND

13 11

23 25

31 33

36 38

30 32

1 7 22

4 9 15 18 21 26 27 29 34 35 40 50 53 54

CLK_PCIE_WLAN (20)

CLK_PCIE_WLAN# (20)

PCIE_RXN4 (20) PCIE_RXP4 (20)

PCIE_TXN4 (20) PCIE_TXP4 (20)

USB_P11USB_P11+

PCH_SMBCLK (14,15,20,79,82)

PCH_SMBDATA (14,15,20,79,82)

CLK_PCIE_WLAN_REQ# (20)

PLT_RST# (5,18,27,71,82,83)

USB_P11-

USB_P11+

1 2

R6406

0R0402-PAD

1 2

R6405

0R0402-PAD

20101230 A00: Change R4606,R4605 to 0R short pad. 20100104 A00: Remove TR6501.

USB_PP11 (18)

USB_PN11 (18)

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

MINICARD(WLAN)/ITP CONN

Size Document Number Rev

Date: Sheet

MINICARD(WLAN)/ITP CONN

A3

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

of

65 104Tuesday, January 18, 2011

1

A00

5

D D

C C

4

3

2

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document Number Rev

A3

Date: Sheet

Reserved

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

of

66 104Tuesday, January 04, 2011

1

A00

5

D D

4

3

2

1

(Blanking)

C C

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet

5

4

3

Date: Sheet

2

Nirvana 13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

of

67 104Tuesday, January 04, 2011

1

A00

5

SSID = User.Interface

D D

RN6801

PWRLED#_C

1

PWRLED#(27) BATT_WHITE_LED#(27)

CHG_AMBER_LED#(27)

SATA_LED#(21)

C C

WLAN_WWAN_LED#(63)

WLAN_LED#(65)

WWAN_LED#( 82)

WPAN_LED#(65)

WLAN_WWAN_LED#

U6801

1

83.BAT54.U81

2

D6801

3

BAS16-6-GP

83.00016.K11

2ND = 83.00016.F11

3

BAT54A-5-GP

1

2

2 3 4 5

SRN15KJ-2-GP

8

WHITE_LED_BAT#

7

AMBER_LED_BAT#

6

SATA_LED#_C

3D3V_S0

DY

12

R6805

R6805 100KR2J-1-GP

100KR2J-1-GP

4

1 2

15KR2J-1-GP

R6802

PWRLED#_C

SATA_LED#_C

WHITE_LED_BAT#

AMBER_LED_BAT#

LED_WLAN_OUT_R#WLAN_WWAN_LED#

3

Power LED(White)

Q6801

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

SATA HDD LED(White)

Q6802

R2

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

Battery LED1(White)

Q6805

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

5V_S5

R2

E

C

12

EC6801

DY

SC220P50V2KX-3GP

5V_S0

E

SATA_LED_R

C

R2

E

WHITE_LED_BAT

C

DY

5V_AUX_S5

DY

12

Battery LED2(Amber)

Q6804

R2

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

5V_AUX_S5

E

C

12

DY

20110103 A00: Change R6804,R6806,R6808,R6810 to 620 ohm 5%. 20100106 A00: Change R6804,R6806,R6808,R6810 to 1k ohm 5%.

R6804

1 2

1KR2J-1-GP

R6801

1 2

1KR2J-1-GP

20110103 A00: Change R6801 to 1k.

R6806

1 2

1KR2J-1-GP

EC6805

SC220P50V2KX-3GP

R6808

1 2

1KR2J-1-GP

EC6604

SC220P50V2KX-3GP

R6809

1 2

390R2J-1-GP

EC6802

EC6802 SC220P50V2KX-3GP

SC220P50V2KX-3GP

WLAN LED (White)

Q6803

R2

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

5V_S0

E

C

DY

12

EC6803

EC6803 SC220P50V2KX-3GP

SC220P50V2KX-3GP

R6810

1 2

1KR2J-1-GP

LED_WLAN_OU T_BWLAN_LED

PWR_LED_BLED_PWR

POWER_SW_LED_B

SATA_LED

BAT_WHITE

BAT_AMBERAMBER_LED_BAT

2

LED BD Connector

LEDBD1

PWR_LED_B

SATA_LED BAT_WHITE BAT_AMBER LED_WLAN_OU T_B

AFTP6801AFTP6801 AFTP6802AFTP6802 AFTP6803AFTP6803 AFTP6804AFTP6804 AFTP6805AFTP6805

AFTP6806AFTP6806 AFTP6807AFTP6807

7

1

2 3 4 5 6

8

ACES-CON6-13-GP

20.K0320.006

PWR_LED_B

1

SATA_LED

1

BAT_WHITE

1

BAT_AMBER

1

LED_WLAN_OUT_B

1

KBC_PWRBTN#_C

1

POWER_SW_LED_B

1

B B

TPLOCK LED

R6807

TP_LOCK_LED#(27)

Need change to LOW actived from KBC GPIO

1 2

15KR2J-1-GP

Q6804_B

Q6812

B

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

Power button LED(White)

KBC_PWRBTN#(27)

A A

5

4

5V_S0

R2

E

R1

TP_LOCK_LED_R TP_LOCK_LED_A

C

12

DY

1 2

R6803 100R2J-2-GPR6803 100R 2J-2-GP

12

EC6806

DY

SCD1U10V2KX-5GP

EC6804

SC220P50V2KX-3GP

KBC_PWRBTN#_C

POWER_SW_LED_B

R6813

1 2

390R2J-1-GP

12

DY

EC6807

20.K0320.004

SCD1U10V2KX-5GP

LED1

A K

LED-Y-57-GP

83.01921.P70

20101224 A00: Rename PWRBTN1 to PWRBT1.

PWRBT1

6

4 3 2

1

5

ACES-CON4-10-GP-U

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

LED Bord/Power Button

Size Document Number Rev

A2

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

Nirvana 13

1

A00

68 104T uesday, January 18, 2011

A00

of

5

4

3

2

1

SSID = KBC

D D

KB1

31 1

KROW7

2

KROW6

3

KROW4

4

KROW2

5

KROW5

6

KROW1

7

KROW3

8

KROW0

9

KCOL5

10

KCOL4

11

KCOL7

12

KCOL6

13

KCOL8

14

KCOL3

15

KCOL1

16

KCOL2

17

KCOL0

18

KCOL12

19

KCOL16

20

KCOL15

21

KCOL13

22

KCOL14

C C

JAE-CON30-7-GP

B B

23 24 25 26 27 28 29 30 32

20.K0565.030

KCOL9 KCOL11 KCOL10 CAP_LED_R

1

Internal KeyBoard Connector

1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AFTP72AFTP72

AFTP6936AFTP6936

AFTP6911AFTP6911 AFTP6912AFTP6912 AFTP6913AFTP6913 AFTP6914AFTP6914 AFTP6917AFTP6917 AFTP6918AFTP6918 AFTP6915AFTP6915 AFTP6916AFTP6916 AFTP6921AFTP6921 AFTP6922AFTP6922 AFTP6919AFTP6919 AFTP6920AFTP6920 AFTP6925AFTP6925 AFTP6926AFTP6926 AFTP6923AFTP6923 AFTP6924AFTP6924 AFTP6929AFTP6929 AFTP6930AFTP6930 AFTP6927AFTP6927 AFTP6928AFTP6928 AFTP6933AFTP6933 AFTP6934AFTP6934 AFTP6931AFTP6931 AFTP6932AFTP6932 AFTP6935AFTP6935

1

AFTP6901AFTP6901

KB_DET# (21)

CAP_LED_R

KROW [0..7] (27)

KCOL[0..16] (27)

KB Backlight Connector

R6904

100KR2J-1-GP

+5V_KB_BL

12

C6905

C6905 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

KB_LED_DET_C

12

C6906

SCD1U10V2KX-5GP

12

R6901

R6901 100KR2J-1-GP

100KR2J-1-GP

G

KBLIT1

5 1

2 3 4

KB_BL_CTRL#

6

ACES-CON4-34-GP

20.K0589.004

2nd = 20.K0613.004

DS

Q6901

Q6901 P8503BMG-GP

P8503BMG-GP

84.P8503.031

2nd = 84.03404.C31

+5V_KB_BL KB_LED_BL_DET KB_BL_CTRL#

1

AFTP79AFTP79

4

1

AFTP76AFTP76

1

AFTP77AFTP77

1

AFTP78AFTP78

3

5V_S0

R6902

1 2

0R0402-PAD

KB_BL_CTRL(27)

5

0R0402-PAD

1 2

51KR2J-1-GP

12

R6903

20101227 A00: Change R6902 to 0R 0402 pad.

KB_LED_BL_DET(18)

A A

CAP LED CONTROL

R6905

AFTP73AFTP73 AFTP74AFTP74 AFTP75AFTP75

5V_S0

23

C6902

1 2

15KR2J-1-GP

1

RN6901

SRN10KJ-5-GP

4

12

DY

1 1 1

12

DY

C6903

C6903 SC33P50V2JN-3GP

SC33P50V2JN-3GP

5V_S0 TPCLK TPDATA

2

CAP_LED(27)

CAP_LED:(X01 Low actived) Connect to KB driving internal LED directly.(MAX 25mA)

TouchPad LOCKED

TPDATA(27)

TPCLK(27)

SC33P50V2JN-3GP

Q6902

R2

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

CAP_LED_1

5V_S0

12

EC6901

DY

SCD1U10V2KX-5GP

AFTP71AFTP71

20110103 A00: Change R6906 to 620 ohm 5%. 20110106 A00:

5V_S5

E

C

R6907 100R2J-2-GP

Change R6906 to 1k ohm 5%.

R6906

1 2

1KR2J-1-GP

1 2

DY

CAP_LED_RCAP_LED_Q

CAP_LED_R

TouchPad Connector

12

C6901

C6901 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

TPAD1

6

4 3 2

1

5

1

PTWO-CON4-9-GP-U1

20.K0382.004

2010/07/16 Modify

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Key Board/Touch Pad/Media Board

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

69 104Tuesday, January 18, 2011

1

A00

5

4

3

2

1

AFTP80 AFTE14P-GPAFTP80 AFTE14P-GP AFTP81 AFTE14P-GPAFTP81 AFTE14P-GP

D D

C C

3D3V_S5

1

LID_CLOSE#_1

1

LID_CLOSE#(27)

3D3V_S5

12

DY

12

DY

3D3V_S5

12

C7002

SCD1U10V2KX-5GP

R7001

R7001 100KR2J-1-GP

100KR2J-1-GP

LID_CLOSE# LID_CLOSE#_1

C7001

C7001 SCD047U16V2KX-1-GP

SCD047U16V2KX-1-GP

1 2

20101227 A00: Change R7002 to 0R 0402 pad.

SCD1U10V2KX-5GP AFTP82

AFTP82

AFTE14P-GP

R7002

0R0402-PAD

C7002

1

20101224 A00: Rename HALLSW1 to LID1.

LID1

1

VCC

2

VOUT

3

GND

TCS20DPR-GP

74.TCS20.03B

2nd = 74.09132.A7B

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet

5

4

3

Date: Sheet

2

Nirvana 13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Hall Sensor

70 104Tuesday, January 18, 2011

1

A00

of

5

D D

4

3

2

1

3D3V_S0

C C

LPC_AD0(21,27,65) LPC_AD1(21,27,65) LPC_AD2(21,27,65) LPC_AD3(21,27,65)

LPC_FRAME#(21,27,65)

PLT_RST#(5,18,27,65,82,83)

CLK_PCI_LPC(18,65,97)

B B

DB1

11

1

2 3 4 5 6 7 8

9 10 12

PAD-10P-177042-GP

ZZ.00PAD.Y41

PCB Footprint = PAD-10P-177042

20101229 A00 Modify: DB1 change to ZZ.00PAD.Y41(solder mask type)

DY

and keep un-stuff at X-Build stage.

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet

5

4

3

Date: Sheet

2

Dubug CONN

Nirvana 13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

of

71 104Tuesday, January 18, 2011

1

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

72 104Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

73 104Tuesday, January 04, 2011

A00

5

SSID = SDIO

4

3

2

1

3D3V_CARD_S0

D D

DY

12

Close to CARD1

12

DY

C7401

C7402

SCD1U10V2KX-5GP

12

C7403

SCD1U10V2KX-5GP

12

C7404

SCD01U16V2KX-3GP

SC2D2U6D3V3KX-GP

C7405

SC10U6D3V5MX-3GP

SD/XD/MS/MMC+ Card Reader

3D3V_CARD_S0

C C

B B

SP4(32) SP3(32) SP13(32) SP12(32)

SP8(32) SP6(32) SP1(32) SP10(32)

SP14(32) SP2(32) SP1(32)

SP9(32) SP12(32) SP8(32) SP5(32)

SP11(32) SP9(32) SP7(32) SP5(32)

CARD1

P13

SD_VCC

P22

MS_VCC

18

XD_VCC

P4

SD_DAT0

P3

SD_DAT1

P25

SD_DAT2

P23

SD_DATA3

P10

SD_CLK

P1

SD_CD

P2

SD_WP

P19

SD_CMD

P9

MS_BS

P16

MS_INS

P20

MS_SCLK

P12

MS_DATA0

P11

MS_DATA1

P14

MS_DATA2

P18

MS_DATA3

P21

MMC_DATA4

P17

MMC_DATA5

P8

MMC_DATA6

P5

MMC_DATA7

CARD-PUSH-46P-1-GP-U

20.I0129.001

2nd = 20.I0135.001

XD_CD

XD_R/B

XD_RE

XD_CE XD_CLE XD_ALE

XD_WE

XD_WP_IN

XD_D0 XD_D1 XD_D2 XD_D3 XD_D4 XD_D5 XD_D6 XD_D7

SD_WP_COM/SDI O_GND

SD_CD_COM/SDIO_GND

SD_GND SD_GND

MS_GND MS_GND

XD_GND XD_GND

NP1 NP2

1 2 3 4 5 6 7 8

10 11 12 13 14 15 16 17

P26 P27 P7 P15

P6 P24

9 19

NP1 NP2

XD_CD# (32) SP1 (32) SP2 (32) SP3 (32) SP4 (32) SP5 (32) SP6 (32) SP7 (32)

SP8 (32) SP9 (32) SP10 (32) SP11 (32) SP12 (32) SP13 (32) SP14 (32) XD_D7 (32)

SP2SP4SP9SP12 SP5SP14 SP6 SP1SP13 SP7SP10XD_D7 SP8SP11XD_CD#

SP3

For EMI Reserved

12

R7404

47R2J-2-GP

SP14_1

12

EC7404

SC220P50V2KX-3GP

DY

12

SP13_1

12

R7403

EC7405

DY

47R2J-2-GP

DY

SC220P50V2KX-3GP

4

12

DY

R7417

47R2J-2-GP

XD_CD#_1

A A

5

DY

12

EC7402

SC220P50V2KX-3GP

XD_D7_1

12

DY

R7402

EC7403

DY

47R2J-2-GP

DY

SC220P50V2KX-3GP

12

R7406

47R2J-2-GP

SP12_1

12

EC7406

SC220P50V2KX-3GP

DY

12

SP11_1

12

R7405

EC7407

12

DY

R7408

47R2J-2-GP

SP10_1

12

DY

EC7408

SC220P50V2KX-3GP

12

R7407

47R2J-2-GP

SP9_1

12

EC7409

SC220P50V2KX-3GP

DY

12

R7410

47R2J-2-GP

SP8_1

12

EC7410

SC220P50V2KX-3GP

DY

12

SP7_1

12

R7409

EC7411

12

DY

R7412

47R2J-2-GP

SP6_1

12

DY

EC7412

SC220P50V2KX-3GP

3

12

R7411

47R2J-2-GP

SP5_1

12

EC7413

SC220P50V2KX-3GP

DY

12

SP4_1

12

R7414

EC7414

12

DY

R7413

47R2J-2-GP

SP3_1

12

DY

EC7415

SC220P50V2KX-3GP

12

R7416

47R2J-2-GP

SP2_1

12

EC7416

SC220P50V2KX-3GP

DY

12

SP1_1

12

R7415

EC7417

47R2J-2-GP

SC220P50V2KX-3GP

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CARD Reader CONN

Size Document Number Rev

A3

Date: Sheet

CARD Reader CONN

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

of

74 104Tuesday, January 18, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

75 104Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

76 104Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

77 104Tuesday, January 04, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

78 104Tuesday, January 04, 2011

A00

5

SSID = User.Interface

4

3

2

1

D D

PCH_SMBCLK(14,15,20,65,82) PCH_SMBDATA(14,15,20,65,82)

3D3V_S0

C C

For ADI G-sensor : R7901 is required. For ST G-sensor : R7901 need DY

09/0422 (#1) Just pull +3.3V_RUN ~ Ref. Rothschild (#2) FAE/ DY is ok, chip internal pull-up resistors (#3) From spec, Slave ADdress(SAD) is 001110xb Pull HIGH SAD is 0011101b Pull GND SAD is 0011100b

B B

Free Fall Sensor

3D3V_S0

12

SC10U6D3V5MX-3GP

GSENSOR_ADI

1 2

C7901

PCH_SMBDATA

R7901

HDD_FALL_SDO

100KR2J-1-GP

12

DY

C7902

C7902 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

U7901

14

SCL/SPC

13

SDA/SDI/SDO

12

SDO

7

CS

3

RESERVED#3

11

RESERVED#11

DE351DLTR8-GP

74.00351.0B3

2nd = 74.00345.0BZ

Note

- no via, trace, under the sensor (keep out area around 2mm)

- stay away from the screw hole or metal shield soldering joints

- design PCB pad based on our sensor LGA pad size (add 0.1mm)

- solder stencil opening to 90% of the PCB pad size

- mount the sensor near the center of mass of the NB as possible as you can

3D3V_S0

1

6

VDD

VDD_IO

INT1

INT2

GND GND GND GND

12

R7902

R7902 100KR2J-1-GP

100KR2J-1-GP

DY

HDD_FALL_INT1PCH_SMBCLK

8

9

2 4 5 10

HDD_FALL_INT1 (18)

12

2nd = 84.DM601.03F

R7904

DY

100KR2J-1-GP

FFS_INT2_R

2N7002KDW-GP

84.2N702.A3F

Q7901

3D3V_S0

12

R7903

R7903 100KR2J-1-GP

100KR2J-1-GP

FALL_INT2

2

34

5

1 2

DY

1

6

0R2J-2-GP

R7905

5V_S03D3V_S0

12

R7906

R7906 10KR2J-3-GP

10KR2J-3-GP

DY

FFS_INT2 (56)

FFS_INT2_R (18)

Note (1) Keep all signals are the same trace width. (included VDD, GND). (2) No VIA under IC bottom.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Free Fall Sensor

Nirvana 13

79 104Tuesday, January 18, 2011

1

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

of

80 104Tuesday, January 04, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

81 104Tuesday, January 04, 2011

A00

5

4

3

2

1

IO Board CONN 80 pin

IOBD 1

80

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

20.F1432.080

NP1 1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NP2NP3

PCIE_TXP5 (20)

PCIE_TXN5 (20)

PCIE_RXP5 (20)

PCIE_RXN5 (20)

CLK_PCIE_LAN (20) CLK_PCIE_LAN# (20)

CLK_PCIE_WWAN (20) CLK_PCIE_WWAN# (20)

5V_S5

at least 160 mil

3D3V_S0

1D5V_S0

PM_LAN_ENABLE (27) PLT_RST# (5,18,27,65,71,83)

PCIE_WAKE# (27)

USB3_PEGB_CLKREQ# (20)

+DC_IN

86%3&,(

/$1&/.

::$1&/.

5V_USB FOR USB3.0 POWER at least 4A

1D05V_VTT FOR USB3.0 POWER at least ?A

3D3V_S5 FOR LAN POWER at least over 3pin amount.

1D5V_S0 FOR USB3.0 POWER at least ?A

NP4

D D

USB3_PWR_ON(27,62)

20101224 A00: Change R8210 to 0402 0 ohm pad. 20101228 A00: VGA_THRM change to USB_PWR_EN. 20101229 A00: Remove R2809 and R8210. Connect USB3_PWR_ON from KBC to IOBD1.61.

C C

86%&/.

::$186%

::$13&,(

::$160%86

/$13&,(

CLK_PCIE_USB3(20)

CLK_PCIE_USB3#(20)

USB_PP4(18) USB_PN4(18)

PS_ID_R(38)

PCIE_RXP3(20) PCIE_RXN3(20)

PCIE_TXP3(20) PCIE_TXN3(20)

PCH_SMBDATA(14,15,20,65,79)

PCH_SMBCLK(14,15,20,65,79)

1V_USB30_LDO_FB(62)

CLK_PCIE_WWAN_REQ#(20)

PCIE_CLK_LAN_REQ#(20)

3G_EN(22) WWAN_LED#(68) USB30_SMI#(18)

PCIE_RXP2(20) PCIE_RXN2(20)

PCIE_TXP2(20) PCIE_TXN2(20)

1V_USB30

3D3V_S5

USB3_PWR_ON

ACES-CONN80C-GP-U

B B

Media Button Board Connector

5V_S5

RN8209

5V_S5

DY

12

EC8201

RN8209

8 7

DY

6

SRN10KJ-6-GP

12

EC8202

DY

SCD1U10V2KX-5GP

3

1 2 3 45

SCD1U10V2KX-5GP

2

MEDIA1_1 MEDIA1_2 MEDIA1_3

INSTANT_ON# DATA_RECOVERY# MEDIA_BTN3#

12

DY

EC8208

SCD1U10V2KX-5GP

Title

Size Document Number Rev

A3

Date: Sheet

SCD1U10V2KX-5GP

IO Board Connector

Nirvana 13

12

DY

EC8206

EC8205

EC8207

EC8205

SCD1U10V2KX-5GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

12

DY

EC8204

SCD1U10V2KX-5GP

of

82 104Tuesday, January 18, 2011

EC8203

SCD1U10V2KX-5GP

A00

MEDIA_LED1# MEDIA_LED2#

20110103 A00: Change R8201~R8203 to 1k. 20110104 A00: Merge R8201~R8203 to RN8201 1k array resistor. 20110113 A00:

MEDIA1

9

1

2 3

A A

AFTP8201AFTP8201 AFTP8202AFTP8202 AFTP8203AFTP8203 AFTP8204AFTP8204 AFTP8205AFTP8205 AFTP8206AFTP8206 AFTP8207AFTP8207

MEDIA1_1

1

MEDIA1_2

1

MEDIA1_3

1

5V_S5

1

INST ANT_O N#

1

DATA_RECOVERY#

1

MEDIA_BTN3#

1

5

4 5 6 7 8

10

ACES-CON8-19-GP

20.K0320.008

Swap RN8201 base on swap report.

RN8201

MEDIA1_1 MEDIA1_2 MEDIA1_3

5V_S5

4 5 3 2 1

SRN1KJ -4-GP

4

RN8201

Low active

6 7 8

MEDIA_LED1# (27) MEDIA_LED2# (27)

MEDIA_LED3# (27) INSTANT_ON# (27)

DATA_RECOVERY# (27)

MEDIA_BTN3# (27)

MEDIA_LED3#

1 2

5

PEG_TXP0 PEG_TXN0

PEG_TXP1 PEG_TXN1

PEG_TXP2 PEG_TXN2

PEG_TXP3 PEG_TXN3

PEG_TXP4 PEG_TXN4

PEG_TXP5 PEG_TXN5

PEG_TXP6 PEG_TXN6

PEG_TXP7 PEG_TXN7

PEG_TXP8 PEG_TXN8

PEG_TXP9 PEG_TXN9

PEG_TXP10 PEG_TXN10

PEG_TXP11 PEG_TXN11

PEG_TXP12 PEG_TXN12

PEG_TXP13 PEG_TXN13

PEG_TXP14 PEG_TXN14

PEG_TXP15 PEG_TXN15

PWRGOOD

VGA_RST#

DY

VGA1A

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

PCIE_RX8P

U31

PCIE_RX8N

U29

PCIE_RX9P

T28

PCIE_RX9N

T30

PCIE_RX10P

R31

PCIE_RX10N

R29

PCIE_RX11P

P28

PCIE_RX11N

P30

PCIE_RX12P

N31

PCIE_RX12N

N29

PCIE_RX13P

M28

PCIE_RX13N

M30

PCIE_RX14P

L31

PCIE_RX14N

L29

PCIE_RX15P

K30

PCIE_RX15N

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

N10

PWRGOOD

AL27

PERST#

12

C8333

C8333 SC47P50V2JN-3GP

SC47P50V2JN-3GP

ROBSON-GP-U

CLOCK

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCI EXPRESS INTERFACE

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P

PCIE_TX10N

PCIE_TX11P

PCIE_TX11N

PCIE_TX12P

PCIE_TX12N

PCIE_TX13P

PCIE_TX13N

PCIE_TX14P

PCIE_TX14N

PCIE_TX15P

PCIE_TX15N

CALIBRATION

PCIE_CALRP

PCIE_CALRN

71.ROBSO.M01

PEG_TXP[0..15](4)

PEG_TXN[0..15](4)

D D

C C

B B

CLK_PCIE_VGA(20) CLK_PCIE_VGA#(20)

R8317 10KR2F-2-GPR8317 10KR2F-2-GP

dGPU reset for PX/SG transitions

PLT_RST#(5,18,27,65,71,82)

A A

1D5V_VGA_PWOK(86)

1D8V_S0_VGA_PG(93)

R8319

DY

0R2J-2-GP

R8325

DY

0R2J-2-GP

5

U8302

12

PLT_RST#

1D8V_S0_VGA_PG_1

12

C8334

C8334 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

U8302

1

B

2

A

3

GND

74LVC1G08GW-1-GP

1 OF 7

3D3V_VGA_S0

VCC

DY

Y

73.01G08.L04

4

PEG_C_RXP0

AH30

PEG_C_RXN0

AG31

PEG_C_RXP1

AG29

PEG_C_RXN1

AF28

PEG_C_RXP2

AF27

PEG_C_RXN2

AF26

PEG_C_RXP3

AD27

PEG_C_RXN3

AD26

PEG_C_RXP4

AC25

PEG_C_RXN4

AB25

PEG_C_RXP5

Y23

PEG_C_RXN5

Y24

PEG_C_RXP6

AB27

PEG_C_RXN6

AB26

PEG_C_RXP7

Y27

PEG_C_RXN7

Y26

PEG_C_RXP8

W24

PEG_C_RXN8

W23

PEG_C_RXP9

V27

PEG_C_RXN9

U26

PEG_C_RXP10

U24

PEG_C_RXN10

U23

PEG_C_RXP11

T26

PEG_C_RXN11

T27

PEG_C_RXP12

T24

PEG_C_RXN12

T23

PEG_C_RXP13

P27

PEG_C_RXN13

P26

PEG_C_RXP14

P24

PEG_C_RXN14

P23

PEG_C_RXP15

M27

PEG_C_RXN15

N26

PCIE_CALRP

Y22

PCIE_CALRN

AA22

PEG_RXP[0..15] (4)

PEG_RXN[0..15] (4)

C8301 SCD1U10V2KX-5GPC8301 SCD1U10V2KX-5GP

1 2

C8302 SCD1U10V2KX-5GPC8302 SCD1U10V2KX-5GP

1 2

C8303 SCD1U10V2KX-5GPC8303 SCD1U10V2KX-5GP

1 2

C8304 SCD1U10V2KX-5GPC8304 SCD1U10V2KX-5GP

1 2

C8305 SCD1U10V2KX-5GPC8305 SCD1U10V2KX-5GP

1 2

C8306 SCD1U10V2KX-5GPC8306 SCD1U10V2KX-5GP

1 2

C8308 SCD1U10V2KX-5GPC8308 SCD1U10V2KX-5GP

1 2

C8307 SCD1U10V2KX-5GPC8307 SCD1U10V2KX-5GP

1 2

C8309 SCD1U10V2KX-5GPC8309 SCD1U10V2KX-5GP

1 2

C8310 SCD1U10V2KX-5GPC8310 SCD1U10V2KX-5GP

1 2

C8311 SCD1U10V2KX-5GPC8311 SCD1U10V2KX-5GP

1 2

C8312 SCD1U10V2KX-5GPC8312 SCD1U10V2KX-5GP

1 2

C8313 SCD1U10V2KX-5GPC8313 SCD1U10V2KX-5GP

1 2

C8314 SCD1U10V2KX-5GPC8314 SCD1U10V2KX-5GP

1 2

C8316 SCD1U10V2KX-5GPC8316 SCD1U10V2KX-5GP

1 2

C8315 SCD1U10V2KX-5GPC8315 SCD1U10V2KX-5GP

1 2

C8318 SCD1U10V2KX-5GPC8318 SCD1U10V2KX-5GP

1 2

C8317 SCD1U10V2KX-5GPC8317 SCD1U10V2KX-5GP

1 2

C8320 SCD1U10V2KX-5GPC8320 SCD1U10V2KX-5GP

1 2

C8319 SCD1U10V2KX-5GPC8319 SCD1U10V2KX-5GP

1 2

C8321 SCD1U10V2KX-5GPC8321 SCD1U10V2KX-5GP

1 2

C8322 SCD1U10V2KX-5GPC8322 SCD1U10V2KX-5GP

1 2

C8323 SCD1U10V2KX-5GPC8323 SCD1U10V2KX-5GP

1 2

C8324 SCD1U10V2KX-5GPC8324 SCD1U10V2KX-5GP

1 2

C8325 SCD1U10V2KX-5GPC8325 SCD1U10V2KX-5GP

1 2

C8326 SCD1U10V2KX-5GPC8326 SCD1U10V2KX-5GP

1 2

C8328 SCD1U10V2KX-5GPC8328 SCD1U10V2KX-5GP

1 2

C8327 SCD1U10V2KX-5GPC8327 SCD1U10V2KX-5GP

1 2

C8330 SCD1U10V2KX-5GPC8330 SCD1U10V2KX-5GP

1 2

C8329 SCD1U10V2KX-5GPC8329 SCD1U10V2KX-5GP

1 2

C8332 SCD1U10V2KX-5GPC8332 SCD1U10V2KX-5GP

1 2

C8331 SCD1U10V2KX-5GPC8331 SCD1U10V2KX-5GP

1 2

R8326 1K27R2F-L-GPR8326 1K27R2F-L-GP

1 2

R8318 2KR2F-3-GPR8318 2KR2F-3-GP

Colay with Seymour-XT-S3 (71.SEYMR.M01)

VGA_RST#

R8321

1 2

5

4

DY

DGPU_HOLD_RST#(18)

0R2J-2-GP

U8301_Y

PEG_RXP0 PEG_RXN0

PEG_RXP1 PEG_RXN1

PEG_RXP2 PEG_RXN2

PEG_RXP3 PEG_RXN3

PEG_RXP4 PEG_RXN4

PEG_RXP5 PEG_RXN5

PEG_RXP6 PEG_RXN6

PEG_RXP7 PEG_RXN7

PEG_RXP8 PEG_RXN8

PEG_RXP9 PEG_RXN9

PEG_RXP10 PEG_RXN10

PEG_RXP11 PEG_RXN11

PEG_RXP12 PEG_RXN12

PEG_RXP13 PEG_RXN13

PEG_RXP14 PEG_RXN14

PEG_RXP15 PEG_RXN15

1V_VGA_S0

20101224 A00: Change R8316 to 0402 0 ohm pad.

R8316

1 2

0R0402-PAD

U8303

1

B

2

A

DY

3

GND

74LVC1G08GW-1-GP

5

VCC

4

Y

73.01G08.L04

3D3V_VGA_S0

VGA_RST#

3

2

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

STRAPS

TX_PWRS_ENB

GPIO8_ROMSO

VGA_DIS

GPIO21_BB_EN

BIOS_ROM_EN

VIP_DEVICE_STRAP_EN

RSVD

AUD[1]

GPIO0

GPIO1TX_DEEMPH_EN

GPIO2BIF_GEN2_EN_A 0

GPIO5GPIO5_AC_BATT

GPIO8 RESERVED 0

GPIO[13:11]ROMIDCFG[2:0]

GPIO21 RESERVED

GPIO_22_ROMCSB

V2SYNC

H2SYNC 0

GENERICC 0RSVD

HSYNC X

DESCRIPTION OF DEFAULT SETTINGS

Transmitter Power Savings Enable 0: 50% Tx output swing 1: Full Tx output swing

PCIE TRANSMITTER DE-EMPHASIS ENABLED 0:Tx de-emphasis disabled 1:Tx de-emphasis enabled

0:Advertises the PCIe device as 2.5GT/s capable at power on. 1:Advertises the PCIe device as 5.0GT/s capable at power on.

optional input allow the system to request a fast power reduction by setting GPIO5 to low.

0:VGA Controller capacity enabled 1:The device won't be recognized as the system's VGA controller

BIOS_ROM_EN=1, Config[2:0] defines the ROM type BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size

0:Disable external BIOS ROM device

VIP Device Strap Enable indicates to the software driver that it sense whether or not a VIP device is connected on the VIP Host interface.

1:Enable external BIOS ROM device

RESERVED

AUD[1:0]:11-Audio for both DisplayPort and HDMI

VSYNC XAUD[0]

3D3V_VGA_S0

PIN STRAPS

R8301 3KR2J-2-GPR8301 3KR2J-2-GP

TX_PWRS_ENB(85)

TX_DEEMPH_EN(85)

BIF_GEN2_EN_A(85)

GPIO8_ROMSO(85)

VGA_DIS(85)

CONFIG0(85)

CONFIG1(85)

CONFIG2(85)

VGA_CRT_VSYNC(50,85)

VGA_CRT_HSYNC(50,85)

VSYNC_DAC2(85)

HSYNC_DAC2(85)

BIOS_ROM_EN(85)

GPIO5_AC_BATT(85)

GPIO21_BB_EN(85)

VGA_RST# (85)

3

1 2

R8302 3KR2J-2-GPR8302 3KR2J-2-GP

1 2

R8303 10KR2J-3-GPR8303 10KR2J-3-GP

1 2

R8304 10KR2J-3-GP

1 2

DY

R8305 10KR2J-3-GP

1 2

DY

R8306 10KR2J-3-GPR8306 10KR2J-3-GP

1 2

R8307 10KR2J-3-GP

1 2

DY

R8308 10KR2J-3-GP

1 2

DY

R8309 10KR2J-3-GP

1 2

DY

R8310 10KR2J-3-GP

R8311 10KR2J-3-GP

R8312 10KR2J-3-GP

R8313 10KR2J-3-GP

R8314 10KR2J-3-GP

R8315 10KR2J-3-GP

DY

1 2

DY

1 2

DY

1 2

DY

DY DY

DY

1 2

DY

1 2

PE_GPIO0

dGPU mode

IGPU

IGPU with BACO

JTAG SIGNAL OPTION

H

L

H

2

1

RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 3K RESISTOR X = DESIGN D EPENDANT NA = NOT A PPLICABLE

RECOMMEND

PLATFORM SETTING

X

1

0

?

0

0GPIO9

XXX

0

X

0

0 0 1 (256MB)

0

1

3D3V_VGA_S0

R8324

10KR2J-3-GP

JTAG_TMS_VGA(85)

TESTEN(84)

JTAG_TRST#_VGA(85)

JTAG_TCK_VGA(20,85)

Signal

1 2

R8328

1 2

DY

R8322 10KR2J-3-GP

1 2

R8323 10KR2J-3-GP

1 2

Normal mode

"1"(PU)TESTEN "1"(PU)

"0"(PD) "1"(PU)JTAG_TRST#

JTAG_TCK

CLK

JTAG_TMS

Title

GPU_PEG/STRAPPING(1/5)

Size Document Number Rev

A3

Date: Sheet of

Date: Sheet

GPU_PEG/STRAPPING(1/5)

Nirvana 13

10KR2J-3-GP

DY

10KR2J-3-GP

12

DY

R8327

5K11R2F-L1-GP

DY

Debug mode

pilot run mode

"0"(PD)

NC

"1"(PU)

"1"(PU)"1"(PU)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

NC

of

83 104Tuesday, January 18, 2011

1

A00

5

D D

PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC

1D5V_VGA_S0 1D5V_VGA_S0

12

Ra

R8410

R8410 40D2R2F-GP

40D2R2F-GP

MVREFDA

12

Rb

R8414

R8414 100R2F-L1-GP-U

100R2F-L1-GP-U

C8402

C8402 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

Ra

Rb

12

R8411

R8411 40D2R2F-GP

40D2R2F-GP

12

R8415

R8415 100R2F-L1-GP-U

100R2F-L1-GP-U

MVREFSA

12

C8403

C8403 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DDR3/GDDR3 Memory Stuff Option (ROBSON-S3/SEYMOUR-XT-S3)

DDR5

MVDDQ

Ra

Rb

C C

1D5V_VGA_S0

R8403 243R 2F-2-GPR8403 243R2F-2-G P

1 2 1 2

R8408 243R 2F-2-GPR8408 243R2F-2-G P

This basic topology should be used for DRAM_RST for

**

DDR3/GDDR3/GDDR5.These Capacitors and Resistor values are an example only. The Series R and || Cap values will depend on the DRAM load and will have to be calculated for different Memory ,DRAM Load and board to pass Reset Signal Spec.

Designator

R_MEM_1

B B

R_MEM_2

R_MEM_3

C_MEM

For SEYMOUR

10R

50R

5K

120pF

1.5V

40.2R

100R

DPC_CALR (Park/Robson-S3): Analog calibration. Connect DPxx_CALR to GND through a 150-ȍ (1%) resistor.

MEM_CALRN0 MEM_CALRP0

MEM_RST(88)

For Robson

10R

50R

5K

120pF

DDR3

1.5V/1.8V

40.2R

100R

Must be tied to ground (0 V) through a 1-k to 10-k resistor for normal ASIC operation

R8405

DRAM_RST_1

1 2

51R2J-2-GP

R_MEM_2 R_MEM_1

Place all these components very close to GPU (Within 25mm) and keep all component close to each Other (within 5mm) except R_MEM_2

C_MEM

C8401

1 2

SC120P50V2JN-1GP

150R2F-1-GP

150R2F-1-GP R8407

R8407

1 2

R8402

1 2

10R2J-2-GP

5K1R2F-2-GP

R_MEM_3

4

VGA1C

DQA0_[31..0](88)

DQA1_[31..0](88)

12

R8404

TESTEN(83)

MEM_CALRP1/DPC_CALR

TP8401TP8401 TP8402TP8402

DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31

MVREFDA MVREFSA

MEM_CALRN0 TESTEN

MEM_CALRP0

DRAM_RST

VGA1C

K27

DQA_0

J29

DQA_1

H30

DQA_2

H32

DQA_3

G29

DQA_4

F28

DQA_5

F32

DQA_6

F30

DQA_7

C30

DQA_8

F27

DQA_9

A28

DQA_10

C28

DQA_11

E27

DQA_12

G26

DQA_13

D26

DQA_14

F25

DQA_15

A25

DQA_16

C25

DQA_17

E25

DQA_18

D24

DQA_19

E23

DQA_20

F23

DQA_21

D22

DQA_22

F21

DQA_23

E21

DQA_24

D20

DQA_25

F19

DQA_26

A19

DQA_27

D18

DQA_28

F17

DQA_29

A17

DQA_30

C17

DQA_31

E17

DQA_32

D16

DQA_33

F15

DQA_34

A15

DQA_35

D14

DQA_36

F13

DQA_37

A13

DQA_38

C13

DQA_39

E11

DQA_40

A11

DQA_41

C11

DQA_42

F11

DQA_43

A9

DQA_44

C9

DQA_45

F9

DQA_46

D8

DQA_47

E7

DQA_48

A7

DQA_49

C7

DQA_50

F7

DQA_51

A5

DQA_52

E5

DQA_53

C3

DQA_54

E1

DQA_55

G7

DQA_56

G6

DQA_57

G1

DQA_58

G3

DQA_59

J6

DQA_60

J1

DQA_61

J3

DQA_62

J5

DQA_63

K26

MVREFDA

J26

MVREFSA

J25

MEM_CALRN0

K7

TESTEN

J8

MEM_CALRP1/DPC_CALR

K25

MEM_CALRP0

L10

DRAM_RST

CLKTESTA

K8

1 1

CLKTESTA

CLKTESTB

L7

CLKTESTB

ROBSON-GP-U

Colay with Seymour-XT-S3 (71.SEYMR.M01)

71.ROBSO.M01

3 OF 7

MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8

MAA_9 MAA_10 MAA_11 MAA_12 MAA_13

MAA_14/BA0 MAA_15/BA1

MAA_BA2

DQMA_0 DQMA_1 DQMA_2 DQMA_3 DQMA_4 DQMA_5 DQMA_6

MEMORY INTERFACE

DQMA_7

RDQSA_0 RDQSA_1 RDQSA_2 RDQSA_3 RDQSA_4 RDQSA_5 RDQSA_6 RDQSA_7

WDQSA_0 WDQSA_1 WDQSA_2 WDQSA_3 WDQSA_4 WDQSA_5 WDQSA_6 WDQSA_7

ODTA0

ODTA1

CLKA0

CLKA0#

CLKA1

CLKA1#

RASA0# RASA1#

CASA0# CASA1#

CSA0#_0 CSA0#_1

CSA1#_0 CSA1#_1

CKEA0

CKEA1

WEA0# WEA1#

PX_EN

RSVD#G14

3

MAA0_[8..0] (88)

MAA0_8

K17 J20 H23 G23 G24 H24 J19 K19 J14 K14 J11 J13 H11

MAA0_8

G20 J16 L15 G11

E32 E30 A21 C21 E13 D12 E3 F4

H28 C27 A23 E19 E15 D10 D6 G5

H27 A27 C23 C19 C15 E9 C5 H4

L18 K16

H26 H25

G9 H9

G22 G17

G19 G16

H22 J22

G13 K13

K20 J17

G25 H10

PX_EN_R

AB16

MAA1_8

G14

MAA0_0

MAA0_1

MAA0_2

MAA0_3

MAA0_4

MAA0_5

MAA0_6

MAA0_7

MAA1_0

MAA1_1

MAA1_2

MAA1_3

MAA1_4

MAA1_6

MAA1_7

MAA1_5

MAA1_8

WCKA0_0 (88) WCKA0_0# ( 88) WCKA0_1 (88) WCKA0_1# ( 88) WCKA1_0 (88) WCKA1#_0 ( 88) WCKA1_1 (88) WCKA1#_1 ( 88)

EDCA0_0 (88) EDCA0_1 (88) EDCA0_2 (88) EDCA0_3 (88) EDCA1_0 (88) EDCA1_1 (88) EDCA1_2 (88) EDCA1_3 (88)

DDBIA0_0 (88) DDBIA0_1 (88) DDBIA0_2 (88) DDBIA0_3 (88) DDBIA1_0 (88) DDBIA1_1 (88) DDBIA1_2 (88) DDBIA1_3 (88)

ADBIA0 (88) ADBIA1 (88)

CLKA0 (88) CLKA0# (88)

CLKA1 (88) CLKA1# (88)

RASA0# (88) RASA1# (88)

CASA0# (88) CASA1# (88)

CSA0#_0 (88)

CSA1#_0 (88)

CKEA0 (88) CKEA1 (88)

WEA0# (88) WEA1# (88)

MAA1_[8..0] (88)

20101227 A00: Change R8409 to 0R 0402 pad.

1 2

R8412

R8412 10KR2J-3-GP

10KR2J-3-GP

1 2

R8409

0R0402-PAD

PX_EN (86)

2

1

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

GPU Memory(2/5)

Nirvana 13

1

84 104T uesday, January 18, 2011

A00

of

MEMORY ID Table

DVPDATA[0:3]

GDDR5 1.25GHZ Hynix-H5GQ2H24MFR-T2C 64M*32

0001

GDDR5 1.25GHZ SAMSUNG-K4G20325FC-HC04 64M*32

0000

For Seymour, DPC_PVDD is DPC_VDD18 DPC_PVSS and all DPC_VSSR are DP_VSSR

D D

20101224 A00 Modify: un-stuff THERMTRIP_VGA related circuit at A00 stage for fixed auto shut down issue.

Q8501

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

PURE_HW_SHUTDOWN#(27,28,36)

R8521

VGA_RST #(83)

GPIO_6,GPIO_15_PWRCNTL_0,GPIO_16_SSIN,GPIO_20_PWRCNTL_1: Voltage control signals for the core (VDDC and VDDCI). At Reset, these signals will be inputs with weak internal pull-down resistors. VBIOS can define all voltage control signals to be either 3.3-V or open drain outputs (all signals must be the same type). The output state (high/low) of these signals is programmable for each PowerPlay state.

C C

20110112 A00: Change C8524,C8525 to 18pF from 12pF base on vendor's report.

B B

C8524

1 2

SC18P50V2JN-1-GP

The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. For X8501 with 12 pF load capacitance, each crystal capacitor would be 12 pF [(12-6) x 2 = 12].

R8521

DY

0R2J-2-GP

Rev 3.05 (June 2010) Renamed the Park/Robson-S3 AF24 ball from TESTEN to RSVD.

1D8V_VGA_S0

1V_VGA_S0

1 2

XTAL_X1

2 3

2nd = 82.30034.651

2nd = 82.30034.651 3rd = 82.30034.681

3rd = 82.30034.681

5

Description

DVPDATA[0:3] Default:Pull down

THERMTRIP_VGA

THERMTRIP_R

10KR2J-3-GP

5

6

DY

123 4

Q5801_2

12

C8529

C8529 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

20101230 A00: Change R8512 to 0R0603 short pad.

R8512

12

0R0603-PAD

C8505

SC4D7U6D3V3KX-GP

L8506

1 2

BLM18PG471SN1D-GP

68.00143.181

2nd = 68.00214.211

SC4D7U6D3V3KX-GP

1D8V_VGA_S0

R8511

DY

1MR2F-GP

X8501

41

XTAL_X2

SC18P50V2JN-1-GP

XTAL-27 MHZ- 85-G P

82.30034.641

MEM_ID Control

12

1V_VGA_S0

R8522

DY

L8507

1 2

0R0402-PAD-2-GP

20100105 A00: Change L8507 to 0 ohm short pad, un-stuff C8526,C8527.

TX_PWRS_ENB(83) TX_DEEMPH_EN(83) BIF_GEN2_EN_A(83)

GPIO5_AC_BATT(83)

GPIO8_ROMSO(83)

VGA_DIS(83)

CONFIG0(83) CONFIG1(83) CONFIG2(83)

PWRCNTL_0(92)

1 2

3D3V_VGA_S0

PWRCNTL_1(92)

GPIO21_BB_EN(83)

BIOS_ROM_EN(83)

PEG_CLKREQ#(20)

JTAG_TRST#_VGA(83)

JTAG_TCK_VGA(20,83) JTAG_TMS_VGA(83)

PLACE VREFG DIVIDER AND CAP CLOSE TO ASIC

(1.8V@75mA DPLL_PVDD )

12

DY

12

C8517

DY

C8525

1 2

DPLL_PVDD

C8516

C8515

12

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

(1.0V@125mA DPLL_VDDC)

12

C8518

C8519

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

20101227 A00: Change R8524 to 0R 0402 pad.

R8524

1 2

0R0402-PAD

12

DY

C8520

SC4D7U6D3V3KX-GP

Clock Input Configuraiton -GDDR3/DDR3 a) 27MHz crystal connected to XTALIN or XTALOUT or b) 27MHz (1.8V) oscillator connected to XTALIN or c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only)

Clock Input Configuration -GDDR5 with Park, Robson and Seymour a) 27MHz (3.3V) oscillator connected to XO_IN, AND b) 100MHz (3.3V) oscillator (no spr ead or spread) connected to XO_IN2

1D8V_VGA_S0

R8519 10KR2J-3-GP

R8519 10KR2J-3-GP R8518 10KR2J-3-GP

R8518 10KR2J-3-GP

Hynix_512

12

C8526

DY

R8503

10KR2J-3-GP

1D8V_VGA_S0

R8516

249R2F-GP

DPLL_VDDC

SC2200P50V2KX-2GP

TSVDD

12

DY

1 2 1 2

(1.0V@110mA DPC_VDD10)

DPC_VDD10

12

C8527

DY

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

TP8517 TPAD14-GPT P8517 TPAD14-GP TP8512 TPAD14-GPT P8512 TPAD14-GP TP8505TPAD14 TP8505TPAD14

TP8510TPAD14 TP8510TPAD14

TP8502TPAD14 TP8502TPAD14

TP8507TPAD14 TP8507TPAD14

12

R8515

R8515 499R2F-2-GP

499R2F-2-GP

12

C8523

(1.8V@20mA TSVDD)

C8521

C8521 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1D8V_VGA_S0

P.87

12

C8528

SCD1U10V2KX-5GP

1 1

1

R8523

1 2

10KR2J-3-GP

1

TP8501TP8501

1

TP8503TP8503

1

TP8506TP8506

1

TP8504TP8504

1

TP8508TP8508

1

TP8509TP8509

1

HDMI_HPD_DET(51)

GPU_VREFG

12

C8514

C8514 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R8525

XTALIN_R

1 2

DY

0R2J-2-GP

R8517 0R2J-2-GP

1 2

DY

R8526 0R2J-2-GP

1 2

DY

12

DY

P2800_VGA_DXP P2800_VGA_DXN

TP8511TP8511

12

C8522

SCD1U10V2KX-5GP

MEM_ID1 MEM_ID0

GPIO_VGA_03_DATA GPIO_VGA_04_CLK

GPIO6_VGA VGA_BLEN

GPIO_10_ROMSCK

PWRCNTL_0 GPIO16_SSIN GPIO17_VGA GPIO18_VGA THERMTRIP_VGA PWRCNTL_1

JTAG_TDI_VGA

JTAG_TDO_VGA RSVD

GEN_A GEN_B

GENERICE_HPD4

HDMI_HPD_DET

XTALIN_R

XTALOUT _R

XO_IN XO_IN2

FAN_PWM_C

1

AE9

AE8 AD9

AC10

AD7 AC8 AC7 AB9 AB8 AB7 AB4 AB2

W6

AC6 AC5

AA5 AA6

W1

AA1

U10 T10

P10

W10

AF24

AB13

W8 W9 W7

AD10

AC14

AC16

AF14 AE14

AD14

AM28 AK28

AC22 AB22

AD17 AC17

4

VGA1B

M93-S3/M92-S2

DVCNTL_0/DVPDATA_18

L9

DVCNTL_1/NC#L9

N9

DVCNTL_2/TESTEN#2 DVDATA_12/DVPDATA_16 DVDATA_11/DVPDATA_20 DVDATA_10/DVPDATA_22 DVDATA_9/DVPDATA_12 DVDATA_8/DVPDATA_14 DVDATA_7/DVPCNTL_0 DVDATA_6/DVPDATA_8 DVDATA_5/DVPDATA_6 DVDATA_4DVPDATA_4 DVDATA_3/DVPDATA_19 DVDATA_2/DVPDATA_21

Y8

DVDATA_1/DVPDATA_2

Y7

DVDATA_0/DVPDATA_0

DVO

M93-S3/M92-S2

DPC_PVDD/DVPDATA_11

V6

DPC_PVSS/GND

DPC_VDD18#1/DVPDAT10 DPC_VDD18#2/DVPDAT23

DPC_VDD10#1/DVPDAT15 DPC_VDD10#2/DVPDAT17

U1

DPC_VSSR#1/DVPCLK DPC_VSSR#2/DVPDAT5

U3

DPC_VSSR#3/GND

Y6

DPC_VSSR#4/GND DPC_VSSR#5/DVPCNTL_MV0

R1

SCL

R3

I2C

SDA

GENERAL PURPOSE I/O

U6

GPIO_0 GPIO_1 GPIO_2

U8

GPIO_3_SMBDATA

U7

GPIO_4_SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

GPIO_7_BLON GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

GPIO_11

N5

GPIO_12

N3

GPIO_13

Y9

GPIO_14_HPD2

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16_SSIN

R6

GPIO_17_THERMAL_INT GPIO_18_HPD3

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21_BB_EN

N8

GPIO_22_ROMCSB

N7

GPIO_23_CLKREQB

L6

JTAG_TRST#

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO RSVD#AF24

GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4

HPD1

VREFG

PLL/CLOCK

DPLL_PVDD DPLL_PVSS

DPLL_VDDC

XTALIN XTALOUT

NC#AC22/XO_IN NC#AB22/XO_IN2

THERMAL

T4

DPLUS

T2

DMINUS

R5

TS_FDO TSVDD TSVSS

ROBSON-GP-U

71.ROBSO.M01

Colay with Seymour-XT-S3 (71.SEYMR.M01)

TXCAP_DPA3P

TXCAM_DPA3N

TX0P_DPA2P

DPA

TX0M_DPA2N

TX1P_DPA1P TX1M_DPA1N

TX2P_DPA0P TX2M_DPA0N

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P TX3M_DPB2N

DPB

TX4P_DPB1P TX4M_DPB1N

TX5P_DPB0P TX5M_DPB0N

M92-S2/M93-S3

DVPDATA_3/TXCCP_DPC3P DVPCNTL_2/TXCCM_DPC3N

DVPDATA_7/TX0P_DPC2P DVPDATA_1/TX0M_DPC2N

DVPCNTL_MV1/TX1P_DPC1P

DVPDATA_9/TX1M_DPC1N

DVPDATA_13/TX2P_DPC0P

DVPCNTL_1/TX2M_DPC0N

NC#AA12

DPC

DAC1

VDD1DI VSS1DI

M92-S2/M93-S3

R2/NC#AM12

R2#/NC#AK12

G2/NC#AL11

G2#/NC#AJ11

B2/NC#AK10 B2#/NC#AL9

C/NC#AH12

DAC2

Y/NC#AM10

COMP/NC#AJ9

H2SYNC V2SYNC

VDD2DI/NC#AD19

VSS2DI/NC#AC19

A2VDD/NC#AE20

A2VDDQ/NC#AE17

A2VSSQ

R2SET/NC#AG13

M92-S2/M93-S3M92-S2/M93-S3

DDC1CLK

DDC1DATA

DDC/AUX

DDC2CLK

DDC2DATA

DDCCLK_AUX5P

DDCDATA_AUX5N

DDC6CLK

DDC6DATA

NC#AD20/DDCCLK_AUX3P

NC#AC20/DDCDATA_AUX3N

2 OF 7

AF2 AF4

AG3 AG5

AH3 AH1

AK3 AK1

AK5 AM3

AK6 AM5

AJ7 AH6

AK8 AL7

V4 U5

W3 V2

Y4 W5

AA3 Y2

AA12

AM26

R

AK26

R#

AL25

G

AJ25

G#

AH24

B

AG25

B#

AH26

HSYNC

AJ27

VSYNC

AVSSQ

AUX1P AUX1N

AUX2P AUX2N

RSET

AVDD

GPU_RSET

AD22

AVDD_A2VDDQ

AG24 AE22

AVDD_A2VDDQ

AE23 AD23

AM12 AK12

AL11 AJ11

AK10 AL9

AH12 AM10 AJ9

AL13

HSYNC_DAC2 (83)

AJ13

VSYNC_DAC2 (83)

VDD2DI_GPU

AD19

AC19_GND

1 2

AC19

DY

R8520 0R2J-2-GP

A2VDD_GP U

AE20

A2VDDQ_G PU

AE17

AE19

R2SET

1 2

AG13

715R2F-GP

AE6

VGA_CRT_DDCCLK (50)

AE5

VGA_CRT_DDCDATA (50)

AD2 AD4

AC11

GPU_HDMI_CLK (51)

AC13

GPU_HDMI_DATA (51)

AD13 AD11

DDC1/DDC2/DDC6 have 5V-tolerant

AE16 AD16

AC1 AC3

AD20 AC20

HDMI_CLK (51) HDMI_CLK# (51)

HDMI_DATA0 (51) HDMI_DATA0# (51)

HDMI_DATA1 (51) HDMI_DATA1# (51)

HDMI_DATA2 (51) HDMI_DATA2# (51)

RN8504

SRN4K7J-8-GP

VGA_CRT _RED (50)

VGA_CRT _GRE EN ( 50)

VGA_CRT _BLU E (50)

VGA_CRT _HSY NC (50, 83) VGA_CRT_VSYNC (50,83)

1 2

R8514 499R2F-2-GPR8514 499R2F-2-GP

AVSSQ

50 mA

DY

R8504 0R2J-2-GP

130 mA

1.5 mA

R8501

DY

12

DY

R8508 0R2J-2-GP

12

DY

R8505 0R2J-2-GP

12

DDC1 channel for CRT

DDC2 channel for HDMI

1Mbit SERIAL EEPROM i s optional for Seymour GDDR5 Design

1Mbit SERIAL EEPROM i s required f or Park/Robson GDDR5 Desi gn

NOTE: Designs that do not include an EEPROM must still provide access to the ROM interface signals for debug purposes

3D3V_VGA_S0

4

1

2 3

GPIO_VGA_04_CLK

GPIO_VGA_03_DATA

AVDD_A2VDDQ

A2VDD

AVDD_A2VDDQ

3

Q8503

1

2

3 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

2

LVDS Interface

VGA1F

6

SML1_CLK (20,27)

5

SML1_DATA (20,27)

ROBSON-GP-U

1D8V_VGA_S0

1 2

R8507 0R0603-PADR8507 0R0603-PAD

20101224 A00: Change R8506,R8509 to 0402 0 ohm pad. Change R8507 to 0603 0 ohm pad.

R8506

0R0402-PAD

AVSSQ

SC4D7U6D3V3KX-GP

12

SCD1U10V2KX-5GP

3D3V_VGA_S0

R8509

0R0402-PAD

LVDS CONTROL

TXCLK_UP_DPF3P TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N

TXOUT_U3P TXOUT_U3N

LVTMDP

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N

TXOUT_L3P TXOUT_L3N

71.ROBSO.M01

(1.8V@65mA AVDD)

12

C8501

DY

(1.8V@100mA VDD1DI)

12

C8502

DY

(1.8V@50mA VDD2DI)

C8508

SCD1U10V2KX-5GP

(1.8V@1.5mA A2VDDQ)

C8510

(3.3V@130mA A2VDD)

12

6 OF 7

VARY_BL

DIGON

12

C8503

SCD1U10V2KX-5GP

12

C8506

DY

SC1U6D3V2KX-GP

12

DY

12

SC1U6D3V2KX-GP

AB11 AB12

AH20 AJ19

AL21 AK20

AH22 AJ21

AL23 AK22

AK24 AJ23

AL15 AK14

AH16 AJ15

AL17 AK16

AH18 AJ17

AL19 AK18

AVDD_A2VDDQ

12

C8504

DY

SC1U6D3V2KX-GP

AVSSQ

AVDD_A2VDDQ

12

C8507

SCD1U10V2KX-5GP

AVDD_A2VDD Q

12

C8509

DY

SC1U6D3V2KX-GP

AVDD_A2VDDQ

12

C8511

DY

SC1U6D3V2KX-GP

12

C8512

DY

20100105 A00: Un-stuff C8501 C8502 C8504 C8506 C8511

A2VDD

12

C8513

C8513 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1

1 2

DY

C8533 SC1U6D3V2KX-GP

10KR2J-3-GP

R8528

1 2

C8532 SCD1U10V2KX-5GPC8532 SCD1U10V2KX-5GP

1 2

DY

C8534 SC1U6D3V2KX-GP

1 2

C8535 SCD1U10V2KX-5GPC8535 SCD1U10V2KX-5GP

XTAL_X1 XTAL_X2

SS_SEL0 SS_SEL1

12

R8530

10KR2J-3-GP

U8606

4

VDD_100M

8

VDD_27M

1

XIN

10

XOUT

7

SS_SEL0 SS_SEL13GND

6V40088DNBGI8-GP

71.64088.003

GND_27M

GND_100M

4

27M

100M

R8527 150R2F-1-GP

R8529 124R2F-U-GP

CLK_27R

9

CLK_100R

5

2 6 11

1 2

DY

1 2

DY

1 2

R8502 47R2J-2-GPR8502 47R2J-2-GP

1 2

R8510 33R2J-2-GPR8510 33R2J-2-GP

XO_IN

XO_IN2

XTALIN_R

1.8V

3.3V

Title

Size Docu ment Nu mber Rev

A1

Date: Sheet

3

2

Date: Sheet

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GPU_DP/LVDS/CRT/GPIO(3/5)

Nirvana 13

85 104Tuesday, January 18, 2011

of

A00

20110105 A00: Un-stuff C8536,C8533,C8534 and change L8501 to 0 ohm short pad.

3D3V_S0

L8501

3D3V_S0_U8606

1 2

0R0603-PAD

12

C8536

C8536 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

A A

3D3V_S0

5

DY

1 2

DY

R8531 10KR2J-3-GP

1 2

DY

R8532 10KR2J-3-GP

5

1D5V_VGA_S0

12

C8608

SC1U6D3V2KX-GP

12

C8623

SCD1U10V2KX-5GP

12

C8700

SC4D7U6D3V3KX-GP

MPV18

12

1 2

BLM15BD121SS1D-GP

68.00084.F81

2ND = 68.00217.701

C8694

SCD1U10V2KX-5GP

U8603

U8603 AO3400A-GP

AO3400A-GP

D S

G

12

C8609

C8610

SC1U6D3V2KX-GP

12

C8625

C8624

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

12

C8652

SC1U6D3V2KX-GP

12

C8666

SC1U6D3V2KX-GP

12

C8674

C8673

SC1U6D3V2KX-GP

C8690

SCD1U10V2KX-5GP

L8606

VGA_CORE

84.03400.B37

2nd = 84.03203.031

20101224 A00:

Change R8601 to 0402 0 ohm pad.

DGPU_PWROK

12

C8611

SCD1U10V2KX-5GP

12

C8626

SCD1U10V2KX-5GP

12

C8653

SCD1U10V2KX-5GP

12

C8667

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

12

SPV10

12

C8724

SC4D7U6D3V3KX-GP

1 2

DY

R8602 0R2J-2-GP

3D3V_VGA_S0

R8601

1 2

0R0402-PAD

U8605

1

2

DY

3

TC7SZ08FU-2-GP

73.7SZ08.EAH

2ND = 73.01G08.L04

3rd = 73.7SZ08.DAH

C8612

SC1U6D3V2KX-GP

C8627

SCD1U10V2KX-5GP

VDDC_CT

MPV18

SPV18

C8727

SC1U6D3V2KX-GP

M11_M12

12

R8604

R8604 1KR2J-1-GP

1KR2J-1-GP

1D5V_VGA_PWOK_R

5

4

H13 H16 H19 J10 J23 J24

K10 K23 K24

L11 L12 L13 L20 L21 L22

AA20 AA21 AB20 AB21

AA17 AA18 AB17 AB18

V12 Y12 U12

AA11

Y11

V11 U11

L17

L16

AM30

12

C8728

M11 M12

SCD1U10V2KX-5GP

U8602

AO3418-GP

84.03418.031

G

2nd = 84.P8503.031

3D3V_VGA_S0

VGA1D

MEM I/O

VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

J9

VDDR1 VDDR1 VDDR1 VDDR1

K9

VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

LEVEL

LEVEL TRANSLATION

TRANSLATION

VDD_CT VDD_CT VDD_CT VDD_CT

M93-S3/M92-S2

VDDR3 VDDR3 VDDR3 VDDR3

VDDR4/VDDR5 VDDR4 VDDR4/VDDR5

NC#AA11/VDDR4 DVCLK/VDDR4

NC#V11/VDDR5 NC#U11

MEM CLK

VDDRHA

VSSRHA

PLL

PCIE_PVDD

L8

MPV18

H7

SPV18

H8

SPV10

J7

SPVSS

BACK BIAS

BBP#1 BBP#2

ROBSON-GP-U

Colay with Seymour-XT-S3 (71.SEYMR.M01)

BIF_VDDC_1V

DS

PX_EN#

PX_EN##

I/O

71.ROBSO.M01

U8604

U8604 AO3418-GP

AO3418-GP

D S

Q8602

6

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

CORE

POWER

VDDC/BIF_VDDC VDDC/BIF_VDDC

ISOLATED

ISOLATED CORE I/O

CORE I/O

G

84.03418.031

2nd = 84.P8503.031

2345

1

PCIE

PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR

PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC

1V_VGA_S0BIF_VDDC

PX_EN#1D5V_VGA_PWOK_R

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI

12

C8606

C8607

SC1U6D3V2KX-GP

12

C8621

C8622

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

(1.8V@110mA VDD_CT)

3D3V_VGA_S0

(Park: 1.8V@75mA MPV18)

C8722

SC4D7U6D3V3KX-GP

1V_VGA_S0

(1.8V@75mA SPV18)

12

C8723

SC4D7U6D3V3KX-GP

U8601

AO3400A-GP

DS

G

84.03400.B37

2nd = 84.03203.031

1D5V_VGA_PWOK(83)

8209A_EN/DEM_VGA(92,93)

SC1U6D3V2KX-GP

12

C8697

SC10U6D3V5KX-1GP

12

C8716

(1.8V@75mA SPV18)

12

C8692

BIF_VDDC_CORE

PX_EN##

12

C8698

SC22U6D3V5MX-2GP

12

C8699

SC4D7U6D3V3KX-GP

SC1U6D3V2KX-GP

SPV18

12

SC1U6D3V2KX-GP

DGPU_PWROK(22,92,93)

D D

1D8V_VGA_S0

R8605

1 2

0R0402-PAD

20101227 A00: Change R8605 to 0R 0402 pad.

L8604

1 2

12

BLM15BD121SS1D-GP

68.00084.F81

2ND = 68.00217.701

L8605

1 2

C C

BLM15BD121SS1D-GP

68.00084.F81

2ND = 68.00217.701

BIF_VDDC

3D3V_VGA_S0

12

R8603

R8603 1KR2J-1-GP

1KR2J-1-GP

B B

4 OF 7

AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22

AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 R21 U21

55mA in BACO mode

M13 M15 M16 M17 M18 M20 M21 N20

PX_EN Mode

4

12

BIF_VDDC

0 Normal

BACO1

12

C8628

SC1U6D3V2KX-GP

12

C8646

12

C8679

12

C8657

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

(1.8V@504mA PCIE_VDDR)

12

C8613

SCD1U10V2KX-5GP

(1.0V@1920mA PCIE_VDDC)

12

C8630

C8629

SC1U6D3V2KX-GP

12

C8650

DY

SC1U6D3V2KX-GP

12

C8649

C8665

SC1U6D3V2KX-GP

12

C8676

C8680

SCD1U10V2KX-5GP

12

C8733

DY

SC10U6D3V5KX-1GP

12

C8656

C8655

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

12

C8738

DY

SC10U6D3V5KX-1GP

BIF_VDDC

VGA_Core

1V_VGA

1D8V_VGA_S0

12

C8729

C8615

C8616

SC1U6D3V2KX-GP

12

C8631

SC1U6D3V2KX-GP

12

C8664

12

C8669

12

C8677

(GDDR3/DDR3 1.12V@4A VDDCI)

12

C8659

Non-BACO

1V_VGA_S0

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

12

C8602

C8730

C8633

C8632

SC1U6D3V2KX-GP

12

C8638

SC1U6D3V2KX-GP

12

C8647

SC1U6D3V2KX-GP

12

C8735

12

C8660

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

12

C8639

SC1U6D3V2KX-GP

12

C8670

SC1U6D3V2KX-GP

12

C8736

SC10U6D3V5KX-1GP

12

C8658

SC1U6D3V2KX-GP

PX_EN 1D5V_VGA_PWOK _R PX_EN# PX_EN##

12

C8640

C8641

SC1U6D3V2KX-GP

12

C8645

C8648

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

VGA_CORE

8209A_EN/DEM_VGA

1

001BACO

PX_EN# = High, BIF_VDDC = 1V_VGA_S0 PX_EN## = High, BIF_VDDC = VGA_CORE

3

VGA_CORE

12

C8642

C8644

SC1U6D3V2KX-GP

12

C8672

C8675

C8671

SC1U6D3V2KX-GP

BIF_VDDC

12

C8601

SC10U6D3V5KX-1GP

1001

20101229 A00: Change C8601 to 10uF 0805 size.

BIF_VDDC

VGA_Core

01

1V_VGA

2

1

R8608

DY

2K2R2J-2-GP

Q8604_B

SCD1U10V2KX-5GP

12

C8693

DY

3D3V_S5

DY

Q8604_C

1

DY

12

R8607

R8607 100KR2J-1-GP

100KR2J-1-GP

3

Q8604

Q8604 PMBS3904-1-GP

PMBS3904-1-GP

2

84.03904.L06

2nd = 84.03904.P11

3rd = 84.03904.T11

Title

Size Docu ment Nu mber Rev

A1

Date: Sheet

4

3

2

Date: Sheet

1

Nirvana 13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GPU_POWER(4/5)

86 104Tuesday, January 18, 2011

A00

of

2N7002K-2-GP

Q8604_C

G

S

Q8601

84.2N702.J31

2ND = 84.2N702.031

2N7002K-2-GP

G

DY

S

Q8603

84.2N702.J31

2ND = 84.2N702.031

5

D

8209A_EN/DEM_VGA

1D5V_VGA_PWOK

3D3V_VGA_S0

R8606

12

10KR2J-3-GP

DY

1D5V_VGA_S0

1D5V_VGA_PWOK

1 2

PX_EN(84)

A A

5

1D8V_VGA_S0 DPEF_VDD18

D D

1V_VGA_S0

VGA1E

AA27

PCIE_VSS

AB24

PCIE_VSS

AB32

PCIE_VSS

AC24

PCIE_VSS

AC26

PCIE_VSS

AC27

PCIE_VSS

AD25

PCIE_VSS

AD32

PCIE_VSS

AE27

PCIE_VSS

AF32

PCIE_VSS

AG27

PCIE_VSS

AH32

PCIE_VSS

K28

PCIE_VSS

K32

PCIE_VSS

L27

PCIE_VSS

M32

W25 W26 W27

N25 N27 P25 P32 R27 T25 T32 U25 U27 V32

Y25 Y32

N11 N12 N13 N16 N18 N21

R12 R15 R17 R20 T13 T16 T18 T21

U15 U17 U20

V13 V16 V18 Y10 Y15 Y17 Y20

M6

P6 P9

T6

U9

PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND

C C

N11_GND N12_GND

B B

5 OF 7

GND GND

GND/EVDDQ

GND GND

GND/EVDDQ

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

VSS_MECH VSS_MECH VSS_MECH

A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6 T11 R11

A32 AM1 AM32

VSS_MECH1 VSS_MECH2 VSS_MECH3

4

20101224 A00: Change L8703,L8704,L8705,L8706 to 0402 0 ohm pad. Un-stuff DPx_VDD18 caps.

L8705

1 2

0R0402-PAD-2-GP

N11_GND

N12_GND

0R0402-PAD-2-GP

L8706

1 2

0R0402-PAD-2-GP

TP8701TPAD14-GP TP8701TPAD14-GP

1

TP8702TPAD14-GP TP8702TPAD14-GP

1

TP8703TPAD14-GP TP8703TPAD14-GP

1

1 2

DY

R8702 0R2J-2-GP

1 2

DY

R8704 0R2J-2-GP

DY

12

C8717

DY

SC4D7U6D3V3KX-GP

12

C8721

DY

SC4D7U6D3V3KX-GP

12

DY

C8718

SC1U6D3V2KX-GP

12

DY

C8720

SC1U6D3V2KX-GP

3

C8719

DPEF_VDD10

SCD1U10V2KX-5GP

C8725

DPEF_VDD18

SCD1U10V2KX-5GP

DPEF_VDD10

DPCD_CALR DPAB_CALR

1 2

R8701 150R2F-1-GPR8701 150R2F-1-GP

DPEF_VDD18

(1.8V@130mA DPB_VDD18)

DY

VGA1G

DP A/B POWERDP E/F POWER

AG15

DPE_VDD18

AG16

DPE_VDD18

AG20

DPE_VDD10

AG21

DPE_VDD10

AG14

DPE_VSSR

AH14

DPE_VSSR

AM14

DPE_VSSR

AM16

DPE_VSSR

AM18

DPE_VSSR

AF16

DPF_VDD18

AG17

DPF_VDD18

AF22

DPF_VDD10

AG22

DPF_VDD10

AF23

DPF_VSSR

AG23

DPF_VSSR

AM20

DPF_VSSR

AM22

DPF_VSSR

AM24

DPF_VSSR

AF17

DPEF_CALR

DP PLL POWER

AG18

AF19

AG19

AF20

DPE_PVDD DPE_PVSS

DPF_PVDD DPF_PVSS

ROBSON-GP-U

DP PLL POWER

71.ROBSO.M01

Colay with Seymour-XT-S3 (71.SEYMR.M01)

1D8V_VGA_S01D8V_VGA_S0

12

C8709

12

C8710

DY

12

C8711

7 OF 7

DPA_VDD18 DPA_VDD18

DPA_VDD10 DPA_VDD10

DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR

DPB_VDD18 DPB_VDD18

DPB_VDD10 DPB_VDD10

DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR

DPAB_CALR

DPA_PVDD DPA_PVSS

DPB_PVDD DPB_PVSS

P.85

AE11 AF11

AF6 AF7

AE1 AE3 AG1 AG6 AH5

AE13 AF13

AF8 AF9

AF10 AG9 AH8 AM6 AM8

AE10

AG8 AG7

AG10 AG11

2

DPAB_VDD18

DPAB_VDD10

DPAB_VDD18

DPAB_VDD10

DPAB_VDD18

12

DY

12

DY

R8703

1 2

150R2F-1-GP

(1.8V@300mA DPAB_VDD18)

12

DY

C8714

SCD1U10V2KX-5GP

(1.0V@220mA DPAB_VDD10)

12

DY

C8702

SCD1U10V2KX-5GP

DY

C8712

SC1U6D3V2KX-GP

DY

C8703

SC1U6D3V2KX-GP

12

C8713

12

1

L8704

1 2

0R0402-PAD-2-GP

SC4D7U6D3V3KX-GP

L8703

1 2

0R0402-PAD-2-GP

C8705

SC10U6D3V5KX-1GP

1D8V_VGA_S0

1V_VGA_S0

SC1U6D3V2KX-GP

ROBSON-GP-U

71.ROBSO.M01

A A

71.ROBSO.M01

SC4D7U6D3V3KX-GP

SC1U6D3V2KX-GP

Colay with Seymour-XT-S3 (71.SEYMR.00U)

5

4

3

SCD1U10V2KX-5GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet

GPU_DPPWR/GND(5/5)

Nirvana 13 A00

Taipei Hsien 221, Taiwan, R.O.C.

of

87 104Tuesday, January 04, 2011

1

5

1D5V_VGA_S0

D D

C8824 SC1U6D3V2KX-GPC8824 SC1U6D3V2KX-GP

1D5V_VGA_S0

C C

1D5V_VGA_S0

CLKA0(84) CLKA0#(84)

B B

1 2

R8814 2K37R 2F-GPR8814 2K37R2F-GP

1 2

R8815 5K49R2F-GPR8815 5K49R2F -GP

1 2

C8825 SC1U6D3V2KX-GPC8825 SC1U6D3V2KX-GP

1 2

C8826 SC1U6D3V2KX-GPC8826 SC1U6D3V2KX-GP

1 2

R8816 2K37R 2F-GPR8816 2K37R2F-GP

1 2

R8817 5K49R2F-GPR8817 5K49R2F-G P

1 2

C8827 SC1U6D3V2KX-GPC8827 SC1U6D3V2KX-GP

1 2

C8829 SC1U6D3V2KX-GPC8829 SC1U6D3V2KX-GP

1 2

R8818 2K37R 2F-GPR8818 2K37R2F-GP

1 2

R8819 5K49R2F-GPR8819 5K49R2F-G P

1 2

C8828 SC1U6D3V2KX-GPC8828 SC1U6D3V2KX-GP

1 2

1D5V_VGA_S0

12

R8809

60D4R2F-GP

1D5V_VGA_S0

R8813 0R2J-2-GP

1 2

R8812 0R0402-PADR8812 0R0402-PAD

1 2

R8811 120R2F-GPR8811 120R2F-GP

1 2

1D5V_VGA_S0

VREFC_A0

VREFD1_A0

VREFD2_A0

MAA0_[8..0](84)

12

ADBIA0(84) RASA0#(84) CSA0#_0(84) CASA0#(84)

R8810

WEA0#(84)

60D4R2F-GP

CKEA0(84)

DDBIA0_1(84) DDBIA0_0(84) DDBIA0_2(84) DDBIA0_3(84)

MEM_RST(84)

DY

WCKA0_0(84) WCKA0_0#(84)

WCKA0_1(84) WCKA0_1#(84)

SEN_A0 VRAM1_ZQ

MAA0_7 MAA0_1 MAA0_0 MAA0_6 MAA0_8

MAA0_2 MAA0_5 MAA0_4 MAA0_3

C5 C10 D11

G1

G4 G11 G14

L1

L4 L11 L14

P11

R5

R10

B1

B3

B12 B14

D1

D3 D12 D14

E5

E10

F1

F3 F12 F14

G2

G13

H3

H12

K3 K12

L2

L13

M1

M3 M12 M14

N5

N10

P1

P3 P12 P14

T1

T3 T12 T14

J14

A10 U10

VRAM1B

K4 H5 H4 K5

J5

H11

K10 K11

H10

J4

G3

G12

L3

L12

J12 J11

J3

D2

D13

P13

P2

J2

J10 J13

J1

D4 D5

P4 P5

H5GQ1H24AFR-T2L-GP

Samsung = 72.20325.00U

Hynix = 72.05224.00U

VRAM1A

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VREFC

VPP/NC#A5

VPP/NC#U5 VREFD VREFD

H5GQ1H24AFR-T2L-GP

A8/A7 A9/A1 A10/A0 A11/A6 A12/RFU#J5/NC#J5

BA0/A2 BA1/A5 BA2/A4 BA3/A3

ABI# RAS# CS# CAS# WE#

CK CK# CKE#

DBI0# DBI1# DBI2# DBI3#

RESET#

SEN ZQ MF

WCK1 WCK1#

WCK23 WCK23#

1 OF 2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

2 OF 2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

A5 U5

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

C2 C13 R13 R2

DQA0_12 DQA0_13

DQA0_8

DQA0_9 DQA0_10 DQA0_11 DQA0_15 DQA0_14

DQA0_0

DQA0_3

DQA0_1

DQA0_2

DQA0_6

DQA0_4

DQA0_7

DQA0_5 DQA0_22 DQA0_20 DQA0_23 DQA0_21 DQA0_19 DQA0_17 DQA0_16 DQA0_18 DQA0_29 DQA0_31 DQA0_26 DQA0_30 DQA0_27 DQA0_28 DQA0_24 DQA0_25

4

DQA0_[31..0] (84)

EDCA0_1 (84) EDCA0_0 (84) EDCA0_2 (84) EDCA0_3 (84)

1D5V_VGA_S0

C8862 SC 1U6D3V2KX-GPC8862 SC 1U6D3V2KX-GP

R8823 2K37R 2F-GPR8823 2K37R2F-GP

1 2

R8822 5K49R2F-GPR8822 5K49R2F-G P

1 2

C8865 SC 1U6D3V2KX-GPC8865 SC 1U6D3V2KX-GP

C8864 S C1U6D3V2KX-GPC8864 SC1U6D3V2KX-GP

1 2

R8820 2K 37R2F-GPR8820 2K37R2F-GP

1 2

R8821 5K49R2F-GPR8821 5K49R2F -GP

1 2

C8863 S C1U6D3V2KX-GPC8863 SC1U6D3V2KX-GP

1 2

C8867 S C1U6D3V2KX-GPC8867 SC1U6D3V2KX-GP

1 2

R8824 2K 37R2F-GPR8824 2K37R2F-GP

1 2

R8825 5K49R2F-GPR8825 5K49R2F -GP

1 2

C8866 S C1U6D3V2KX-GPC8866 SC1U6D3V2KX-GP

1 2

1D5V_VGA_S0

12

R8827

60D4R2F-GP

R8829 0R2J-2-GP

R8829 0R2J-2-GP R8830 0R0402-PADR8830 0R0402-PAD R8828 120R2F-GPR8828 120R2F-GP

MF=1 Mirror

1D5V_VGA_S0

CLKA1(84) CLKA1#(84)

20101227 A00: Change R8812,R8830 to 0R 0402 pad.

1 2

MAA1_[8..0](84)

R8826

60D4R2F-GP

1 2

DY

1 2 1 2

MAA1_0 MAA1_6 MAA1_7 MAA1_1 MAA1_8

MAA1_4 MAA1_3 MAA1_2 MAA1_5

VREFC_A1

VREFD1_A1 VREFD2_A1

SEN_A1 VRAM2_ZQ

3

VRAM2A

C5

VDD

C10

VDD

D11

VDD

G1

VDD

G4

VDD

G11

VDD

G14

VDD

L1

VDD

L4

VDD

L11

VDD

L14

VDD

P11

VDD

R5

VDD

R10

VDD

B1

VDDQ

B3

VDDQ

B12

VDDQ

B14

VDDQ

D1

VDDQ

D3

VDDQ

D12

VDDQ

D14

VDDQ

E5

VDDQ

E10

VDDQ

F1

VDDQ

F3

VDDQ

F12

VDDQ

F14

VDDQ

G2

VDDQ

G13

VDDQ

H3

VDDQ

H12

VDDQ

K3

VDDQ

K12

VDDQ

L2

VDDQ

L13

VDDQ

M1

VDDQ

M3

VDDQ

M12

VDDQ

M14

VDDQ

N5

VDDQ

N10

VDDQ

P1

VDDQ

P3

VDDQ

P12

VDDQ

P14

VDDQ

T1

VDDQ

T3

VDDQ

T12

VDDQ

T14

VDDQ

J14

VREFC

A10

VREFD

U10

VREFD

H5GQ1H24AFR-T 2L-GP

VRAM2B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK1

D5

WCK1#

P4

WCK23

P5

WCK23#

H5GQ1H24AFR-T 2L-GP

1 OF 2

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VPP/NC#A5 VPP/NC#U5

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

2 OF 2

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

A5 U5

DQA1_22

A4

DQ0

DQA1_20

A2

DQ1

DQA1_23

B4

DQ2

DQA1_21

B2

DQ3

DQA1_18

E4

DQ4

DQA1_19

E2

DQ5

DQA1_17

F4

DQ6

DQA1_16

F2

DQ7

DQA1_30

A11

DQ8

DQA1_29

A13

DQ9

DQA1_27

B11

DQA1_26

B13

DQA1_31

E11

DQA1_28

E13

DQA1_24

F11

DQA1_25

F13

DQA1_8

U11

DQA1_9

U13

DQA1_10

T11

DQA1_11

T13

DQA1_13

N11

DQA1_14

N13

DQA1_12

M11

DQA1_15

M13

DQA1_0

U4

DQA1_1

U2

DQA1_2

T4

DQA1_3

T2

DQA1_4

N4

DQA1_7

N2

DQA1_6

M4

DQA1_5

M2

C2

EDCA1_2 (84)

C13

EDCA1_3 (84)

R13

EDCA1_1 (84)

R2

EDCA1_0 (84)

DQA1_[31..0] (84)

1D5V_VGA_S0

12

ADBIA1(84) CASA1#(84) WEA1#(84) RASA1#(84) CSA1#_0(84)

CKEA1(84)

DDBIA1_2(84) DDBIA1_3(84) DDBIA1_1(84) DDBIA1_0(84)

MEM_RST(84)

1D5V_VGA_S0

WCKA1_1(84) WCKA1#_1(84)

WCKA1_0(84) WCKA1#_0(84)

2

1

Use internal Vref memory voltage

1D5V_VGA_S0

12

C8832

C8830

C8831

SCD1U10V2KX-5GP

1D5V_VGA_S0

A A

5

12

C8801

SC10U6D3V5KX-1GP

12

C8833

C8834

C8835

C8836

C8837

SCD1U10V2KX-5GP

12

C8839

C8838

C8840

SC1U6D3V2KX-GP

12

C8845

C8841

C8842

C8843

C8844

SC1U6D3V2KX-GP

4

1D5V_VGA_S0

12

C8855

1D5V_VGA_S0

12

3

12

C8849

C8847

SCD1U10V2KX-5GP

C8802

SC10U6D3V5KX-1GP

12

C8851

C8853

C8860

C8858

C8856

SCD1U10V2KX-5GP

12

C8848

C8846

C8850

SC1U6D3V2KX-GP

12

C8861

C8859

C8857

C8852

C8854

SC1U6D3V2KX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

GPU-VRAM1,2 (1/4)

Nirvana 13

1

88 104T uesday, January 18, 2011

A00

of

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

RESERVED

Size Document Number Rev

A3

Date: Sheet

RESERVED

Taipei Hsien 221, Taiwan, R.O.C.

Nirvana 13

of

89 104Tuesday, January 04, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

of

90 104Tuesday, January 04, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Nirvana 13

of

91 104Tuesday, January 04, 2011

1

A00

5

4

3

2

1

3D3V_AUX_S5

PR9218

DY

100KR2J-1-GP

1 2

PWR_VGA_CORE_EN_R#

12

SCD1U10V2KX-4GP

PU9206_Y

12

PC9212

SCD1U10V2KX-4GP

VGA_CORE

12

6

123 4

PR9217

PR9217 3D3R5J-GP

3D3R5J-GP

PQ9203_D

VGA_CORE

PC9213

G

PQ9206

PQ9206 DMN66D0LDW -7-GP

DMN66D0LDW -7-GP

8209A_EN/DEM_VGA PQ9206_3

12

DY

PC9211

PC9210

SC22U6D3V5MX-2GP

12

PG9211

GAP-CLOSE-PWR

VSENSE-TRACE ROUTED DIFFERENTIALLY PARALLEL TO VSENSE+

12

PG9212

GAP-CLOSE-PWR

5V_S5

PC9218

5

4

5

DY

12

SC6800P25V2KX-1GP

VGA_CORE

12

PR9216

PR9216 3D3R5J-GP

3D3R5J-GP

DS

PQ9203

PQ9203 AO3404A-GP

AO3404A-GP

84.03404.B31

VGA_CORE

DY

1 2

PR9220

PR9220 100R2J-2-GP

100R2J-2-GP

VX#D1 VX#D2 VX#D3 VX#D4 VX#D5

VSENSE+

VDES

AGND

VT357FCX-ADJ-007- GP

B1

12

PG9210

AGND_VGA

1 2

52K3R2F-L-GP

3D3V_VGA_S0

DGPU_PWR _EN(93)

D1 D2 D3 D4 D5

A4 A3

PR9219

PR9222

1 2

52K3R2F-L-GP

PWR_VGA_VX

5V_S0

D D

3D3V_VGA_S0

12

PR9214

PR9214 10KR2J-3-GP

10KR2J-3-GP

PWR_VGA_CORE_PGOOD

SC100P50V2JN-3GP

C C

3D3V_VGA_S0

PR9209

10KR2F-2-GP

DY

PWRCNTL_1(85)

3D3V_VGA_S0

12

PR9213

B B

PR9213

10KR2F-2-GP

DY

PWRCNTL_0(85)

VID1 VID0 GPIO20 GPIO15 Voltage

PC9219

12

PR9215

1 2

0R0402-PAD

12

20101224 A00: Change PR9215 to 0402 0 ohm pad.

PD9202

K A

DY

B0530WS-7-F-G P

PD9203

K A

B0530WS-7-F-G P

PR9210

1 2

10K7R2F-GP

PWRCNTL_1_D

1 2

10K7R2F-GP

PWRCNTL_0_D

PR9208

DY

0 0 1.05V

0 1 1.0V

1 0 0.9V

1 1 0.95V

A A

12

PC9202

PC9201

SCD1U10V2KX-4GP

SCD01U16V2KX-3GP

DGPU_PWR OK (22,86,93)

1 2

DY

PR9207

PR9207 5K1R2F-2-GP

5K1R2F-2-GP

PWRCNTL_1_R

1 2

PR9212

PR9212 5K1R2F-2-GP

5K1R2F-2-GP

PWRCNTL_0_R

12

PC9204

SC10U10V5KX-2GP

1 2

1 2 1 2

12

DY

PC9222

SCD047U16V2KX-1-GP

12

PC9223

SCD047U16V2KX-1-GP

PWRCNTL_1_R

PWRCNTL_0#

10R2J-2-GP

5V_S0

12

PR9201

12

PC9205

AGND_VGA

8209A_EN/DEM_VGA PWR_VGA_CORE_PGOOD

SC1U10V2KX-1GP

PWR_VGA_AVDD

PWR_VGA_IRIPL

PWR_VGA_BIAS PWR_VGA_R_SEL/ILOAD

12

PC9215

DY

PQ9204

1

6

2

5

3 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

PU9201

B2

IRIPL

B4

TEMP

A1

BIAS

A2

R_SEL/ILOAD

A5

OE

B5

STAT

PWRCNTL_1#

PWRCNTL_0_R

B3

VDDC4VDD

AVDD

GNDC1GNDC2GND

GNDE1GNDE2GND

C3

GAP-CLOSE-PWR

PWRCNTL_0(85)

PWRCNTL_1(85)

C5

E5

VDDE4VDD

E3

DY

PC9203

SC10U10V5KX-2GP

AGND_VGA

1 2

PR9202

PR9211

SCD22U10V3KX-2GP

PR9205 23K7R2F-GPPR 9205 23K7R 2F-GP

PR9203 44K2R2D-GPPR9203 44K2R2D-GP PR9204 6K49R2F-1-GPPR9204 6K49R 2F-1-GP

100KR2J-1-GP

PL9201 IND-D2U H-11-GP

PU9202_6

PC9220

PC9220 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

1 2

PQ9202_11

PC9221

PC9221 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

1 2

PR9221 10KR2J- 3-GPPR 9221 10KR2J-3-GP

PD9201

2 1

DY

CH551H-30PT-GP

1 2

68.R2010.10I

PWR_VGA_VDES

453KR2F-1-GPDYPR9224

453KR2F-1-GP

12

DY

PWRCNTL_1#

2

3

PU9202_1

5

6

8

9

PQ9202_10

11

12

73.07402.EHB

PR9224

365KR2F-GP

5V_S5

147

8209A_EN/DEM_VGA

12

PC9216

PC9216 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

12

PC9206

SC22U6D3V5MX-2GP

PR9223

12

PWRCNTL_0#

PU9202A

1

TSLVC02APW-G P

PU9202B

4

TSLVC02APW-G P

PU9202C

10

TSLVC02APW-G P

PU9202D

13

TSLVC02APW-G P

12

PC9207

SC22U6D3V5MX-2GP

PWR_VGA_VSENSE+

SC2200P50V2KX-2GP

PC9214

12

PWR_VGA_VSENSE-

PC9217

PQ9202_4

PQ9202_13

8209A_EN/DEM_VGA ( 86,93)

Design Current = 9.03A

14.19A<OCP< 16.77A

12

DY

PC9209

PC9208

SC22U6D3V5MX-2GP

close output MLCC

PR9206

PR9206 38K3R2F-GP

38K3R2F-GP

close output MLCC

12

SCD1U10V2KX-4GP

PU9206

1

B

VCC

2

A

GND3Y

74LVC1G32GW-1G P

73.01G32.AHH

PR9206 38.3 kohm

PR9224 DY

PR9223 365 kohm

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

VT357_+VGA_CORE

Nirvana 13

1

92 104T uesday, January 18, 2011

of

A00

5

3D3V_S0 to 3D3V_VGA_S0 Transfer

DY

1 2

DMP2130L-7-GP

PQ9303

PQ9303 2N7002KDW-GP

2N7002KDW-GP

84.2N702.A3F

PR9305

1 2

10KR2F-2-GP

L

H

L

S

G

2ND = 84.03413.A31

G

6

123 4

3D3V_S0

D D

20110105 A00: Change PR9316 to 10k ohm (follow the standard schematics).

C C

PR9316

PR9316 10KR2J-3-GP

10KR2J-3-GP

1 2

dGPU mode

12

PC9324

PC9324 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

PR9319

3D3V_S0

PR9319

1 2

10KR2J-3-GP

2nd = 84.DM601.03F

PR9319_1 PR9319_2

DGPU_PWR_EN#

IGPU

IGPU with BACO

Power on sequence for Robson-XT and SEYMOUR-XT: 3D3V_VGA_S0 --> 1V_VGA_S0 --> 1D8V_VGA_S0

PR9301

0R2J-2-GP

3D3V_VGA_S0

PQ9302

D

84.02130.031

5

3.3V_RUN_VGA_1

DGPU_PWR_EN

3D3V_VGA discharge

PR9314

PR9314 470R2J-2-GP

470R2J-2-GP

1 2

DGPU_PWR _EN (92)

4

PQ9311

1

DGPU_PWR _EN#(18)

DIS_1D8V_VGA_S0

2

3 4

DGPU_PWR _EN

6

1D8V_VGA_EN#

5

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

3

1D8V_VGA_S0

20101228 A00 Modify: Change PR9320 to short pad at X-Build.

DGPU_PWR _EN(92)

1D8V_VGA_S0_PG

20101224 A00 Modify: un-stuff 1D8V_S0_VGA_PG related circuit at X-Build stage.

1D8V_VGA_S0

PR9320

1 2

0R0402-PAD

1D8V_VGA_ENG9731_PGOOD_1V

PC9323

12

DY

PD9303

2 1

DY

CH551H-30PT-GP

2nd = 84.03904.P11

2nd = 84.03904.P11 3rd = 84.03904.T11

3rd = 84.03904.T11

PR9340

1 2

DY

2K2R2J-2-GP

3D3V_AUX_S5

SCD1U10V2KX-5GP

84.03904.L06

AO4468, SO-8 Id=??A, Qg=9~12nC Rdson=17.4~22m ohm

SC10U6D3V3MX-GP

1 2

PR9334

2nd = 84.DM601.03F

PQ9310_B

1

SCD1U10V2KX-5GP

12

PC9301

DY

2

1D8V_S0

PU9306

S

D

S

D

1

8

S

D

S

D

2

7

S

D

S

D

3

6

GD

12

PC9330

2nd = 84.08882.037

1D8V_VGA_EN# 1D8V_ENABLE_RC

100KR2J-1-GP

5

6

PQ9306

2N7002KDW-GP

84.2N702.A3F

PQ9310_C

3

DY

2

12

PR9338

PR9338 100KR2J-1-GP

100KR2J-1-GP

DY

PQ9310

PQ9310 PMBS3904-1-GP

PMBS3904-1-GP

123 4

GGDDSS

1D8V_ENABLE

3D3V_VGA_S03D3V_S5

PQ9309

G

D

DY

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

AO4468-GP

84.04468.037

15V_S5

1 2

12

PR9339

10KR2J-3-GP

DY

45

PR9335

PR9335 100KR2J-1-GP

100KR2J-1-GP

PR9333

20KR2F-L-GP

1D8V_S0_VGA_PG (83)

1D8V_VGA_S0

12

PC9331

SC10U6D3V3MX-GP

12

PC9329

PC9329 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

1D8V_VGA_S0

12

PR9337

PR9337 470R2J-2-GP

470R2J-2-GP

DIS_1D8V_VGA_S0

1

Discharge Circuit

1D5V_VGA_S0

1D5V_S3 to 1D5V_VGA_S0 trace need increase to avoid 1D5V_VGA_S0 DROP Voltage.

B B

Park_Madison Does Not Support BACO, So follow Old Sequence Seymour_Whistler_Robson Support BACO, So Change Sequence

PD9301

DGPU_PWR_EN(92)

8209A_EN/DEM_VGA(86,92)

A A

2 1

CH551H-30PT-GP

DGPU_PWROK(22,86,92)

5

change low Rds(on) MOSFET

AO4468, SO-8 Id=?A, Qg=9~12nC Rdson=17.4~22m ohm

3D3V_AUX_S5

DY

PR9326

1 2

DY

0R2J-2-GP

PR9327

1 2

0R0402-PAD

20101224 A00 Modify: Change PR9327 to short pad at X-Build.

1 2

100KR2J-1-GP

PR9332

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

1D5V_VGA_EN

1D5V_VGA_EN#

1D5V_S3 1D5V_VGA_S0

PU9305

D

8

D

7

D

6

12

PC9327

PQ9305

PC9327

SCD01U50V2KX-1GP

5

6

123 4

GGDDSS

2nd = 84.08882.037

SC10U6D3V3MX-GP

PC9326

1D5V_ENABLE

AO4468-GP

84.04468.037

1 2

20KR2F-L-GP

12

15V_S5

PR9331

PR9331 100KR2J-1-GP

100KR2J-1-GP

1 2

PR9330

S

1

S

2

S

3

GD

45

1D5V_ENABLE_RC

12

PC9332

SC10U6D3V3MX-GP

Discharge Circuit

1D5V_VGA_S0

12

PR9336

PR9336 470R2J-2-GP

470R2J-2-GP

PQ9307

DIS_1D5V_VGA_S0

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

4

G

S

1D5V_VGA_EN#

G9731 for 1V_VGA_S0

Park_Madison Does Not Support BACO, So follow Old Sequence

Seymour_Whistler_Robson Support BACO, So Change Sequence

3D3V_VGA_S0 should ramp-up before VGA_Core

VGA_Core should ramp-up before 1V_VGA_S0

1V_VGA_S0 should ramp up before 1D8V_VGA_S0

so 1V_VGA_S0 EN have to fine tune RC delay after VGA_Core

PR9312

3D3V_AUX_S5

3

1 2

10KR2J-3-GP

PD9302

2 1

CH551H-30PT-GP

3D3V_VGA_S0

0629 Modify: Reserved PD9302 connect DGPU_PWR_EN to PWR_1V_EN for power down sequence.

DGPU_PWR _EN(92)

1D5V_S3 1V_VGA_S0_LDOIN

DY

PR9302

PWR_1V_EN#

1 2

100KR2J-1-GP

PQ9301

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

PWR_1V_EN

PG9301

1 2

GAP-CLOSE-PWR

PG9302

1 2

GAP-CLOSE-PWR

3D3V_VGA_S0

G9731_PGOOD_1V

PWR_1V_EN

5

6

123 4

PR9304 100KR2J- 1-GPPR9304 100KR2J-1-GP

20101224 A00 Modify: Change PR9311 to short pad at X-Build.

12

PQ9311_3

PC9303

SC10U10V5KX-2GP

5V_S5

PC9313

1 2

PWR_1V_PGOOD

1 2

PR9311

1 2

0R0402-PAD

PC9318

SCD1U10V2KX-5GP

Discharge Circuit

PR9303

12

1V_VGA_S0

470R2J-2-GP

1V_VGA Design current = 1.72A

PU9303

5

VIN

SC1U10V2KX-1GP

12

2

6

VO#4

VPP POK7VO#3

8

VEN

ADJ

9

GND

G9731F11U-GP

74.G9731.03D

2nd = 74.05930.03D

4 3 2 1

Vo(cal.)=1.0036V

12

1K27R2F-L-GP

PR9322

PR9315_2

12

4K99R2F-L-GP

PR9315

1V_PWR 1V_VGA_S0

12

PC9012

DY

PC9317

12

DY

SCD01U16V2KX-3GP

SC22U6D3V5MX-2GP

1 2

GAP-CLOSE-PWR

1 2

PC9316

GAP-CLOSE-PWR

20100106 A00: Power: un-stuff PC9317.

SC22U6D3V5MX-2GP

PG9305

PG9306

Vout=0.8V*(R1+R2)/R2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

DISCRETE VGA POWER

Size Document Number Rev

A2

Nirvana 13

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

1

93 104T uesday, January 18, 2011

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Reserved

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

of

94 104Tuesday, January 04, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

of

95 104Tuesday, January 04, 2011

A00

5

D D

4

3

2

1

C C

B B

A A

(Blanking)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document Number Rev

A3

Date: Sheet

5

4

3

2

Date: Sheet

Reserved

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

of

96 104Tuesday, January 04, 2011

1

A00

5

H4

34.4ID01.001

H4 STF296R138H83-GP

STF296R138H83-GP

1

H15

H15 HOLE335R115-GP

HOLE335R115-GP

1

H5

H5 HOLE256R115-GP

HOLE256R115-GP

ZZ.00PAD.D11

1

ZZ.00PAD.D01

H3 STF 276R160H209-1-GP

H2

H2 HOLE335R115-GP

H1

H1 HT85B85X925R29-S-GP

HT85B85X925R29-S-GP

1

D D

H13

H13 HOLE197R166-1-GP

HOLE197R166-1-GP

1

ZZ.00PAD.V71

C C

HOLE335R115-GP

ZZ.00PAD.D01

H14

H14 HT85BE85R29-U-5-GP

HT85BE85R29-U-5-GP

1

ZZ.00PAD.D41

H3 STF 276R160H209-1-GP

1

H12

H12 HOLE197R166-1-GP

HOLE197R166-1-GP

1

ZZ.00PAD.V71

H6

H6 HT85BE85R29-U-5-GP

HT85BE85R29-U-5-GP

ZZ.00PAD.D41

1

H16

H16 HT85B85X925R29-S-GP

HT85B85X925R29-S-GP

1

DY

1

4

SPR1

SPR1 SPRING-51-GP

SPRING-51-GP

34.4F822.002

H7

H7 HOLE256R115-GP

HOLE256R115-GP

ZZ.00PAD.D11

1

H17

H17 HOLE276R158-GP

HOLE276R158-GP

1

ZZ.00PAD.U61

SPR2

3

H8

H8 HOLE256R115-GP

HOLE256R115-GP

1

SPR3

DY

1

SPRING-24-GP-U

H10

H10 HT85BE85R29-U-5- GP

HT85BE85R29-U-5- GP

SPR6

1

SPRING-24-GP-U

1

SPR4

SPR4 SPRING-24-GP-U

SPRING-24-GP-U

DY

1

34.45T31.001

H11

H11 HOLE197R166-1-GP

HOLE197R166-1-GP

1

ZZ.00PAD.V71

34.42T14.002

SPR7

SPR7 SPRING-57-GP

SPRING-57-GP

1

SPR8

SPR8 SPRING-51-GP

SPRING-51-GP

DY

1

34.4F822.002

2

1

RF Request

CLK_PCI_LPC (18,65,71)

EC9701

DY

SC4D7P50V2CN-1GP

1 2

B B

3D3V_S5

A A

3D3V_S5

3D3V_S5 5V_S5 5V_S5 3D3V_S5 3D3V_S5 3D3V_S5 5V _S5

12

EC9758SC56P50V2JN-2GP EC9758SC56P50V2JN-2GP

EC9759SC56P50V2JN-2GP EC9759SC56P50V2JN-2GP

EC9757SC56P50V2JN-2GP EC9757SC56P50V2JN-2GP

EC9760SC56P50V2JN-2GP EC9760SC56P50V2JN-2GP

12

EC9762SC56P50V2JN-2GP EC9762SC56P50V2JN-2GP

EC9761SC56P50V2JN-2GP EC9761SC56P50V2JN-2GP

5

DCBATOUT

12

EC9702SCD1U50V3KX -GP EC9702SCD1U50V3KX-GP

DY

EC9703

1D5V_S3 3D3V_S0

EC9746SC1U6D3V2KX-GPDYEC9746SC1U6D3V2KX-GP

EC9745SC56P50V2JN-2GPDYEC9745SC56P50V2JN-2GP

12

DY

5V_S0

EC9752SC56P50V2JN-2GPDYEC9752SC56P50V2JN-2GP

12

DY

12

EC9764SC56P50V2JN-2GPDYEC9764SC56P50V2JN-2GP

EC9763SC56P50V2JN-2GP EC9763SC56P50V2JN-2GP

EC9765SC56P50V2JN-2GPDYEC9765SC56P50V2JN-2GP

DY

12

EC9704SCD1U50V3KX -GP EC9704SCD1U50V3KX-GP

1 2

SC4D7P50V2CN-1GP

EC9747SC1U6D3V2KX-GPDYEC9747SC1U6D3V2KX-GP

12

DY

5V_S0

3D3V_S0

EC9753SC56P50V2JN-2GPDYEC9753SC56P50V2JN-2GP

12

DY

12

EC9767SC56P50V2JN-2GP EC9767SC56P50V2JN-2GP

EC9766SC56P50V2JN-2GP EC9766SC56P50V2JN-2GP

5V_S5 5V_S53D3V_S0

EC9705

1 2

SC56P50V2JN-2GP

3D3V_S0 5V_S5 5V_S5

EC9754SC1KP50V2KX-1GPDYEC9754SC1KP50V2KX-1GP

12

DY

1 2

EC9707

EC9706

SC4D7P50V2CN-1GP

EC9748SC56P50V2JN-2GPDYEC9748SC56P50V2JN-2GP

EC9749SC1KP50V2KX-1GPDYEC9749SC1KP50V2KX-1GP

12

DY

5V_S0

DY

1 2

EC9708

SC82P50V2JN-3GP

EC9750SC1KP50V2KX-1GPDYEC9750SC1KP50V2KX-1GP

EC9751SC1KP50V2KX-1GPDYEC9751SC1KP50V2KX-1GP

12

DY

4

EMI Request

EC9709

DY

1 2

SC56P50V2JN-2GP

SC4D7P50V2CN-1GP

CLK_PCH_48M

1D5V_S3

1D5V_S3 VCC_CORE

5V_S5 3D3V_S5

EC9733 SC56P50V2JN-2GPEC 9733 SC56P50V2JN-2GP

EC9710

CLK_PCH_48M(20,32) AUD_DMIC_CLK(29,49) AUD_DMIC_IN0(29,49) LVDS_DDC_DATA_R( 17,49) LVDS_DDC_CLK_R(17,49)

DY

EC9723

12

EC9711

DY

SCD1U10V2KX-5GP

12

SCD1U10V2KX-5GP

5V_S5

EC9724

12

DY

SCD1U10V2KX-5GP

EC9726

12

DY

SCD1U10V2KX-5GP

EC9729

12

DY

SCD1U10V2KX-5GP

EC9727

12

DY

SCD1U10V2KX-5GP

EC9731

12

DY

SCD1U10V2KX-5GP

12

EC9737

12

DY

SC1U6D3V2KX-GP

12

EC9712

DY

SCD1U10V2KX-5GP

12

EC9713

DY

SCD1U10V2KX-5GP

Place close to H2

5V_S5

12

EC9725

DY

SCD1U10V2KX-5GP

Place close to H7

5V_S5

12

EC9730

DY

SCD1U10V2KX-5GP

5V_S5 3D3V_S0

EC9715

EC9714

1 2

SC56P50V2JN-2GP

EC9732

12

DY

SCD1U10V2KX-5GP

EC9740

12

DY

SCD1U10V2KX-5GP

EC9741

12

DY

SCD1U10V2KX-5GP

12

EC9716

DY

SCD1U10V2KX-5GP

AUD_DMIC_CLK

12

EC9718

EC9717

DY

1 2

SCD1U10V2KX-5GP

SC56P50V2JN-2GP

+PVDD 5V_S0

EC9755

12

DY

SCD1U10V2KX-5GP

5V_S5 5V_S0

EC9756

12

DY

SCD1U10V2KX-5GP

Place close to SPR2

1D5V_S3

12

EC9728

DY

SC56P50V2JN-2GP

Place close to H14

5V_S0

12

DY

EC9735

SC56P50V2JN-2GP

5V_S5 5V_S0

12

EC9734 SC56P50V2JN-2GPEC9734 SC56P50V2JN- 2GP

EC9739

12

DY

SCD1U10V2KX-5GP

3

12

47R2J-2-GP

DY

R9701

AUD_DMIC_CLK1

12

DY

EC9719

AUD_DMIC_IN0

12

DY

R9702

AUD_DMIC_IN01

12

DY

EC9720

SCD1U10V2KX-5GP

Place close to H6

5V_S0

12

EC9736

DY

SCD1U10V2KX-5GP

Place close to H10

5V_S5

12

EC9738

DY

SCD1U10V2KX-5GP

3D3V_S5 1D05V_VTT

EC9742

DY

SCD1U10V2KX-5GP

1D5V_S3

EC9743

DY

SCD1U10V2KX-5GP

3D3V_S5 5V_S5

EC9744

DY

SCD1U10V2KX-5GP

LVDS_DDC_CLK_RLVDS_DDC_DATA_R

47R2J-2-GP

DY

EC9721

SCD1U10V2KX-5GP

12

5V_S0

12

DY

EC9722

SCD1U10V2KX-5GP

+DC_IN +DC_IN DCBATOUT

PC4035SCD1U5 0V3KX-GP PC4035SCD1U50V3KX-GP

3D3V_DAC_S0

EC9769SC56P50V2JN-2GPDYEC9769SC56P50V2JN-2GP

2

12

3D3V_DAC_S0

12

DY

12

PC4036SCD1U5 0V3KX-GP PC4036SCD1U50V3KX-GP

12

EC9770SC56P50V2JN-2GPDYEC9770SC56P50V2JN-2GP

DY

3D3V_DAC_S0

12

EC9768SCD1U5 0V3KX-GP EC9768SCD1U50V3KX-GP

12

EC9771SC56P50V2JN-2GPDYEC9771SC56P50V2JN-2GP

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Nirvana 13

1

Taipei Hsien 221, Taiw an, R.O.C.

97 104T uesday, January 18, 2011

A00

of

Title

UNUSED PARTS/EMI Capacitors

Size Document Number Rev

A2

Date: Sheet

5

4

3

2

1

Huron River Platform Power Sequence

(AC mode)

+RTC_VCC

RTC_RST#

Within logic high level and disable if

D D

it is less than the logic low level.

V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within

0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V.

Not floating.

Sense the power button status

This signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input.

C C

V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V.

DCBATOUT

3D3V_AUX_S5

S5_ENABLE

5V_S5

3D3V_S5

+5VA_PCH_VCC5REFSUS

PM_RSMRST#(EC Delay 40ms) T6

PCH_SUSCLK_KBC

AC_PRESENT

KBC_PWRBTN#

AC

PM_PWRBTN#

AC

PM_SLP_S4#

PM_SLP_S3#

PM_LAN_ENABLE

1D5V_S3

DDR_VREF_S3(0.75V)

5V_S0

3D3V_S0

+5VS_PCH_VCC5REF

1D5V_S0

1D8V_S0

0D75V_S0

RUNPWROK

1D05V_VTT

1.05VTT_PWRGD

0D85V_S0

D85V_PWRGD

CPU SVID BUS

VCC_CORE

VCC_GFXCORE

IMVP_PWRGD

B B

This signal represents the Power Good for all the non-CORE and non-graphics power rails.

CLK_EXP_P

PWROK

VDDPWRGOOD

H_CPUPWRGD

SYS_PWROK

PLT_RST#

DMI

AC

T1

PM_PWRBTN#

>9ms

T2

T3

T4

3D3V_AUX_KBC

T10

0D85V_S0

ALL_SYS_PWRGD=D85V_PWRGD

D85V_PWRGD

1D8V_S0

T5

>10ms

Press Power button

T11

>30us

T12

T13

T14

T15

T17

T18

T19

T24

>99ms

T27

<650ms2ms<

T29

red word: KBC GPIO

KBC GPIO34 control power on by 3V_5V_EN

>5ms

0ms<

T8T7<90ms

>16ms

T9

+5V_RUN & +3.3V_RUN need meet 0.7V difference

T16

T20

>0us

T28

>1ms

T30

>2ms

T31

<650ms5ms<

T32

KBC GPIO43 to PCH

PCH to KBC GPIO00

KBC GPO84 to PCH

Platform to KBC PSL_IN2

KBC GPIO20 to PCH

PCH to KBC GPIO44

PCH to KBC GPIO01

KBC GPIO23 to LAN

Enable by PM_SLP_S4#

T21

T22

SetVID ACK

T33

1ms<

T35

1D8V_S0 & 1D5V_S3 power ready

T23

TPS51461RGER PGOOD

50us< <2000us

T25

T26

ISL95831 PGOOD to system

<5ms

>0ms

<100ms

VT357FCX PGOOD

KBC GPIO77 to PCH

PCH to CPU

>1ms+60us

T34

PCH to all system

<200us

T36

(DC mode)

Sense the power button status

V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within

0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V.

V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V.

This signal represents the Power Good for all the non-CORE and non-graphics power rails.

+RTC_VCC

RTC_RST#

DCBATOUT

3D3V_AUX_S5

KBC_PWRBTN#

3D3V_AUX_KBC

S5_ENABLE

5V_S5

3D3V_S5

+5VA_PCH_VCC5REFSUS

PM_PWRBTN#

PM_RSMRST#

PCH_SUSCLK_KBC

PM_SLP_S4#

PM_SLP_S3#

PM_LAN_ENABLE

1D5V_S3

DDR_VREF_S3(0.75V)

5V_S0

3D3V_S0

+5VS_PCH_VCC5REF

1D5V_S0

1D8V_S0

0D75V_S0

1D05V_VTT

1.05VTT_PWRGD

0D85V_S0

D85V_PWRGD

CPU SVID BUS

VCC_CORE

VCC_GFXCORE

IMVP_PWRGD

CLK_EXP_P

PWROK

VDDPWRGOOD

H_CPUPWRGD

SYS_PWROK

PLT_RST#

DMI

DC

PCH_RSMRST#

red word: KBC GPIO

>9ms

T1

T2

Press Power button

T10

0D85V_S0

ALL_SYS_PWRGD=D85V_PWRGD

D85V_PWRGD

1D8V_S0

Platform to KBC PSL_IN2

T3

T4

T5

T6

T11

>30us

T12

T13

T14

T15

T17

T18

T19

T24

>99ms

T27

T28

<650ms2ms<

T29

EC_ENABLE#_1(G PIO31) keep low

KBC GPIO34 control power on by 3V_5V_EN

+5V_ALW & +3.3V_ALW need meet 0.7V difference

T7

>16ms

T8

>10ms

>5ms

T9

KBC GPIO20 to PCH

KBC GPIO43 to PCH

PCH to KBC GPIO00

+5V_RUN & +3.3V_RUN need meet 0.7V difference

T16

T20RUNPWROK

T21

>0us

>1ms

T30

>2ms

T31

<650ms5ms<

T32

PCH to KBC GPIO44

PCH to KBC GPIO01

KBC GPIO23 to LAN

Enable by PM_SLP_S4#

1D8V_S0 & 1D5V_S3 power ready

T22

T23

ACKSetVID

50us< <2000us

T25

T26

<5ms

>0ms

T33

1ms<

<100ms

T35

VT357FCX PGOOD

TPS51461RGER PGOOD

ISL95831 PGOOD to system

KBC GPIO77 to PCH

PCH to CPU

>1ms+60us

T34

PCH to all system

<200us

T36

Robson XT Power-Up/Down Sequence

DGPU_PWR_EN#(Discrete only)

3D3V_VGA_S0(Discrete only)

A A

8209A_EN/DEM_VGA(Discrete only)

VGA_CORE(Discrete only)

1V_VGA_S0(Discrete only)

9035_PGOOD_1V(Discrete only)

1D8V_VGA_S0(Discrete only)

DGPU_PWROK(Discrete only)

1D5V_VGA_S0(Discrete only)

3D3V_S0

Ta

>0ms

Tb

Tc

Td

>0ms

<20ms

For power-down, reversing the ramp-up sequence is recommended.

5

4

PCH GPIO54 output

3D3V_VGA_S0 above VT357 VIH

RT9035 PGOOD

VT357 PGOOD

Title

Size Docu ment Nu mber Rev

A1

Date: Sheet

Tuesday, January 04, 2011

Date: Sheet

Tuesday, January 04, 2011

Date: Sheet

3

2

Tuesday, January 04, 2011

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Power Sequence

Nirvana 13

A00

98

of

104

5

4

3

2

1

Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM

AC

D D

DC

Battery

Page39

C C

B B

Adapter in

PWR_CHG_ACOK

BT+

Page38

5

RUNPWROK

AD+

SWITCH

Page40

BQ24745 Charger

Page40

ACOK

-1

Power Button

5V_S5 DCBATOUT

TPS51218DSCR

EN

5V_S5

-6.1

DCBATOUT

-4

AC_IN#

KBC_PWRBTN#

PM_SLP_S4#

PM_SLP_S3#

V5IN VIN

Page45

DCBATOUT

-3.1 -3.1 -3.1

3V_5V_EN

-3.3

15V_S5

PUMP

-5

-2

BJT

SLP_S4# SLP_S3#

RSMRST#

PWRBTN#

Cougar Point PCH

APWROK

PWROK

SYS_PWROK

3

PM_SLP_S4#

4

PM_SLP_S3#

DRAMPWRGD

PROCPWRGD

PLTRST#

1

PWR_5V3D3V_ENC

ENC

RT8223MGQW DC/DC (3V/5V)

VIN

-3

3D3V_AUX_KBC

GPIO70

KBC NPCE795P

GPIO6

GPIO44

GPIO01

GPIO34

GPIO43

GPIO20

Page27

GPIO77

LL1

LL2

VREG5

VREG3

PGOOD

Page41

-3.2

5V_S5

3D3V_S5

5V_AUX_S5

3D3V_AUX_S5

3V_5V_POK

-3.1

S5_ENABLE

-2.1

PM_RSMRST#

PM_PWRBTN#

S0_PWR_GOOD

SYS_PWROK

2

10

1D05_VTT

VOUT

PGOOD

1.05VTT_PWRGD

S0_PWR_GOOD

IMVP_PWRGD

AND GATE

A

B

Y

10

SYS_PWROK

5a

S5_ENABLE

11

12

13

PLT_RST#

SWITCH

Page37

SWITCH

Page37

SWITCH

Page37

5V_S0

3D3V_S0

1D5V_S0

0D75V_EN

PM_DRAM_PWRGD

H_CPUPWRGD

AND GATE

B

A

Y

VDDPWRGOOD

H_CPUPWRGD_R

BUF_CPU_RST#

SM_DRAMPWROK

UNCOREPWRGOOD

Sandy Bridge CPU

RSTIN#

SVID

3

PM_SLP_S4#

4

PM_SLP_S3#

SVID

8

-6

DCBATOUT5V_S5

VDDP VIN

EN

TPS51116RGER

Page46

5V_S5 3D3V_S5

VIN

VDD

TPS53311RGTR

EN

Page47

VOUT

REF

VTT

PGD

VOUT

PGD

1D5V_S3

DDR_VREF_S3

0D75V_S0

RUNPWROK

5

1D8V_S0

RUNPWROK

5

5a

1.05VTT_PWRGD

VIN

RT8208BGQW

EN

Page48

PGOOD

VOUT

0D85_S0

D85V_PWRGD

-7

RTC_AUX_S5

VDDP

6

DCBATOUT

A A

6

D85V_PWRGD

8

SVID

7

IMVP_VR_ON

VIN

VR

OUTPUT

SVID

ISL95831HRTZ

VR_ON

Page42 & 43 & 44

PGOOD

VCC_CORE

VCC_GFXCORE

IMVP_PWRGD

9

Power Up Sequence: -8 ~ 13

5

4

3

3D3V_AUX_S5

+RTC_VCC

RTC battery

-5

-8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Nirvana 13

1

Taipei Hsien 221, Taiw an, R.O.C.

99

A00

of

104

Title

Power Up Sequence Diagram

Size Document Number Rev

A2

Tuesday, January 04, 2011

Date: Sheet

Tuesday, January 04, 2011

Date: Sheet

Tuesday, January 04, 2011

2

Date: Sheet

5

D D

4

3

2

1

Adapter

DCBATOUT

POLYSW

DCBATOUT_LCD

AO4407A

Charger

BQ24745

Battery

+PBATT

TPS51427

C C

15V_S5

3D3V_AUX_S5

RT9026

0D75V_S0DDR_VREF_S3

B B

5V_AUX_S5

VT1316+VT1317

VCC_CORE

VT1317

VCC_GFXCORE

VT357

1D05V_VTT

RT9035

1V_VGA_S0

5V_S5

1D5V_S3

G547F2P81

5V_USB1_S3

TPCA8062

1D5V_S0

AO4468

5V_S0

VT357

VGA_CORE

3D3V_S5

TPS51461

0D85V_S0

AO4468 DMP2130L

AO4468

3D3V_S0

G5285T11

TPS51311

RTS5138

1D8V_S0

AO3403

3D3V_LAN_S5

1D8V_VGA_S0

LCDVDD

3D3V_CARD_S0

3D3V_VGA_S0

Power Shape

A A

5

4

Regulator LDO Switch

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Block Diagram

Size Document Number Rev

A3

Date: Sheet

2

Date: Sheet

Power Block Diagram

Nirvana 13

Taipei Hsien 221, Taiwan, R.O.C.

of

100 104Tuesday, January 04, 2011

1

A00

Wistron Nirvana 13 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual