Wistron Morar, Aspire 3600, TravelMate 2400, TravelMate 2410 Schematic
A
B
C
D
Morar Block Diagram 2005/05/28
E
CLK GEN.
4 4
DDR II
IDT CV125
3 4, 5
400MHz
400 MHz
11,12
DDR II
400MHz
400 MHz
11,12
3 3
Line In
Int.
MIC In
Line Out
27
Codec
ALC655
27
OP AMP
27
G1421B
ACLINK
26
27
Mobile CPU
Dothan
HOST BUS
400MHz
Intel 910GML
6,7,8,9,10
DMI I/F
100MHz
ICH6-M
G792
PCI BUS
19
RGB
LVDS
ENE
CB1410
10/100
CRT
CONN
LCD
XGA/WXGA
24,25
LAN
RTL8110CL
2 2
INT.SPKR
27
MODEM
MDC Card
21
22, 23
LPC BUS
15,16,17,18
PATA
USB
HDD
20
1 1
A
CD ROM
20
B
4 PORT
21
MINI USB
21
Blue-tooth
C
Project Code:91.4E101.001
PCB:05210-SB
14
13
Mini-PCI
802.11 B/G
KBC
ENE KB3910
Pad
30 30
PWR SW
CP2211
25
28
TXFM
23
Xbus
INT_KBTouch
PCMCIA
ONE SLOT
RJ45
23
BIOS ROM
4M BITS
PM39LV040-70JCE
3129
25
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
D
SYSTEM DC/DC
INPUTS
DCBATOUT
INPUTS OUTPUTS
DCBATOUT
5V_S5
DCBATOUT
INPUTS
DCBATOUT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
MORAR
MORAR
MORAR
TPS5130
OUTPUTS
3D3V_S5
5V_S5
1D05V_S0
2D5V_S0(LDO)
SYSTEM DC/DC
ISL6227
5V_S5
3D3V_S3
TPS51100DGQ
CHARGER
DDR_VREF
DDR_VREF_S3
ISL6255
OUTPUTSINPUTS
BT+
16.8V 3A
CPU DC/DC
ISL6218CV-T
OUTPUTS
VCC_CORE
0.844~1.3V
27A
140Thursday, June 09, 2005
140Thursday, June 09, 2005
140Thursday, June 09, 2005
of
of
of
E
35,36
37
37
38
34
SB
SB
SB
A
B
C
D
E
Alviso Strapping Signals
and Configuration
Pin Name
CFG[2:0]
4 4
CFG[3:4]
CFG5
CFG6
CFG7
CFG[8:11]
CFG[12:13]
CFG[14:15]
CFG16
CFG17
CFG18
3 3
CFG19
CFG20
SDVOCRTL
_DATA
All strap signals are sampled with respect to the leading
NOTE:
edge of the Alviso GMCH PWORK In signal.
Strap Description
FSB Frequency Select
Reversed
DMI x2 Select
DDR I / DDR II
CPU Strap
Reversed
XOR/ALL Z test
straps
Reversed
FSB Dynamic ODT 0 = Dynamic ODT Disabled
Reversed
CPU core VCC
Select
CPU VTT Select
Reversed
SDVO Present
Configuration
000 = Reserved
001 = FSB533
010 = FSB800
011-111 = Reversed
0 = DMI x2
1 = DMI x4
0 = DDR II
1 = DDR I
0 = Prescott
1 = Dothan
00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation
(Default)
1 = Dynamic ODT Enabled
(Default)
0 = 1.05V
1 = 1.5V
0 = 1.05V
1 = 1.2V
0 = No SDVO device present
(Default)
1= SDVO device present
(Default)
(Default)
(Default)
(Default)
page 7
PCI Routing
7411
MiniPCI
LAN
25
21
23
IRQ
B.F.G
F
E
REQ/GNTIDSEL
0
1
2
ICH6-M Integrated Pull-up
and Pull-down Resistors
ACZ_BIT_CLK,
EE_DOUT,
GNT[6]#/GPO[16],
LAD[3:0]#/FB[3:0]#, LDRQ[0],
PME#, PWRBTN#,
LAN_RXD[2:0]
ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC,
ACZ_SDOUT,ACZ_BITCLK,
SPKR,
USB[7:0][P,N]
DD[7],
LAN_CLK
DPRSLP#, EE_DIN,
GNT[5]#/GPO[17],
TP[3]
EE_CS,
SDDREQ
LDRQ[1]/GPI[41],
DPRSLPVR,
ICH6 internal 20K pull-ups
ICH6 internal 10K pull-ups
ICH6 internal 20K pull-downs
ICH6 internal 15K pull-downs
ICH6 internal 11.5K pull-downs
ICH6 internal 100K pull-downs
ICH6-M EDS 14308 0.8V1
ICH6-M IDE Integrated Series
Termination Resistors
DD[15:0],
DDACK#,
DCS3#,
IORDY,
IDEIRQ
DIOR#, DREQ,DIOW#,
DA[2:0],
DCS1#,
approximately 33 ohm
2 2
1 1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Memo
Memo
Memo
MORAR
MORAR
MORAR
SB
SB
240Saturday, May 28, 2005
240Saturday, May 28, 2005
240Saturday, May 28, 2005
of
of
of
SB
3D3V_S0 3D3V_S03D3V_S0
12
C201
C201
SCD1U16V
SCD1U16V
R191
R191
1 2
0R3-U
0R3-U
3D3V_APWR_S0 3D3V_CLKGEN_S03D3V_48MPWR_S0
12
C203
C203
SC4D7U10V5ZY
SC4D7U10V5ZY
12
C215
C215
SCD1U16V
SCD1U16V
12
R166
R166
1 2
0R3-U
0R3-U
C192
C192
SCD1U16V
SCD1U16V
12
C191
C191
SC4D7U6D3V3KX
SC4D7U6D3V3KX
12
SCD1U16V
SCD1U16V
C190
C190
12
C200
C200
SCD1U16V
SCD1U16V
R155
R155
1 2
0R3-U
0R3-U
12
C202
C202
SC10U10V5ZY-L
SC10U10V5ZY-L
12
C214
C214
SCD1U16V
SCD1U16V
12
C216
C216
SCD1U16V
SCD1U16V
12
C217
C217
SCD1U16V
SCD1U16V
12
C189
C189
SCD1U16V
SCD1U16V
12
C193
C193
SCD1U16V
SCD1U16V
12
C194
C194
SCD1U16V
SCD1U16V
12
C188
C188
SCD1U16V
SCD1U16V
6218_PGOOD32,34
IN
(3D3V_S0)
H
X
3D3V_CLKGEN_S0
R162
R162
1KR2
1KR2
R165
R165
DUMMY-R2
DUMMY-R2
EN
(6218_PGOOD)
12
12
R159
R159
DUMMY-R2
DUMMY-R2
12
12
R158
R158
DUMMY-R2
DUMMY-R2
Morar_SB
Q14
Q14
R1
R1
2
IN
IN
R2
R2
DTC124EKA
DTC124EKA
L
1D05V_S0
12
R221
R221
DUMMY-R2
DUMMY-R2
12
R220
R220
DUMMY-R2
DUMMY-R2
3D3V_S0
12
R151
R151
10KR2
10KR2
VTT_PWRGD#
OUT
OUT
3
GND
GND
1
OUT
(VTT_PWRGD#)
H
Hi - ZH
FS_A
FS_B
FS_C
0
0
0
0
1
1
0
0
1
1 100M
0
1
1
1
1
CPU_SEL1 7
CPU_SEL0 4,7
CPU
FS_A
0
266M
133M
01200M
166M
1
00333M
1
0
400M
1 Reserved
PCLK_MINI28
PCLK_LAN22
PCLK_PCM24
PCLK_KBC29
CLK_ICHPCI16
C205
C205
1 2
SC33P50V2JN
SC33P50V2JN
C204
C204
1 2
SC33P50V2JN
SC33P50V2JN
3D3V_S0
DY
DY
R222 33R2R222 33R2
R175 33R2R175 33R2
R174 22R2R174 22R2
R173 33R2R173 33R2
R172 33R2R172 33R2
X1
X1
X-14D31818M-1
X-14D31818M-1
1 2
12
R167
R167
10KR2
10KR2
12
R169
R169
10KR2
10KR2
CLK_PCIE_ICH
CLK_PCIE_ICH#
DREFSSCLK#
DREFSSCLK
DREFCLK
DREFCLK#
1 2
1 2
1 2
1 2
1 2
PM_STPPCI#16
SMBC_ICH11,18
SMBD_ICH11,18
DREFCLK7
DREFCLK#7
12
R168
R168
10KR2
10KR2
12
R170
R170
10KR2
10KR2
CLK_Audio26
CLK_ICH1416
CLK_ICH14 & CLK14_SIO
need equal length
ITP_EN
SS_SEL
DY
DY
R206 49D9R2FR206 49D9R2F
1 2
R205 49D9R2FR205 49D9R2F
1 2
R156 49D9R2FR156 49D9R2F
1 2
R157 49D9R2FR157 49D9R2F
1 2
R161 49D9R2FR161 49D9R2F
1 2
R160 49D9R2FR160 49D9R2F
1 2
H/L: 100/96MHz
SS_SEL
ITP_EN
H/L : CPU_ITP/SRC7
RN17 SRN33-2-U2RN17 SRN33-2-U2
23
1
4
R218 33R2R218 33R2
1 2
R217 33R2R217 33R2
1 2
R212 475R2FR212 475R2F
1 2
VTT_PWRGD#
U13
U13
56
PCI0
3
PCI1
4
PCI2
5
PCI3
9
PCIF1/SEL100/96#
8
PCIF0/ITP_EN
55
PCI_STOP#
46
SCL
47
SDA
14
DOT96
15
DOT96#
50
XTAL_IN
49
XTAL_OUT
52
REF
39
IREF
10
VTT_PWRGD#/PD
2
VSS_PCI
6
VSS_PCI
51
VSS_REF
45
VSS_CPU
38
VSSA
13
VSS48
29
VSS_SRC
IDTCV125PA
IDTCV125PA
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_XDP_CPU
CLK_XDP_CPU#
LVDS
LVDS#
SRC1
SRC1#
SRC2
SRC2#
SRC3
SRC3#
SRC4
SRC4#
SRC5
SRC5#
SRC6
SRC6#
CPU2_ITP/SRC7
CPU2_ITP#/SRC7#
CPU0
CPU0#
CPU1
CPU1#
CPU_STOP#
FSC/TEST_SEL
FSB/TEST_MODE
USB48/FSA
VDD_SRC
VDD_SRC
VDD_PCI
VDD_PCI
VDD_REF
VDD_CPU
VDDA
VDD48
VDD_SRC
R216 49D9R2FR216 49D9R2F
1 2
R215 49D9R2FR215 49D9R2F
1 2
R214 49D9R2FR214 49D9R2F
1 2
R213 49D9R2FR213 49D9R2F
1 2
R209 49D9R2FR209 49D9R2F
1 2
R207 49D9R2FR207 49D9R2F
1 2
R211 49D9R2FR211 49D9R2F
1 2
R210 49D9R2FR210 49D9R2F
1 2
17
18
19
20
22
23
24
25
26
27
CLK_PCIE_ICH1
31
CLK_PCIE_ICH#1
30
CLK_MCH_3GPLL1
33
CLK_MCH_3GPLL#1
32
CLK_XDP_CPU1
36
CLK_XDP_CPU#1
35
CLK_CPU_BCLK1
44
CLK_CPU_BCLK#1
43
CLK_MCH_BCLK1
41
CLK_MCH_BCLK#1
40
54
CPU_SEL0
53
CPU_SEL1
16
12
34
21
7
1
48
42
37
11
28
DREFSSCLK1
DREFSSCLK#1
FS_A
R163 22R2R163 22R2
3D3V_CLKGEN_S0
3D3V_APWR_S0
3D3V_48MPWR_S0
2 3
1
4
RN16
RN16
SRN33-2-U2
SRN33-2-U2
RN20 SRN33-2-U2RN20 SRN33-2-U2
1
4
2 3
RN21 SRN33-2-U2RN21 SRN33-2-U2
1
4
2 3
RN22 SRN33-2-U2RN22 SRN33-2-U2
1
4
2 3
RN24 SRN33-2-U2RN24 SRN33-2-U2
1
4
2 3
RN23 SRN33-2-U2RN23 SRN33-2-U2
1
4
2 3
12
CLK48_ICH 16
EMI capacitor
CLK_ICH14
PCLK_PCM
PCLK_MINI
PCLK_KBC
CLK_ICHPCI
CLK48_ICH
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
EC111 SC10P50V2JN-1
EC111 SC10P50V2JN-1
DY
DY
EC93 SC10P50V2JN-1
EC93 SC10P50V2JN-1
DY
DY
EC113 SC10P50V2JN-1
EC113 SC10P50V2JN-1
DY
DY
EC92 SC10P50V2JN-1
EC92 SC10P50V2JN-1
DY
DY
EC91 SC10P50V2JN-1
EC91 SC10P50V2JN-1
DY
DY
EC90 SC10P50V2JN-1
EC90 SC10P50V2JN-1
DY
DY
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Clock Generator - IDT125
Clock Generator - IDT125
Clock Generator - IDT125
MORAR
MORAR
MORAR
340Friday, June 24, 2005
340Friday, June 24, 2005
340Friday, June 24, 2005
DREFSSCLK 7
DREFSSCLK# 7
CLK_PCIE_ICH 16
CLK_PCIE_ICH# 16
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_XDP_CPU 4
CLK_XDP_CPU# 4
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
PM_STPCPU# 16,34
SB
SB
SB
A
U35A
U35A
BGA479-SKT-2-U
BGA479-SKT-2-U
H_A#3
4 4
3 3
H_STPCLK#
H_A#[31..3]6
H_ADSTB#06
H_REQ#[4..0]6
H_ADSTB#16
H_A20M#15
H_FERR#15
H_IGNNE#15
R360
R360
1 2
0R0402-PAD
0R0402-PAD
H_INTR15
H_NMI15
H_SMI#15
H_STPCLK_R
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
AA3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5
P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
Y3
U3
R2
P3
T2
P1
T1
C2
D3
A3
C6
D1
D4
B4
A3#
A4#
ADDR GROUP 0
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB#0
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
ADDR GROUP 1
A31#
ADSTB#1
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
connector
connector
62.10053.061
62.10053.061
THERMTRIP#
HCLK THERM XTP/ITP SIGNALS CONTROL
Morar_SA:62.10053.061
Morar_SB:62.10053.061
2 2
1 1
A
Morar_SB:62.10055.011(2nd)
B
N2
ADS#
L1
BNR#
J3
BPRI#
L4
DEFER#
H2
DRDY#
M2
DBSY#
N4
BR0#
A4
IERR#
B5
INIT#
J2
LOCK#
B11
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
ITP_CLK1
ITP_CLK0
BCLK1
BCLK0
CPU_PROCHOT#
XDP_TDI
XDP_TMS
XDP_TDO
H_CPURST#
XDP_DBRESET#
XDP_TCK
XDP_TRST#
H_RS#0
H1
H_RS#1
K1
H_RS#2
L2
M3
K3
K4
XDP_BPM#0
C8
XDP_BPM#1
B8
XDP_BPM#2
A9
XDP_BPM#3
C9
XDP_BPM#4
A10
XDP_BPM#5
B10
XDP_TCK
A13
XDP_TDI
C12
XDP_TDO
A12
XDP_TMS
C11
XDP_TRST#
B13
XDP_DBRESET#
A7
CPU_PROCHOT#
B17
B18
A18
C17
A15
A16
B14
B15
R376 56R2FR376 56R2F
1 2
R370 150R2FR370 150R2F
1 2
R369 39D2R3FR369 39D2R3F
1 2
R371 54D9R2FR371 54D9R2F
1 2
R366 54D9R2FR366 54D9R2F
1 2
R365 150R2FR365 150R2F
1 2
R372 27D4R2FR372 27D4R2F
1 2
R373 680R3FR373 680R3F
1 2
All place within 2" to CPU
B
TP6
TP6
TPAD28
TPAD28
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BREQ#0 6
H_INIT# 15
H_LOCK# 6
H_CPURST# 6
H_TRDY# 6
H_HIT# 6
H_HITM# 6
H_THERMDA 19
H_THERMDC 19
PM_THRMTRIP-A# 7
R377 0R0402-PADR377 0R0402-PAD
1 2
CLK_XDP_CPU# 3
CLK_XDP_CPU 3
CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3
H_IERR#
1D05V_S0
3D3V_S0
1D05V_S0
H_RS#[2..0] 6
TP10TPAD28 TP10TPAD28
TP9TPAD28 TP9TPAD28
TP11TPAD28 TP11TPAD28
TP12TPAD28 TP12TPAD28
TP14TPAD28 TP14TPAD28
TP13TPAD28 TP13TPAD28
TP72TPAD28 TP72TPAD28
TP70TPAD28 TP70TPAD28
TP71TPAD28 TP71TPAD28
TP69TPAD28 TP69TPAD28
TP73TPAD28 TP73TPAD28
TP68TPAD28 TP68TPAD28
TP74TPAD28 TP74TPAD28
12
R362
R362
56R2J
56R2J
Place testpoint on
H_IERR# with a GND
0.1" away
PM_THRMTRIP-I# 15,19
PM_THRMTRIP#
should connect to
ICH6 and Alviso
without T-ing
( No stub)
CPU_SEL03,7
C
TP15 TPAD28TP15 TPAD28
R320
R320
1KR2F
1KR2F
R315
R315
2KR2F
2KR2F
C
R374 0R3-UR374 0R3-U
1D05V_S0
12
12
To V-CORE SWITCH
1 2
TP8 TPAD28TP8 TPAD28
TP67 TPAD28TP67 TPAD28
TP5 TPAD28TP5 TPAD28
TP16 TPAD28TP16 TPAD28
Layout Note:
0.5" max length.
BSEL[1:0] Freq.(MHz)
(A Stepping)
L L 100
L H 133
BSEL[1:0] Freq.(MHz)
(B Stepping)
L H 100
L L 133
TP7
TP7
TPAD28
TPAD28
GTLREF0
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
C23
C22
D25
H23
G25
M26
H24
G24
M23
N24
M25
H26
N25
K25
K24
C16
C14
AF7
AC1
E26
AD26
L23
F25
J23
J25
L26
L24
J26
E1
C3
D
U35B
U35B
BGA479-SKT-2-U
BGA479-SKT-2-U
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
DATA GRP 0DATA GRP 1
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
PSI#
BSEL0
BSEL1
MISC
RSVD2
RSVD3
RSVD4
RSVD5
GTLREF0
connector
connector
62.10053.061
62.10053.061
D
Y26
D32#
AA24
D33#
T25
D34#
U23
D35#
V23
D36#
R24
D37#
R26
D38#
R23
D39#
AA23
D40#
U26
D41#
V24
D42#
U25
D43#
V26
D44#
DATA GRP 2
Y23
D45#
AA26
D46#
Y25
D47#
W25
DSTBN2#
W24
DSTBP2#
T24
DINV2#
AB25
D48#
AC23
D49#
AB24
D50#
AC20
D51#
AC22
D52#
AC25
D53#
AD23
D54#
AE22
D55#
AF23
D56#
AD24
D57#
AF20
D58#
AE21
D59#
AD21
D60#
DATA GRP 3
AF25
D61#
AF22
D62#
AF26
D63#
AE24
DSTBN3#
AE25
DSTBP3#
AD20
DINV3#
P25
COMP0
P26
COMP1
AB2
COMP2
AB1
COMP3
G1
DPRSTP#
B7
DPSLP#
C19
DPWR#
SLP#
TEST1
TEST2
E4
A6
C5
F23
PWRGOOD
E
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
COMP0
R35 27D4R2FR35 27D4R2F
COMP1
R36 54D9R2FR36 54D9R2F
COMP2
R24 27D4R2FR24 27D4R2F
COMP3
R27 54D9R2FR27 54D9R2F
TEST1
TEST2
12
R43
R43
1KR2
1KR2
DY
DY
12
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
1 2
1 2
1 2
1 2
H_DPRSLP# 15
H_DPSLP# 15
H_DPWR# 6
H_CPUSLP# 6,15
R359
R359
1KR2
1KR2
DY
DY
H_D#[63..0] 6
H_DINV#[3..0] 6
H_DSTBN#[3..0] 6
H_DSTBP#[3..0] 6
1D05V_S0
12
R41
R41
200R2F
200R2F
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU (1 of 2)
CPU (1 of 2)
CPU (1 of 2)
MORAR SB
MORAR SB
MORAR SB
440Saturday, May 28, 2005
440Saturday, May 28, 2005
440Saturday, May 28, 2005
E
H_PWRGD 15,19
of
of
of
A
VCC_CORE_S0
U35C
U35C
BGA479-SKT-2-U
BGA479-SKT-2-U
AA11
VCC0
AA13
VCC1
AA15
VCC2
AA17
VCC3
AA19
VCC4
AA21
VCC5
AA5
VCC6
4 4
3 3
2 2
1 1
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
D6
D8
E17
E19
E21
E5
E7
E9
F18
F20
F22
F6
F8
G21
connector
connector
62.10053.061
62.10053.061
Layout Note:
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCCA0
VCCA1
VCCA2
VCCA3
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCQ0
VCCQ1
VID0
VID1
VID2
VID3
VID4
VID5
VCCSENSE
VSSSENSE
VCCSENSE and VSSSENSE lines
should be of equal length.
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
A
G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6
F26
B1
N1
AC26
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21
P23
W4
E2
F2
F3
G3
G4
H4
AE7
AF6
VCC_CORE_S0
CPU_D10
TP_VCCSENSE
TP_VSSSENSE
1D5V_VCCA_S0
R33
R33
1 2
0R0402-PAD
0R0402-PAD
H_VID0 34
H_VID1 34
H_VID2 34
H_VID3 34
H_VID4 34
H_VID5 34
12
R314
R314
R313
R313
54D9R2F
54D9R2F
DY
DY
54D9R2F
54D9R2F
DY
DY
C338
C338
12
12
12
C339
C339
1D05V_S0
SCD01U16V2KX
SCD01U16V2KX
1D05V_S0
12
VCC_CORE_S0
12
VCC_CORE_S0
12
VCC_CORE_S0
12
B
SC10U10V5ZY-L
SC10U10V5ZY-L
12
SCD1U16V
SCD1U16V
C44
C44
12
C320
C320
DY
DY
SC10U6D3V5MX
SC10U6D3V5MX
12
SCD1U16V
SCD1U16V
C36
C36
12
C49
C49
DY
DY
SC10U6D3V5MX
SC10U6D3V5MX
B
C
12
12K7R3F
12K7R3F
R334
R334
DY
DY
Place these
and dummy
12K7R3F for
1D8V_VCCA_S0
PM_SLP_S3#_ICH 16
12
R352
R352
DUMMY-R2
DUMMY-R2
I max = 120 mA
U36
U36
12
BC9
BC9
SC1U10V3ZY
SC1U10V3ZY
DY
DY
1 2
12
SCD1U16V
SCD1U16V
C54
C54
R332
R332
0R3-U
0R3-U
12
1
2
3
C43
C43
SHDN#
GND
IN
G913C-U
G913C-U
12
SCD1U16V
SCD1U16V
DY
DY
SCD1U16V
SCD1U16V
C35
C35
3D3V_S0
1D5V_S0 1D5V_VCCA_S0
12
12
SCD1U16V
SCD1U16V
C46
C46
C51
C51
12
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
C28
C28
C27
C27
1D5V_VCCA_S0
12
12
DY
DY
5
SET
4
OUT
12
SCD1U16V
SCD1U16V
C34
C34
12
BC8
BC8
SC1U10V3ZY
SC1U10V3ZY
DY
DY
12
12
SCD1U16V
SCD1U16V
TC8
TC8
C15
C15
DY
DY
ST100U6D3VM-U
ST100U6D3VM-U
R333
R333
BC7
BC7
22KR3F
22KR3F
DY
DY
SC22P50V2JN-1
SC22P50V2JN-1
12
DY
DY
R335
R335
49K9R2F
49K9R2F
Morar_SB
12
12
DY
DY
SC10U6D3V5MX
SC10U6D3V5MX
SCD1U16V
SCD1U16V
12
12
12
12
12
12
12
DY
DY
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
12
C19
C19
C16
C16
DY
DY
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
12
12
C26
C26
DY
DY
SC10U6D3V5MX
SC10U6D3V5MX
12
C14
C14
C325
C325
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
C11
C11
C18
C18
C25
C25
C23
C23
C22
C22
C20
C333
C333
DY
DY
SC10U6D3V5MX
SC10U6D3V5MX
12
12
SCD1U16V
SCD1U16V
C38
C38
DY
DY
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
12
12
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
C50
C50
C55
C55
DY
DY
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
12
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
C33
C33
C45
C45
C
C20
SC10U6D3V5MX
SC10U6D3V5MX
12
12
C40
C40
C17
C17
SC10U6D3V5MX
SC10U6D3V5MX
12
12
C324
C324
C321
C321
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
12
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
C52
C52
C53
C53
12
C48
C48
C42
C42
DY
DY
DY
DY
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
C332
C332
C336
C336
SC10U6D3V5MX
SC10U6D3V5MX
12
12
SCD1U16V
SCD1U16V
C37
C37
C47
C47
12
C39
C39
SC10U6D3V5MX
SC10U6D3V5MX
D
U35D BGA479-SKT-2-U
U35D BGA479-SKT-2-U
A2
VSS0
A5
VSS1
A8
VSS2
A11
VSS3
A14
VSS4
A17
VSS5
A20
VSS6
A23
VSS7
A26
VSS8
AA1
VSS9
AA4
VSS10
AA6
VSS11
AA8
VSS12
AA10
VSS13
AA12
VSS14
AA14
VSS15
AA16
VSS16
AA18
VSS17
AA20
VSS18
AA22
VSS19
AA25
VSS20
AB3
VSS21
AB5
VSS22
AB7
VSS23
AB9
VSS24
AB11
VSS25
AB13
VSS26
AB15
VSS27
AB17
VSS28
AB19
VSS29
AB21
VSS30
AB23
VSS31
AB26
VSS32
AC2
VSS33
AC5
VSS34
AC8
VSS35
AC10
VSS36
AC12
VSS37
AC14
VSS38
AC16
VSS39
AC18
VSS40
AC21
VSS41
AC24
VSS42
AD1
VSS43
AD4
VSS44
AD7
VSS45
AD9
VSS46
AD11
VSS47
AD13
VSS48
AD15
VSS49
AD17
VSS50
AD19
VSS51
AD22
VSS52
AD25
VSS53
AE3
VSS54
AE6
VSS55
AE8
VSS56
AE10
VSS57
AE12
VSS58
AE14
VSS59
AE16
VSS60
AE18
VSS61
AE20
VSS62
AE23
VSS63
AE26
VSS64
AF2
VSS65
AF5
VSS66
AF9
VSS67
AF11
VSS68
AF13
VSS69
AF15
VSS70
AF17
VSS71
AF19
VSS72
AF21
VSS73
AF24
VSS74
B3
VSS75
B6
VSS76
B9
VSS77
B12
VSS78
B16
VSS79
B19
VSS80
B22
VSS81
B25
VSS82
C1
VSS83
C4
VSS84
C7
VSS85
C10
VSS86
C13
VSS87
C15
VSS88
C18
VSS89
C21
VSS90
C24
VSS91
D2
VSS92
D5
VSS93
D7
VSS94
D9
VSS95
D11
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
D
Date: Sheet
VSS96
CPU (2 of 2)
CPU (2 of 2)
CPU (2 of 2)
MORAR SB
MORAR SB
MORAR SB
E
D13
VSS97
D15
VSS98
D17
VSS99
D19
VSS100
D21
VSS101
D23
VSS102
D26
VSS103
E3
VSS104
E6
VSS105
E8
VSS106
E10
VSS107
E12
VSS108
E14
VSS109
E16
VSS110
E18
VSS111
E20
VSS112
E22
VSS113
E25
VSS114
F1
VSS115
F4
VSS116
F5
VSS117
F7
VSS118
F9
VSS119
F11
VSS120
F13
VSS121
F15
VSS122
F17
VSS123
F19
VSS124
F21
VSS125
F24
VSS126
G2
VSS127
G6
VSS128
G22
VSS129
G23
VSS130
G26
VSS131
H3
VSS132
H5
VSS133
H21
VSS134
H25
VSS135
J1
VSS136
J4
VSS137
J6
VSS138
J22
VSS139
J24
VSS140
K2
VSS141
K5
VSS142
K21
VSS143
K23
VSS144
K26
VSS145
L3
VSS146
L6
VSS147
L22
VSS148
L25
VSS149
M1
VSS150
M4
VSS151
M5
VSS152
M21
VSS153
M24
VSS154
N3
VSS155
N6
VSS156
N22
VSS157
N23
VSS158
N26
VSS159
P2
VSS160
P5
VSS161
P21
VSS162
P24
VSS163
R1
VSS164
R4
VSS165
R6
VSS166
R22
VSS167
R25
VSS168
T3
VSS169
T5
VSS170
T21
VSS171
T23
VSS172
T26
VSS173
U2
VSS174
U6
VSS175
U22
VSS176
U24
VSS177
V1
VSS178
V4
VSS179
V5
VSS180
V21
VSS181
V25
VSS182
W3
VSS183
W6
VSS184
W22
VSS185
W23
VSS186
W26
VSS187
Y2
VSS188
Y5
VSS189
Y21
VSS190
Y24
VSS191
connector
connector
62.10053.061
62.10053.061
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
540Thursday, May 26, 2005
540Thursday, May 26, 2005
540Thursday, May 26, 2005
E
of
A
H_XRCOMP
12
R356
R356
24D9R2F
24D9R2F
4 4
1D05V_S0
R355
R355
54D9R2F
54D9R2F
1 2
H_XSCOMP
1D05V_S0
12
R358
R358
221R2F-L
221R2F-L
H_XSWING
3 3
2 2
12
12
1D05V_S0
1 2
1D05V_S0
12
12
R357
R357
100R2F
100R2F
H_YRCOMP
R368
R368
24D9R2F
24D9R2F
R363
R363
54D9R2F
54D9R2F
H_YSCOMP
R364
R364
221R2F-L
221R2F-L
H_YSWING
R367
R367
100R2F
100R2F
1 2
1 2
C343
C343
SCD1U16V
SCD1U16V
C345
C345
SCD1U16V
SCD1U16V
B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
C
U45A
U45A
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
C1
C2
D1
T1
L1
P1
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
71.0GMCH.08U
71.0GMCH.08U
HCPURST#
HOST
HOST
HCPUSLP#
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB#0
HADSTB#1
HVREF
HBNR#
HBPRI#
HBREQ0#
HCLKINN
HCLKINP
HDBSY#
HDEFER#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS0#
HRS1#
HRS2#
HTRDY#
G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
F8
B9
E13
J11
A5
D5
E7
H10
AB1
AB2
C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_VREF
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
TP_H_EDRDY#
TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#_1
D
H_A#[31..3] 4H_D#[63..0]4
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_CPURST# 4
CLK_MCH_BCLK# 3
CLK_MCH_BCLK 3
H_DBSY# 4
H_DEFER# 4
H_DPWR# 4
H_DRDY# 4
TP19TPAD28 TP19TPAD28
H_HIT# 4
H_HITM# 4
H_LOCK# 4
TP75TPAD28 TP75TPAD28
H_TRDY# 4
C105
C105
SCD1U16V
SCD1U16V
1 2
H_DINV#[3..0] 4
H_DSTBN#[3..0] 4
H_DSTBP#[3..0] 4
H_REQ#[4..0] 4
H_RS#[2..0] 4
R361 0R2-0R361 0R2-0
1 2
DUMMY FOR DOTHAN A STEPPING
1D05V_S0
12
12
R73
R73
100R2F
100R2F
R72
R72
200R2F
200R2F
E
H_CPUSLP# 4,15
1 1
A
Place them near to the chip
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
GMCH (1 of 5)
GMCH (1 of 5)
GMCH (1 of 5)
MORAR SB
MORAR SB
MORAR SB
640Friday, June 24, 2005
640Friday, June 24, 2005
640Friday, June 24, 2005
E
of
A
U45B
U45B
DMI_TXN0
DMI_TXN016
4 4
3 3
Layout Note:
Route as short
as possible
12
R74
R74
R95
R95
40D2R2F
40D2R2F
40D2R2F
40D2R2F
DDR_VREF_S3
2 2
1 1
DMI_TXN116
DMI_TXN216
DMI_TXN316
DMI_TXP016
DMI_TXP116
DMI_TXP216
DMI_TXP316
DMI_RXN016
DMI_RXN116
DMI_RXN216
DMI_RXN316
DMI_RXP016
DMI_RXP116
DMI_RXP216
DMI_RXP316
M_CLK_DDR011
M_CLK_DDR111
M_CLK_DDR311
M_CLK_DDR411
M_CLK_DDR#011
M_CLK_DDR#111
M_CLK_DDR#311
M_CLK_DDR#411
M_CKE011,12
M_CKE111,12
M_CKE211,12
M_CKE311,12
M_CS#011,12
M_CS#111,12
M_CS#211,12
M_CS#311,12
M_OCDCOMP0
M_OCDCOMP1
12
M_ODT011,12
M_ODT111,12
M_ODT211,12
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
12
C433
C433
M_ODT311,12
12
SCD1U16V
SCD1U16V
BC3
BC3
12
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
C349
C349
12
SCD1U16V
SCD1U16V
BC6
BC6
M_RCOMPN
M_RCOMPP
SMXSLEW
SMYSLEW
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
2D5V_S0
1D8V_S3
12
12
AA31
AB35
AC31
AD35
Y31
AA35
AB31
AC35
AA33
AB37
AC33
AD37
Y33
AA37
AB33
AC37
AM33
AL1
AE11
AJ34
AF6
AC10
AN33
AK1
AE10
AJ33
AF5
AD10
AP21
AM21
AH21
AK21
AN16
AM14
AH15
AG16
AF22
AF16
AP14
AL15
AM11
AN10
AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10
R103
R103
1 2
10KR2
10KR2
R102
R102
1 2
10KR2
10KR2
R75
R75
80D6R2F
80D6R2F
R76
R76
80D6R2F
80D6R2F
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
71.0GMCH.08U
71.0GMCH.08U
PM_EXTTS#0
PM_EXTTS#1
M_RCOMPN
M_RCOMPP
DMI
DMI
DDR MUXING
DDR MUXING
CFG/RSVD
CFG/RSVD
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PM
PM
PWROK
RSTIN#
DREF_CLKN
DREF_CLKP
DREF_SSCLKN
CLK
CLK
DREF_SSCLKP
NC
NC
B
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
1D05V_S0
R70
R70
10KR2
10KR2
CFG0
G16
H13
G14
CFG3
F16
CFG4
F15
CFG5
G15
CFG6
E16
CFG7
D17
CFG8
J16
CFG9
D15
CFG10
E15
CFG11
D14
CFG12
E14
CFG13
H12
CFG14
C14
CFG15
H15
CFG16
J15
CFG17
H14
CFG18
G22
CFG19
G23
CFG20
D23
G25
G24
J17
A31
A30
D26
D25
VGATE_PWRGD
J23
PM_EXTTS#0
J21
PM_EXTTS#1
H22
F5
AD30
AE29
1 2
R428 100R2R428 100R2
A24
A23
C37
D37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
12
DY
DY
R107
R107
10KR2
10KR2
CFG[2:0] Freq.(MHz)
101 400
001 533
CPU_SEL1 3
CPU_SEL0 3,4
GMCH_VSYNC14
12
PM_BMBUSY# 16
PM_THRMTRIP-A# 4
VGATE_PWRGD 16,32
DREFCLK# 3
DREFCLK 3
DREFSSCLK# 3
DREFSSCLK 3
2D5V_S0
R106 DUMMY-R2R106 DUMMY-R2
R101 DUMMY-R2R101 DUMMY-R2
R105 DUMMY-R2R105 DUMMY-R2
R65 DUMMY-R2R65 DUMMY-R2
R83 DUMMY-R2R83 DUMMY-R2
R66 DUMMY-R2R66 DUMMY-R2
R86 2K2R2R86 2K2R2
R82 DUMMY-R2R82 DUMMY-R2
R85 DUMMY-R2R85 DUMMY-R2
R69 DUMMY-R2R69 DUMMY-R2
R84 DUMMY-R2R84 DUMMY-R2
R64 DUMMY-R2R64 DUMMY-R2
R63 DUMMY-R2R63 DUMMY-R2
R51 DUMMY-R2R51 DUMMY-R2
R61 DUMMY-R2R61 DUMMY-R2
R68 DUMMY-R2R68 DUMMY-R2
R67 DUMMY-R2R67 DUMMY-R2
R62 DUMMY-R2R62 DUMMY-R2
GMCH_HSYNC14
PLT_RST1# 16,18,29
When High 1K Ohm
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
When Low choice
lower than 3.5K
Ohm
C
Alviso will provide SDVO_CTRLCLK
and CTRLDATA pulldowns on-die
Morar_SB
GMCH_DDCCLK14
GMCH_DDCDATA14
GMCH_BLUE14
R411150R2F R411150R2F
1 2
GMCH_GREEN14
R408150R2F R408150R2F
1 2
GMCH_RED14
R407150R2F R407150R2F
1 2
CFG18
CFG19
CFG20
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
TP23 TPAD28TP23 TPAD28
TP22 TPAD28TP22 TPAD28
CLK_MCH_3GPLL#3
CLK_MCH_3GPLL3
12
R410
R410
0R2-0
0R2-0
0R2-0
0R2-0
1 2
R81 39R2JR81 39R2J
1 2
R80 39R2JR80 39R2J
1 2
R94 255R2FR94 255R2F
BL_ON29
CLK_DDC_EDID13
DAT_DDC_EDID13
GMCH_LCDVDD_ON13
TP25 TPAD28TP25 TPAD28
TP26 TPAD28TP26 TPAD28
TP27 TPAD28TP27 TPAD28
GMCH_TXACLK-13
GMCH_TXACLK+13
GMCH_TXBCLK-13
GMCH_TXBCLK+13
GMCH_TXAOUT0-13
GMCH_TXAOUT1-13
GMCH_TXAOUT2-13
GMCH_TXAOUT0+13
GMCH_TXAOUT1+13
GMCH_TXAOUT2+13
GMCH_TXBOUT0-13
GMCH_TXBOUT1-13
GMCH_TXBOUT2-13
GMCH_TXBOUT0+13
GMCH_TXBOUT1+13
GMCH_TXBOUT2+13
LCTLA_CLK
LCTLB_DATA
CLK_DDC_EDID
DAT_DDC_EDID
BL_ON
LBKLT_CRTL
LIBG
R412
R412
12
0R2-0
0R2-0
GMCH_TV_COMP
GMCH_TV_LUMA
GMCH_TV_CRMA
12
R409
R409
R104 2K2R2
R104 2K2R2
1 2
R90 2K2R2
R90 2K2R2
1 2
R87 2K2R2R87 2K2R2
1 2
R88 2K2R2R88 2K2R2
1 2
R98 100KR2R98 100KR2
1 2
R97 100KR2R97 100KR2
1 2
R427 1K5R2FR427 1K5R2F
1 2
SDVOC_CTRLDATA
SDVOC_CTRLCLK
1 2
R71
R71
0R2-0
0R2-0
VSYNC
HSYNC
CRTIREF
R92
R92
12
0R2-0
0R2-0
LBKLT_CRTL
LCTLA_CLK
LCTLB_DATA
CLK_DDC_EDID
DAT_DDC_EDID
LIBG
L_LVBG
L_VREFH
L_VREFL
DY
DY
DY
DY
AB29
AC29
2D5V_S0
H24
SDVOCTRL_DATA
H25
SDVOCTRL_CLK
GCLKN
GCLKP
A15
TVDAC_A
C16
TVDAC_B
A17
TVDAC_C
J18
TV_REFSET
B15
TV_IRTNA
B16
TV_IRTNB
B17
TV_IRTNC
E24
DDCCLK
E23
DDCDATA
E21
BLUE
D21
BLUE#
C20
GREEN
B20
GREEN#
A19
RED
B19
RED#
H21
VSYNC
G21
HSYNC
J20
REFSET
E25
LBKLT_CRTL
F25
LBKLT_EN
C23
LCTLA_CLK
C22
LCTLB_DATA
F23
LDDC_CLK
F22
LDDC_DATA
F26
LVDD_EN
C33
LIBG
C31
LVBG
F28
LVREFH
F27
LVREFL
B30
LACLKN
B29
LACLKP
C25
LBCLKN
C24
LBCLKP
B34
LADATAN0
B33
LADATAN1
B32
LADATAN2
A34
LADATAP0
A33
LADATAP1
B31
LADATAP2
C29
LBDATAN0
D28
LBDATAN1
C27
LBDATAN2
C28
LBDATAP0
D27
LBDATAP1
C26
LBDATAP2
U45G
U45G
71.0GMCH.08U
71.0GMCH.08U
D
EXP_COMPI
EXP_ICOMPO
EXP_RXN0
MISCTVVGALVDS
MISCTVVGALVDS
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
E
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
A
B
C
D
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
GMCH (2 of 5)
GMCH (2 of 5)
GMCH (2 of 5)
MORAR SB
MORAR SB
MORAR SB
E
of
of
of
740Saturday, May 28, 2005
740Saturday, May 28, 2005
740Saturday, May 28, 2005
A
4 4
U45C
M_A_DQ[63..0]11 M_B_DQ[63..0]11
3 3
2 2
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
U45C
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_RCVENIN#
SA_RCVENOUT#
SA_BS0#
SA_BS1#
SA_BS2#
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_WE#
B
AK15
AK16
AL21
M_A_DM0
AJ37
M_A_DM1
AP35
M_A_DM2
AL29
M_A_DM3
AP24
M_A_DM4
AP9
M_A_DM5
AP4
M_A_DM6
AJ2
M_A_DM7
AD3
M_A_DQS0
AK36
M_A_DQS1
AP33
M_A_DQS2
AN29
M_A_DQS3
AP23
M_A_DQS4
AM8
M_A_DQS5
AM4
M_A_DQS6
AJ1
M_A_DQS7
AE5
M_A_DQS#0
AK35
M_A_DQS#1
AP34
M_A_DQS#2
AN30
M_A_DQS#3
AN23
M_A_DQS#4
AN8
M_A_DQS#5
AM5
M_A_DQS#6
AH1
M_A_DQS#7
AE4
M_A_A0
AL17
M_A_A1
AP17
M_A_A2
AP18
M_A_A3
AM17
M_A_A4
AN18
M_A_A5
AM18
M_A_A6
AL19
M_A_A7
AP20
M_A_A8
AM19
M_A_A9
AL20
M_A_A10
AM16
M_A_A11
AN20
M_A_A12
AM20
M_A_A13
AM15
AN15
AP16
SA_RCVENIN#
AF29
SA_RCVENOUT#
AF28
AP15
Place Test PAD Near to Chip
as could as possible
C
U45D
U45D
M_A_BS#0 11,12
M_A_BS#1 11,12
M_A_BS#2 11,12
M_A_DM[7..0] 11
M_A_DQS[7..0] 11
M_A_DQS#[7..0] 11
M_A_A[13..0] 11,12
M_A_CAS# 11,12
M_A_RAS# 11,12
TP24 TPAD28TP24 TPAD28
TP28 TPAD28TP28 TPAD28 TP20 TPAD28TP20 TPAD28
M_A_WE# 11,12
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
D
AJ15
SB_BS0#
AG17
SB_BS1#
AG21
SB_BS2#
AF32
SB_DM0
AK34
SB_DM1
AK27
SB_DM2
AK24
SB_DM3
AJ10
SB_DM4
AK5
SB_DM5
AE7
SB_DM6
AB7
SB_DM7
AF34
SB_DQS0
AK32
SB_DQS1
AJ28
SB_DQS2
AK23
SB_DQS3
AM10
SB_DQS4
AH6
SB_DQS5
AF8
SB_DQS6
AB4
SB_DQS7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_WE#
AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5
AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15
AH14
AK14
AF15
AF14
AH16
Place Test PAD Near to Chip
ascould as possible
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_RCVENIN#
SB_RCVENOUT#
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
SB_RCVENIN#
SB_RCVENOUT#
M_B_BS#0 11,12
M_B_BS#1 11,12
M_B_BS#2 11,12
M_B_DM[7..0] 11
M_B_DQS[7..0] 11
M_B_DQS#[7..0] 11
M_B_A[13..0] 11,12
M_B_CAS# 11,12
M_B_RAS# 11,12
TP21 TPAD28TP21 TPAD28
M_B_WE# 11,12
E
71.0GMCH.08U
71.0GMCH.08U
1 1
A
B
C
71.0GMCH.08U
71.0GMCH.08U
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
D
Date: Sheet of
GMCH (3 of 5)
GMCH (3 of 5)
GMCH (3 of 5)
MORAR SB
MORAR SB
MORAR SB
840Friday, June 24, 2005
840Friday, June 24, 2005
840Friday, June 24, 2005
E
of
A
R423
R423
1 2
DY
DY
1KR2
1KR2
R58
R58
1 2
DY
DY
0R3-U
0R3-U
3D3V_S0
4 4
3 3
R60
R60
1 2
DY
DY
0R3-U
0R3-U
R57
R57
1 2
DY
DY
0R3-U
0R3-U
R59
R59
1 2
DY
DY
10R3
10R3
When GML replace to PM
3D3V_S0
12
C85
C85
SC10U10V5ZY-L
SC10U10V5ZY-L
DY
DY
Route ASSATVBG gnd from GMCH to
decoupling cap groung lead and
then connect to the gnd plane
12
C104
C104
0R2-0
0R2-0
12
C118
C118
0R2-0
0R2-0
12
C120
C120
0R2-0
0R2-0
12
C103
C103
0R2-0
0R2-0
D39
D39
DY
DY
3D3V_TVDACA_S0
3D3V_TVDACB_S0
3D3V_TVDACC_S0
1D5V_S0
21
SSM5818SL
SSM5818SL
3D3V_ATVBG_S0
12
C122
C122
SCD022U16V2KX
SCD022U16V2KX
DY
DY
1D5V_DLVDS_S0 1D8V_S3
H17
B26
VSSA_TVBG
D19
B25
VCCD_LVDS0
VCCD_TVDAC
VCCDQ_TVDAC
F17
E17
D18
C18
F18
E18
G18
H18
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVBG
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
1D5V_TVDAC_S0
1D5V_QTVDAC_S0
2D5V_ALVDS_S0
A25
A35
VCCA_LVDS
VCCD_LVDS1
VCCD_LVDS2
B
1D5V_S0
12
C119
C119
0R2-0
0R2-0
12
C124
C124
0R2-0
0R2-0
2D5V_TVDAC_S0
C404
C404
SCD1U16V
SCD1U16V
12
C415
C415
SCD1U16V
SCD1U16V
Note: All VCCSM
pins shorted
12
internally
C432
C432
SCD1U16V
SCD1U16V
V1.8_DDR_CAP1
1 2
C416
C416
SCD1U16V
SCD1U16V
V1.8_DDR_CAP2
V1.8_DDR_CAP5
AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
B22
B21
A21
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
AL26
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
1 2
R100 0R3-U
R100 0R3-U
DY
DY
R99
R99
DY
DY
0R3-U
0R3-U
1 2
Morar_SB
R406
R406
1 2
12
AK26
AJ26
AH26
VCCSM10
VCCSM11
12
0R3-U
0R3-U
C390
C390
SC10U10V5ZY-L
SC10U10V5ZY-L
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
POWER
POWER
C
1D5V_S0
R425
R425
1 2
0R3-U
0R3-U
C413
C413
SCD1U16V
SCD1U16V
2D5V_S0 2D5V_ALVDS_S0
R426
R426
1 2
0R3-U
0R3-U
C426
C426
SCD1U16V
SCD1U16V
2D5V_S0
AF25
AE25
AE24
VCCSM24
VCCSM25
VCCSM26
2D5V_S0 2D5V_TXLVDS_S0
R424
R424
1 2
0R3-U
0R3-U
SCD1U16V
SCD1U16V
12
AE23
AE22
VCCSM27
VCCSM28
AE21
VCCSM29
C405
C405
SC10U10V5ZY-L
SC10U10V5ZY-L
AE20
AE19
VCCSM30
12
C406
C406
SC10U10V5ZY-L
SC10U10V5ZY-L
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
C414
C414
12
AL13
AK13
VCCSM40
C391
C391
AJ13
VCCSM41
12
12
12
SC10U10V5ZY-L
SC10U10V5ZY-L
AH13
AG13
VCCSM42
VCCSM43
VCCSM44
1D5V_DLVDS_S0
12
12
12
AF13
AE13
AP12
AN12
VCCSM45
VCCSM46
VCCSM47
VCCSM48
C412
C412
SC10U10V5ZY-L
SC10U10V5ZY-L
C427
C427
SCD01U16V2KX
SCD01U16V2KX
C411
C411
SC4D7U10V5ZY
SC4D7U10V5ZY
Note: All VCCSM
pins shorted
internally
SCD1U16V
SCD1U16V
AM12
AL12
AK12
AJ12
AH12
AG12
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
C375
C375
1 2
AF12
AE12
VCCSM55
D
1 2
12
12
C132
C132
SCD1U16V
SCD1U16V
12
12
C351
C351
SCD1U16V
SCD1U16V
12
C350
C350
SCD1U16V
SCD1U16V
2D5V_TXLVDS_S0
V1.8_DDR_CAP4
V1.8_DDR_CAP3
V1.8_DDR_CAP6
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1
B28
A28
A27
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
AE37
W37
U37
R37
AF20
AP19
AF19
AF18
VCCA_SM0
VCCA_SM1
VCCA_SM2
N37
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCCA_SM3
C431
C431
SC10U10V5ZY-L
SC10U10V5ZY-L
L37
VCC3G4
VCC3G5
12
J37
VCC3G6
C142
C142
Y29
VCCA_3GPLL0
C393
C393
ST100U6D3VM-U
ST100U6D3VM-U
12
C441
C441
SC10U10V5ZY-L
SC10U10V5ZY-L
1D5V_3GPLL_S0
12
C417
C417
SCD1U16V
SCD1U16V
Y27
Y28
G37
F37
VSSA_3GBG
VCCA_3GBG
VCCA_3GPLL2
VCCA_3GPLL1
E
R420
R420
2D5V_3GBG_S0 2D5V_S0
1D5V_S01D5V_DDRDLL_S0
0R3-U
0R3-U
R112
R112
1 2
12
SC10U10V5ZY-L
SC10U10V5ZY-L
0R3-U
0R3-U
C430
C430
SC10U10V5ZY-L
SC10U10V5ZY-L
R429
R429
1 2
0R3-U
0R3-U
R446
R446
1 2
12
0R3-U
0R3-U
C429
C429
SCD1U16V
SCD1U16V
U45E
U45E
71.0GMCH.08U
71.0GMCH.08U
Route ASSA3GBG gnd from GMCH to
decoupling cap groung lead and
then connect to the gnd plane
1D5V_S01D5V_PCIE_S0
1D5V_S0
VCC 1D05_S0 for low speed
graphic clock.1D5V_S0 for
high speed clock.default
12
use 1D05V_S0
1D05V_S0
12
C126
C126
SC4D7U6D3V3KX
SC4D7U6D3V3KX
C140
C140
SC4D7U6D3V3KX
SC4D7U6D3V3KX
12
12
C125
C125
C128
C128
SC4D7U6D3V3KX
SC4D7U6D3V3KX
A
SC4D7U6D3V3KX
SC4D7U6D3V3KX
2 2
1 1
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCCH_MPLL1
VCCH_MPLL0
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCC_SYNC
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51
J29
T29
R29
N29
12
12
SCD1U16V
SCD1U16V
C127
C127
C108
C108
M29
T28
K29
V28
U28
R28
12
SCD1U16V
SCD1U16V
C129
C129
1D5V_S0
J28
L28
P28
K28
N28
M28
12
SCD1U16V
SCD1U16V
R375
R375
0R5J-1
0R5J-1
T27
V27
H28
U27
R27
G28
SCD1U16V
SCD1U16V
C141
C141
1 2
1 2
12
1 2
1 2
B
P27
N27
M27
L18
L18
IND-D1UH
IND-D1UH
L19
L19
IND-D1UH
IND-D1UH
L10
L10
IND-D1UH
IND-D1UH
L11
L11
IND-D1UH
IND-D1UH
L27
J27
K27
K26
K25
H27
H26
12
C402
C402
SC10U10V5ZY-L
SC10U10V5ZY-L
12
C425
C425
SC10U10V5ZY-L
SC10U10V5ZY-L
12
C347
C347
SC10U10V5ZY-L
SC10U10V5ZY-L
12
C348
C348
SC10U10V5ZY-L
SC10U10V5ZY-L
J25
K24
T20
K23
K22
K21
U20
W20
12
12
12
12
K20
V19
K19
U19
1D5V_HMPLL_S0
1D5V_DPLLA_S0
C403
C403
SCD1U16V
SCD1U16V
1D5V_DPLLB_S0
C428
C428
SCD1U16V
SCD1U16V
1D5V_HPLL_S0
C86
C86
SCD1U16V
SCD1U16V
1D5V_MPLL_S0
C87
C87
SCD1U16V
SCD1U16V
W18
T18
V18
K18
K17
AC2
AC1
F19
B23
E19
C35
AA1
AA2
G19
C
J13
H20
K13
T11
K12
V11
U11
W11
Morar_SB
2D5V_CRTDAC_S0
C545
GMCH_VCC_SYNC
C545
SC4D7U6D3V3KX
SC4D7U6D3V3KX
DY
DY
R93
R93
1 2
0R2-0
0R2-0
Layout Notes: VSSA_CRTDAC
Route caps within 250mil
of Alviso. Route FB
within 3" of Alviso.
R11
P11
12
N11
M11
L11
T10
K11
V10
U10
W10
R91
R91
1 2
DY
DY
0R3-U
0R3-U
R89
R89
1 2
0R3-U
0R3-U
12
C121
C121
SCD1U16V
SCD1U16V
12
C123
C123
SCD1U16V
SCD1U16V
Route VSSA_CRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.
R10
P10
N10
2D5V_S0
J10
K10
M10
1D05V_S0
1 2
D
R422
R422
1KR2
1KR2
VCCP_GMCH_CAP1
12
C374
C374
SCD47U10V3ZY
SCD47U10V3ZY
1D05V_S0
D38
D38
21
SSM5818SL
SSM5818SL
Morar_SB
SC4D7U10V5ZY
SC4D7U10V5ZY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
C342
C342
1D05V_S0
C106
C106
12
SCD47U10V3ZY
SCD47U10V3ZY
C346
C346
12
G1
VCCP_GMCH_CAP3
VCCP_GMCH_CAP4
VCCP_GMCH_CAP2
12
12
C344
C344
SCD22U16V3ZY
SCD22U16V3ZY
SCD22U16V3ZY
GMCH (4 of 5)
GMCH (4 of 5)
GMCH (4 of 5)
SCD22U16V3ZY
C107
C107
12
C109
SCD1U16V
C109
SCD1U16V
940Saturday, May 28, 2005
940Saturday, May 28, 2005
940Saturday, May 28, 2005
of
of
E
of
12
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
MORAR SB
MORAR SB
MORAR SB
A
H29
G29
F29
E29
D29
A29
AC28
AB28
AA28
W28
E28
AN27
AL27
AJ27
AG27
AF27
AB27
AA27
W27
G27
E27
B27
J26
G26
E26
A26
AN24
U45F
U45F
4 4
71.0GMCH.08U
71.0GMCH.08U
AL24
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS259P2VSS258T2VSS257V2VSS256
VSS255
VSS254
VSS253
VSS252
VSS251A3VSS250C3VSS249
VSS248
VSS247
VSS246
AA3
AB3
AC3
VSS245C4VSS244H4VSS243L4VSS242P4VSS241U4VSS240Y4VSS239
AJ3
AF4
VSSALVDS
B36
VSS260L2VSS268J2VSS269G2VSS270D2VSS271
Y1
AL2
AE2
AD2
AH2
AN2
B
V31
U31
T31
R31
P31
N31
M31
L31
K31
J31
H31
G31
F31
E31
D31
AP30
AE30
AC30
AB30
AA30
Y30
C30
AM29
AJ29
AG29
AD29
AA29
W29
V29
U29
P29
L29
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS238
VSS237E5VSS236W5VSS235
VSS234
VSS233B6VSS232J6VSS231L6VSS230P6VSS229T6VSS228
AL5
AP5
AN4
AA6
VSS227
VSS226
VSS225
VSS224G7VSS223V7VSS222
VSS221
VSS220
VSS219
VSS218C8VSS217E8VSS216L8VSS215P8VSS214Y8VSS213
AJ6
AE6
AA7
AC6
AK7
AN7
AG7
VSS212A9VSS211H9VSS210K9VSS209T9VSS208V9VSS207
AL8
AA9
W31
AC9
C
C34
AL33
AF33
AD33
W33
V33
U33
T33
R33
P33
N33
M33
L33
K33
J33
H33
G33
F33
E33
D33
AN32
AJ32
AD32
AC32
AB32
AA32
Y32
C32
A32
AL31
AG31
AD31
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS
VSS
VSS196
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
J12
AE9
L10
F11
Y11
Y10
D10
AH9
AN9
H11
AA10
B12
AJ11
AL11
AF11
AA11
AN11
AG11
D12
J14
F14
A14
B14
K14
AG14
VSS175
K15
A16
C15
AJ14
D16
AL14
AN14
D
AF36
AE36
AD36
AC36
AB36
AA36
C36
AE35
Y35
W35
V35
U35
T35
R35
P35
N35
M35
L35
K35
J35
H35
G35
F35
E35
D35
B35
AN34
AH34
AD34
AC34
AB34
AA34
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
J19
H16
K16
AL16
C17
G17
A18
AJ17
AF17
AN17
T19
B18
U18
C19
H19
W19
AL18
F20
A20
D20
AN19
AG19
F21
E20
G20
V20
A22
C21
D22
AF21
AK20
AN21
E
AL36
AJ36
K37
H37
E37
AN36
VSS7
VSS8
VSS9
VSS10
VSS11
VSS141
VSS140
VSS139
VSS138
VSS137
J22
E22
H23
AL22
AF23
AH22
M37
VSS6
VSS136
B24
P37
VSS5
VSS135
D24
T37
VSS4
VSS134
F24
V37
VSS3
VSS133
J24
Y37
VSS2
VSS132
AG24
AG37
VSS1
VSS131
AJ24
VSS0
VSS130
1D8V_S3
12
C392
C392
3 3
U45H
U45H
71.0GMCH.08U
2 2
71.0GMCH.08U
SC10U10V5ZY-L
SC10U10V5ZY-L
AD13
AC13
AB13
AD12
AC12
AB12
VCCSM_NCTF27
VCCSM_NCTF28
VCCSM_NCTF29
VCCSM_NCTF30
VCCSM_NCTF31
12
C110
C110
SCD1U16V
SCD1U16V
AD17
AC17
AD16
AC16
AD15
AC15
AD14
AC14
VCCSM_NCTF19
VCCSM_NCTF20
VCCSM_NCTF21
VCCSM_NCTF22
VCCSM_NCTF23
VCCSM_NCTF24
VCCSM_NCTF25
VCCSM_NCTF26
1D05V_S0
Place these Hi-Freq decoupling caps near GMCH
VCCSM_NCTF2
VTT_NCTF8
AC26
M13
VCCSM_NCTF1
VTT_NCTF7
AD26
N13
VCCSM_NCTF0
VTT_NCTF6
12
C111
C111
DY
DY
SCD1U16V
SCD1U16V
L17
VCC_NCTF78
VTT_NCTF5
VTT_NCTF4
P13
R13
M17
T13
VCC_NCTF77
VTT_NCTF3
N17
U13
VCC_NCTF76
VTT_NCTF2
SCD1U16V
SCD1U16V
W17
V17
U17
T17
P17
VCC_NCTF71
VCC_NCTF72
VCC_NCTF73
VCC_NCTF74
VCC_NCTF75
VTT_NCTF1
VTT_NCTF0
V13
W13
C130
C130
12
SCD1U16V
SCD1U16V
AD19
AC19
AD18
AC18
VCCSM_NCTF15
VCCSM_NCTF16
VCCSM_NCTF17
VCCSM_NCTF18
12
C135
C135
SCD1U16V
SCD1U16V
AD21
AC21
AD20
AC20
AD22
AC22
VCCSM_NCTF9
VCCSM_NCTF10
VCCSM_NCTF11
VCCSM_NCTF12
VCCSM_NCTF13
VCCSM_NCTF14
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
L12
P12
N12
M12
VCCSM_NCTF8
VTT_NCTF14
AC23
R12
VCCSM_NCTF7
VTT_NCTF13
AD23
T12
VCCSM_NCTF6
VTT_NCTF12
AC24
U12
AD24
VCCSM_NCTF5
VTT_NCTF11
V12
SCD1U16V
SCD1U16V
VCCSM_NCTF4
VTT_NCTF10
AC25
W12
VCCSM_NCTF3
VTT_NCTF9
12
C134
C134
AD25
L13
12
C112
C112
L18
VCC_NCTF70
M18
VCC_NTTF69
N18
Y12
12
C133
C133
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
Y19
R19
P19
N19
M19
L19
Y18
R18
P18
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
L14
M14
N14
T14
P14
R14
Y13
AA12
AA13
12
C143
C143
L20
VCC_NCTF58
VSS_NCTF58
U14
M20
V14
N20
VCC_NCTF57
NCTF
NCTF
VSS_NCTF57
W14
12
C131
C131
SCD1U16V
SCD1U16V
1D05V_S0
P21
N21
M21
L21
Y20
R20
P20
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
L15
Y14
AA14
AB14
V21
U21
T21
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF47
VCC_NCTF48
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
T15
P15
N15
R15
U15
M15
R22
P22
N22
M22
L22
W21
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
L16
V15
Y15
W15
AA15
AB15
M23
L23
W22
V22
U22
T22
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
T16
P16
N16
R16
U16
M16
V23
U23
T23
R23
P23
N23
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
V16
Y16
R17
W16
AA16
AB16
R24
P24
N24
M24
L24
W23
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
Y17
AA17
AB17
AA18
AB18
AA19
M25
L25
W24
V24
U24
T24
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
Y21
R21
AB19
AA20
AB20
AA21
V25
U25
T25
R25
P25
N25
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
Y22
AB21
AA22
AB22
N26
M26
L26
W25
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
Y23
Y24
AA23
AB23
AA24
AB24
VCC_NCTF6
VSS_NCTF6
W26
V26
U26
T26
R26
P26
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0
Y25
Y26
AA25
AB25
AA26
AB26
1 1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
A
B
C
D
Date: Sheet of
GMCH (5 of 5)
GMCH (5 of 5)
GMCH (5 of 5)
MORAR
MORAR
MORAR
E
SB
SB
10 40Friday, June 24, 2005
10 40Friday, June 24, 2005
10 40Friday, June 24, 2005
of
of
SB
A
DM1
M_B_A[13..0]8,12
4 4
M_B_BS#28,12
M_B_BS#08,12
M_B_BS#18,12
M_B_DQ[63..0]8
3 3
2 2
M_B_DQS#[7..0]8
M_B_DQS[7..0]8
1 1
C138
C138
SC4D7U6D3V3KX
SC4D7U6D3V3KX
M_ODT37,12
12
DDR_VREF_S3
12
BC4
BC4
SCD1U16V
SCD1U16V
A
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
DM1
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
/DQS0
29
/DQS1
49
/DQS2
68
/DQS3
129
/DQS4
146
/DQS5
167
/DQS6
186
/DQS7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
ODT0
119
ODT1
1
VREF
2
VSS
202
GND
DDR2-200P-2
DDR2-200P-2
connector
connector
62.10017.741
62.10017.741
Morar_SA:62.10017.741
VDDSPD
NC#163/TEST
REVISED TYPE
Morar_SB:62.10017.691
/RAS
/WE
/CAS
/CS0
/CS1
CKE0
CKE1
CK0
/CK0
CK1
/CK1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
SA0
SA1
NC#50
NC#69
NC#83
NC#120
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
5.2mm
108
109
113
110
115
79
80
30
32
164
166
10
26
52
67
130
147
170
185
195
197
199
198
200
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
B
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
1 2
R32
R32
10KR2
10KR2
B
M_B_RAS# 8,12
M_B_WE# 8,12
M_B_CAS# 8,12
M_CS#2 7,12
M_CS#3 7,12
M_CKE2 7,12
M_CKE3 7,12
M_CLK_DDR3 7
M_CLK_DDR#3 7
M_CLK_DDR4 7
M_CLK_DDR#4 7
SMBD_ICH 3,18
SMBC_ICH 3,18
3D3V_S0
BC1
BC1
Morar_SB
1D8V_S3
Place near DM1
C56 SC10P50V2JN-1
C56 SC10P50V2JN-1
DY
DY
C136 SC10P50V2JN-1
C136 SC10P50V2JN-1
DY
DY
M_B_DM[7..0] 8
12
12
DY
DY
SCD1U16V
SCD1U16V
M_CLK_DDR4
12
M_CLK_DDR#4
M_CLK_DDR3
12
M_CLK_DDR#3
C
DM2
M_A_A[13..0]8,12
M_A_BS#28,12
M_A_BS#08,12
M_A_BS#18,12
M_A_DQ[63..0]8
3D3V_S0
C31
C31
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
M_A_DQS[7..0]8
M_A_DQS#[7..0]8
M_ODT07,12
C137
C137
M_ODT17,12M_ODT27,12
12
DDR_VREF_S3
SC4D7U6D3V3KX
SC4D7U6D3V3KX
12
BC5
BC5
SCD1U16V
SCD1U16V
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
DM2
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
11
29
49
68
129
146
167
186
13
31
51
70
131
148
169
188
114
119
1
2
202
NC#163/TEST
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF
VSS
GND
connector
connector
62.10017.751
62.10017.751
Morar_SA:62.10017.751
Morar_SB:62.10017.991
C
D
108
/RAS
109
/WE
113
/CAS
110
/CS0
115
/CS1
79
CKE0
80
CKE1
30
CK0
32
/CK0
164
CK1
166
/CK1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
VDDSPD
NC#50
NC#69
NC#83
NC#120
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
REVISED TYPE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
M_A_DM0
10
M_A_DM1
26
M_A_DM2
52
M_A_DM3
67
M_A_DM4
130
M_A_DM5
147
M_A_DM6
170
M_A_DM7
185
SMBD_ICH
195
SMBC_ICH
197
199
198
SA0
200
SA1
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
1D8V_S3
9.2mm
D
M_A_RAS# 8,12
M_A_WE# 8,12
M_A_CAS# 8,12
M_CS#0 7,12
M_CS#1 7,12
M_CKE0 7,12
M_CKE1 7,12
M_CLK_DDR0 7
M_CLK_DDR#0 7
M_CLK_DDR1 7
M_CLK_DDR#1 7
M_A_DM[7..0] 8
12
BC2
BC2
SCD1U16V
SCD1U16V
DY
DY
Place near DM2
C139 SC10P50V2JN-1
C139 SC10P50V2JN-1
DY
DY
C57 SC10P50V2JN-1
C57 SC10P50V2JN-1
DY
DY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
DDR Socket
DDR Socket
DDR Socket
E
3D3V_S0
12
C32
C32
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
DY
DY
M_CLK_DDR0
12
M_CLK_DDR#0
M_CLK_DDR1
12
M_CLK_DDR#1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
MORAR
MORAR
MORAR
11 40Saturday, May 28, 2005
11 40Saturday, May 28, 2005
11 40Saturday, May 28, 2005
E
SB
SB
SB
of
of
of
A
B
C
D
PARALLEL TERMINATION Decoupling Capacitor
E
Put decap near power(0.9V) and pull-up resistor
DDR_VREF
4 4
3 3
2 2
1 1
DDR_VREF
R395 56R2JR395 56R2J
R379 56R2JR379 56R2J
R381 56R2JR381 56R2J
R391 56R2JR391 56R2J
R48 56R2JR48 56R2J
R380 56R2JR380 56R2J
R52 56R2JR52 56R2J
R396 56R2JR396 56R2J
R397 56R2JR397 56R2J
R392 56R2JR392 56R2J
R393 56R2JR393 56R2J
R378 56R2JR378 56R2J
R394 56R2JR394 56R2J
R383 56R2JR383 56R2J
R384 56R2JR384 56R2J
R382 56R2JR382 56R2J
A
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
RN6
RN6
8
7
6
SRN56-1
SRN56-1
RN5
RN5
8
7
6
SRN56-1
SRN56-1
RN9
RN9
8
7
6
SRN56-1
SRN56-1
1 2
1 2
1 2
1 2
RN29
RN29
8
7
6
SRN56-1
SRN56-1
RN30
RN30
8
7
6
SRN56-1
SRN56-1
RN8
RN8
8
7
6
SRN56-1
SRN56-1
RN10
RN10
8
7
6
SRN56-1
SRN56-1
RN31
RN31
8
7
6
SRN56-1
SRN56-1
RN7
RN7
8
7
6
SRN56-1
SRN56-1
M_B_A3
M_B_A8
M_B_A9
M_B_A12
M_B_A10
1
2
3
M_B_A13
45
M_B_A4
1
M_B_A2
2
M_B_A0
3
45
1
M_B_A11
2
M_B_A7
3
M_B_A6
45
M_B_A5
M_B_A1
1
2
3
M_A_A13
45
M_A_A4
1
M_A_A2
2
M_A_A0
3
45
1
2
3
45
M_A_A8
1
M_A_A9
2
M_A_A12
3
45
1
M_A_A11
2
M_A_A7
3
M_A_A6
45
M_A_A10
1
M_A_A1
2
M_A_A3
3
M_A_A5
45
M_CKE2 7,11
M_ODT3 7,11
M_B_WE# 8,11
M_B_BS#2 8,11
M_ODT1 7,11
M_CS#3 7,11
M_CKE0 7,11
M_B_RAS# 8,11
M_CS#2 7,11
M_ODT2 7,11
M_B_BS#1 8,11
M_CKE3 7,11
M_B_BS#0 8,11
M_B_CAS# 8,11
M_A_RAS# 8,11
M_CS#0 7,11
M_ODT0 7,11
M_A_BS#1 8,11
M_CS#1 7,11
M_A_CAS# 8,11
M_A_WE# 8,11
M_A_BS#0 8,11
M_A_BS#2 8,11
M_CKE1 7,11
B
M_A_A[13..0] 8,11
M_B_A[13..0] 8,11
1D8V_S3
1D8V_S3
12
C93
C93
SCD1U16V
SCD1U16V
12
C379
C379
SCD1U16V
SCD1U16V
Put decap near power(0.9V)
and pull-up resistor
12
SCD1U16V
SCD1U16V
12
SCD1U16V
SCD1U16V
12
C96
C96
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
12
DY
DY
EC43
EC43
SCD1U16V
SCD1U16V
12
DY
DY
C65
C65
SCD1U16V
SCD1U16V
12
DY
DY
C357
C357
SCD1U16V
SCD1U16V
12
C88
C88
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
12
DY
DY
EC39
EC39
SCD1U16V
SCD1U16V
12
DY
DY
EC42
EC42
SCD1U16V
SCD1U16V
C
C78
C78
C358
C358
Place these Caps near DM1
12
DY
DY
EC44
EC44
SCD1U16V
SCD1U16V
Place these Caps near DM2
12
C97
C97
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
12
SCD1U16V
SCD1U16V
DY
DY
EC41
EC41
12
C377
C377
SCD1U16V
SCD1U16V
12
C356
C356
SCD1U16V
SCD1U16V
12
C83
C83
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
12
DY
DY
EC40
EC40
SCD1U16V
SCD1U16V
12
DY
DY
EC47
EC47
SCD1U16V
SCD1U16V
12
C355
C355
SCD1U16V
SCD1U16V
12
C380
C380
SCD1U16V
SCD1U16V
12
12
DY
DY
EC38
EC38
SCD1U16V
SCD1U16V
12
C84
C84
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
C376
C376
C67
C67
12
SCD1U16V
SCD1U16V
12
SCD1U16V
SCD1U16V
12
C80
C80
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
12
SCD1U16V
SCD1U16V
12
SCD1U16V
SCD1U16V
C82
C82
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
DY
DY
C69
C69
C68
C68
12
C354
C354
SCD1U16V
SCD1U16V
12
DY
DY
C90
C90
SCD1U16V
SCD1U16V
12
C75
C75
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
D
12
DY
DY
C378
C378
SCD1U16V
SCD1U16V
12
C76
C76
SCD1U16V
SCD1U16V
12
12
C81
C81
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
12
12
DY
DY
C64
C64
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
12
12
C91
C91
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
C89
C89
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
Title
Title
Title
DDR2 Termination Resistor
DDR2 Termination Resistor
DDR2 Termination Resistor
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
DY
DY
C352
C352
C79
C79
12
SCD1U16V
SCD1U16V
12
SCD1U16V
SCD1U16V
MORAR
MORAR
MORAR
12
DY
DY
C353
C353
C66
C66
SCD1U16V
SCD1U16V
12
C77
C77
C92
C92
SCD1U16V
SCD1U16V
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
12 40Friday, June 24, 2005
12 40Friday, June 24, 2005
12 40Friday, June 24, 2005
E
of
SB
SB
SB
NEED FOLLOW BOLSENA
D4 LED-G-31D4 LED-G-31
1 2
D3 LED-G-31D3 LED-G-31
1 2
D2 LED-G-31D2 LED-G-31
1 2
D7 LED-G-31
D7 LED-G-31
1 2
1 2
1 2
D1 LED-G-31D1 LED-G-31
1 2
D6 LED-G-31D6 LED-G-31
1 2
1 2
D49 LED-G-31D49 LED-G-31
D47 LED-G-31D47 LED-G-31
1 2
D43 LED-B-27-U-GP
D43 LED-B-27-U-GP
D48 LED-Y-22D48 LED-Y-22
D46 LED-Y-22D46 LED-Y-22
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
DY
DY
D5 LED-G-31D5 LED-G-31
D44 LED-Y-22D44 LED-Y-22
DY
DY
1 2
1 2
LCD CONN & LED
LCD CONN & LED
LCD CONN & LED
D45
D45
D19
D19
5V_S0
2
DY
DY
1
2
DY
DY
1
LED
NUM_LED#29
CAP_LED#29
MAIL_LED#29
Near Mail
Button
IDE_LED#20
WLAN_LED#28
Near Power
Button
FRONT_PWRLED#29
DC_BATFULL#29
NUM_LED#
CAP_LED#
MAIL_LED#
MAIL_LED#
IDE_LED#
WLAN_LED#
FRONT_PWRLED#
DC_BATFULL#
1 2
R14 100R2R14 100R2
1 2
R13 100R2R13 100R2
1 2
R12 100R2R12 100R2
1 2
R21 100R2
R21 100R2
DY
DY
1 2
R15 100R2R15 100R2
1 2
R551 100R2R551 100R2
1 2
R9 100R2R9 100R2
1 2
R20 100R2R20 100R2
1 2
R297 100R2R297 100R2
1 2
R295 100R2R295 100R2
NUM_LED#
CAP_LED#
MAIL_LED#
IDE_LED#
FRONT_PWRLED#
STDBY_LED#
DC_BATFULL#
CHARGE_LED#
BLT_LED#
WLAN_LED#
DY
DY
EC18 SC100P50V2JN-U
EC18 SC100P50V2JN-U
1 2
DY
DY
EC17 SC100P50V2JN-U
EC17 SC100P50V2JN-U
1 2
DY
DY
EC11 SC100P50V2JN-U
EC11 SC100P50V2JN-U
1 2
DY
DY
EC19 SC100P50V2JN-U
EC19 SC100P50V2JN-U
1 2
DY
DY
EC144 SC100P50V2JN-U
EC144 SC100P50V2JN-U
1 2
DY
DY
EC143 SC100P50V2JN-U
EC143 SC100P50V2JN-U
1 2
DY
DY
EC141 SC100P50V2JN-U
EC141 SC100P50V2JN-U
1 2
DY
DY
EC139 SC100P50V2JN-U
EC139 SC100P50V2JN-U
1 2
DY
DY
1 2
EC140 SC100P50V2JN-U
EC140 SC100P50V2JN-U
DY
DY
1 2
EC142 SC100P50V2JN-U
EC142 SC100P50V2JN-U
WLAN_LED#
BLT_LED#
BAV99LT1
BAV99LT1
3
BAV99LT1
BAV99LT1
3
Morar_SB
DY
3D3V_S0
1
EDID_CLK
EDID_DAT
LCDVDD
C9
23
SRN2K2J
SRN2K2J
RN28
RN28
4
Layout 40 mil
LCDVDD_ON_1
12
SC1U10V3ZYC9SC1U10V3ZY
12
C10
C10
SCD1U16V
SCD1U16V
U3
U3
1
OUT
2
GND
ON/OFF#3IN
AAT4280IGU-3-T1
AAT4280IGU-3-T1
GND
on KB cover
LED
Button
V
V
POWER1 E-MAIL INTERNET e-BTN PROGRAM
Front panel
3D3V_S0
6
IN
5
4
BRIGHTNESS29
FPBACK29
12
C8
C8
SC1U10V3ZY
SC1U10V3ZY
EC155
EC155
DY
DY
SC100P50V2JN-U
SC100P50V2JN-U
C298
C298
EC154
EC154
1 2
1 2
DY
DY
SC100P50V2JN-U
SC100P50V2JN-U
LED
ButtonVV
LCD CONN
3D3V_S0
EDID_CLK
EDID_DAT
DCBATOUT
EC156
EC156
SCD1U50V3ZY
SCD1U50V3ZY
12
12
DY
DY
JST-CONN40A-2
JST-CONN40A-2
SC10U35V0ZY-L
SC10U35V0ZY-L
BlutToothWireless Charger Power2
LCD1
LCD1
42
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
41
connector
connector
20.F0439.040
20.F0439.040
2D5V_S0
Morar_SB
Q26
Q26
G
G
FDN337N-U
FDN337N-U
CLK_DDC_EDID7
DAT_DDC_EDID7
GMCH_LCDVDD_ON7
1
2 3
D
D
S
S
G
G
2 3
S
S
Q27
Q27
FDN337N-U
FDN337N-U
GMCH_LCDVDD_ON
1
D
D
R19
R19
1 2
1KR2
1KR2
BLT_LED#29
STDBY_LED#29
CHARGE_LED#29
V
VVVV
V
V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Morar_SA:20.F0687.040
Morar_SB:20.F0687.040
Morar_SB:20.F0737.040(2nd)
BLT_LED#
STDBY_LED#
CHARGE_LED#
VV
(Please See M.E. drawing LED position)
LCDVDD
12
C5
C5
DY
DY
SC10U10V5ZY-L
SC10U10V5ZY-L
GMCH_TXBCLK+ 7
GMCH_TXBCLK- 7
GMCH_TXBOUT2+ 7
GMCH_TXBOUT2- 7
GMCH_TXBOUT1+ 7
GMCH_TXBOUT1- 7
GMCH_TXBOUT0+ 7
GMCH_TXBOUT0- 7
GMCH_TXACLK+ 7
GMCH_TXACLK- 7
GMCH_TXAOUT2+ 7
GMCH_TXAOUT2- 7
GMCH_TXAOUT1+ 7
GMCH_TXAOUT1- 7
GMCH_TXAOUT0+ 7
GMCH_TXAOUT0- 7
DY
1 2
R548 470R2
R548 470R2
1 2
R296 100R2R296 100R2
1 2
R294 100R2R294 100R2
VVV
CAPS NUM HDD
Charger:
Green : DC only or Battery full with DC
Orange : Charging
Orange Blink : Battery low
12
C6
C6
SCD1U16V
SCD1U16V
12
EC22
EC22
SCD1U16V
SCD1U16V
DY
DY
12
MORAR
MORAR
MORAR
5V_S0
on KB Cover
on KB Cover
on KB Cover,UP
on KB Cover,DOWN
on KB Cover
on Front Panel
on KB Cover,UP
on KB Cover,DOWN
on Front Panel
5V_S5
on Front Panel
5V_S0
on Front Panel
5V_S5
on Front Panel
on Front Panel
Power2:
Green : S0
Orange : S3
Orange Blinking : Enter S4
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
of
of
of
13 40Saturday, May 28, 2005
13 40Saturday, May 28, 2005
13 40Saturday, May 28, 2005
SB
SB
SB
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