Wistron LLW-1, LGG-1 Schematic

5
4
3
2
1
LLW-1/LGG-1 Schematics
D D
Sandy Bridge Cougar Point
C C
2011-01-18
REV : -1
DY:None Installed UMA:UMA platform installed only
B B
PX:Discrete(both Robson and Whistler) SKU installed RBS:Robson SKU installed only WTL:Whistler SKU installed only SAMSUNG:Use SAMSUNG VRAM Hynix:Use Hynix VRAM VRAM_1G:Use 1G VRAM VRAM_2G:Use 2G VRAM
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Cover Page
Cover Page
Cover Page
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
of
194
of
194
of
194
-1
-1
-1
PCB Layer Stackup
ThermalSensor
EMC2103
RFID I2C/SM Bus Switch
14" HD 1366*768
VGA connector
AUDIO COMBO Jack 58
28
80
49
50
SIM Slot
USB 2.0
USB 2.0
Camera
##OnMainBoard
SM Bus
LVDS
VGA Port
66
PORT2
PORT1
LLW-1 / LGG-1 Block Diagram
VRAM
2GB/1GB
AMD GPU
Whistler-LP 1G/2G Seymour-XT 1G
SATA CONN
ODD CONN
Mini PCI-E WWAN Card
HD AUDIO CODEC CX20671
eSATA Combo CN
eSATA
USB 2.0
CH1
61
CH9
61
CH12
49
DDR3 800MHz
PORT3
88~91
83~87
56
56
66
29
57
PEG x16
SATA Port 0
SATA Port 4
SATA
USB 2.0 CH4
Azalia bus
SATA Port5
CH8
USB 2.0
FingerPrint
Bluetooth
69
63
Intel CPU
Sandy Bridge
DDR3 1333MHz
DMI x4
Intel
PCH
USB 2.0 (14 ports)
AC97 2.3/Azalia Interface
Serial ATA 150MB/s
ACPI 2.0
LPC I/F PCI Rev 2.3 PCI Express
INT. RTC
CH2
HDMI
USB 2.0
CH3
connector
4~10
FDI
17~25
Display Port
51
XDP Conn.
Channel A
DDR3 1333
Channel B
DDR3 1333
USB 2.0 CH11
PCI Express 4
PCI Express 2
11
Project Code: 91.4MH01.001 PCB(Raw Card):10282
UNBUFFERED DDR3 SODIMM
204-PIN DDR3 SODIMM
UNBUFFERED DDR3 SODIMM
Mini PCI-E WLAN Card
PCI Express 2
CONNCONN
82
PCI Express 3
USB 2.0 CH13
PCI Express 8
USB 2.0 CH10 USB 2.0 CH10
Media Card Reader
R5U220
PCI Express 8
82
LPC Bus / 33MHz
KBC Nuvoton NPCE795
27
G-Sensor
SPI FLASH
79
Int.KB/Track point Touch Pad
60
65
32
USB 2.0 CH13
LPC Debug Board Conn
14
15
LOM
RTL8111E
NEW CARD
USB 2.0 PORT4
71
69
L1: TOP L5: VCC L2: GND L3: Signal L4: Signal
L6: Signal L7: GND L8: BOTTOM
Battery Charger/Selector
BQ24745
OUTPUTSINPUTS
DCBATOUT BT+
System DC/DC
BD95280
PWR_3D3V_DCBATOUT
PWR_5V_DCBATOUT
3D3V_S5 5V_S5
CPU DC/DC
NCP6131
DCBATOUT
DCBATOUT_VCC_GFXCOREVCC_GFXCORE
42~44
VCC_CORE
1D05V_VTT
TPS51218
PWR_1D05V_DCBATOUT
1D05V_VTT
1D5V_S3
TPS51218
PWR_1D5V_DCBATOUT 1D5V_S3
0D75V
RJ45
RT9026
1D5V_S3
DDR_VREF_S3
0D75V_S0
1D8V_S0
RT8015
3D3V_S5
1D8V_S0
VCCSA
RT8208B
PWR_VCCSA_DCBATOUT
0D85V_S0
GFX CORE
RT8208B
PWR_DCBATOUT_VGA_COREVGA_CORE
1V_VGA
RT9025
1V_VGA_S01D5V_S3
1D8V_VGA
RT9025
3D3V_S5 1D8V_VGA_S0
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
of
of
of
294Tuesday, January 18, 2011
294Tuesday, January 18, 2011
294Tuesday, January 18, 2011
40
41
45
46
46
47
48
92
93
93
-1
-1
-1
A
PCH Strapping
Name Schematics Notes
SPKR
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
GNT3#/GPIO55
4 4
GNT2#/GPIO53 GNT1#/GPIO51
SPI_MOSI
NV_ALE
Reboot option at power-up
Internal weak Pull-down.
Default Mode:
Connect to Vcc3_3 with 8.2-kȍ
No Reboot Mode with TCO Disabled:
- 10-kȍ weak pull-up resistor.
GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.
Enable Danbury:
Disable Danbury:
Enable Danbury:
Disable Danbury:
Huron River Schematic Checklist Rev.0_7
Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.
Left floating, no pull-down required.
Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]
Leave floating (internal pull-down)
B
C
Processor Strapping
Pin Name Strap Description Configuration (Default value for each bit is
CFG[2]
PCI-Express Static Lane Reversal
CFG[4]
CFG[6:5]
CFG[7]
PCI-Express Port Bifurcation Straps
PEG DEFER TRAINING
1 unless specified otherwise)
1:
Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
0:
Disabled - No Physical Display Port attached to
1:
Embedded DisplayPort. Enabled - An external Display Port device is
0:
connectd to the EMBEDDED display Port
11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled
1:
PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training
0:
D
Huron River Schematic Checklist Rev.0_7
Default Value
1
0
11
1
E
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features.
HAD_DOCK_EN# /GPIO[33]
3 3
High (1) - Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions.
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
HDA_SYNC
GPIO15
GPIO8
2 2
GPIO27
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality
Note : This is an un-muxed signal. This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled.
Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.
POWER PLANE
5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0
5V_USBX_S3 1D5V_S3 DDR_VREF_S3
BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5
3D3V_AUX_KBC
3D3V_AUX_S5
VOLTAGE DESCRIPTION
5V
3.3V
1.8V
1.5V
1.05V
0.95 - 0.85V
0.75V
0.35V to 1.5V
0.4 to 1.25V
1.8V
3.3V 1V
5V
1.5V
0.75V
6V-14.1V 6V-14.1V 5V 5V
3.3V
3.3V
3.3V3D3V_LAN_S5
3.3V
3.3V
Voltage Rails
ACTIVE IN
S0
CPU Core Rail Graphics Core Rail
S3
AC Brick Mode only
All S states
WOL_EN
DSW, Sx ON for supporting Deep Sleep states
G3, Sx
Legacy WOL
Powered by Li Coin Cell in G3 and +V3ALW in Sx
USB Table
Pair Device
X
PCIE Routing
LANE1
LANE2
LANE3
LANE4
1 1
LANE5
LANE6
LANE7
LANE8 NEW CARD
RESERVED
LAN
CARD READER
MiniCard WLAN
RESERVED
RESERVED
RESERVED
SATA Table
SATA
Pair
0
1
2
3
4
5
Device
HDD
mSATA
N/A
N/A
ODD
ESATA
0
USB2
1
FINGERPRINT
2
BLUETOOTH
3
Mini Card2 (WWAN)
4
X
5
X
6
X
7
ESATA1
8
USB1
9
USB Ext. port 4
10
Mini Card1 (WLAN)
11
CAMERA
12
New Card
13
SMBus ADDRESSES
2
I C / SMBus Addresses
Device
EC SMBus 1 Battery Capacity Board
EC SMBus 2 PCH MXM LCD Thermal Sensor
PCH SMBus CK505 Clock Generator SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot
HURON RIVER ORB
Address Hex Bus Ref Des
KBC_SDA1/KBC_SCL1 KBC_SDA1/KBC_SCL1
KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2
PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Table of Content
Table of Content
Table of Content
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
of
394Tuesday, January 18, 2011
of
394Tuesday, January 18, 2011
of
394Tuesday, January 18, 2011
-1
-1
-1
5
4
3
2
1
SSID = CPU
Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1 OF 9
CPU1A
CPU1A
D D
C C
B B
NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.
Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.
Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.
Note: Lane reversal does not apply to FDI sideband signals.
Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.
DMI_TXN[3..0]19
DMI_TXP[3..0]19
DMI_RXN[3..0]19
DMI_RXP[3..0]19
FDI_TXN[7:0]19
FDI_TXP[7:0]19
FDI_FSYNC019 FDI_FSYNC119
FDI_INT19 FDI_LSYNC019
FDI_LSYNC119
1D05V_VTT
R402 24D9R2F-L-GPR402 24D9R2F-L-GP
1 2
R403 10KR2J-3-GP
R403 10KR2J-3-GP
1 2
DY
DY
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7
FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7
DP_COMP eDP_HPD
B27 B25 A25 B24
B28 B26 A24 B23
G21 E22 F21 D21
G22 D22 F20 C21
A21 H19 E19 F18 B21 C20 D18 E17
A22 G19 E20 G18 B20 C19 D19 F17
H20
H17
A18 A17 B16
C15 D15
C17 F16 C16 G15
C18 E16 D16 F15
J18 J17
J19
SANDY
SANDY
DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3
DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3
DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3
DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3
FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3
FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3
FDI0_FSYNC FDI1_FSYNC
FDI_INT FDI0_LSYNC
FDI1_LSYNC
EDP_COMPIO EDP_ICOMPO EDP_HPD
EDP_AUX EDP_AUX#
EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3
EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3
SANDY
SANDY
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
1 OF 9
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8
PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15
PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8
PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15
PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9
PEG_TX#10 PEG_TX#11
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15
J22 J21 H22
K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32
J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32
M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25
M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25
PEG_IRCOMP_R
PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0
PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0
PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0
PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0
R401 24D9R2F-L-GPR401 24D9R2F-L-GP
1 2
PEG_RXN[0..15]
C401 SCD1U6D3V1KX-GP
C401 SCD1U6D3V1KX-GP
1 2
PX
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX PX
PX
C402 SCD1U6D3V1KX-GP
C402 SCD1U6D3V1KX-GP C403 SCD1U6D3V1KX-GP
C403 SCD1U6D3V1KX-GP C404 SCD1U6D3V1KX-GP
C404 SCD1U6D3V1KX-GP C405 SCD1U6D3V1KX-GP
C405 SCD1U6D3V1KX-GP C406 SCD1U6D3V1KX-GP
C406 SCD1U6D3V1KX-GP C407 SCD1U6D3V1KX-GP
C407 SCD1U6D3V1KX-GP C408 SCD1U6D3V1KX-GP
C408 SCD1U6D3V1KX-GP C409 SCD1U6D3V1KX-GP
C409 SCD1U6D3V1KX-GP C410 SCD1U6D3V1KX-GP
C410 SCD1U6D3V1KX-GP C411 SCD1U6D3V1KX-GP
C411 SCD1U6D3V1KX-GP C412 SCD1U6D3V1KX-GP
C412 SCD1U6D3V1KX-GP C413 SCD1U6D3V1KX-GP
C413 SCD1U6D3V1KX-GP C414 SCD1U6D3V1KX-GP
C414 SCD1U6D3V1KX-GP C415 SCD1U6D3V1KX-GP
C415 SCD1U6D3V1KX-GP C416 SCD1U6D3V1KX-GP
C416 SCD1U6D3V1KX-GP C417 SCD1U6D3V1KX-GP
C417 SCD1U6D3V1KX-GP C418 SCD1U6D3V1KX-GP
C418 SCD1U6D3V1KX-GP C419 SCD1U6D3V1KX-GP
C419 SCD1U6D3V1KX-GP C420 SCD1U6D3V1KX-GP
C420 SCD1U6D3V1KX-GP C421 SCD1U6D3V1KX-GP
C421 SCD1U6D3V1KX-GP C422 SCD1U6D3V1KX-GP
C422 SCD1U6D3V1KX-GP C423 SCD1U6D3V1KX-GP
C423 SCD1U6D3V1KX-GP C424 SCD1U6D3V1KX-GP
C424 SCD1U6D3V1KX-GP C425 SCD1U6D3V1KX-GP
C425 SCD1U6D3V1KX-GP C426 SCD1U6D3V1KX-GP
C426 SCD1U6D3V1KX-GP C427 SCD1U6D3V1KX-GP
C427 SCD1U6D3V1KX-GP C428 SCD1U6D3V1KX-GP
C428 SCD1U6D3V1KX-GP C429 SCD1U6D3V1KX-GP
C429 SCD1U6D3V1KX-GP C430 SCD1U6D3V1KX-GP
C430 SCD1U6D3V1KX-GP C431 SCD1U6D3V1KX-GP
C431 SCD1U6D3V1KX-GP C432 SCD1U6D3V1KX-GP
C432 SCD1U6D3V1KX-GP
1D05V_VTT
PEG_RXN[0..15] 83
PEG_RXP[0..15]
NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect
PEG Static Lane Reversal
PEG_RXP[0..15] 83
PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0
PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0
PEG_TXN[0..15] 83
PEG_TXP[0..15] 83
Table 4.1- Central Processing Unit slot multi-source
Supplier
FOXCONN
TYCO
<Core Design>
<Core Design>
A A
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
Description Lenovo P/N Wistron P/N
PZ98827-364B-41F
N/A 62.10055.421
N/A2-2013620-3
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU (PCIE/DMI/FDI)
CPU (PCIE/DMI/FDI)
CPU (PCIE/DMI/FDI)
LLW-1 / LGG-1
LLW-1 / LGG-1
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
LLW-1 / LGG-1
494
494
494
62.10040.771
of
of
of
-1
-1
-1
SSID = CPU
5
1D05V_VTT
R501 62R2J-GPR501 62R2J-GP
1 2
D D
H_PROCHOT#
12
C502
C502 SC47P50V2JN-3GP
SC47P50V2JN-3GP
H_SNB_IVB#18
4
CPU1B
CPU1B
SANDY
SANDY
C26
SNB_IVB#
SKTOCC#_R
H_CATERR#
AN34
AL33
SKTOCC#
CATERR#
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
1
TP501TPAD14-GP TP501TPAD14-GP
1
TP502TPAD14-GP TP502TPAD14-GP
3
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLOCKS
CLOCKS
2 OF 9
2 OF 9
BCLK
BCLK#
A28 A27
A16 A15
CLK_DP_P_R CLK_DP_N_R
CLK_EXP_P 20 CLK_EXP_N 20
CLK_DP_P_R 20 CLK_DP_N_R 20
2
Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted.
RN502
CLK_DP_P_R CLK_DP_N_R
RN502
1 2 3
SRN1KJ-11-GP-U
SRN1KJ-11-GP-U
DY
DY
1
1D05V_VTT
4
H_PECI22,27
R513
R513
H_PROCHOT#27,42
Connect EC to PROCHOT# through inverting OD buffer.
R506
R506
1 2
H_CPUPWRGD_R
10KR2J-3-GP
10KR2J-3-GP
C C
H_THERMTRIP#22,36,85
H_PM_SYNC19
H_CPUPWRGD22,36
PM_DRAM_PWRGD19,37
VDDPWRGOOD37
12
R502
R502 1KR2J-1-GP
1KR2J-1-GP
1 2
1 2
R504 0R2J-2-GPR504 0R2J-2-GP
R505
R505
1D05V_VTT3D3V_S0
B B
D
Q501
Q501
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
S
G
PLT_RST#18,27,32,36,65,66,71,80,82,83
G
H_PROCHOT#_R
56R2J-4-GP
56R2J-4-GP
H_CPUPWRGD_R
DY
DY
VDDPWRGOOD XDP_TMS
1 2
12
D
0R2J-2-GP
0R2J-2-GP
BUF_PLT_RST#
R509
R509 75R2F-2-GP
75R2F-2-GP
R512
R512 43R2J-GP
43R2J-GP
1 2
Q502
Q502 2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
S
AN33
AL32
AN32
AM34
AP33
V8
AR33
BUF_PLT_RST#
PECI
PROCHOT#
THERMTRIP#
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWROK
RESET#
SANDY
SANDY
SM_DRAMRST#
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2
DDR3
MISC
DDR3
MISC
JTAG & BPM
JTAG & BPM
R8
SM_RCOMP_0
AK1
SM_RCOMP_1
A5
SM_RCOMP_2
A4
Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils.
AP29
PRDY#
AP27
PREQ#
AR26
TCK
AR27
TMS
AP30
TRST#
AR28
TDI
AP26
TDO
AL35
DBR#
XDP_BPM0
AT28
BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7
XDP_BPM1
AR29
XDP_BPM2
AR30
XDP_BPM3
AT30
XDP_BPM4
AP32
XDP_BPM5
AR31
XDP_BPM6
AT31
XDP_BPM7
AR32
XDP_DBRESET# XDP_PREQ# XDP_PRDY# XDP_TDO XDP_TDI XDP_TRST# XDP_TCLK XDP_TMS
R508 140R2F-GPR508 140R2F-GP R507 25D5R2F-GPR507 25D5R2F-GP R510 200R2F-L-GPR510 200R2F-L-GP
XDP_PRDY# XDP_PREQ#
XDP_TCLK XDP_TMS XDP_TRST#
XDP_TDI XDP_TDO
XDP_DBRESET#
1 1 1 1 1 1 1 1
1 2 1 2 1 2
TP503TP503 TP504TP504 TP505TP505 TP506TP506 TP507TP507 TP508TP508 TP509TP509 TP510TP510
XDP_DBRESET# 11,19 XDP_PREQ# 11 XDP_PRDY# 11
1
TP511TP511
1
TP512TP512
1
TP513TP513
1
TP514TP514
1
TP515TP515
SM_DRAMRST# 37
R503
R503 4K99R2F-L-GP
4K99R2F-L-GP
1 2
XDP_TDI XDP_TDO
XDP_TCLK
XDP_TRST#
R511 51R2J-2-GPR511 51R2J-2-GP
1 2
XDP_DBRESET#
Table 5.1- N-Channel MOSFET multi-source
Supplier
PANJIT
Description Lenovo P/N Wistron P/N
2N7002K
DIODES
1D05V_VTT
RN501
RN501
4 5 3
6
2
7
1
8
SRN51J-1-GP
SRN51J-1-GP
R516 1KR2J-1-GPR516 1KR2J-1-GP
1 2
N/A 84.2N702.J31
N/A2N7002K
3D3V_S0
84.2N702.031
84.07002.I31NXP N/A2N7002BK
<Core Design>
<Core Design>
A A
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (Thermal/CLK/PM)
CPU (Thermal/CLK/PM)
CPU (Thermal/CLK/PM)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
of
594Tuesday, January 18, 2011
of
594Tuesday, January 18, 2011
of
594Tuesday, January 18, 2011
-1
-1
-1
5
4
3
2
1
SSID = CPU
4 OF 9
3 OF 9
CPU1C
CPU1C
SANDY
SANDY
M_A_DQ[63:0]14 M_B_DQ[63:0]15
D D
C C
B B
M_A_DQ[63:0]
M_A_BS014 M_A_BS114 M_A_BS214
M_A_CAS#14 M_A_RAS#14 M_A_WE#14
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
G10
N10
M10
AG6 AG5 AK6 AK5 AH5 AH6
AK8 AK9
AH8 AH9 AL9
AL8 AP11 AN11
AL12 AM12 AM11
AL11 AP12 AN12
AJ14 AH14
AL15 AK15
AL14 AK14
AJ15 AH15
AE10
AF10
AE8 AD9 AF9
C5
SA_DQ0
D5
SA_DQ1
D3
SA_DQ2
D2
SA_DQ3
D6
SA_DQ4
C6
SA_DQ5
C2
SA_DQ6
C3
SA_DQ7
F10
SA_DQ8
F8
SA_DQ9 SA_DQ10
G9
SA_DQ11
F9
SA_DQ12
F7
SA_DQ13
G8
SA_DQ14
G7
SA_DQ15
K4
SA_DQ16
K5
SA_DQ17
K1
SA_DQ18
J1
SA_DQ19
J5
SA_DQ20
J4
SA_DQ21
J2
SA_DQ22
K2
SA_DQ23
M8
SA_DQ24 SA_DQ25
N8
SA_DQ26
N7
SA_DQ27 SA_DQ28
M9
SA_DQ29
N9
SA_DQ30
M7
SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37
AJ5
SA_DQ38
AJ6
SA_DQ39
AJ8
SA_DQ40 SA_DQ41
AJ9
SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55
V6
SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
SA_BS0 SA_BS1 SA_BS2
SA_CAS# SA_RAS# SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
3 OF 9
SA_CLK0
SA_CLK#0
SA_CKE0
SA_CLK1
SA_CLK#1
SA_CKE1
SA_CLK2
SA_CLK#2
SA_CKE2
SA_CLK3
SA_CLK#3
SA_CKE3
SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3
SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3
SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8
SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15
AB6 AA6 V9
AA5 AB5 V10
AB4 AA4 W9
AB3 AA3 W10
AK3 AL3 AG1 AH1
AH3 AG3 AG2 AH2
C4 G6 J3 M6 AL6 AM8 AR12 AM15
D4 F6 K3 N6 AL5 AM9 AR11 AM14
AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7
M_A_DIM0_CLK_DDR0 14 M_A_DIM0_CLK_DDR#0 14 M_A_DIM0_CKE0 14
M_A_DIM0_CLK_DDR1 14 M_A_DIM0_CLK_DDR#1 14 M_A_DIM0_CKE1 14
M_A_DIM0_CS#0 14 M_A_DIM0_CS#1 14
M_A_DIM0_ODT0 14 M_A_DIM0_ODT1 14
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
M_A_DQS#[7:0] 14
M_A_DQS[7:0] 14
M_A_A[15:0] 14
M_B_DQ[63:0]
M_B_BS015 M_B_BS115 M_B_BS215
M_B_CAS#15 M_B_RAS#15 M_B_WE#15
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
D10
K10
AM5 AM6 AR3
AP3 AN3 AN2 AN1
AP2
AP5 AN9
AT5
AT6
AP6 AN8 AR6 AR5 AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11 AN14 AR14
AT14
AT12 AN15 AR15
AT15
AA9 AA7
AA10
AB8 AB9
CPU1D
CPU1D
SANDY
SANDY
C9
SB_DQ0
A7
SB_DQ1 SB_DQ2
C8
SB_DQ3
A9
SB_DQ4
A8
SB_DQ5
D9
SB_DQ6
D8
SB_DQ7
G4
SB_DQ8
F4
SB_DQ9
F1
SB_DQ10
G1
SB_DQ11
G5
SB_DQ12
F5
SB_DQ13
F2
SB_DQ14
G2
SB_DQ15
J7
SB_DQ16
J8
SB_DQ17 SB_DQ18
K9
SB_DQ19
J9
SB_DQ20
J10
SB_DQ21
K8
SB_DQ22
K7
SB_DQ23
M5
SB_DQ24
N4
SB_DQ25
N2
SB_DQ26
N1
SB_DQ27
M4
SB_DQ28
N5
SB_DQ29
M2
SB_DQ30
M1
SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54
R6
SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
SB_BS0 SB_BS1 SB_BS2
SB_CAS# SB_RAS# SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
4 OF 9
SB_CLK0
SB_CLK#0
SB_CKE0
SB_CLK1
SB_CLK#1
SB_CKE1
SB_CLK2
SB_CLK#2
SB_CKE2
SB_CLK3
SB_CLK#3
SB_CKE3
SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3
SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3
SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8
SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15
AE2 AD2 R9
AE1 AD1 R10
AB2 AA2 T9
AA1 AB1 T10
AD3 AE3 AD6 AE6
AE4 AD4 AD5 AE5
D7 F3 K6 N3 AN5 AP9 AK12 AP15
C7 G3 J6 M3 AN6 AP8 AK11 AP14
AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4
M_B_DIM0_CLK_DDR0 15 M_B_DIM0_CLK_DDR#0 15 M_B_DIM0_CKE0 15
M_B_DIM0_CLK_DDR1 15 M_B_DIM0_CLK_DDR#1 15 M_B_DIM0_CKE1 15
M_B_DIM0_CS#0 15 M_B_DIM0_CS#1 15
M_B_DIM0_ODT0 15 M_B_DIM0_ODT1 15
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
M_B_DQS#[7:0] 15
M_B_DQS[7:0] 15
M_B_A[15:0] 15
SANDY
SANDY
SANDY
A A
5
4
3
SANDY
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (DDR)
CPU (DDR)
CPU (DDR)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
2
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
-1
-1
of
694
of
694
of
694
-1
5
4
3
2
1
SSID = CPU
CFG011
TP701TP701
D D
TP714TP714 TP715TP715
TP702TP702
TP703TP703 TP704TP704 TP705TP705 TP706TP706 TP707TP707 TP708TP708 TP709TP709 TP710TP710 TP711TP711 TP712TP712
VCC_VALIDATION_SENSE
1
VSS_VALIDATION_SENSE
1
M3 - Processor Generated SO-DIMM VREF_DQ
DY
DY
R708 0R2J-2-GP
R708 0R2J-2-GP
M_VREF_DQ_DIMM014,37
C C
B B
M_VREF_DQ_DIMM115
M_VREF_CA_DIMM014 M_VREF_CA_DIMM115
1 2
R709 0R2J-2-GP
R709 0R2J-2-GP
1 2
DY
DY DY
DY
R707 0R2J-2-GP
R707 0R2J-2-GP
1 2
R706 0R2J-2-GP
R706 0R2J-2-GP
1 2
DY
DY
12
R711
R711 1KR2F-3-GP
1KR2F-3-GP
CFG0 CFG1
1
CFG2 CFG3
1
CFG4 CFG5 CFG6 CFG7 CFG8
1
CFG9
1
CFG10
1
CFG11
1
CFG12
1
CFG13
1
CFG14
1
CFG15
1
CFG16
1
CFG17
1
B4:VREF_DQ CHA
M_VREF_DQ_DIMM0_C M_VREF_CA_DIMM0_CM_VREF_CA_DIMM0_C
D1:VREF_DQ CHB
12
R712
R712 1KR2F-3-GP
1KR2F-3-GP
3D3V_S5
20 mils
12
R710
R710 10KR2J-3-GP
10KR2J-3-GP
H_VCCP_SEL
AK28 AK29 AL26 AL27 AK26 AL29
AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27
AK31 AN29
AJ31
AH31
AJ33
AH33
AJ26
F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29
B18 A19
B4 D1
J20
J15
CPU1E
CPU1E
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17
RSVD#AJ31 RSVD#AH31 RSVD#AJ33 RSVD#AH33
RSVD#AJ26
RSVD#B4 RSVD#D1
RSVD#F25 RSVD#F24 RSVD#F23 RSVD#D24 RSVD#G25 RSVD#G24 RSVD#E23 RSVD#D23 RSVD#C30 RSVD#A31 RSVD#B30 RSVD#B29 RSVD#D30 RSVD#B31 RSVD#A30 RSVD#C29
RSVD#J20 RSVD#B18 RSVD#A19
RSVD#J15
SANDY
SANDY
SANDY
SANDY
RESERVED
RESERVED
5 OF 9
5 OF 9
RSVD#L7 RSVD#AG7 RSVD#AE7 RSVD#AK2
RSVD#W8
RSVD#AT26
RSVD#AM33
RSVD#AJ27
RSVD#T8
RSVD#J16 RSVD#H16
RSVD#G16
RSVD#AR35
RSVD#AT34 RSVD#AT33 RSVD#AP35
RSVD#AR34
RSVD#B34 RSVD#A33 RSVD#A34 RSVD#B35 RSVD#C35
RSVD#AJ32 RSVD#AK32
RSVD#AH27
RSVD#AN35 RSVD#AM35
RSVD#AT2 RSVD#AT1 RSVD#AR1
L7 AG7 AE7 AK2 W8
AT26 AM33 AJ27
T8 J16 H16 G16
AR35 AT34 AT33 AP35 AR34
B34 A33 A34 B35 C35
AJ32 AK32
AH27
AN35 AM35
AT2 AT1 AR1
VCC_DIE_SENSE
PCIE_CLK_XDP_P 11,20 PCIE_CLK_XDP_N 11,20
1
CFG2
TP716TP716
12
PX
PX
R702
R702 1KR2J-1-GP
1KR2J-1-GP
PEG Static Lane Reversal
CFG2
1: Normal Operation; Lane # definition matches socket pin map definition
0:Lane Reversed
CFG7
12
DY
DY
R705
R705 1KR2J-1-GP
1KR2J-1-GP
CFG5 CFG6
A A
12
DY
DY
R701
R701 1KR2J-1-GP
1KR2J-1-GP
12
DY
DY
R704
R704 1KR2J-1-GP
1KR2J-1-GP
5
PEG DEFER TRAINING
CFG7
1: PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
PCIE Port Bifurcation Straps
CFG[6:5]
11: x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
4
3
CFG4
12
DY
DY
R703
R703 1KR2J-1-GP
1KR2J-1-GP
Display Port Presence Strap
CFG4
2
1: Disabled; No Physical Display Port attached to Embedded Display Port
0: Enabled; An external Display Port device is connected to the Embedded Display Port
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
CPU (RESERVED)
CPU (RESERVED)
CPU (RESERVED)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
-1
-1
of
794
of
794
of
794
-1
5
SSID = CPU
PROCESSOR CORE POWER
53A
D D
C C
B B
A A
VCC_CORE
12
C801
C801
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
C815
C815
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
C816
C816
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C837
C837
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCC Output Decoupling Recommendation: 4 x 470 uF at Bottom Socket Edge 8 x 22 uF at Top Socket Cavity 8 x 22 uF at Top Socket Edge 8 x 22 uF at Bottom Socket Cavity
12
12
C803
C803
C802
C802
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
12
C818
C818
C817
C817
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
12
C821
C821
C822
C822
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C836
C836
C835
C835
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
5
12
12
C804
C804
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
12
C819
C819
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
12
C823
C823
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C834
C834
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C811
C811
C820
C820
C824
C824
C833
C833
12
12
C826
C826
C825
C825
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C832
C832
C831
C831
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
4
POWER
CPU1F
CPU1F
VCC_CORE
AG35
VCC
AG34
VCC
AG33
VCC
AG32
VCC
AG31
VCC
AG30
VCC
AG29
VCC
AG28
VCC
AG27
VCC
AG26
VCC
AF35
VCC
AF34
VCC
AF33
VCC
AF32
VCC
AF31
VCC
AF30
VCC
AF29
VCC
AF28
VCC
AF27
VCC
AF26
VCC
AD35
VCC
AD34
VCC
AD33
VCC
AD32
VCC
AD31
VCC
AD30
VCC
AD29
VCC
AD28
VCC
AD27
VCC
AD26
VCC
AC35
VCC
AC34
VCC
AC33
VCC
AC32
VCC
12
C827
C827
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C828
C828
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
4
AC31 AC30 AC29 AC28 AC27 AC26
AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Y35
VCC
Y34
VCC
Y33
VCC
Y32
VCC
Y31
VCC
Y30
VCC
Y29
VCC
Y28
VCC
Y27
VCC
Y26
VCC
V35
VCC
V34
VCC
V33
VCC
V32
VCC
V31
VCC
V30
VCC
V29
VCC
V28
VCC
V27
VCC
V26
VCC
U35
VCC
U34
VCC
U33
VCC
U32
VCC
U31
VCC
U30
VCC
U29
VCC
U28
VCC
U27
VCC
U26
VCC
R35
VCC
R34
VCC
R33
VCC
R32
VCC
R31
VCC
R30
VCC
R29
VCC
R28
VCC
R27
VCC
R26
VCC
P35
VCC
P34
VCC
P33
VCC
P32
VCC
P31
VCC
P30
VCC
P29
VCC
P28
VCC
P27
VCC
P26
VCC
SANDY
SANDY
POWER
SANDY
SANDY
CORE SUPPLY
CORE SUPPLY
3
6 OF 9
6 OF 9
AH13
VCCIO
AH10
VCCIO
AG10
VCCIO
AC10
VCCIO
Y10
VCCIO
U10
VCCIO
P10
VCCIO
L10
VCCIO
J14
VCCIO
J13
VCCIO
J12
VCCIO
J11
VCCIO
H14
VCCIO
H12
VCCIO
H11
VCCIO
G14
VCCIO
G13
VCCIO
G12
VCCIO
F14
VCCIO
F13
VCCIO
F12
VCCIO
F11
VCCIO
E14
VCCIO
E12
VCCIO
E11
VCCIO
D14
VCCIO
D13
VCCIO
D12
VCCIO
D11
VCCIO
C14
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VCCIO
VIDALERT#
VIDSCLK
VIDSOUT
C13 C12 C11 B14 B12 A14 A13 A12 A11
J23
AJ29 AJ30 AJ28
AJ35 AJ34
B10 A10
PEG AND DDR
PEG AND DDR
VCC_SENSE
VSS_SENSE
VCCIO_SENSE VSSIO_SENSE
SENSE LINES SVID
SENSE LINES SVID
3
VCCIO Output Decoupling Recommendation: 2 x 330 uF (3 x 330 uF for 2012 capable designs) 5 x 22 uF & 5 x 0805 no-stuff at Bottom 7 x 22 uF & 2 x 0805 no-stuff at Top
12
12
C806
C806
C805
C805
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
No-stuff sites outside the socket may be removed. No-stuff sites inside the socket cavity need to remain.
12
C812
C812
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7 For CRB VIDALERT# need to pull high 75 ohm close to CPU
H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT
R803 43R2J-GPR803 43R2J-GP
R801, R802 need to close to CPU
VCCIO_SENSE 45 VSSIO_SENSE 45
12
C813
C813
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
VCC_CORE
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
R801
R801 100R2F-L1-GP-U
100R2F-L1-GP-U
12
R802
R802 100R2F-L1-GP-U
100R2F-L1-GP-U
2
1D05V_VTT
12
12
C807
C807
12
C814
C814
12
12
C808
C808
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C829
C829
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C809
C809
12
C830
C830
H_CPU_SVIDDAT
C810
C810
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C842
C842
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C839
C839
C838
C838
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1D05V_VTT
12
12
C844
C844
C843
C843
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
R804 130R2F-1-GPR804 130R2F-1-GP
1 2
12
C840
C840
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C845
C845
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1D05V_VTT
1
12
C841
C841
S-HS_20100610 V1.0
VR_SVID_ALERT# 42
H_CPU_SVIDCLK 42
H_CPU_SVIDDAT 42
VCCSENSE 42 VSSSENSE 42
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (VCC_CORE)
CPU (VCC_CORE)
CPU (VCC_CORE)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
2
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
-1
-1
-1
of
894
of
894
of
894
5
VAXG Output Decoupling Recommendation:
SSID = CPU
VCC_GFXCORE
2 x 470 uF at Bottom Socket Edge 2 x 22 uF at Top Socket Cavity 4 x 22 uF at Top Socket Edge 2 x 22 uF at Bottom Socket Cavity 4 x 22 uF at Bottom Socket Edge
PROCESSOR VAXG: 24A
D D
12
C901
C901
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C907
C907
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C C
Disabling Guidelines for External Graphics Designs: Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed. Can be left floating (Gfx VR keeps VAXG rail from floating)
B B
if the VR is stuffed
12
12
12
C903
C903
C902
C902
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C918
C918
C908
C908
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1D8V_S0
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCCPLL Output Decoupling Recommendation: 1 x 330 uF 2 x 1 uF 1 x 10 uF
4
12
12
12
C904
C904
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C919
C919
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C905
C905
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C920
C920
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C906
C906
C921
C921
PROCESSOR VCCPLL: 1.2A
12
12
C925
C925
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C923
C923
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
C922
C922
SC1U10V2KX-1GP
SC1U10V2KX-1GP
3
POWER
CPU1G
CPU1G
AT24
VAXG
AT23
VAXG
AT21
VAXG
AT20
VAXG
AT18
VAXG
AT17
VAXG
AR24
VAXG
AR23
VAXG
AR21
VAXG
AR20
VAXG
AR18
VAXG
AR17
VAXG
AP24
VAXG
AP23
VAXG
AP21
VAXG
AP20
VAXG
AP18
VAXG
AP17
VAXG
AN24
VAXG
AN23
VAXG
AN21
VAXG
AN20
VAXG
AN18
VAXG
AN17
VAXG
AM24
VAXG
AM23
VAXG
AM21
VAXG
AM20
VAXG
AM18
VAXG
AM17
VAXG
AL24
VAXG
AL23
VAXG
AL21
VAXG
AL20
VAXG
AL18
VAXG
AL17
VAXG
AK24
VAXG
AK23
VAXG
AK21
VAXG
AK20
VAXG
AK18
VAXG
AK17
VAXG
AJ24
VAXG
AJ23
VAXG
AJ21
VAXG
AJ20
VAXG
AJ18
VAXG
AJ17
VAXG
AH24
VAXG
AH23
VAXG
AH21
VAXG
AH20
VAXG
AH18
VAXG
AH17
VAXG
B6
VCCPLL
A6
VCCPLL
A2
12
C924
C924
VCCPLL
SANDY
SANDY
POWER
SANDY
SANDY
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
SENSE
SENSE
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
7 OF 9
7 OF 9
VAXG_SENSE
VSSAXG_SENSE
LINES
LINES
SM_VREF
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA
VCCSA_SENSE
FC_C22
VCCSA_VID1
AK35 AK34
VCC_AXG_SENSE 42 VSS_AXG_SENSE 42
Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation.
+V_SM_VREF_CNT should have 10 mil trace width
+V_SM_VREF_CNT
AL1
Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.
AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C909
C909
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
+V_SM_VREF_CNT 37
PROCESSOR VDDQ: 10A
C910
C910
PROCESSOR VCCSA: 6A
12
C916
C916
M27 M26 L26 J26 J25 J24 H26 H25
H23
C22 C24
RN901
RN901 SRN1KJ-7-GP
SRN1KJ-7-GP
VCCSA_SENSE
H_FC_C22 VCCSA_SEL
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
0D85V_S0
12
1
23
4
R902
R902 10R2J-2-GP
10R2J-2-GP
H_FC_C22 48 VCCSA_SEL 48
2
R906,R907 close to CPU
1D5V_S0
12
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C911
C911
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C915
C915
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C912
C912
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
0D85V_S0
12
C917
C917
R902 need be close to pin H23.
VCCSA_SENSE 48
12
12
12
C914
C914
C913
C913
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VDDQ Output Decoupling Recommendation: 1 x 330 uF 6 x 10 uF
TC903
TC903 ST330U2VDM-4-GP
ST330U2VDM-4-GP
VCCSA Output Decoupling Recommendation: 1 x 330 uF 2 x 10 uF at Bottom Socket Cavity 1 x 10 uF at Bottom Socket Edge
VCC_GFXCORE
VCC_AXG_SENSE VSS_AXG_SENSE
S-HR_20100609 V1.0
1
12
12
R906
R906 100R2F-L1-GP-U
100R2F-L1-GP-U
R907
R907 100R2F-L1-GP-U
100R2F-L1-GP-U
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (VCC_GFXCORE)
CPU (VCC_GFXCORE)
CPU (VCC_GFXCORE)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
of
994
of
994
of
994
-1
-1
-1
5
4
3
2
1
SSID = CPU
9 OF 9
8 OF 9
CPU1H
CPU1H
AT35
VSS
AT32
VSS
AT29
VSS
AT27
VSS
AT25
VSS
AT22
VSS
D D
C C
B B
AT19 AT16 AT13 AT10
AT7 AT4
AT3 AR25 AR22 AR19 AR16 AR13 AR10
AR7
AR4
AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10
AP7
AP4
AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10
AN7
AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10
AM7 AM4 AM3 AM2
AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10
AL7 AL4
AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10
AK7
AK4
AJ25
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
SANDY
SANDY
VSS
VSS
8 OF 9
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2
M34
H33 H30 H27 H24 H21 H18 H15 H13 H10
G35 G32 G29 G26 G23 G20 G17 G11
T35 T34 T33 T32 T31 T30 T29 T28 T27 T26
N35 N34 N33 N32 N31 N30 N29 N28 N27 N26
L33 L30 L27
K35 K32 K29 K26 J34 J31
F34 F31 F29
CPU1I
CPU1I
SANDY
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
P9
VSS
P8
VSS
P6
VSS
P5
VSS
P3
VSS
P2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
L9
VSS
L8
VSS
L6
VSS
L5
VSS
L4
VSS
L3
VSS
L2
VSS
L1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
H9
VSS
H8
VSS
H7
VSS
H6
VSS
H5
VSS
H4
VSS
H3
VSS
H2
VSS
H1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
SANDY
VSS
VSS
9 OF 9
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3
SANDY
SANDY
SANDY
A A
5
4
3
SANDY
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
2
Date: Sheet
CPU (VSS)
CPU (VSS)
CPU (VSS)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Taipei Hsien 221, Taiwan, R.O.C.
of
10 94
of
10 94
of
10 94
1
-1
-1
-1
5
4
3
2
1
D D
12
DY
DY
R1110
R1110 200R2J-L1-GP
200R2J-L1-GP
PCH_TCK21
PCH_TMS21 PCH_TDI21
PCH_TDO21
XDP_DBRESET#5,19
PCIE_CLK_XDP_N7,20
PCIE_CLK_XDP_P7,20
XDP_PRDY#5
XDP_PREQ#5
C C
1
TP1101TP1101
1
TP1102TP1102
1
CFG07
TP1103TP1103
1
TP1104TP1104
1
TP1105TP1105
PM_RSMRST#19
R1124 1KR2J-1-GP
R1124 1KR2J-1-GP
1 2
DY
DY
R1123 1KR2J-1-GP
R1123 1KR2J-1-GP
1 2
DY
DY
12
DY
DY
R1116
R1116 100R2J-2-GP
100R2J-2-GP
12
DY
DY
R1111
R1111 200R2J-L1-GP
200R2J-L1-GP
12
DY
DY
R1117
R1117 100R2J-2-GP
100R2J-2-GP
12
12
DEBUG Interface for Processor.
CPU XDP SFF 26pin IF Pin 1 OBSFN_A0 (PREQ#, I/O) Pin 2 OBSFN_A1 (PRDY#, I/O) Pin 3 GND Pin 4 OBSDATA_A0 (Open, I/O)
B B
A A
Pin 5 OBSDATA_A1 (Open, I/O) Pin 6 GND Pin 7 OBSDATA_A2 (Open, I/O) Pin 8 OBSDATA_A3 (Open, I/O) Pin 9 GND Pin 10 HOOK0 (PWRGD, In) Pin 11 HOOK1 (BP_PWRGD_RST#, Out) Pin 12 HOOK2 (CFG0, Out) Pin 13 HOOK3 (vr_READYSYS_PWROK,Out) Pin 14 HOOK4 (BCLK, In) Pin 15 HOOK5 (BCLK#, In) Pin 16 VCCOBS_AB (VCCP Voltage of CPU, In) Pin 17 HOOK6 (RESET#, Out) Pin 18 HOOK7 (DBR#, Out) Pin 19 GND Pin 20 TDO, In Pin 21 TRST#, Out Pin 22 TDI, Out Pin 23 TMS, Out Pin 24 TCK1 (Open) Pin 25 GND Pin 26 TCK0 ,Out
TABLE
PCH PIN
TDO
TMS
TDI
TCK
TRST#
REF DES
R1110 R1116 R2 R1112 R1118 R91 R1111 R1117 R90 R541 R953 R535 R103
PCH ES1 JTAG
Enable EnableDisable Disable
DY DY DY DY DY DY 51 Ohms
200 Ohms
DY DY 200 Ohms 100 Ohms
DY DY 51 Ohms 51 Ohms 20K Ohms 10K Ohms
DY DY
DY DY
DY DY
20K Ohms 10K Ohms
DY DY
PCH ES2 JTAG
200 Ohms 100 Ohms
200 Ohms
100 Ohms100 Ohms
DY DY 200 Ohms 100 Ohms
51 Ohms 51 Ohms
DY
DY
DY DY
DY DY
DY DY
DY DY DYDY
DY DY
PRODUCTION
Enable Disable
DY DY
DY DY
51 Ohms
DY
DY 51 Ohms 51 Ohms
DY
DY
DY
DY DY DY DY DY DY DY DY DY
51 Ohms
DY DY DY
3D3V_S53D3V_S5
DY
DY
R1112
R1112 200R2J-L1-GP
200R2J-L1-GP
DY
DY
R1118
R1118 100R2J-2-GP
100R2J-2-GP
XDP1102
XDP1102
28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2
1
27
MLX-CON26-8-GP
MLX-CON26-8-GP
DY
DY
DEBUG Interfac e for PCH.
PCH XDP SFF 26pin IF Pin 1 OBSFN_A0 (Open), I/O) Pin 2 OBSFN_A1 (Open, I/O) Pin 3 GND Pin 4 OBSDATA_A0 (Open, I/O) Pin 5 OBSDATA_A1 (Open, I/O) Pin 6 GND Pin 7 OBSDATA_A2 (Open, I/O) Pin 8 OBSDATA_A3 (Open, I/O) Pin 9 GND Pin 10 HOOK0 (RSMRST#, In) Pin 11 HOOK1 (BP_PWRGD_RST#, Out) Pin 12 HOOK2 (Open) Pin 13 HOOK3 (Open) Pin 14 HOOK4 (Open) Pin 15 HOOK5 (Open) Pin 16 VCCOBS_AB (3.3VSUS, In) Pin 17 HOOK6 (RSMRST#, Out) Pin 18 HOOK7 (DBR#, Out) Pin 19 GND Pin 20 TDO (JTAG, In) Pin 21 TRST# (Open) Pin 22 TDI (JTAG, Out) Pin 23 TMS (JTAG, Out) Pin 24 TCK1 (Open) Pin 25 GND Pin 26 TCK0 (JTAG, Out)
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
LOGIC
5
4
3
2
Title
Title
Title
XDP CONN
XDP CONN
XDP CONN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
-1
-1
of
11 94Tuesday, January 18, 2011
of
11 94Tuesday, January 18, 2011
of
11 94Tuesday, January 18, 2011
-1
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
5
4
3
Date: Sheet
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
12 94Tuesday, January 18, 2011
12 94Tuesday, January 18, 2011
12 94Tuesday, January 18, 2011
1
-1
-1
-1
of
of
of
A
4 4
3 3
B
C
D
E
BLANK
2 2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
1 1
Title
Title
Title
CLOCK GEN
CLOCK GEN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
A
B
C
Date: Sheet
D
CLOCK GEN
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
13 94Tuesday, January 18, 2011
13 94Tuesday, January 18, 2011
13 94Tuesday, January 18, 2011
of
of
of
E
-1
-1
-1
5
SSID = MEMORY
DDR_VREF_S3
20100706
12
R1405
R1405 0R2J-2-GP
0R2J-2-GP
D D
M_VREF_CA_DIMM0
12
12
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DDR_VREF_S3
12
M_VREF_DQ_DIMM0
12
C C
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
B B
A A
C1423
C1423
20100706
R1404
R1404 0R2J-2-GP
0R2J-2-GP
C1411
C1411
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
12
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
0D75V_S0
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DY
DY
C1425
C1425
DY
DY
C1412
C1412
12
C1419
C1419
C1424
C1424
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C1413
C1413
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Place these caps close to VTT1 and VTT2.
12
DY
DY
C1420
C1420
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
5
12
C1421
C1421
M_A_A[15:0] 6
M_A_BS26 M_A_BS06
M_A_BS16
M_A_DQ[63:0]6
12
12
DY
DY
DY
DY
C1422
C1422
C1418
C1418
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
M_A_DQS#[7:0] 6 M_A_DQS[7:0] 6
M_A_DIM0_ODT06 M_A_DIM0_ODT16
M_VREF_CA_DIMM07 M_VREF_DQ_DIMM07,37
DDR3_DRAMRST#15,37
M_VREF_CA_DIMM0 M_VREF_DQ_DIMM0
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7
0D75V_S0
H =9.2mm
4
DM1
DM1
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12
119
A13
80
A14
78
A15
79
A16/BA2
109
BA0
108
BA1
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
10
DQS0#
27
DQS1#
45
DQS2#
62
DQS3#
135
DQS4#
152
DQS5#
169
DQS6#
186
DQS7#
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
116
ODT0
120
ODT1
126
VREF_CA
1
VREF_DQ
30
RESET#
203
VTT1
204
VTT2
DDR3-204P-82-GP
DDR3-204P-82-GP
4
RAS#
WE#
CAS# CS0#
CS1# CKE0
CKE1
CK0#
CK1#
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
SDA
EVENT#
VDDSPD
NC#1 NC#2
NC#/TEST
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8
VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
NP1 NP2
CK0
CK1
SCL
SA0 SA1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
NP1 NP2
110 113 115
114 121
73 74
101 103
102 104
11 28 46 63 136 153 170 187
200 202
198 199 197
201 77
122 125
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206
M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6
M_A_DIM0_CS#0 6 M_A_DIM0_CS#1 6
M_A_DIM0_CKE0 6 M_A_DIM0_CKE1 6
M_A_DIM0_CLK_DDR0 6 M_A_DIM0_CLK_DDR#0 6
M_A_DIM0_CLK_DDR1 6 M_A_DIM0_CLK_DDR#1 6
TS#_DIMM0_1 15
SA0_DIM0 SA1_DIM0
3
PCH_SMBDATA 15,20,65,66 PCH_SMBCLK 15,20,65,66
1D5V_S3
3
12
C1401
C1401 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1D5V_S3
ST330U2VDM-4-GP
ST330U2VDM-4-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3D3V_S0
12
12
DY
DY
12
C1402
C1402 SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
TC1401
TC1401
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C1414
C1414
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
SA0_DIM0 SA1_DIM0
12
R1401
R1401 10KR2J-3-GP
10KR2J-3-GP
12
R1402
R1402 10KR2J-3-GP
10KR2J-3-GP
Thermal EVENT
TS#_DIMM0_1
R1403 10KR2J-3-GPR1403 10KR2J-3-GP
1 2
1
Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30
If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32
3D3V_S0
SODIMM A DECOUPLING
12
12
12
C1403
C1403
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C1415
C1415
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1404
C1404
C1416
C1416
DY
DY
C1405
C1405
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C1417
C1417
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
C1407
C1407
C1406
C1406
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Layout Note: Place these Caps near SO-DIMMA.
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom Date: Sheet
Date: Sheet
Date: Sheet
12
12
12
12
DY
DY
C1408
C1408
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
12
DY
DY
DY
DY
C1409
C1409
C1410
C1410
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H s ichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
DDR3-SODIMM1
DDR3-SODIMM1
DDR3-SODIMM1
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
of
14 94
of
14 94
of
14 94
-1
-1
-1
5
SSID = MEMORY
M_B_A[15:0] 6
D D
C1521
C1521
M_B_DQ[63:0]6
M_VREF_CA_DIMM17
M_VREF_DQ_DIMM17
DDR3_DRAMRST#14,37
M_B_BS26 M_B_BS06
M_B_BS16
M_B_DQS#[7:0] 6 M_B_DQS[7:0] 6
M_B_DIM0_ODT06 M_B_DIM0_ODT16
M_VREF_CA_DIMM1 M_VREF_DQ_DIMM1
DDR_VREF_S3
R1504
R1504 0R2J-2-GP
0R2J-2-GP
1 2
M_VREF_CA_DIMM1
12
12
C1523
C1523
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
C C
DDR_VREF_S3
R1503
R1503 0R2J-2-GP
0R2J-2-GP
1 2
M_VREF_DQ_DIMM1
12
C1515
C1515
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
B B
0D75V_S0
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
A A
DY
DY
C1524
C1524
12
DY
DY
C1516
C1516
12
DY
DY
C1518
C1518
12
C1522
C1522
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C1517
C1517
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Place these caps close to VTT1 and VTT2.
12
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
5
C1519
C1519
DY
DY
C1520
C1520
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
4
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
0D75V_S0
H = 5.2mm
4
DM2
DM2
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12
119
A13
80
A14
78
A15
79
A16/BA2
109
BA0
108
BA1
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
10
DQS0#
27
DQS1#
45
DQS2#
62
DQS3#
135
DQS4#
152
DQS5#
169
DQS6#
186
DQS7#
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
116
ODT0
120
ODT1
126
VREF_CA
1
VREF_DQ
30
RESET#
203
VTT1
204
VTT2
DDR3-204P-83-GP
DDR3-204P-83-GP
62.10017.T91
62.10017.T91
RAS# CAS# CS0#
CS1# CKE0
CKE1
CK0#
CK1#
EVENT#
VDDSPD
NC#1 NC#2
NC#/TEST
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8
VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
NP1 NP2
WE#
CK0
CK1
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
SDA SCL
SA0 SA1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
NP1 NP2
110 113 115
114 121
73 74
101 103
102 104
11 28 46 63 136 153 170 187
200 202
198 199 197
201 77
122 125
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206
SA0_DIM1 SA1_DIM1
1D5V_S3
3
M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6
M_B_DIM0_CS#0 6 M_B_DIM0_CS#1 6
M_B_DIM0_CKE0 6 M_B_DIM0_CKE1 6
M_B_DIM0_CLK_DDR0 6 M_B_DIM0_CLK_DDR#0 6
M_B_DIM0_CLK_DDR1 6 M_B_DIM0_CLK_DDR#1 6
PCH_SMBDATA 14,20,65,66 PCH_SMBCLK 14,20,65,66
TS#_DIMM0_1 14
3
12
C1501
C1501 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Layout Note: Place these Caps near SO-DIMMB.
1D5V_S3
2
3D3V_S0
DY
DY
12
C1502
C1502 SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
SODIMM B DECOUPLING
12
12
DY
DY
C1503
C1503
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C1511
C1511
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
DY
DY
C1504
C1504
C1512
C1512
1
3D3V_S0
12
R1501
R1501 10KR2J-3-GP
10KR2J-3-GP
SA1_DIM1 SA0_DIM1
12
R1502
R1502 10KR2J-3-GP
10KR2J-3-GP
12
12
C1505
C1505
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C1513
C1513
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C1506
C1506
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C1514
C1514
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34
SO-DIMMB is placed farther from the Processor than SO-DIMMA
12
12
DY
DY
C1508
C1508
C1507
C1507
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C1509
C1509
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
DDR3-SODIMM2
DDR3-SODIMM2
DDR3-SODIMM2
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
12
DY
DY
C1510
C1510
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1
of
15 94
of
15 94
of
15 94
-1
-1
-1
5
D D
4
3
2
1
C C
B B
A A
5
(Blanking)
4
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
DDR3-SODIMM2
DDR3-SODIMM2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A4
A4
A4
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
3
Date: Sheet
2
DDR3-SODIMM2
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
16 94
16 94
16 94
-1
-1
of
of
of
1
-1
5
D D
3D3V_S0
RN1701
RN1701
1 2 3
SRN2K2J-1-GP
SRN2K2J-1-GP
RN1702
RN1702
1 2 3
SRN100KJ-6-GP
SRN100KJ-6-GP
4
4
L_CTRL_DATA L_CTRL_CLK
L_BKLT_EN LVDS_VDD_EN
L_DDC_DATA(PAGE17): This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display
Place near PCH
C C
Impedance:90 ohm
Close to PCH side
CRT_RED CRT_GREEN CRT_BLUE
B B
678
RN1705
RN1705 SRN150F-1-GP
SRN150F-1-GP
123
4 5
4
12
R1701
R1701 2K37R2F-GP
2K37R2F-GP
3
4 OF 10
PCH1D
PCH1D
L_BKLT_EN27 LVDS_VDD_EN49
L_BKLT_CTRL49 LVDS_DDC_CLK49
LVDS_DDC_DATA49
TP1701TPAD14-GP TP1701TPAD14-GP
LVDSA_CLK#49 LVDSA_CLK49
LVDSA_DATA0#49 LVDSA_DATA1#49 LVDSA_DATA2#49
LVDSA_DATA049 LVDSA_DATA149 LVDSA_DATA249
CRT_DDC_CLK50
CRT_DDC_DATA50
L_CTRL_CLK L_CTRL_DATA
LVDS_IBG LVDS_VBG
1
CRT_BLUE50
CRT_GREEN50
CRT_RED50
CRT_HSYNC50
CRT_VSYNC50
DAC_IREF_R
12
R1702
R1702 1KR2D-1-GP
1KR2D-1-GP
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
Cougar
Cougar Point
Point
LVDS
LVDS
CRT
CRT
Digital Display Interface
Digital Display Interface
4 OF 10
SDVO_TVCLKINN SDVO_TVCLKINP
SDVO_STALLN SDVO_STALLP
SDVO_INTN SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN DDPB_AUXP
DDPB_HPD
DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN DDPC_AUXP
DDPC_HPD
DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN DDPD_AUXP
DDPD_HPD
DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P
AP43 AP45
AM42 AM40
AP39 AP40
P38 M39
AT49 AT47 AT40
AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49
P46 P42
AP47 AP49 AT38
AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49
M43 M36
AT45 AT43 BH41
BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42
DDBP_DATA2# DDBP_DATA2 DDBP_DATA1# DDBP_DATA1 DDBP_DATA0# DDBP_DATA0 DDBP_CLK# DDBP_CLK
2
3D3V_S0
4
RN1706
RN1706 SRN2K2J-1-GP
SRN2K2J-1-GP
1
2 3
PCH_HDMI_CLK 51 PCH_HDMI_DATA 51
C1708 SCD1U10V2KX-5GPC1708 SCD1U10V2KX-5GP
1 2
C1707 SCD1U10V2KX-5GPC1707 SCD1U10V2KX-5GP
1 2
C1706 SCD1U10V2KX-5GPC1706 SCD1U10V2KX-5GP
1 2
C1705 SCD1U10V2KX-5GPC1705 SCD1U10V2KX-5GP
1 2
C1704 SCD1U10V2KX-5GPC1704 SCD1U10V2KX-5GP
1 2
C1703 SCD1U10V2KX-5GPC1703 SCD1U10V2KX-5GP
1 2
C1702 SCD1U10V2KX-5GPC1702 SCD1U10V2KX-5GP
1 2
C1701 SCD1U10V2KX-5GPC1701 SCD1U10V2KX-5GP
1 2
DDI Port B Detect:(SDVO_CTRL_ DATA) 1: Port B detected 0: Port B not detected
Close to level shifter side
Impedance:90 ohm
1
PCH_HDMI_DET 51 HDMI_DATA2_R# 51
HDMI_DATA2_R 51
HDMI_DATA1_R# 51
HDMI_DATA1_R 51
HDMI_DATA0_R# 51
HDMI_DATA0_R 51
HDMI_CLK_R# 51
HDMI_CLK_R 51
Impedance:100 ohm
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
PCH (LVDS/CRT/DDI)
PCH (LVDS/CRT/DDI)
PCH (LVDS/CRT/DDI)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Taipei Hsien 221, Taiwan, R.O.C.
of
17 94
of
17 94
of
17 94
1
-1
-1
-1
5
4
3
2
1
SSID = PCH
3D3V_S0 3D3V_S0
RN1801
D D
SATA_ODD_DA# INT_PIRQD# INT_PIRQB# BDC_PRESENCE#
R1801 4K7R2J-2-GP
R1801 4K7R2J-2-GP
A16 swap override Strap/Top-Block Swap Override jumper
PCI_GNT#3 Low = A16 swap
C C
R1802 1KR2J-1-GP
R1802 1KR2J-1-GP
1 2
R1803 1KR2J-1-GP
R1803 1KR2J-1-GP
1 2
RN1801
1 2 3 4 5 6
SRN8K2J-2-GP-U
SRN8K2J-2-GP-U
DY
DY
12
override/Top-Block Swap Override enabled High = Default
DY
DY
DY
DY
10
LCD_PRESENCE#
9 8 7
PCI_GNT3#
BBS_BIT1 BBS_BIT0
WWAN_IN INT_PIRQA# INT_PIRQC#
USB_OC#0_1 USB_OC#12_13 USB_OC#8_9 USB_OC#6_7 USB_OC#2_3
BBS_BIT0 21
BOOT BIOS Strap
GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19
0 0 LPC
0 1 Reserved
01
B B
A A
11
5
Reserved
SPI(Default)
CLK_PCI_LPC65,71 CLK_PCI_FB20 CLK_PCI_KBC27
3D3V_S5 3D3V_S5
RN1802
RN1802
1 2 3 4 5 6
SRN8K2J-2-GP-U
SRN8K2J-2-GP-U
DGPU_HOLD_RST# DGPU_PWR_EN#
DGPU_HOLD_RST#83
DGPU_PWR_EN#93
TP1804TP1804
LCD_PRESENCE#49 SATA_ODD_DA#56 BDC_PRESENCE#63 WWAN_IN66
R1804 22R2J-2-GPR1804 22R2J-2-GP R1805 22R2J-2-GPR1805 22R2J-2-GP R1806 0R2J-2-GPR1806 0R2J-2-GP
DY
DY
EC1802
EC1802 SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
1 2
KBC CLK EMI
4
10
PCH_GPIO14
9 8
USB_OC#10_11
7
LAN_PWR_ON
RN1803
RN1803
1 2 3
SRN10KJ-5-GP
SRN10KJ-5-GP
3D3V_S0
R1814
R1814 8K2R2J-3-GP
8K2R2J-3-GP
1 2
DGPU_PWM_SELECT#
1
TP1801TP1801
TP1806TP1806
1 2 1 2 1 2
DY
DY
EC1801
EC1801 SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
1 2
PLT_RST#5,27,32,36,65,66,71,80,82,83
4
DGPU_SELECT# DGPU_PWR_EN#
1
LCD_PRESENCE# SATA_ODD_DA# BDC_PRESENCE#
1
CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R
12
DY
DY
R1816
R1816 100KR2J-1-GP
100KR2J-1-GP
INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#
BBS_BIT1 PCI_GNT3#
PCI_PME# PCI_PLTRST#
3D3V_S0
DY
DY
PCH1E
PCH1E
Cougar
BG26
BJ26
BH25
BJ16 BG16 AH38 AH37 AK43 AK45
C18 N30
H3
AH12
AM4 AM5
Y13 K24
L24 AB46 AB45
B21
M20 AY16 BG46
BE28 BC30 BE32
BJ32 BC28 BE30
BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28
AW30
K40 K38
H38
G38
C46 C44 E40
D47 E42 F46
G42 G40
C42 D44
K10
C6
H49 H43
J48 K42 H40
DY
DY
5
4
73.01G08.L04
73.01G08.L04
2ND = 73.7SZ08.DAH
2ND = 73.7SZ08.DAH
R1807 0R2J-2-GPR1807 0R2J-2-GP
12
C1801
C1801 SC220P50V2KX-3GP
SC220P50V2KX-3GP
Cougar
TP1
Point
Point
TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20
TP21 TP22 TP23 TP24
TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40
PIRQA# PIRQB# PIRQC# PIRQD#
REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54
GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55
PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
PME# PLTRST#
CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
U1801
U1801
B
VCC
A
Y
GND
74LVC1G08GW-1-GP
74LVC1G08GW-1-GP
1 2
3
5 OF 10
5 OF 10
AY7
RSVD
AV7
RSVD
AU3
RSVD
BG4
RSVD
AT10
RSVD
BC8
RSVD
AU2
RSVD
AT4
RSVD
AT3
RSVD
AT1
RSVD
AY3
RSVD
AT5
RSVD
AV3
RSVD
AV1
RSVD
BB1
RSVD
BA3
RSVD
BB5
NVRAM
NVRAM
RSVD
RSVD
PCI
PCI
USB
USB
1 2 3
PCI_PLTRST#
12
RSVD RSVD RSVD RSVD RSVD RSVD
RSVD
DF_TVS
RSVD RSVD RSVD
RSVD RSVD
RSVD
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P
USBRBIAS#
USBRBIAS
OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43
OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14
DY
DY
C1802
C1802 SC220P50V2KX-3GP
SC220P50V2KX-3GP
BB3 BB7 BE8 BD4 BF6
NV_ALE
AV5
NV_CLE
AY1 AV10 AT8 AY5
BA2 AT12
BF3
C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32
USB_RBIAS
C33
B33
A14 K20 B17 C16 L16 A16 D14 C14
OC[3:0]# for Device 29 (Ports 0-7) OC[7:4]# for Device 26 (Ports 8-13)
R1811 22D6R2F-L1-GPR1811 22D6R2F-L1-GP
1 2
USB_OC#0_1 USB_OC#2_3 LAN_PWR_ON USB_OC#6_7 USB_OC#8_9 USB_OC#10_11 USB_OC#12_13 PCH_GPIO14
2
USB_PN1 61 USB_PP1 61 USB_PN2 69 USB_PP2 69 USB_PN3 63 USB_PP3 63 USB_PN4 66 USB_PP4 66
USB_PN8 57 USB_PP8 57 USB_PN9 61 USB_PP9 61 USB_PN10 82 USB_PP10 82 USB_PN11 65 USB_PP11 65 USB_PN12 49 USB_PP12 49 USB_PN13 82 USB_PP13 82
USB_OC#0_1 61 LAN_PWR_ON 31 USB_OC#8_9 57,61
USB_OC#10_11 82
Danbury Technology: Disabled when Low. Enable when High.
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
NV_CLE
DMI & FDI Termination Voltage
NV_CLE
Pair
0
1
2
3
4
5
6
7
8
9
10
11
12
13
PCH (PCI/USB/NVRAM)
PCH (PCI/USB/NVRAM)
PCH (PCI/USB/NVRAM)
+V_NVRAM_VCCQ
12
R1808
R1808 2K2R2J-2-GP
2K2R2J-2-GP
R1809
R1809
1 2
1KR2J-1-GP
1KR2J-1-GP
H_SNB_IVB# 5
Set to Vss when LOW
Set to Vcc when HIGH
+V_NVRAM_VCCQ
NV_ALE
USB
Device
X
USB2
FINGERPRINT
BLUETOOTH
Mini Card2 (WWAN)
X
X
X
ESATA1
USB1
USB Ext. port 4
Mini Card1 (WLAN)
CAMERA
New Card
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
of
18 94Tuesday, January 18, 2011
of
18 94Tuesday, January 18, 2011
of
18 94Tuesday, January 18, 2011
12
DY
DY
R1810
R1810 1KR2J-1-GP
1KR2J-1-GP
-1
-1
-1
5
4
3
2
1
SSID = PCH
D D
DY
DY
R1926
R1926 10KR2J-3-GP
10KR2J-3-GP
1 2
C C
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
B B
A A
Signal Routing Guideline: DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.
PWROKSYS_PWROK
R1904
R1904 100KR2J-1-GP
100KR2J-1-GP
1 2
XDP_DBRESET#5,11
SYS_PWROK36
R1924 0R2J-2-GPR1924 0R2J-2-GP
S0_PWR_GOOD27,36 D85V_PWRGD42,48
RUNPWROK36,37,45,46,47
PM_DRAM_PWRGD5,37
SUS_PWR_ACK27
PM_PWRBTN#27
AC_PRESENT27
3D3V_S5
R1921 10KR2J-3-GPR1921 10KR2J-3-GP
DY
DY
R1922 10KR2J-3-GP
R1922 10KR2J-3-GP R1920 10KR2J-3-GPR1920 10KR2J-3-GP
1 2
R1927 0R2J-2-GPR1927 0R2J-2-GP
1 2
RN1901
RN1901
8 7 6
SRN10KJ-6-GP
SRN10KJ-6-GP
12 12 12
Need Check!!
R1908 10KR2J-3-GPR1908 10KR2J-3-GP
5
12
1D05V_VTT
1 2 3 45
DMI_RXN[3..0]4 DMI_RXP[3..0]4
DMI_TXN[3..0]4 DMI_TXP[3..0]4
R1901 49D9R2F-GPR1901 49D9R2F-GP
1 2
R1902 750R2F-GPR1902 750R2F-GP
1 2
3D3V_S0
R1903 0R2J-2-GP
R1903 0R2J-2-GP
1 2
R1925 0R2J-2-GP
R1925 0R2J-2-GP
1 2
R1905 10KR2J-3-GPR1905 10KR2J-3-GP
1 2
R1923 0R2J-2-GP
R1923 0R2J-2-GP
1 2
R1906 0R2J-2-GPR1906 0R2J-2-GP
1 2
R1907 0R2J-2-GP
R1907 0R2J-2-GP
1 2
PM_RSMRST#11
AC_PRESENT SUS_PWR_ACK
PCIE_WAKE# PM_PWRBTN# PM_SLP_LAN#
PM_RSMRST#
PEG_B_CLK_RQ# 20
DMI_RXN34 DMI_RXN24 DMI_RXN14 DMI_RXN04
DMI_RXP34 DMI_RXP24 DMI_RXP14 DMI_RXP04
DMI_TXN34 DMI_TXN24 DMI_TXN14 DMI_TXN04
DMI_TXP34 DMI_TXP24 DMI_TXP14 DMI_TXP04
DMI_COMP_R
RBIAS_CPY
DY
BATLOW#20
DY DY
DY
DY
DY
DY
DY
PM_RI#20
SUSACK#SUS_PWR_ACK
SYS_RESET#
PWROK
MEPWROK
PM_RSMRST#
SUS_PWR_ACK
AC_PRESENT
PCIE_WAKE# CRB : 1K CEKLT: 10K
PM_RSMRST# CRB : PL 10K ANNIE : PL 100K
4
PCH1C
PCH1C
BC24
DMI0RXN
Cougar
BE20 BG18 BG20
BE24 BC20
BJ18 BJ20
AW24 AW20
BB18 AV18
AY24 AY20 AY18 AU18
BJ24 BG25 BH21
C12
K3
P12
L22
L10
B13
C21
K16
E20
H20
E10
A10
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
Cougar
DMI1RXN
Point
Point
DMI2RXN DMI3RXN
DMI0RXP DMI1RXP DMI2RXP DMI3RXP
DMI0TXN DMI1TXN DMI2TXN DMI3TXN
DMI0TXP DMI1TXP DMI2TXP DMI3TXP
DMI_ZCOMP DMI_IRCOMP DMI2RBIAS
SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#
SUSWARN#/SUSPWRDNACK/GPIO30
PWRBTN#
ACPRESENT/GPIO31
BATLOW#/GPIO72
RI#
FDI_TXN[7:0] 4 FDI_TXP[7:0] 4
3 OF 10
3 OF 10
BJ14
FDI_RXN0
AY14
FDI_RXN1
BE14
FDI_RXN2
BH13
FDI_RXN3
BC12
FDI_RXN4
BJ12
FDI_RXN5
BG10
FDI_RXN6
BG9
FDI_RXN7
BG14
FDI_RXP0
BB14
FDI_RXP1
BF14
FDI_RXP2
BG13
FDI_RXP3
BE12
FDI_RXP4
BG12
FDI_RXP5
BJ10
DMI
DMI
System Power Management
System Power Management
3D3V_AUX_S5
FDI_RXP6
FDI
FDI
FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1
DSWVRMEN
CLKRUN#/GPIO32
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
SLP_LAN#/GPIO29
R1909 100KR2J-1-GPR1909 100KR2J-1-GP
12
R1916
R1916 10KR2J-3-GP
10KR2J-3-GP
3V_5V_POK_#
BH9
FDI_RXP7
AW16
FDI_INT
AV12 BC10 AV14 BB10
A18
E22
DPWROK
B9
WAKE#
N3
G8
N14
D10
H4
SLP_S4#
F4
SLP_S3#
G10
SLP_A#
G16
SLP_SUS#
AP14
PMSYNCH
K14
1 2
2nd = 84.DM601.03F
2nd = 84.DM601.03F
3
5 6
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
DSWODVREN
PCH_DPWROK
PCIE_WAKE#
PM_CLKRUN#
PM_SUS_STAT#
SUS_CLK
PM_SLP_S5#
SLP_S4#_R
SLP_S3#_R
PM_SLP_A#
PM_SLP_SUS#
H_PM_SYNC
PM_SLP_LAN#
Q1901
Q1901
34 2 1
FDI_TXN7 4 FDI_TXN6 4 FDI_TXN5 4 FDI_TXN4 4 FDI_TXN3 4 FDI_TXN2 4 FDI_TXN1 4 FDI_TXN0 4
FDI_TXP7 4 FDI_TXP6 4 FDI_TXP5 4 FDI_TXP4 4 FDI_TXP3 4 FDI_TXP2 4 FDI_TXP1 4 FDI_TXP0 4
FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4
DY
DY
R1911 10KR2J-3-GP
R1911 10KR2J-3-GP
1 2
R1910 0R2J-2-GPR1910 0R2J-2-GP
1 2
PCIE_WAKE# 65,82
PM_CLKRUN# 27
1
TP1901 TPAD14-GPTP1901 TPAD14-GP
R1913 0R2J-2-GPR1913 0R2J-2-GP
1 2
TP1902 TPAD14-GPTP1902 TPAD14-GP
1
R1914 0R2J-2-GPR1914 0R2J-2-GP
1 2
R1915 0R2J-2-GPR1915 0R2J-2-GP
1 2
TP1903TPAD14-GPTP1903TPAD14-GP
1
TP1904TPAD14-GPTP1904TPAD14-GP
1
TP1905TPAD14-GPTP1905TPAD14-GP
1
PM_RSMRST#
R1912 1KR2J-1-GPR1912 1KR2J-1-GP
1 2
3V_5V_POK 41
For platforms not supporting Deep S4/S5
1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)
2.DPWROK and RSMRST# will rise at the same time (connected on board)
3.SLP_SUS# and SUSACK# are left as ‘no connect’
4.SUSWARN# used as SUSPWRDNACK/GPIO30
RTC_AUX_S5
PM_RSMRST#
PCH_SUSCLK_KBC 27
PM_SLP_S4# 27,46,82
PM_SLP_S3# 27,36,37,47,82
H_PM_SYNC 5
RSMRST#_KBC 27
2
DSWODVREN - On Die DSW VR Enable
HIGH Enabled (DEFAULT)
LOW Disabled
R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP
1 2
DSWODVREN
PM_CLKRUN#
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
R1918 330KR2J-L1-GP
R1918 330KR2J-L1-GP
1 2
DY
DY
R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP
1 2
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
PCH (DMI/FDI/PM)
PCH (DMI/FDI/PM)
PCH (DMI/FDI/PM)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
19 94Tuesday, January 18, 2011
19 94Tuesday, January 18, 2011
19 94Tuesday, January 18, 2011
1
RTC_AUX_S5
3D3V_S0
of
of
of
-1
-1
-1
5
SSID = PCH
PCH1B
TP2004TPAD14-GP TP2004TPAD14-GP
1
TP2005TPAD14-GP TP2005TPAD14-GP
1
TP2006TPAD14-GP TP2006TPAD14-GP
1
TP2007TPAD14-GP TP2007TPAD14-GP
PCIE_RXN282
PCIE_RXP282 PCIE_TXN282 PCIE_TXP282
D D
PCIE_RXN332
PCIE_RXP332 PCIE_TXN332 PCIE_TXP332
PCIE_RXN465
PCIE_RXP465 PCIE_TXN465 PCIE_TXP465
PCIE_RXN882
PCIE_RXP882
PCIE_TXN882 PCIE_TXP882
/$1&/.
PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW. PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN
C C
&$5'5($'(5&/.
PCIE_CLK_LAN_RQ0#82
PCIE_CLK_CR_RQ2#32
:/$1&/.
PCIECLKRQ1# and PCIECLKRQ 2#
3D3V_S0
support S0 power only
B B
PCIE_CLK_WLAN_R Q3#65
RN2018
RN2018
PCIE_CLK_RQ1#
1
4
PCIE_CLK_CR_RQ2#
2 3
SRN10KJ-5-GP
SRN10KJ-5-GP
PCIE_CLK_NEW_R Q5#82
PL 10K FOR Integrated CLOCK GEN mode.
CLK_BUF_REF14 CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P
1
C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP
1 2
C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP
1 2
C2003 SCD1U10V2KX-5GPC2003 SCD1U10V2KX-5GP
1 2
C2004 SCD1U10V2KX-5GPC2004 SCD1U10V2KX-5GP
1 2
C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP
1 2
C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP
1 2
C2009 SCD1U10V2KX-5GPC2009 SCD1U10V2KX-5GP
1 2
C2010 SCD1U10V2KX-5GPC2010 SCD1U10V2KX-5GP
1 2
CLK_PCIE_LAN#82 CLK_PCIE_LAN82
CLK_PCIE_CR#32 CLK_PCIE_CR32
CLK_PCIE_WLAN#65 CLK_PCIE_WLAN65
CLK_PCIE_NEW#82 CLK_PCIE_NEW82
RN2009
RN2009
1 2 3 4 5 6
SRN10KJ-L3-GP
SRN10KJ-L3-GP
need very close to PCH
RN2012 SRN0J-6-GPRN2012 SRN0J-6-GP
2 3 1
1 2 3
RN2015 SRN0J-6-GPRN2015 SRN0J-6-GP
1 2 3
PCIE_CLK_XDP_N7,11 PCIE_CLK_XDP_P7,11
10
CLK_BUF_EXP_N
9
CLK_BUF_EXP_P
8
CLK_BUF_DOT96_N
7
CLK_BUF_DOT96_P
PCIE_RXN1 PCIE_RXP1 PCIE_TXN1_C PCIE_TXP1_C
PCIE_TXN2_C PCIE_TXP2_C
PCIE_TXN3_C PCIE_TXP3_C
PCIE_TXN4_C PCIE_TXP4_C
PCIE_TXN8_C PCIE_TXP8_C
CLK_PCH_SRC0_N
1
4
CLK_PCH_SRC0_P
2 3
PCIE_CLK_LAN_RQ0#
PCIE_CLK_RQ1#
RN2013
RN2013
CLK_PCH_SRC2_N CLK_PCH_SRC2_P
4
PCIE_CLK_CR_RQ2#
SRN0J-6-GP
SRN0J-6-GP RN2014 SRN10J-7-GPRN2014 SRN10J-7-GP
CLK_PCH_SRC3_N
4
CLK_PCH_SRC3_P
PCIE_CLK_WLAN_R Q3#
PCIE_CLK_RQ4#
CLK_PCH_SRC5_N
4
CLK_PCH_SRC5_P
PCIE_CLK_NEW_R Q5#
PEG_B_CLK_RQ#19
PCIE_CLK_RQ6#
PCIE_CLK_RQ7#
PCH1B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0#/GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1#/GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2#/GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3#/GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4#/GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5#/GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ#/GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6#/GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7#/GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
3D3V_S5
Cougar
Cougar Point
Point
LAN
Card Reader
WLAN
NEW CARD
RN2001
RN2001
1 2 3 4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
RN2002
RN2002
1 2 3 4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
8 7 6
8 7 6
SMBUSController
SMBUSController
SML1ALERT#/PCHHOT#/GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
PCIE_CLK_WLAN_R Q3#
PCIE_CLK_RQ7#
PCIE_CLK_NEW_R Q5#
PCIE_CLK_LAN_RQ0#
PCIE_CLK_RQ4#
EC_SWI#
4
SMBALERT#/GPIO11
SML0ALERT#/GPIO60
SML1CLK/GPIO58
SML1DATA/GPIO75
Link
Link
PEG_A_CLKRQ#/GPIO47
CLKOUT_PEG_A_N CLKOUT_PEG_A_P
CLKOUT_DMI_N CLKOUT_DMI_P
CLKOUT_DP_N CLKOUT_DP_P
CLKIN_GND1_N CLKIN_GND1_P
CLKIN_DOT_96N CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
CLKIN_PCILOOPBACK
CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67
FLEX CLOCKS
FLEX CLOCKS
BATLOW# 19
PM_RI# 19
2 OF 10
2 OF 10
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
CLKIN_DMI_N
CLKIN_DMI_P
REFCLK14IN
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
E12
SMB_CLK
H14
SMB_DATA
C9
DRAMRST_CNTRL_PCH
A12
SML0_CLK
C8
SML0_DATA
G12
PCH_GPIO74
C13
SML1_CLK
E14
SML1_DATA
M16
CL_CLK
M7
CL_DATA
T11
CL_RST#
P10
PEG_CLKREQ#_R
M10
CLKOUT_PEG_A_N
AB37
CLKOUT_PEG_A_P
AB38
CLKOUT_DMI_N
AV22
CLKOUT_DMI_P
AU22
CLKOUT_DP_N
AM12
CLKOUT_DP_P
AM13
CLK_BUF_EXP_N
BF18
CLK_BUF_EXP_P
BE18
CLK_BUF_CPYCLK_N
BJ30
CLK_BUF_CPYCLK_P
BG30
CLK_BUF_DOT96_N
G24
CLK_BUF_DOT96_P
E24
CLK_BUF_CKSSCD_N
AK7
CLK_BUF_CKSSCD_P
AK5
CLK_BUF_REF14
K45
H45
XTAL25_IN
V47
XTAL25_OUT
V49
XCLK_RCOMP
Y47
JTAG_TCK
K43
CLK_48_USB30
F47
LAN_25M
H47
DGPU_PRSNT#
K49
EC_SWI# 27
SMB_CLK 80,82 SMB_DATA 80,82
DRAMRST_CNTRL_PCH 37
SML1_CLK 27 SML1_DATA 27
1
TP2001 TPAD14-GPTP2001 TPAD 14-GP
1
TP2002 TPAD14-GPTP2002 TPAD 14-GP
1
TP2003 TPAD14-GPTP2003 TPAD 14-GP
PX
PX
R2003 0R2J-2-GP
R2003 0R2J-2-GP
1 2
RN2016 SRN10J-7-G PRN 2016 SRN 10J-7-GP
1 2 3
RN2010 SRN10J-7-GPRN2010 SRN10J-7-GP
1 2 3
RN2017 SRN0J-6-GP
RN2017 SRN0J-6-GP
1 2 3
DY
DY
2 3 1
R2007 90D9R2F-1-GPR2007 90D9R2F-1-GP
1 2
DY
DY
22R2J-2-GP
1 2
1
1 2
DY
DY
22R2J-2-GP
TP2008 TPAD14-GPTP2008 TPAD 14-GP
22R2J-2-GP
22R2J-2-GP
R2001
R2001
R2015
R2015
4
CLK_PCIE_VGA# 83 CLK_PCIE_VGA 83
4
CLK_EXP_N 5 CLK_EXP_P 5
4
CLK_DP_N_R 5 CLK_DP_P_R 5
RN2011
RN2011
4
SRN10KJ-5-GP
SRN10KJ-5-GP
CLK_PCI_FB 18
+VCCDIFFCLKN
JTAG_TCK_VGA 83,85
For VGA_ 27M
LAN_XI 82
3
PEG_CLKREQ#_R
SMB_DATA
SMB_CLK
PEG_CLKREQ# 85
3D3V_S5 3D3V_S5
12
R2004
R2004 10KR2J-3-GP
10KR2J-3-GP
12
DY
DY
R2005
R2005 10KR2J-3-GP
10KR2J-3-GP
3D3V_S0
RN2007
RN2007
2 3 1
SRN2K2J-1-GP
SRN2K2J-1-GP
6
XTAL25_IN
XTAL25_IN
XTAL25_OUT
3D3V_S0 3D3V_S0
12
R2012
R2012 10KR2J-3-GP
10KR2J-3-GP
12
DY
DY
R2010
R2010 10KR2J-3-GP
10KR2J-3-GP
SMB_CLK SMB_DATA
SML0_DATA SML0_CLK
SML1_CLK SML1_DATA
PCIE_CLK_RQ6# PCH_GPIO74
DRAMRST_CNTRL_PCH
4
2nd = 84.DM601.03F
2nd = 84.DM601.03F
84.2N702.A3F
84.2N702.A3F
2N7002KDW-G P
2N7002KDW-G P
1 2345
Q2001
Q2001
DY
DY
R2008 0R2J-2-GP
R2008 0R2J-2-GP
1 2
R2008 and C2008 CO-LAY
R2006
R2006 1M1R2J-GP
1M1R2J-GP
1 2
12
UMA
UMA
R2013
R2013 10KR2J-3-GP
10KR2J-3-GP
UMA_DIS#
DGPU_PRSNT#
12
PX
PX
R2011
R2011 10KR2J-3-GP
10KR2J-3-GP
1
4
23 23
1
4 2 3
1
4
1
4
2 3
1 2
R2009
R2009
CRB : 1K CEKLT: 10K
PCH_SMBDATA 14,15,65,66
PCH_SMBCLK 14,15,65,66
C2008
C2008
12
SC12P50V2JN-3GP
SC12P50V2JN-3GP
X2001
X2001 XTAL-25MHZ-96GP
XTAL-25MHZ-96GP
1 2
C2007
C2007
12
SC12P50V2JN-3GP
SC12P50V2JN-3GP
UMA_DISCRETE# UMA: 1 1 DIS :0 1 SG(PX) : 0 0 Optimus(Muxless) : 1 0
UMA_DIS# 22
RN2003
RN2003 SRN2K2J-1-GP
SRN2K2J-1-GP RN2004
RN2004 SRN2K2J-1-GP
SRN2K2J-1-GP RN2005
RN2005 SRN2K2J-1-GP
SRN2K2J-1-GP RN2006
RN2006 SRN10KJ-5-GP
SRN10KJ-5-GP
1KR2J-1-GP
1KR2J-1-GP
2
1
Table 20.1- Dual N-Channel MOSFET multi-source
Supplier
PANJIT
A A
DIODES
Descri pt ion L enovo P/N Wi stron P/N
2N7002KDW
N/A 84.2N702.A3F
84.DM601.03F
N/ADMN601DWK-7
84.2N702.E3FNXP N/A2N7002BKS
<Core Design>
<Core Design>
<Core Design>
Wistron Corporat ion
Wistron Corporat ion
Wistron Corporat ion
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
Title
Title
Title
PCH (PCI-E/SMBUS/CLOCK/CL)
PCH (PCI-E/SMBUS/CLOCK/CL)
PCH (PCI-E/SMBUS/CLOCK/CL)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Taipei Hsien 221, Taiw an, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
-1
-1
20 94Tuesday, January 18, 2011
20 94Tuesday, January 18, 2011
20 94Tuesday, January 18, 2011
-1
of
of
of
5
SSID = PCH
RTC_X1
R2101 10MR2J-L-GPR2101 10MR2J-L-GP
1 2
D D
12
C2101
C2101
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
C C
X-32D768KHZ-40GPU
X-32D768KHZ-40GPU
HDA_CODEC_SYNC29 HDA_CODEC_SDOUT29
HDA_CODEC_RST#29 HDA_CODEC_BITCLK29
X2101
X2101
1
2 3
4
RTC_X2
12
C2102
C2102 SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
RN2102
RN2102
2 3 1
SRN33J-5-GP-U
SRN33J-5-GP-U
RTC_AUX_S5
R2111 20KR2J-L2-GPR2111 20KR2J-L2-GP
1 2
R2116 20KR2J-L2-GPR2116 20KR2J-L2-GP
1 2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
HDA_SYNC
R21220R2J-2-GP R21220R2J-2-GP
12
HDA_SDOUT
R21230R2J-2-GP R21230R2J-2-GP
12
HDA_RST# HDA_BITCLK
4
Flash Descriptor Security Overide
+3VS_+1.5VS_HDA_IO
DY
R2115 1KR2J-1-GP
R2115 1KR2J-1-GP
3D3V_S0
R2106 1KR2J-1-GP
R2106 1KR2J-1-GP
+3VS_+1.5VS_HDA_IO
B B
This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310
DY
1 2
DY
DY
1 2
R2103 1KR2J-1-GPR2103 1KR2J-1-GP
1 2
HDA_SDOUT
NO REBOOT STRAP
HDA_SPKR
HDA_SYNC
HDA_SDOUT
HDA_SPKR
Low = Default High = Enable
No Reboot Strap
Low = Default High = No Reboot
PLL ODVR VOLTAGE
HDA_SYNC
Low = 1.8V (Default) High = 1.5V
For EMI
HDA_BITCLK HDA_RST#
DY
DY
12
EC2101
A A
EC2101
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
5
HDA_CODEC_SDOUT SPI_CS0#_R
DY
DY
EC2102
EC2102 SC22P50V2JN-4GP
SC22P50V2JN-4GP
DY
DY
EC2103
EC2103 SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
1 2
4
12
C2104
C2104
DY
DY
EC2105
EC2105 SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
1 2
4
3
SRTC_RST#
12
C2103
C2103 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
RTC_RST#
21
G2101
G2101 GAP-OPEN
GAP-OPEN
ME_UNLOCK27
HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.
INTVRMEN- Integrated SUS
1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs
RTC_AUX_S5
R2104 1M1R2J-GPR2104 1M1R2J-GP
1 2
R2105 330KR2F-L-GPR2105 330KR2F-L-GP
1 2
HDA_SPKR29
HDA_SDIN029
R2107 1KR2J-1-GPR2107 1KR2J-1-GP
1 2
PCH_TCK11 PCH_TMS11 PCH_TDI11
PCH_TDO11
SPI_CLK_R27,60 SPI_CS0#_R27,60
SPI_SI_R27,60
SPI_SO_R27,60
PCH1A
PCH1A
RTC_X1 RTC_X2 RTC_RST# SRTC_RST#
SM_INTRUDER# PCH_INTVRMEN
HDA_BITCLK HDA_SYNC
HDA_RST#
HDA_SDOUT
PCH_GPIO33
1
TP2105TPAD14-GP TP2105TPAD14-GP
PCH_TCK
SPI_CS0#_R
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN#/GPIO33
N32
HDA_DOCK_RST#/GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
PSW_CLR#22 MFG_MODE22 S_GPIO22
3
Cougar
Cougar Point
Point
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
SRN10KJ-6-GP
SRN10KJ-6-GP
PCH_GPIO33
PCH_TCK
1 OF 10
1 OF 10
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
LPC
LPC
FWH4/LFRAME#
LDRQ1#/GPIO23
SATA0RXN
SATA1RXN
SATA 6G
SATA 6G
SATA2RXN
SATA3RXN
SATA4RXN
SATA
SATA
SATA5RXN
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATA0GP/GPIO21 SATA1GP/GPIO19
RN2103
RN2103
1 2 3 4 5
R2125 1KR2J-1-GP
R2125 1KR2J-1-GP
R2102 51R2J-2-GPR2102 51R2J-2-GP
C38 A38 B37 C37
D36 E36
LDRQ0#
K36 V5
SERIRQ
AM3 AM1
SATA0RXP
AP7
SATA0TXN
AP5
SATA0TXP
AM10 AM8
SATA1RXP
AP11
SATA1TXN
AP10
SATA1TXP
AD7 AD5
SATA2RXP
AH5
SATA2TXN
AH4
SATA2TXP
AB8 AB10
SATA3RXP
AF3
SATA3TXN
AF1
SATA3TXP
Y7 Y5
SATA4RXP
AD3
SATA4TXN
AD1
SATA4TXP
Y3 Y1
SATA5RXP
AB3
SATA5TXN
AB1
SATA5TXP
Y11 Y10
AB12 AB13
AH1
P3
SATALED#
V14 P1
3D3V_S0 3D3V_S0
8 7 6
DY
DY
12
1 2
2
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
SATA_COMP
SATA3_COMP
RBIAS_SATA3
BBS_BIT0
2
Table 21.1 Project_ID
LPC_AD[0..3]
LPC_FRAME# 27,65,71
LW_GG_SEL
INT_SERIRQ 22,27
SATA_RXN0 56 SATA_RXP0 56 SATA_TXN0 56 SATA_TXP0 56
SATA_RXN1 66 SATA_RXP1 66 SATA_TXN1 66 SATA_TXP1 66
SATA_RXN4 56 SATA_RXP4 56 SATA_TXN4 56 SATA_TXP4 56
SATA_RXN5 57 SATA_RXP5 57 SATA_TXN5 57 SATA_TXP5 57
R2112 37D4R2F-GPR2112 37D4R2F-GP
R2113 49D9R2F-GPR2113 49D9R2F-GP
R2114 750R2F-GPR2114 750R2F-GP
1
3D3V_S0
GG
LW_GG_SEL
HighLW
LOW
LPC_AD[0..3] 27,65,71
LW_GG_SEL
12
LW
LW
R2109
R2109 10KR2J-3-GP
10KR2J-3-GP
12
GG
GG
R2110
R2110 10KR2J-3-GP
10KR2J-3-GP
HDD
mSATA
ODD
ESATA
1D05V_VTT
1 2
1 2
1 2
SATA_LED# 22 SATA_DET#0 22
BBS_BIT0 18
0827
BBS_BIT0
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
PCH (SPI/RTC/LPC/SATA/IHDA)
PCH (SPI/RTC/LPC/SATA/IHDA)
PCH (SPI/RTC/LPC/SATA/IHDA)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
1D05V_VTT
R2108 10KR2J-3-GPR2108 10KR2J-3-GP
1 2
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
of
21 94Tuesday, January 18, 2011
of
21 94Tuesday, January 18, 2011
of
21 94Tuesday, January 18, 2011
1
-1
-1
-1
5
4
3
2
1
SSID = PCH
Note: For PCH debug with XDP, need to NO STUFF R2218
R2218 100R2J-2-GPR2218 100R2J-2-GP
3D3V_S0
R2202 200KR2F-L-GPR2202 200KR2F-L-GP
1 2 3
SRN10KJ-5-GP
SRN10KJ-5-GP
R2223
R2223
1 2
PCH_GPIO12 PCH_GPIO57
PCH_GPIO15
PCH_GPIO24
1 2
RN2203
RN2203
4
FFS_INT2_R
10KR2J-3-GP
10KR2J-3-GP
RN2204
RN2204
4
SRN10KJ-5-GP
SRN10KJ-5-GP
R2201 1KR2J-1-GPR2201 1KR2J-1-GP
1 2
R2221 10KR2J-3-GPR2221 10KR2J-3-GP
1 2
INT_SERIRQ21,27
SATA_LED#21
SATA_DET#021
5
D D
3D3V_S0
GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.
C C
3D3V_S0
B B
A A
SATA_ODD_PRSNT#
H_A20GATE H_RCIN#
23 1
PCH_GPIO22 PCH_TEMP_ALERT#
EC_SMI# EC_SCI# DGPU_HPD_INTR#
SATA_ODD_PRSNT#56
3D3V_S5
PSW_CLR#21
RN2201
RN2201
1 2 3 4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
RN2202
RN2202
1 2 3 4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
S_GPIO21
R2213 0R2J-2-GPR2213 0R2J-2-GP
1 2
DGPU_PWROK86,92,93
TP2202
TP2202
TPAD14-GP
TPAD14-GP
mSATA_DTCT#27,66
TP2204
TP2204
TPAD14-GP
TPAD14-GP
GAP-OPEN
GAP-OPEN
21
G2201
G2201
MFG_MODE21
PCH_TEMP_ALERT#27
TP2212TPAD14-GP TP2212TPAD14-GP
TP2209TPAD14-GP TP2209TPAD14-GP TP2210TPAD14-GP TP2210TPAD14-GP
TP2211TPAD14-GP TP2211TPAD14-GP
3D3V_S0
8 7 6
8 7 6
1 2
EC_SMI# DGPU_HPD_INTR#
EC_SCI#27
4
EC_SCI# ICC_EN# PCH_GPIO12 PCH_GPIO15
GPIO16
PCH_GPIO22 PCH_GPIO24
1
mSATA_DTCT# PLL_ODVR_EN
NC_FP_DET#
1
DMI_OVRVLTG FDI_OVRVLTG
GFX_CRB_DET FFS_INT2_R PCH_TEMP_ALERT# PCH_GPIO57
PCH_NCTF_1
1
PCH_NCTF_2
1
PCH_NCTF_3
1
PCH_NCTF_4
1
mSATA_DTCT#
12
DY
DY
R2225
R2225 10KR2J-3-GP
10KR2J-3-GP
PCH1F
PCH1F
T7
BMBUSY#/GPIO0
A42
TACH1/GPIO1
H36
TACH2/GPIO6
E38
TACH3/GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL/GPIO12
G2
GPIO15
U2
SATA4GP/GPIO16
D40
TACH0/GPIO17
T5
SCLOCK/GPIO22
E8
GPIO24/MEM_LED
E16
GPIO27
P8
GPIO28
K1
STP_PCI#/GPIO34
K4
GPIO35
V8
SATA2GP/GPIO36
M5
SATA3GP/GPIO37
N2
SLOAD/GPIO38
M3
SDATAOUT0/GPIO39
V13
SDATAOUT1/GPIO48
V3
SATA5GP/GPIO49
D6
GPIO57
A4
NCTF_VSS#A4
A44
NCTF_VSS#A44
A45
NCTF_VSS#A45
A46
NCTF_VSS#A46
A5
NCTF_VSS#A5
A6
NCTF_VSS#A6
B3
NCTF_VSS#B3
B47
NCTF_VSS#B47
BD1
NCTF_VSS#BD1
BD49
NCTF_VSS#BD49
BE1
NCTF_VSS#BE1
BE49
NCTF_VSS#BE49
BF1
NCTF_VSS#BF1
BF49
NCTF_VSS#BF49
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
12
Cougar
Cougar Point
Point
GPIO
GPIO
NCTF
NCTF
NCTF TEST PIN:
NCTF TEST PIN:
D1,D49,E1,E49,F1,F49
D1,D49,E1,E49,F1,F49
A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49
A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49
BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48
BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48
NC_FP_DET#
R2220
R2220 10KR2J-3-GP
10KR2J-3-GP
3
6 OF 10
6 OF 10
TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71
A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
CPU/MISC
CPU/MISC
INIT3_3V#
TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4
NC_1
NCTF_VSS#BG2
NCTF_VSS#BG48
NCTF_VSS#BH3
NCTF_VSS#BH47
NCTF_VSS#BJ4 NCTF_VSS#BJ44 NCTF_VSS#BJ45 NCTF_VSS#BJ46
NCTF_VSS#BJ5
NCTF_VSS#BJ6
NCTF_VSS#C2
NCTF_VSS#C48
NCTF_VSS#D1
NCTF_VSS#D49
NCTF_VSS#E1
NCTF_VSS#E49
NCTF_VSS#F1
NCTF_VSS#F49
0827
PLL_ODVR_EN
C40
UMA_DIS#
B41
VRAM_SIZE1
C41
VRAM_SIZE2
A40
H_A20GATE
P4
H_PECI_R
AU16 P5 AY11
PCH_THERMTRIP_R
AY10
INIT3_3V#
T14
AH8 AK11 AH10
TS_VSS
AK10 P37
BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49
TP2207TP2207
1
TP2208TP2208
1
3D3V_S5
1 2
0R0402-PAD
0R0402-PAD
SATA_ODD_PWRGT 56 UMA_DIS# 20
TP2206
TP2206
1
TP2205
TP2205
1
H_A20GATE 27
R2203 0R2J-2-GP
R2203 0R2J-2-GP
H_RCIN# 27
H_CPUPWRGD 5,36
R2204 390R2J-1-GPR2204 390R2J-1-GP
1
R2222
R2222
3D3V_S0
0827
12
R2215
R2215 10KR2J-3-GP
10KR2J-3-GP
12
DY
DY
R2212
R2212 1KR2J-1-GP
1KR2J-1-GP
TPAD14-GP
TPAD14-GP TPAD14-GP
TPAD14-GP
1 2
1 2
TP2201
TP2201
3D3V_S0
12
DY
DY
R2209
R2209 10KR2J-3-GP
10KR2J-3-GP
12
R2210
R2210 10KR2J-3-GP
10KR2J-3-GP
3D3V_S5
DY
DY
TPAD14-GP
TPAD14-GP
12
DY
DY
R2207
R2207 10KR2J-3-GP
10KR2J-3-GP
FDI_OVRVLTG
12
R2208
R2208 10KR2J-3-GP
10KR2J-3-GP
DMI_OVRVLTG
12
R2214
R2214 10KR2J-3-GP
10KR2J-3-GP
ICC_EN#
12
DY
DY
R2211
R2211 1KR2J-1-GP
1KR2J-1-GP
2
H_PECI 5,27
H_THERMTRIP# 5,36,85
FDI TERMINATION VOLTAGE OVERRIDE
GPIO37 (FDI_OVRVLTG)
DMI TERMINATION VOLTAGE OVERRIDE
GPIO36
Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.
Integrated Clock Chip Enable
ICC_EN#
Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
INTERNAL GFX EXTERNAL GFX
R2205 DY 10K
R2206 100K DY
3D3V_S0
12
DY
DY
R2205
R2205 10KR2J-3-GP
10KR2J-3-GP
GFX_CRB_DET
12
R2206
R2206 100KR2J-1-GP
100KR2J-1-GP
PCH_THERMTRIP_R
56R2F-1-GP
56R2F-1-GP
DY
DY
R2224
R2224
12
20100723 V1.62
LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)
LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)
HIGH (R2211 DY)- DISABLED [DEFAULT]
LOW (R2211)- ENABLED
PLL ON DIE VR ENABLE
ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED)
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
PCH (GPIO/CPU)
PCH (GPIO/CPU)
PCH (GPIO/CPU)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
of
22 94Tuesday, January 18, 2011
of
22 94Tuesday, January 18, 2011
of
22 94Tuesday, January 18, 2011
1D05V_VTT
-1
-1
-1
5
4
3
2
1
SSID = PCH
3D3V_S03D3V_DAC_S0
1D05V_VTT
D D
12
C2301
C2301
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1D05V_VTT
C C
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C2305
C2305
12
C2306
C2306
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
6A
12
C2302
C2302
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
TP2301TPAD14-GP TP2301TPAD14-GP
12
C2307
C2307
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1D05V_VTT
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
1
12
C2303
C2303
VCCAPLLEXP
C2308
C2308
12
C2304
C2304
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C2309
C2309
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
20100625 V1.2
1D05V_VTT
L2302
L2302
DY
DY
DY
DY
VCCAPLLEXP
12
C2324
C2324 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
0.266A (Totally VCC3_3 current)
3D3V_S0
12
C2310
C2310 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
IND-1UH-100-GP
IND-1UH-100-GP
AA23 AC23 AD21 AD23
AF21
AF23 AG21 AG23 AG24 AG26 AG27 AG29
AJ23
AJ26
AJ27
AJ29
AJ31
AN19
BJ22
AN16 AN17
AN21 AN26 AN27 AP21 AP23 AP24 AP26
AT24
AN33 AN34
BH29
PCH1G
PCH1G
VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE
VCCIO
VCCAPLLEXP
VCCIO VCCIO
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VCCIO VCCIO
VCC3_3
POWER
POWER
Cougar
Cougar Point
Point
VCC CORE
VCC CORE
VCCIO
VCCIO
CRTLVDS
CRTLVDS
DMI
DMI
0.159A(Totally current of VCCVRM)
VCCAFDI_VRM
VCCFDIPLL
+1.05VS_VCC_DMI
TP2302TPAD14-GP TP2302TPAD14-GP
1D05V_VTT
1 2
R2302 0R3J-0-U-GPR2302 0R3J-0-U-GP
1
B B
1D5V_S0_1D8V_S0
0.042A (Totally current of VCCDMI)
AP16
VCCVRM
BG6
VCCAFDIPLL
AP17
VCCIO
AU20
VCCDMI
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
FDI
FDI
NAND / SPI HVCMOS
NAND / SPI HVCMOS
7 OF 10
7 OF 10
VCCADAC
VSSADAC
VCCALVDS VSSALVDS
VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS
VCC3_3
VCC3_3
VCCVRM
VCCDMI
VCCCLKDMI
VccDFTERM
VccDFTERM
VccDFTERM
VccDFTERM
VCCSPI
+VCCA_DAC_1_2
U48
U47
+3VS_VCCA_LVD
AK36 AK37
AM37 AM38 AP36 AP37
V33
V34
AT16
+1.05VS_VCC_DMI
AT20
AB36
+1.05VS_VCC_DMI_CCI
AG16
AG17
AJ16
AJ17
V1
12
C2313
C2313 SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
R2303 SCD1U25V2KX-GPR2303 SCD1U25V2KX-GP
1 2
+1.8VS_VCCTX_LVDS
12
R2309
R2309 SCD1U25V2KX-GP
SCD1U25V2KX-GP
3D3V_S0
12
C2319
C2319 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
1 2
C2320
C2320 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
0.02A
C2321
C2321 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
+V_NVRAM_VCCQ 1D8V_S0
0.19A
12
C2322
C2322 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2323
C2323 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C2314
C2314 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2316
C2316 SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
1D5V_S0_1D8V_S0
1 2
0.02A
(1uFx1)
R23060R2J-2-GP R23060R2J-2-GP
0.001A
1D05V_VTT
1D05V_VTT
R23070R2J-2-GP R23070R2J-2-GP
L2301
L2301
1 2
12
0.06A
12
C2317
C2317 SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
R23080R2J-2-GP R23080R2J-2-GP
12
VCCSPI
HCB1608KF-181-GP
HCB1608KF-181-GP
C2315
C2315 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
3D3V_S5 3D3V_S0
12
R2313
R2313 0R2J-2-GP
0R2J-2-GP
3D3V_S0
R23040R3J-0-U-GP R23040R3J-0-U-GP
12
1 2
12
C2318
C2318 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
DY
DY
R2314
R2314 0R2J-2-GP
0R2J-2-GP
C2311
C2311
The same BIOS SPI ROM power
1 2
1D8V_S0
R23050R5J-5-GP R23050R5J-5-GP
3.3V CRT LDO
1 2
DY
DY
R23120R2J-2-GP
R23120R2J-2-GP
U2301
U2301
VIN
VOUT GND EN3NC#4
G9091-330T11U-GP
G9091-330T11U-GP
3D3V_DAC_S05V_S0
5 4
12
C2312
C2312
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
Table 23.1- LDO Regulator multi-source
Supplier
VCCVRM(Internal PLL and VRMs): A.1.5V for Mobile B.1.8 V for Desktop co-operate with R2103
A A
5
4
1D5V_S0 1D5V_S0_1D8V_S0
1 2
R23100R3J-0-U-GP R23100R3J-0-U-GP
3
2
GMT
RICHTEK
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Description Lenovo P/N Wistron P/N
G9091-330T11U
N/A 74.09091.J3F
N/ART9198-33GBR
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
PCH (POWER1)
PCH (POWER1)
PCH (POWER1)
A3
A3
A3
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
23 94Tuesday, January 18, 2011
23 94Tuesday, January 18, 2011
23 94Tuesday, January 18, 2011
74.09198.Q7F
of
of
of
-1
-1
-1
5
4
3
2
1
SSID = PCH
3D3V_AUX_S5
DY
DY
R2418 0R3J-0-U-GP
R2418 0R3J-0-U-GP
1 2
12
D D
1D05V_VTT
3D3V_S0
C C
1D05V_VTT
2nd = 68.10010.10T
2nd = 68.10010.10T
B B
2nd = 68.10010.10T
2nd = 68.10010.10T
1D05V_VTT
A A
1D05V_VTT
DY
DY
R2417 0R2J-2-GP
R2417 0R2J-2-GP R2419
R2419 0R3J-0-U-GP
0R3J-0-U-GP
DY
DY
R2420 0R2J-2-GP
R2420 0R2J-2-GP
1 2
1R2F-GP
1R2F-GP
68.1001A.10B
68.1001A.10B
68.1001A.10B
68.1001A.10B
R2404 0R2J-2-GPR2404 0R2J-2-GP
R2405 0R2J-2-GPR2405 0R2J-2-GP
12
L2404
1 2
DY
DY
R2401 0R3J-0-U-GP
R2401 0R3J-0-U-GP
R2402
R2402
1 2
1 2
L2404
DY
DY
DY
DY
2nd = 68.10010.10T
2nd = 68.10010.10T
12
1 2
1 2
68.1001A.10B
68.1001A.10B
2nd = 68.10010.10T
2nd = 68.10010.10T
L2402
L2402
IND-10UH-66-GP
IND-10UH-66-GP
L2403
L2403
IND-10UH-66-GP
IND-10UH-66-GP
12
12
+VCCPDSW
DY
DY
C2438
C2438 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
IND-10UH-66-GP
IND-10UH-66-GP
68.1001A.10B
68.1001A.10B
DY
DY
12
C2442
C2442 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
L2401
L2401
IND-10UH-66-GP
IND-10UH-66-GP
0.08A
+1.05VS_VCCA_A_DPL
DY
DY
12
C2444
C2444 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
0.08A
+1.05VS_VCCA_B_DPL
DY
DY
12
C2445
C2445 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
+VCCDIFFCLK
12
C2412
C2412 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
+V1.05S_SSCVCC
12
C2413
C2413 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
5
VCCACLK
+VCCAPLL_CPY_PCH
+V3.3S_VCC_CLKF33
+VCCSUS1
12
SC1U10V2KX-1GP
SC1U10V2KX-1GP
DCPSUS
12
C2401
C2401
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
12
DCPSUSBYP
DY
DY
DY
C2441
C2441
12
C2409
C2409 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C2410
C2410 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1D05V_VTT
DY
C2439
C2439
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
C2440
C2440 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1D05V_VTT
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C2402
C2402
SC1U10V2KX-1GP
SC1U10V2KX-1GP
R2406 0R3J-0-U-GPR2406 0R3J-0-U-GP
1D05V_VTT
0.002A
3D3V_S5
R2403 0R3J-0-U-GPR2403 0R3J-0-U-GP
1 2
TPAD14-GP
TPAD14-GP
1D05V_VTT
TP2404
TP2404
1.01A (Total current of VCCASW)
12
12
C2404
C2403
C2403
C2414
C2414 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C2404
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
+VCCDIFFCLKN
12
C2406
C2406
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
(22uFx2_0603)
(1uFx3)
+VCCRTCEXT
0.16A (Totally current of VCCVRM
C2411
C2411 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
0.055A
12
0.095A
C2415 SCD1U10V2KX-5GPC2415 SCD1U10V2KX-5GP
12
TP2406TPAD14-GP TP2406TPAD14-GP
0.001A
6uA
12
C2420
C2420 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
4
12
C2418
C2418 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2417
C2417 SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
RTC_AUX_S5
TP2401TPAD14-GP TP2401TPAD14-GP
TP2405TPAD14-GP TP2405TPAD14-GP
+V3.3S_VCC_CLKF33
+VCCAPLL_CPY_PCH
1
TP2402TPAD14-GP TP2402TPAD14-GP
12
C2407
C2407
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1D5V_S0_1D8V_S0
+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL
+VCCDIFFCLK
+V1.05S_SSCVCC
DCPSUS
1
12
12
C2421
C2421 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VCCACLK
1
+VCCPDSW
DCPSUSBYP
1
+VCCSUS1
1
12
C2408
C2408
+VCCSST
C2419
C2419 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PCH1J
PCH1J
AD49
VCCACLK
T16
VCCDSW3_3
V12
DCPSUSBYP
T38
VCC3_3
BH23
VCCAPLLDMI2
AL29
VCCIO
AL24
DCPSUS
AA19
VCCASW
AA21
VCCASW
AA24
VCCASW
AA26
VCCASW
AA27
VCCASW
AA29
VCCASW
AA31
VCCASW
AC26
VCCASW
AC27
VCCASW
AC29
VCCASW
AC31
VCCASW
AD29
VCCASW
AD31
VCCASW
W21
VCCASW
W23
VCCASW
W24
VCCASW
W26
VCCASW
W29
VCCASW
W31
VCCASW
W33
VCCASW
N16
DCPRTC
Y49
VCCVRM
BD47
VCCADPLLA
BF47
VCCADPLLB
AF17
VCCIO
AF33
VCCDIFFCLKN
AF34
VCCDIFFCLKN
AG34
VCCDIFFCLKN
AG33
VCCSSC
V16
DCPSST
T17
DCPSUS
V19
DCPSUS
BJ8
V_PROC_IO
A22
VCCRTC
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
12
C2422
C2422 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
POWER
POWER
Cougar
Cougar Point
Point
Clock and Miscellaneous
Clock and Miscellaneous
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
SATA USB
SATA USB
CPURTC
CPURTC
HDA
HDA
3
10 OF 10
10 OF 10
VCCIO VCCIO VCCIO VCCIO VCCIO
VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3
VCCIO
V5REF_SUS
DCPSUS
VCCSUS3_3
V5REF
VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3
VCC3_3 VCC3_3 VCC3_3
VCC3_3
VCCIO
VCCIO VCCIO
VCCIO
VCCAPLLSATA
VCCVRM
VCCIO VCCIO VCCIO
VCCASW
VCCASW
VCCASW
VCCSUSHDA
1D05V_VTT
N26 P26 P28 T27 T29
T23 T24 V23 V24 P24
T26
M26
AN23 AN24
P34
N20 N22 P20 P22
AA16 W16 T34
AJ2
AF13
AH13 AH14
AF14 AK1
AF11
AC16 AC17 AD17
T21
V21
T19
P32
12
3D3V_S5
12
1D05V_VTT
+5VA_PCH_VCC5REFSUS
+VCCA_USBSUS +V3.3A_VCCPSUS
+5VS_PCH_VCC5REF
+V3.3A_VCCPSUS
12
C2430
C2430 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
+V1.05S_VCCAPLL_SATA3
+V1.05S_VCC_SATA
1D05V_VTT
+3VS_+1.5VS_HDA_IO
0.01A
C2423
C2423 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C2424
C2424 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3D3V_S5
12
12
3D3V_S0
12
C2429
C2429 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1D05V_VTT
12
1D5V_S0_1D8V_S0
12
C2435
C2435 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C2433
C2433 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2425
C2425 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2443
C2443
DY
DY
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C2428
C2428 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
3D3V_S0
12
C2431
C2431 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2432
C2432 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
1 2
2
TP2403 TPAD14-GPTP2403 TPAD14-GP
1
0.001A
1 2
DY
DY
1 2
C2434
C2434 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
DY
DY
R24120R3J-0-U-GP R24120R3J-0-U-GP
3D3V_S5
AK
D2401
D2401 CH751H-40-1-GP
CH751H-40-1-GP
12
C2426
C2426 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
5V_S5
R240810R2J-2-GP R240810R2J-2-GP
0.001A
3D3V_S0
AK
D2402
D2402 CH751H-40-1-GP
CH751H-40-1-GP
3D3V_S5
R24100R3J-0-U-GP R24100R3J-0-U-GP
3D3V_S5
12
DY
DY
C2436
C2436
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
1D05V_VTT
R24110R3J-0-U-GP
R24110R3J-0-U-GP
1D05V_VTT
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
12
1 2
1 2
C2427
C2427 SC1U10V2KX-1GP
SC1U10V2KX-1GP
DY
DY
U2401
U2401
VIN
VOUT GND EN3NC#4
G9091-150T11U-GP
G9091-150T11U-GP
R2414 0R3J-0-U-GPR2414 0R3J-0-U-GP
1 2
R2415 0R3J-0-U-GP
R2415 0R3J-0-U-GP
1 2
DY
DY
R2413 0R3J-0-U-GP
R2413 0R3J-0-U-GP
1 2
DY
DY
PCH (POWER2)
PCH (POWER2)
PCH (POWER2)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
5V_S0
R240710R2J-2-GP R240710R2J-2-GP
1D5V_S5
5 4
12
DY
DY
C2437
C2437
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
1D5V_S01D5V_S5+3VS_+1.5VS_HDA_IO 3D3V_S5
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
of
24 94Tuesday, January 18, 2011
of
24 94Tuesday, January 18, 2011
of
24 94Tuesday, January 18, 2011
1
12
DY
DY
C2416
C2416
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
-1
-1
-1
5
4
3
2
1
SSID = PCH
D D
C C
B B
A A
5
PCH1H
PCH1H
H5
VSS
AA17
VSS
AA2
VSS
AA3
VSS
AA33
VSS
AA34
VSS
AB11
VSS
AB14
VSS
AB39
VSS
AB4
VSS
AB43
VSS
AB5
VSS
AB7
VSS
AC19
VSS
AC2
VSS
AC21
VSS
AC24
VSS
AC33
VSS
AC34
VSS
AC48
VSS
AD10
VSS
AD11
VSS
AD12
VSS
AD13
VSS
AD19
VSS
AD24
VSS
AD26
VSS
AD27
VSS
AD33
VSS
AD34
VSS
AD36
VSS
AD37
VSS
AD38
VSS
AD39
VSS
AD4
VSS
AD40
VSS
AD42
VSS
AD43
VSS
AD45
VSS
AD46
VSS
AD8
VSS
AE2
VSS
AE3
VSS
AF10
VSS
AF12
VSS
AD14
VSS
AD16
VSS
AF16
VSS
AF19
VSS
AF24
VSS
AF26
VSS
AF27
VSS
AF29
VSS
AF31
VSS
AF38
VSS
AF4
VSS
AF42
VSS
AF46
VSS
AF5
VSS
AF7
VSS
AF8
VSS
AG19
VSS
AG2
VSS
AG31
VSS
AG48
VSS
AH11
VSS
AH3
VSS
AH36
VSS
AH39
VSS
AH40
VSS
AH42
VSS
AH46
VSS
AH7
VSS
AJ19
VSS
AJ21
VSS
AJ24
VSS
AJ33
VSS
AJ34
VSS
AK12
VSS
AK3
VSS
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
Cougar
Cougar Point
Point
8 OF 10
8 OF 10
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28
4
PCH1I
PCH1I
AY4
VSS
AY42
VSS
AY46
VSS
AY8
VSS
B11
VSS
B15
VSS
B19
VSS
B23
VSS
B27
VSS
B31
VSS
B35
VSS
B39
VSS
B7
VSS
F45
VSS
BB12
VSS
BB16
VSS
BB20
VSS
BB22
VSS
BB24
VSS
BB28
VSS
BB30
VSS
BB38
VSS
BB4
VSS
BB46
VSS
BC14
VSS
BC18
VSS
BC2
VSS
BC22
VSS
BC26
VSS
BC32
VSS
BC34
VSS
BC36
VSS
BC40
VSS
BC42
VSS
BC48
VSS
BD46
VSS
BD5
VSS
BE22
VSS
BE26
VSS
BE40
VSS
BF10
VSS
BF12
VSS
BF16
VSS
BF20
VSS
BF22
VSS
BF24
VSS
BF26
VSS
BF28
VSS
BD3
VSS
BF30
VSS
BF38
VSS
BF40
VSS
BF8
VSS
BG17
VSS
BG21
VSS
BG33
VSS
BG44
VSS
BG8
VSS
BH11
VSS
BH15
VSS
BH17
VSS
BH19
VSS
H10
VSS
BH27
VSS
BH31
VSS
BH33
VSS
BH35
VSS
BH39
VSS
BH43
VSS
BH7
VSS
D3
VSS
D12
VSS
D16
VSS
D18
VSS
D22
VSS
D24
VSS
D26
VSS
D30
VSS
D32
VSS
D34
VSS
D38
VSS
D42
VSS
D8
VSS
E18
VSS
E26
VSS
G18
VSS
G20
VSS
G26
VSS
G28
VSS
G36
VSS
G48
VSS
H12
VSS
H18
VSS
H22
VSS
H24
VSS
H26
VSS
H30
VSS
H32
VSS
H34
VSS
F3
VSS
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
3
Cougar
Cougar Point
Point
9 OF 10
9 OF 10
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
2
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
PCH (VSS)
PCH (VSS)
PCH (VSS)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
-1
-1
of
25 94Tuesday, January 18, 2011
of
25 94Tuesday, January 18, 2011
of
25 94Tuesday, January 18, 2011
-1
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
5
4
3
Date: Sheet
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
26 94Tuesday, January 18, 2011
26 94Tuesday, January 18, 2011
26 94Tuesday, January 18, 2011
1
-1
-1
-1
of
of
of
SSID = KBC
3D3V_AUX_KBC
R2771
R2771 2D2R3-1-U-GP
2D2R3-1-U-GP
1 2
12
C2701
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
R2714
R2714
1 2
R2729
R2729
1 2
R2727
R2727
1 2
12
UMA
UMA
R2713
R2713 10KR2J-3-GP
10KR2J-3-GP
DISCRETE_ID
12
PX
PX
R2741
R2741 10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP R2740
R2740
1 2
EXC_PWR_SHDN_R#
AD_OFF
R2770 1KR2J-1-GPR2770 1KR2J-1-GP
C2701
PAD_DETECT#
HDD_DTCT#
D D
3D3V_AUX_KBC
3D3V_S0
3D3V_AUX_S5
3D3V_AUX_KBC
C C
EC_AGND
3D3V_S5
5
R2702 0R3J-0-U-GPR2702 0R3J-0-U-GP
12
12
C2705
C2705
C2704
C2704
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
EC_AGND
ACDC_ID2
10KR2J-3-GP
10KR2J-3-GP
100KR2J-1-GP
100KR2J-1-GP
1
TP2708TP 2708
100KR2J-1-GP
100KR2J-1-GP
TP2705TP 2705
12
12
12
12
12
C2707
C2707
C2706
C2706
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
C2714 SCD1U10V2KX-5GP
C2714 SCD1U10V2KX-5GP
1 2
AD_IA40 ACDC_ID282
GSENSE_Z79
USB_AO_SEL182 GSENSE_TST79 3G_EN66
SUS_PWR_ACK19 GSENSE_X79
TP2707TP 2707
FAN_ID28
GSENSE_Y79
PAD_DETECT#69 AD_OFF82 BEEP_ENABLE29 S5_ENABLE36 3G_POWERON66
BAT_IN#39
LID_CLOSE#49 RSMRST#_KBC19
PM_SLP_S4#19,46,82
ME_UNLOCK21 HDD_DTCT#56
EC_ENABLE
1
RTC_AUX_S5
WIFI_RF_EN65 BLUETOOTH_EN63 S0_PWR_GOOD19,36
EXC_PWR_SHDN_R#82
USB_PWR_EN57,61 AC_PRESENT19
NOTE: C2712 must place close to VCORF pin.
R2725 0R5J-5-GPR2725 0R5J-5-GP
12
C2709
C2709
C2708
C2708
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
EC_AGND
PCB_VER_AD
VGA_THRM
1
KBC_PWRBTN_EC# PAD_DETECT#
AC_IN_KBC
DISCRETE_ID
KBC_VCORF
12
C2712
C2712 SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
EC_SWI#20
B B
EC_SCI#22
R2712
R2712
AC_IN_KBC
1 2
0R0402-PAD
0R0402-PAD
12
DY
DY
R2706
R2706 100KR2J-1-GP
100KR2J-1-GP
3D3V_AUX_S5
12
R2717
R2717 22KR2J-GP
22KR2J-GP
A A
FAN_ID
AC_IN 40
3D3V_S0
SML1_CLK
SML1_DATA
3D3V_AUX_S53D 3V _A UX_KBC
1 2
3D3V_AUX_KBC_VCC
12
C2710
C2710
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
104
97 98 99
100 101
105 106
79 95 96
108
93 94
114
6
109
14 15 80 17 20 21 23 26 73 74 75 82 83 84
91 110 112 107
44
NPCE795GA0DX-GP
NPCE795GA0DX-GP
71.00795.A0G
71.00795.A0G
DY
DY
R2715 0R2J-2-GP
R2715 0R2J-2-GP
1 2
D2701
D2701
1
2
BAS16GP-GP
BAS16GP-GP
DY
DY
R2716 0R2J-2-GP
R2716 0R2J-2-GP
1 2
D2704
D2704
1
2
BAS16GP-GP
BAS16GP-GP
Q2703
Q2703
2345 1
6
2N7002KDW-G P
2N7002KDW-G P
VBAT
U2701A
U2701A
VREF GPIO90/AD0
GPIO91/AD1 GPIO92/AD2 GPIO93/AD3
GPIO94/DA0 GPIO95/DA1 GPIO96/DA2
GPIO2 GPIO3/AD6 GPIO4/AD5 GPIO5/AD4 PSL_IN2_GPI6# GPIO7/AD7 GPIO16 GPIO24 GPIO30 GPIO34/CIRRXL GPIO36 GPIO41 GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO46/CIRRXM/TRST# GPIO51 PSL_IN1_GPI70 PSL_OUT_GPIO71 VBKUP GPIO75 GPO76/SHBM GPIO77 GPIO81 GPO82/IOX_LDSH/TEST# GPI/O84/IOX_SCLK/XORTR# GPIO97
VCORF
3
3
2nd = 84.DM601.03F
2nd = 84.DM601.03F
5
4
115
VCC19VCC46VCC76VCC88VCC
GND18GND45GND78GND89GND
GND
5
116
NOTE: Pleae place R2711 close to AGND pin.
ECSWI#_KBC
ECSCI#_KBC
SMBC_THERM SMBD_THERM
84.2N702.A3F
84.2N702.A3F
4
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
4
102
VDD
AVCC
LRESET#
LFRAME#
GPIO11/CLKRUN#
GPIO65/SMI#
ECSCI#/GPIO54
GPIO10/LPCPD#
GPIO67/PWUREQ#
GPIO85/GA20
KBRST#/GPIO86
GPIO52/PSDAT3/RDY#
GPIO50/PSCLK3/TDO
GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1
GPIO17/SCL1 GPIO22/SDA1 GPIO73/SCL2 GPIO74/SDA2 GPIO23/SCL3 GPIO31/SDA3 GPIO47/SCL4 GPIO53/SDA4
F_SDI/F_SDIO1
F_SDIO/F_SDIO0
AGND
103
R2711
R2711
EC_AGND
12
0R2J-2-GP
0R2J-2-GP
EC_AGND
3D3V_S0
RN48
RN48
23 1
4
SRN10KJ-5-GP
SRN10KJ-5-GP
SMBC_THERM 28,85
SMBD_THERM 28,85
3D3V_S0
12
12
C2702
C2702
DY
DY
C2711
C2711 SC220P50V2KX-3GP
1 OF 2
1 OF 2
SERIRQ
F_CS0#
F_SCK
LCLK LAD3
LAD2 LAD1 LAD0
SC220P50V2KX-3GP
PLT_RST#_EC
1 2
7 2 3
LPC_AD3
1
LPC_AD2
128
LPC_AD1
127
LPC_AD0
126 125 8 9
ECSCI#_KBC
29 124
ECSWI#_KBC
123 121 122
27 25 11 10 71 72
70 69 67 68 119
GSENSOR_ID
120
PROCHOT_EC
24 28
EC_SPI_CS#_C
90
EC_SPI_CLK_C
92
EC_SPI_DI_C
86
EC_SPI_DO_C
87
NOTE: Locate resistors R2719 and R2722 close to the NPCE791L.
NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connection.
EC_GPIO47 High Active
PROCHOT_EC
12
R2732
R2732 100KR2J-1-GP
100KR2J-1-GP
PCB_VER_AD
C2703
C2703 SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
1 2
R2735
R2735 0R2J-2-GP
0R2J-2-GP
PLT_RST# 5,18,32,36,65,66,71,80,82,83 CLK_PCI_KBC 18 LPC_FRAME# 21,65,71
INT_SERIRQ 21,22 PM_CLKRUN# 19 L_BKLT_EN 17
PCH_TEMP_ALERT# 22 H_A20GATE 22
H_RCIN# 22
BLON_OUT 49 PCIE_RST# 83,85 GSENSE_ON# 79 USB_AO_SEL0 82
TPDATA 69 TPCLK 69
BAT_SCL 39,40 BAT_SDA 39,40 SML1_CLK 20 SML1_DATA 20
USB_PWR_EN2 82
CHG_ON# 40
33R2J-2-GPR2736 33R2J -2-GPR2736
12
33R2J-2-GPR2719 33R2J -2-GPR2719
12
R2737 0R2J-2-GPR2737 0R2J-2-GP
12
R2722 33R2J-2-GPR2722 33R2J-2-GP
12
Q2702
Q2702
G
D
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
KBC_PWRBTN#82
3
3D3V_AUX_KBC
1 2
12
EC_AGND
LPC_AD[0..3] 21,65,71
PCB Version A/D (PIN 98) Pull-Low Resistor Pull-High Resistor (3D3V_AUX_S5) Voltage
SA 100K 10K 3.0V
R2724
R2724 10KR2J-3-GP
10KR2J-3-GP
BOM Ctrl
BOM Ctrl
SB 100K 20K 2.75V
SC 100K 33K 2.48V
SD 100K 47K 2.24V
R2726
R2726 100KR2J-1-GP
100KR2J-1-GP
-1 100K 64.9K 2.0V
Reserved 100K 76.8K 1.87V
Reserved 100K 100K 1.65V
NOTE: PWM Signal :
1. If unused, select altrnative GPIO function and enable internal pull-down.
2. Please measure and make sure that the rise time of VCC_POR is less than 10us.
<------ TP
<------ BATTERY / CHARGER <------PCH / eDP
SPI_CS0#_R 21,60 SPI_CLK_R 21,60 SPI_SO_R 21,60
SPI_SI_R 21,60
H_PROCHOT#_EC
R2733 0R2J-2- GPR2733 0R2J-2-G P
3D3V_AUX_S5
G2701
G2701 GAP-OPEN
GAP-OPEN
2 1
1 2
12
R2704
R2704 10KR2J-3-GP
10KR2J-3-GP
R2703 470R2J-2-GPR2703 470R2J-2-GP
12
R2774
R2774 100KR2J-1-GP
100KR2J-1-GP
3
mSATA_DTCT#22,66
PM_PWRBTN#19
TP4_RESET69
PM_SLP_S3#19,36,37,47,82
PANEL_LED49
KBC_BEEP29
TP2711TP 2711
1
STOP_CHG#40
1
TP2710TP 2710
PAD_RESET#69
AC_IN_LED82 PALM_LED69
AMP_MUTE#29
PCH_SUSCLK_KBC19
R2721 43R2J-GPR 2721 43R2J-GP
H_PECI5,22
1D05V_VTT
NOTE: Please be aware that the SPI interf ace trace length between PCH and EC should not exceed 6500mils,. The mismatch of SPI interface signals between EC and SPI flash should not exceed 500mils.
H_PROCHOT# 5,42
KBC_PWRBTN_EC#
12
DY
DY
12
C2717
C2717 SC220P50V2KX-3GP
SC220P50V2KX-3GP
R2720 0R2J-2-GPR2720 0R2J-2-GP
R2701 and C2716 Need very close to EC
PURE_HW_SHUTDOWN#28,36
2
R2700
R2700 1MR2J-1-GP
1MR2J-1-GP
1 2
E51_RxD65 E51_TxD65
1 2 1 2
mSATA_DTCT#_C
BRIGHTNESS FAN1_PWM
ECRST#
AMP_MUTE#
12
C2716
C2716 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
U2701B
U2701B
31
GPIO56/TA1
117
GPIO20/TA2/IOX_DIN_DIO
63
GPIO14/TB1
64
GPIO1/TB2
32
GPIO15/A_PWM
118
GPIO21/B_PWM
62
GPIO13/C_PWM
65
GPIO32/D_PWM
81
GPIO66/G_PWM
66
GPIO33/H_PWM
22
GPIO45/E_PWM
16
GPIO40/F_PWM
85
VCC_POR#
113
GPIO87/CIRRXM/SIN_CR
111
GPI/O83/SOUT_CR/TRIST#
30
GPIO55/CLKOUT/IOX_DIN_DIO
77
GPIO0/EXTCLK
PECI
13
PECI
EC_VTT
12
VTT
NPCE795GA0DX-GP
NPCE795GA0DX-GP
71.00795.A0G
71.00795.A0G
R2723 10KR2J-3-GPR2723 10KR2J-3-GP
12
EC GPIO standard PH/PL
RN2701
BAT_SCL BAT_SDA
BAT_IN#
S5_ENABLE LID_CLOSE#
ECRST#
AMP_MUTE# PCIE_RST#
E51_RxD
BLUETOOTH_EN
RN2701
23 1
4
SRN4K7J-8-GP
SRN4K7J-8-GP
R2701 100KR2J-1-GPR 2701 100KR2J-1-GP
12
RN2705
RN2705
1
4
23
SRN10KJ-5-GP
SRN10KJ-5-GP
R2709 10KR2J-3-GPR 2709 10KR2J-3-GP
12
RN2702
RN2702
1
4
23
SRN10KJ-5-GP
SRN10KJ-5-GP
DY
DY
R2708 10KR2J- 3-GP
R2708 10KR2J- 3-GP
1 2
DY
DY
R2707 10KR2J- 3-GP
R2707 10KR2J- 3-GP
1 2
2
KBSOUT0/JENK#
KBSOUT1/TCK KBSOUT2/TMS
KBSOUT4/JEN0#
KBSOUT5/TDO
KBSOUT6/RDY#
KBSOUT9/SDP_VIS# KBSOUT10/P80_CLK
KBSOUT11/P80_DAT
KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16 GPIO57/KBSOUT17
ECRST#
E
Q2701
Q2701
B
MMBT3906-4-GP
MMBT3906-4-GP
C
3D3V_AUX_KBC
3D3V_S0
2 OF 2
2 OF 2
KBSOUT3/TDI
KBSOUT7 KBSOUT8
KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7
20100709
53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33
54 55 56 57 58 59 60 61
DY
DY
12
C2715
C2715 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1
3D3V_S0
12
R2718
R2718 100KR2J-1-GP
100KR2J-1-GP
G Sensor ID:
12
DY
DY
R2710
R2710 100KR2J-1-GP
100KR2J-1-GP
KCOL[0..17] 69
KROW[0..7] 69
TP2709TP 2709
High: ST Low:ADI
mSATA_DTCT#_C
1
10KR2J-3-GP
10KR2J-3-GP
KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17
KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7
GSENSOR_ID
Prevent BIOS data loss solution
3D3V_AUX_S5
12
DY
DY
R2705
R2705 10KR2J-3-GP
10KR2J-3-GP
U2702
U2702
1
GND
PURE_HW_SHUTDOWN#
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A2
A2
A2
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
VCC
2
RESET#
G690L293T73UF-GP
G690L293T73UF-GP
74.00690.I7B
74.00690.I7B
Wistron Corporat ion
Wistron Corporat ion
Wistron Corporat ion
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
KBC Nuvoton NPCE795
KBC Nuvoton NPCE795
KBC Nuvoton NPCE795
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
3D3V_AUX_S5
3
27 94
27 94
27 94
R2728
R2728
12
-1
-1
-1
of
of
of
5
4
3
2
1
SSID = Thermal
Close to SO-DIMM side.
SA 0905 change to 390p
3
D D
E
Q2803
Q2803
C
MMBT3904WT1G-GP
MMBT3904WT1G-GP
2
E
Q2802
Q2802
C
THER_UMA_DXP
MMBT3904WT1G-GP
MMBT3904WT1G-GP
B
UMA
UMA
B
12
C2802
C2802 SC390P50V2KX-GP
SC390P50V2KX-GP
R2813 0R2J-2-GP
R2813 0R2J-2-GP
UMA
UMA
12
C2805
C2805 SC390P50V2KX-GP
SC390P50V2KX-GP
R2814 0R2J-2-GP
R2814 0R2J-2-GP
Thermal sensor
UMA
UMA
1 2
UMA
UMA
1 2
2200p close to smsc2103 chip
REMOTE2-THER_UMA_DXN
12
C2806
C2806 SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
REMOTE2+
T8
1
C
Q2801
Q2801
E
MMBT3904WT1G-GP
MMBT3904WT1G-GP
CPU TEMP: H_THERMDA and H_THERMDC routing 10mil trace width and spacing. Locate Capacity near Thermal diode.
12
C2809
C2809 SC390P50V2KX-GP
B
SC390P50V2KX-GP
CPU backside or inside the socket
2200p close to smsc2103 chip
H_THERMDA
12
C2804
C2804 SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
H_THERMDC
5V_S0
between CPU, VGA and DIMM on bottom side
12
3D3V_S0
C C
3D3V_S0
12
Close to VGA side.
THER_VGA_DXP
2
C
PX
PX
Q2805
Q2805
E
THER_VGA_DXN
MMBT3904WT1G-GP
MMBT3904WT1G-GP
1
TP2802
TP2802 TPAD14-GP
TPAD14-GP
B B
A A
PX
PX
12
C2808
C2808
B
SC390P50V2KX-GP
SC390P50V2KX-GP
pin6, ALERT# OD pin7, SYS_SHDN# OD
PX
PX
R2811 0R0402-PAD
R2811 0R0402-PAD
1 2
PX
PX
R2812 0R0402-PAD
R2812 0R0402-PAD
1 2
THERM_SCI#
R2802 0R0402-PADR2802 0R0402-PAD
1 2
SMBC_THERM27,85 SMBD_THERM27,85
C2803
C2803
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2103_VDD
1 2
H_THERMDA
H_THERMDC REMOTE2+ REMOTE2-
THERM_SYS_SHDN# SHDN_SEL THERM_SCI#_R
PURE_HW_SHUTDOW N#27,36
R2801
R2801 68R2-GP
68R2-GP
U2801
U2801
3
VDD
2
DP1
1
DN1
16
DP2/DN3
15
ND2/DP3
7
SYS_SHDN#
6
ALERT#
9
SMCLK
8
SMDATA
EMC2103-2-AP-GP
EMC2103-2-AP-GP
83.00054.T81
83.00054.T81
2ND = 83.BAT54.D81
2ND = 83.BAT54.D81
3rd = 83.BAT54.S81
3rd = 83.BAT54.S81
12
DY
DY
R2810
R2810 10KR2J-3-GP
10KR2J-3-GP
TRIP_SET
SHDN_SEL
DY
DY
D2803
D2803 BAT54PT-GP
BAT54PT-GP
SHDN_SEL
SHDN --> 2N3904 ON External diode
4
GPIO1
5
GPIO2
10
TACH
11
PWM
14 13
12
GND
17
GND
3D3V_AUX_S5
3
1
2
DY
DY
12
C2807
C2807 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
TRIP_SET
12
R2804
R2804 6K8R2J-GP
6K8R2J-GP
2103_4 2103_5
TP2801TPAD14-GPTP2801TPAD14-GP
1
TP2803TPAD14-GPTP2803TPAD14-GP
1
R2803 2K05R2F-GPR2803 2K05R2F-GP
1 2
Q2804
Q2804
D
2N7002K-2-GP
2N7002K-2-GP
T8 = 105
THERM_SYS_SHDN#
S
R2808 0R2J-2-GP
R2808 0R2J-2-GP R2809 0R2J-2-GPR2809 0R2J-2-GP
G
SRN10KJ-5-GP
SRN10KJ-5-GP
CH551H-30GP-GP
CH551H-30GP-GP
3D3V_S0
DY
DY
1 2 1 2
RN2801
RN2801
2 3 1
D2802
D2802
12
R2807
R2807 100KR2J-1-GP
100KR2J-1-GP
20100709_EMI
3D3V_S0
4
FAN_TACH
KA
FAN_PWM
SA 0905
3D3V_S0
IMVP_PWRGD 36,42
FAN_TACH
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
FAN_ID27
R2806 0R0402-PADR2806 0R0402-PAD
1 2
DY
DY
12
EC2801
EC2801 SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
Table 28.1- General Purpose Transistors multi-source
Supplier
PANJIT
CHENMKO N/ACH3904WGP 84.03904.Y11
Table 28.2- Surface Mount Schottky Barrier
Supplier
PANJIT Power Silicon
Inc.
<Core Design>
<Core Design>
<Core Design>
12
C2801
C2801
R2805
R2805 10KR2J-3-GP
10KR2J-3-GP
FAN_PWM_CFAN_PWM
DY
DY
12
EC2802
EC2802 SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
ACES-CON6-35-GP
ACES-CON6-35-GP
5V_S0 FAN_PWM_C FAN_TACH FAN_ID
FAN1
FAN1
8 6
5 4 3 2
1 7
1 1 1 1
Description Lenovo P/N Wistron P/N
MMBT3904WT1G
MMBT3904W 84.M3904.A11
N/A
N/A
Description Lenovo P/N Wistron P/N
BAT54PT
BAT54 83.BAT54.D81
N/A
N/A
N/ABAT54C 83.BAT54.S81
TP2101TP2101 TP2102TP2102 TP2103TP2103 TP2104TP2104
84.03904.R11ON
83.00054.T81CHENMKO
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
THERMAL SENSOR SMSC EMC2 10 3
THERMAL SENSOR SMSC EMC2 10 3
THERMAL SENSOR SMSC EMC2 10 3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Taipei Hsien 221, Taiwan, R.O.C.
of
28 94
of
28 94
of
28 94
1
-1
-1
-1
5
D D
AUD_3D3V
12
C2908
C2908
SC1U10V2KX-1GP
SC1U10V2KX-1GP
HDA_CODEC_RST#21
HDA_CODEC_BITCLK21
1 2
D
HDA_SDIN021
AUD_DMIC_CLK49
AUD_DMIC_DATA49
D2901
C C
HDA_SPKR21
KBC_BEEP27
BEEP_ENABLE27
D2901
2
1
BAT54CGP-GP
BAT54CGP-GP
AUD_PC_BEEP_C_R
3
R2906 100R2J-2- GPR2906 100R2J-2-GP
Q2903
Q2903
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
AUD_3D3V
12
C2909
C2909
12
DY
DY
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
C2910
C2910
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
R2912 0R2J-2-GPR2912 0R2J-2-GP
1 2
DY
DY
C2915
C2915 SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
1 2
AUD_PC_BEEP_C
12
R2907 100R2F-L1-GP-UR2907 100R2F-L1-GP-U
12
C2905
C2905
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
AUD_3D3V
12
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
C2917 SCD1U10V2KX-5GPC2917 SCD1U10V2KX-5GP
R2905
R2905 10KR2J-3-GP
10KR2J-3-GP
1 2
DY
DY
12
C2934
C2934
SC33P50V2JN-3GP
SC33P50V2JN-3GP
For EMI issue.
DY
DY
R2921 0R2J-2-GP
R2921 0R2J-2-GP
1 2
DY
DY
R2922 0R2J-2-GP
R2922 0R2J-2-GP
B B
AU_GND
Place R2913/R2914 under CODEC, and place R2921/R2922 near CODEC
20100705_AUD
AUD_SYNC_G
12
C2931
C2931 SC33P50V2JN-3GP
SC33P50V2JN-3GP
HDA_CODEC_SYNC21 HDA_CODEC_SDOUT21
A A
5
1 2
R2913 0R0805-PAD-1-GPR2913 0R0805-PAD-1-GP
1 2
R2914 0R0805-PAD-1-GPR2914 0R0805-PAD-1-GP
1 2
Q2901
Q2901
D
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
12
C2906
C2906
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
C2911
C2911
10KR2F-2-GP
10KR2F-2-GP
12
C2914
C2914 SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
1 2
AUD_3D3V
G
S
12
DY
DY
R2903
R2903
AUD_SDATAIN
DY
DY
AMP_MUTE#27
12
AUD_SYNC
4
12
C2907
C2907
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
AUD_DMIC_CLK_R
DY
DY
12
C2933
C2933 SC33P50V2JN-3GP
SC33P50V2JN-3GP
R2918
R2918 33KR2F-GP
33KR2F-GP
4
12
C2912
C2912
AUD_SYNC AUD_SDATA_OUT
DY
DY
C2916
C2916 SC22P50V2JN-4GP
SC22P50V2JN-4GP
1 2
AUD_PC_BEEP
12
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
3
AUDIO CODEC
AUD_LDO_OUT_3D3V
AUD_FILT_1D65V
12
12
C2902
C2902
C2901
C2901
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
AU_GND
AUD_FILT_1D8V
C2913
C2913
9 5
8 6 4
10
39 38 37
40
1
71.20671.A03
71.20671.A03
U2901
U2901
CX20671-21Z-GP
CX20671-21Z-GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
2
3
7
VDD_IO
FILT_1_8
RESET# BIT_CLK
SYNC SDATA_IN SDATA_OUT
PC_BEEP
SPDIF GPIO0/EAPD# GPIO1/SPK_MUTE#
DMIC_CLK DMIC_1/2
VAUX_3_3
LEFT+
11
AUD_SPK_L+
Should be used at least 20 MIL width copper line for "AUD_SPK_L+","AUD_SPK_L-", "AUD_SPK_R+", "AUD_SPK_R-
AUD_SDATA_OUT_G
12
DY
DY
C2932
C2932
12
C2903
C2903
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
26
28
29
27
AVDD_5V
AVDD_HP
FILT_1_65
AVDD_3_3
DVDD_3_3
LEFT-13RIGHT-
RIGHT+
14
16
AUD_SPK_R-
AUD_SPK_R+
R2911 0R2J-2- GPR2911 0R2J-2-G P R2910 0R2J-2- GPR2910 0R2J-2-G P R2909 0R2J-2- GPR2909 0R2J-2-G P R2908 0R2J-2- GPR2908 0R2J-2-G P
DY
DY
Q2902
Q2902
D
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
1 2
12
15
LPWR_5_0
PORTB_R
PORTC_R
PORTA_R
1 2 1 2 1 2 1 2
G
S
18
AUD_SPK_L-
R2919 0R2J-2- GPR2919 0R2J-2-G P
12
C2904
C2904
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
AU_GND
12
C2924
C2924
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C2926
C2926
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
AUD_CLASSDREF
17
RPWR_5_0
CLASS_D_REF
SENSE_A
PORTB_L
B_BIAS
C_BIAS
PORTC_L
NC#25 NC#24
PORTA_L
AVEE FLY_N FLY_P
GND
41
AUD_3D3V
12
DY
DY
R2920
R2920 33KR2F-GP
33KR2F-GP
AUD_SDATA_OUT
36
35 34 33
32 31 30
25 24
23 22
21 20 19
AUD_5V
12
C2925
C2925
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
C2927
C2927
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
AUD_PORTC_R AUD_PORTC_L
AUD_FLY_N AUD_FLY_P
C2919
C2919 SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
AUD_SPK_R+_L 58 AUD_SPK_R-_L 58 AUD_SPK_L-_L 58 AUD_SPK_L+_L 58
3
AUD_SENSE_A
Layout Note: Path from +5V to LPWR_5.0 and RPWR_5.0 must be very low resistance ( <0.01 ohms).
Place bypass caps very close to device.
12
12
C2928
C2928
C2929
C2929
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
C2922 SC2D2U10V3KX-1GPC2922 SC2D2U10V3KX-1GP
1 2
C2923 SC2D2U10V3KX-1GPC2923 SC2D2U10V3KX-1GP
1 2
AUD_PORTA_R 58 AUD_PORTA_L 58
1 2
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
AUD_SPK_R+ AUD_SPK_R­AUD_SPK_L­AUD_SPK_L+
AUD_5V 5V_S0
R2901 0R5J-5-GPR2901 0R5J-5- GP
1 2
3D3V_S0AUD_3D3V
R2902 0R3J-0-U-GPR2902 0R3J-0-U-G P
1 2
12
C2930
C2930
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
AUD_AVEE
12
C2920
C2920
12
EC2904
EC2904 SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
C2921
C2921
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
Port Configuration
Port A: Headphone jack Port B: Port C: Microphone jack Port G: Internal stereo speakers Port J: Internal stereo digital mic
AUD_PORTC_R_C 58 AUD_PORTC_L_C 58
12
EC2903
EC2903 SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
Place EMI components close to audio codec.
12
EC2902
EC2902 SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
2
12
EC2901
EC2901 SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
2
1
JACK DETECT RESISTORS
Close to Pin36
SENSE PIN A
AUD_3D3V
12
R2915
R2915 5K11R2F-L1-GP
5K11R2F-L1-GP
AUD_SENSE_A
AUD_SENSE_A 58
<Core Design>
<Core Design>
<Core Design>
Wistron Corporat ion
Wistron Corporat ion
Wistron Corporat ion
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A2
A2
A2
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiw an, R.O.C.
AUDIO CODEC
AUDIO CODEC
AUDIO CODEC
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
29 94
29 94
29 94
of
of
of
-1
-1
-1
5
D D
C C
4
3
2
1
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
AMP
AMP
AMP
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Taipei Hsien 221, Taiwan, R.O.C.
of
30 94
of
30 94
of
30 94
1
-1
-1
-1
5
D D
3D3V_S5
4
R3135 0R3J-0-U-GP
R3135 0R3J-0-U-GP
1 2
DY
DY
3
3D3V_LAN_S5
2
1
-1 0114
12
C3151
C C
B B
C3151 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
LAN_PWR_ON18
12
C3152
C3152 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
D
G
R3133
R3133 100KR2J-1-GP
100KR2J-1-GP
LAN_PWR_ON_T
S
S
Q3103
Q3103
Q3104
Q3104 2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
D
AO3419L-GP
AO3419L-GP
G
84.03419.031
84.03419.031
12
C3150
C3150 SC1U10V2KX-1GP
SC1U10V2KX-1GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
LAN PWR SW
LAN PWR SW
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A4
A4
A4
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
5
4
3
Date: Sheet
2
LAN PWR SW
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
-1
-1
31 94
31 94
31 94
of
of
of
1
-1
5
4
3
2
1
3D3V_S0
1 2
0R3J-0-U-GP
0R3J-0-U-GP
D D
C C
Please place these capacitors, for PCIE_VIN as close to R5U220 as possible.
RICOH recommends strongly, Trace length Difference among these SDXC signals are smaller than 0.5 inches. MDIF_05, SD_CLK MDIF_08, SD_CMD MDIF_02, SD_DATA0 MDIF_01, SD_DATA1 MDIF_11, SD_DATA2 MDIF_1O, SD_DATA3
RICOH recommends strongly, the trace length for these SDXC signals are less than 6-inches. MDIF_05, SD_CLK MDIF_08, SD_CMD MDIF_02, SD_DATA0 MDIF_01, SD_DATA1 MDIF_11, SD_DATA2 MDIF_1O, SD_DATA3
B B
Please place these capacitors, for PCIE_VOUT as close to R5U220 as possible.
12
C3206
C3206
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C3209
C3209
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
12
C3205
C3205
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C3208
C3208
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C3204
C3204
12
C3207
C3207
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C3201
C3201
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SD_WP74 SD_D174 SD_D074
SD_CLK74
SD_CMD74
SD_D374 SD_D274
R3202 0R2J-2-GPR3202 0R2J-2-GP
1 2
R3203 0R2J-2-GPR3203 0R2J-2-GP
1 2
R3204
R3204
1 2
R3205
R3205
1 2
R3206 0R2J-2-GPR3206 0R2J-2-GP
1 2
R3207 0R2J-2-GPR3207 0R2J-2-GP
1 2
12
C3210
C3210 SC1U10V2KX-1GP
SC1U10V2KX-1GP
Please apply capacitor C3210 for SD18C as close as possible to R5U220.
Please apply 50 ohm impedance control for these SDXC signals; MDIF_05, SD_CLK MDIF_08, SD_CMD MDIF_02, SD_DATA0 MDIF_01, SD_DATA1 MDIF_11, SD_DATA2 MDIF_1O, SD_DATA3
XDMEMORYSTICKMEDIA I/F SD/MMC
MFIO00 MFIO01 MFIO02 MFIO03 MFIO04 MFIO05
SDWP# SD_D1 SD_D0 (SD_D7) (SD_D6) SD_CLK
MSBS
MS_D1
(MS_D5)
MSD0 MFIO06 MFIO07 MFIO08 MFIO09 MFIO10
A A
MFIO11
(SD_D5) SD_CDM (SD_D4) SD_D3 SD_D2
(MS_D4)
MS_D2
(MS_D6)
MS_D3
MFIO12 MFIO13 MFIO14 MFCD0# MFCD1#
SDDC#
5
(MS_D7)
MS_CLK
MSINS#
XD_D7 XD_D6 XD_D5 XD_D4 XD_D3 XD_D2 XD_D1 XD_D0 XD_WP# XD_WE# XD_ALE XD_CLE XD_CE# XD_RE# XD_R/B XDCD0# XDCD1#
Please use Microstrip trace routing for these SDXC signals MDIF_05, SD_CLK MDIF_08, SD_CMD MDIF_02, SD_DATA0 MDIF_01, SD_DATA1 MDIF_11, SD_DATA2 MDIF_1O, SD_DATA3
4
3D3V_CARD_S0
R3201
R3201
12
C3202
C3202
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
CDR_PCIE_VOUT_VIN
CDR_SD18C_R
CDR_MFIO5_MEDIA
33R2J-2-GP
33R2J-2-GP
CDR_MFIO8_MEDIA
0R2J-2-GP
0R2J-2-GP
SD_DET#74
12
C3203
C3203
SD_D1_U SD_D0_U
SD_D3_U SD_D2_U
Please place these capacitors for VCC_3Vx as close to R5U220 as possible
CPO
RXC RXN RXP TXN
TXP
GND
3
+3.3V_RUN_CARD
1 4 5 6 7
36 11
CDR_RREF_MEDIA
24
CDR_CPO_MEDIA
22
15 14
PLT_RST#_CR
10
CDR_RXC_MEDIA
17 18 16
PCIE_RXN3_C
21
PCIE_RXP3_C
20
CDR_UDIO0_MEDIA
46
CDR_LUDIO2_R
45 44 2 3
49
R3208
R3208 5K1R2F-2-GP
5K1R2F-2-GP
1 2 1 2
C3214
C3214 SC8200P25V2JX-GP
SC8200P25V2JX-GP
C3212 SCD1U10V2KX-5GPC3212 SCD1U10V2KX-5GP C3211 SCD1U10V2KX-5GPC3211 SCD1U10V2KX-5GP
1 2
U3201
U3201
12
VCC_3V
37
VCC_3V
48
VCC_3V
13
PCIE_VOUT
32
PCIE_VOUT
47
PCIE_VOUT
19
PCIE_VIN
23
PCIE_VIN
30
SD18C
25
MDIF0
26
MDIF1
27
MDIF2
28
MDIF3
29
MDIF4
31
MDIF5
33
MDIF6
34
MDIF7
35
MDIF8
38
MDIF9
39
MDIF10
40
MDIF11
SROMEN/SCL/UDIO2
41
MDIF12
42
MDIF13
43
MDIF14
8
MFCD0#
9
MFCD1#
R5U220-QFN48P-1-GP
R5U220-QFN48P-1-GP
71.5U220.A03
71.5U220.A03
NCTEST0 NCTEST1 NCTEST2 NCTEST3 NCTEST4
MF_VOUT
TEST
RREF
REFCLKN REFCLKP
PERST#
CLKREQ#/UDIO1
SDA/UDIO3
UDIO4 UDIO5
Please apply wide trace for MF_VOUT between R5U220 and SD Card Slot.
- 2A (W=2mm) Recommended.
- Please consider the number of vias when layer of MF_VOUT is changed.
Please apply external parts, R456, C457, R415 for RXC, CPO, and RREF, as close as possible to R5U220.
R3209 0R2J-2-GPR3209 0R2J-2-GP C3213SCD022U25V2KX-GP C3213SCD022U25V2KX-GP
1 2
C E
PDTC115TE-GP
PDTC115TE-GP
PCIE_CLK_CR_RQ2# 20
3D3V_S0
Q3201
Q3201
R1
R1
B
2
1 2
1 2 1 2
R3210
R3210 33KR2F-GP
33KR2F-GP
Please apply capacitors for MF_VOUT as close as possible to connector Otherwise
CLK_PCIE_CR# 20 CLK_PCIE_CR 20 PLT_RST# 5,18,27,36,65,66,71,80,82,83
PCIE_TXN3 20 PCIE_TXP3 20
PCIE_RXN3 20 PCIE_RXP3 20
Please apply equal trace length for these signal pairs; CLK_PCIE_CR, CLK_PCIE_CR# PCIE_TXN3, PCIE_TXP3 PCIE_RXN3_C, PCIE_RXP3_C PCIE_RXN3, PCIE_RXP3
Please apply differential impedance control for these signal pairs in conformity with Motherboard Design Guide; CLK_PCIE_CR, CLK_PCIE_CR# PCIE_TXN3, PCIE_TXP3 PCIE_RXN3_C, PCIE_RXP3_C PCIE_RXN3, PCIE_RXP3
Please apply AC Coupling capacitors, C455 and C454, for TXP/TXN as close as possible to R5U220.
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
R5U220 (CARD READER)
R5U220 (CARD READER)
R5U220 (CARD READER)
LLW-1 / LGG-1
LLW-1 / LGG-1
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
LLW-1 / LGG-1
Taipei Hsien 221, Taiwan, R.O.C.
1
of
32 94
of
32 94
of
32 94
-1
-1
-1
A
4 4
3 3
B
C
D
E
BLANK
2 2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
1 1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
A
B
C
Date: Sheet
D
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1394
1394
1394
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
33 94Tuesday, January 18, 2011
33 94Tuesday, January 18, 2011
33 94Tuesday, January 18, 2011
of
of
of
E
-1
-1
-1
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
5
4
3
Date: Sheet
2
Smart Card Reader
Smart Card Reader
Smart Card Reader
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
34 94Tuesday, January 18, 2011
34 94Tuesday, January 18, 2011
34 94Tuesday, January 18, 2011
of
of
of
1
-1
-1
-1
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
5
4
3
Date: Sheet
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
USB3.0
USB3.0
USB3.0
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
35 94Tuesday, January 18, 2011
35 94Tuesday, January 18, 2011
35 94Tuesday, January 18, 2011
of
of
of
1
-1
-1
-1
A
B
C
D
E
DY
IMVP_PWRGD
R3609 0R2-PT5-LILY-GPR3609 0R2-PT5-LILY-GP
IMVP_PWRGD28,42
4 4
S0_PWR_GOOD19,27 PWR_1D05V_EN 45
1 2
R3610 0R2-PT5-LILY-GPR3610 0R2-PT5-LILY-GP
1 2
IMVP_PWRGD_R S0_PWR_GOOD_R
DY
DY
12
C3613
C3613 SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
DY
R3614 0R2J-2-GP
R3614 0R2J-2-GP
1 2
U3603
U3603
1
B
2
A
3
GND
74LVC1G08GW-1-GP
74LVC1G08GW-1-GP
VCC
Y
SYS_PWROK
5 4
3D3V_S5
R3613
R3613
1 2
0R2-PT5-LILY-GP
0R2-PT5-LILY-GP
Run Power
DCBATOUT
R3619 10KR2J-3-GPR3619 10KR2J-3-GP
3 3
3D3V_AUX_S5
R3612 10KR2J-3-GPR3612 10KR2J-3-GP
PM_SLP_S3#19,27,37,47,82
2 2
H_CPUPWRGD5,22
PLT_RST#5,18,27,32,65,66,71,80,82,83
1 1
A
1 2
R3618 330KR2J-L1-GPR3618 330KR2J-L1-GP
1 2
1 2
Q3603
Q3603
G
D
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
R3601 1KR2J-1-GP
R3601 1KR2J-1-GP
1 2
R3616 4K7R2J-2-GPR3616 4K7R2J-2-GP
3V_5V_EN41
12
12
DY
DY
R3602
R3602 200KR2J-L1-GP
200KR2J-L1-GP
PM_SLP_S3 PM_SLP_S3#
DY
DY
12
R3632
R3632
2K2R2J-2-GP
2K2R2J-2-GP
Q3604
Q3604 NDS0610-G-GP
NDS0610-G-GP
Z_12V
Z_12V_G3
1D05V_VTT
2
1
R3603 2KR2F-3-GPR3603 2KR2F-3-GP
DS
G
12
R3617
R3617 100KR2J-1-GP
100KR2J-1-GP
2nd = 84.DM601.03F
2nd = 84.DM601.03F
R3622 56R2F-1-GP
R3622 56R2F-1-GP
H_PWRGD_R
12
C3602
C3602 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3
D3601
D3601 BAS16GP-GP
BAS16GP-GP
12
B
12
R3620
R3620 10KR2J-3-GP
10KR2J-3-GP
Z_12V_D4
Q3605
Q3605
5 6
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
DY
DY
12
B
34 2 1
E
C
Power Sequence
SYS_PWROK 19
12
C3612
C3612 SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
RUN_ENABLE
12
12
C3606
C3606
SCD22U25V3KX-GP
SCD22U25V3KX-GP
H_THERMTRIP# 5,22,85
Q3601
Q3601
CHT2222AGP-GP-U
CHT2222AGP-GP-U
PURE_HW_SHUTDOW N# 27,28
S5_ENABLE 27
R3621
R3621 330KR2J-L1-GP
330KR2J-L1-GP
KA
DY
DY
C3607
C3607 SCD1U25V3KX-GP
SCD1U25V3KX-GP
1 2
R3626
R3626 0R2J-2-GP
0R2J-2-GP
1 2
D3602
D3602 MMPZ5239BGP-GP
MMPZ5239BGP-GP
RUN_ENABLE_S
C
RUNPWROK19,37,45,46,47
12
C3611
C3611 SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
5V_S0
3D3V_S0
1D5V_S0
PM_SLP_S3#
1 2 3 4 5
1 2 3 4 5
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
2nd = 84.08039.037
2nd = 84.08039.037
1D5V_S0
MAX Current 3000 mA Design Current 2100 mA
PM_SLP_S3#
DY
DY
U3609
U3609
1
B
2
A
3
GND
74LVC1G08GW-1-GP
74LVC1G08GW-1-GP
5V_S5
U3608
U3608
S
D
S
D
S
S S
S GD
GD
AO4468-GP
AO4468-GP
84.04468.037
84.04468.037
U3607
U3607
S
S S
S S
S GD
GD
AO4468-GP
AO4468-GP
84.04468.037
84.04468.037
84.00460.037
84.00460.037
8
D
D
7
D
D
6
D
D
8
D
D
7
D
D
6
U3605
U3605
S
D
S
1 2 3 4 5
D
S
D
S
D
S
D
S
D D
D
G
G
3D3V_S5
8 7 6
Total= 15A
5V_S5
U3610
U3610
1
VCC
2
ON
3
DIS2
4
GND
SLG55221-130010VTR-GP
SLG55221-130010VTR-GP
74.55221.0E3
74.55221.0E3
VCC
Y
1D5V_S3
D
5 4
NC#9
G1/G2
S/DIS1
3D3V_S5
3D3V_S5
R3608 100KR2J-1-GPR3608 100KR2J-1-GP
1 2
5V_S5
9 8
PG
7 6 5
D
PS_S3CNTRL
D
Q3606
Q3606 2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
S
G
PM_SLP_S3#
20100805 V1.8
3D3V_S0
5V_S0
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
RUN_ENABLE_S
SLG_RUN_ENABLE
POWER SEQUENCE
POWER SEQUENCE
POWER SEQUENCE
PS_S3CNTRL 37
12
DY
DY
R3615
R3615 0R2J-2-GP
0R2J-2-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
E
of
36 94Tuesday, January 18, 2011
of
36 94Tuesday, January 18, 2011
of
36 94Tuesday, January 18, 2011
-1
-1
-1
5
Close to CPU S3 Power Reduction Circuit Processor VREF_DQ Implementation
D D
R3708 0R2J-2-GPR3708 0R2J-2-GP
M_VREF_DQ_DIMM07,14
PS_S3CNTRL36
C C
5V_S5
12
DY
DY
R3714
R3714 100KR2J-1-GP
1D5V_S0
DY
DY
R3715
R3715 4K7R2J-2-GP
4K7R2J-2-GP
1.5V_RUN_CPU_EN
12
DY
DY
12
C3704
C3704 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
100KR2J-1-GP
1.5V_RUN_CPU_EN#
3
DY
DY
Q3706
Q3706
PMBS3904-1-GP
PMBS3904-1-GP
1
84.03904.L06
84.03904.L06
2ND = 84.03904.P11
2ND = 84.03904.P11
2
3rd = 84.03904.L06
3rd = 84.03904.L06
1 2
Q3705
Q3705
G
S
DY
DY
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
4
Q3704
Q3704
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
0D75V_EN_L
D
+V_SM_VREF
0D75V_EN
D
PM_SLP_S3#
DY
DY
R3707 0R2J-2-GP
R3707 0R2J-2-GP
1 2
Q3708
Q3708
D
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
3D3V_S0
12
DY
DY
R3712
R3712 10KR2J-3-GP
10KR2J-3-GP
R3711
R3711
12
0R0402-PAD
0R0402-PAD
1 2
DY
DY
R3716
R3716 0R2J-2-GP
0R2J-2-GP
S
G
R3710
R3710 0R2J-2-GP
0R2J-2-GP
1 2
DY
DY
12
C3705
C3705 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3
+V_SM_VREF_CNT 9
R3705
R3705 100KR2J-1-GP
100KR2J-1-GP
1 2
PM_SLP_S3# 19,27,36,47,82
1.05VTT_PWRGD 45,48
0D75V_EN 46
2
Close to DIMM S3 Power Reduction Circuit SM_DRAMPWROK
1D5V_S00D75V_S0
12
R3703
R3703 22R2J-2-GP
22R2J-2-GP
Q3701
Q3701
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK
DY
DY
1 2
Q3703
Q3703
SM_DRAMRST#5
S
G
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
R37090R2J-2-GP
R37090R2J-2-GP
1D5V_S3
D
D
S
G
12
R3706
R3706 1KR2J-1-GP
1KR2J-1-GP
S3 Power Reduction Circuit SM_DRAMRST#
SM_DRAMRST#_D
12
C3702
C3702 SC100P50V2JN-3GP
SC100P50V2JN-3GP
DRAMRST_CNTRL_PCH 20
2
PS_S3CNTRLPS_S3CNTRL
R3721
R3721 1KR2J-1-GP
1KR2J-1-GP
1 2
12
D
G
1
DY
DY
R3704
R3704 220R2J-L2-GP
220R2J-L2-GP
DY
DY
Q3702
Q3702 2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
S
DDR3_DRAMRST# 14,15
B B
3D3V_S5
12
R3718
R3718 200R2F-L-GP
200R2F-L-GP
U3701
U3701
PM_DRAM_PWRGD5,19
DY
DY
R3701 0R2J-2-GP
R3701 0R2J-2-GP
RUNPWROK19,36,45,46,47
1.05VTT_PWRGD45,48
A A
5
1 2
R3713 0R2J-2-GPR3713 0R2J-2-GP
1 2
SM_DRAMPWROK must have a maximum of 15ns rise or fall time over VDDQ * 0.55± 200mV and the edge must be monotonic
0D75V_EN_1
DY
DY
12
C3701
C3701 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PM_DRAM_PWRGD5,19
4
1
IN B
2
IN A GND3OUT Y
74VHC1G09DFT2G-GP
74VHC1G09DFT2G-GP
OD AND gate required
DY
DY
R3722
R3722
Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK
1D5V_S03D3V_S5
CEKLT V1.0: PCH to 1K,CUP to 200R
12
R3702
R3702 200R2F-L-GP
5
VCC
4
VDDPWRGOOD_R
12
0R2J-2-GP
0R2J-2-GP
VDDPWRGOOD_R
200R2F-L-GP
1 2
R3719
R3719 130R2F-1-GP
130R2F-1-GP
1 2
For U3701 not OD AND gate R3719 to 64.15015.6DL R3720 to 64.75005.6DL R3702 to DY
3
VDDPWRGOOD 5
DY
DY
R3720
R3720 0R2J-2-GP
0R2J-2-GP
C3703
C3703
2
DRAMRST_CNTRL_PCH
12
SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
ADAPTER OCP / S3 reduction
ADAPTER OCP / S3 reduction
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
ADAPTER OCP / S3 reduction
A3
A3
A3
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
37 94Tuesday, January 18, 2011
37 94Tuesday, January 18, 2011
37 94Tuesday, January 18, 2011
1
of
of
of
-1
-1
-1
5
D D
C C
4
3
2
1
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
Date: Sheet
2
DCIN_JACK
DCIN_JACK
DCIN_JACK
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
of
38 94Tuesday, January 18, 2011
of
38 94Tuesday, January 18, 2011
of
38 94Tuesday, January 18, 2011
1
-1
-1
-1
5
D D
4
BT+
3
2
1
BATTERY CONNECTOR
12
PC3901
PC3901 SCD1U50V3KX-GP
SCD1U50V3KX-GP
C C
BATT_SENSE40
12
DY
DY
PL3903
PL3903 MLVS0402M04-GP
MLVS0402M04-GP
BAT_SCL27,40 BAT_SDA27,40
BAT_IN#27
PD3901
PD3901 MMPZ5232BGP-GP
MMPZ5232BGP-GP
KA
PRN3901
PRN3901
1 2 3 4 5
SRN33J-7-GP
SRN33J-7-GP
8 7 6
DY
DY
12
PC3905
PC3905 SC1000P50V3JN-GP-U
SC1000P50V3JN-GP-U
12
DY
DY
PL3901
PL3901 MLVS0402M04-GP
MLVS0402M04-GP
12
DY
DY
PL3902
PL3902 MLVS0402M04-GP
MLVS0402M04-GP
12
PC3902
PC3902 SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
PR3901 0R2J-2-GPPR3901 0R2J-2-GP
1 2
BATA_SCL_1
BATA_SDA_1
BAT_IN#_1
DY
DY
12
PC3904
PC3904 SC10P50V2JN-4GP
SC10P50V2JN-4GP
12
12
F3901
F3901 FUSE-20A24V-1-GP
FUSE-20A24V-1-GP
BT+_F3901
DY
DY
PC3903
PC3903 SC10P50V2JN-4GP
SC10P50V2JN-4GP
BAT1
BAT1
1
BAT_VCC
2
BAT_VCC
3
I2C_CLK
4
I2C_DATA
5
TEMP
TYCO-CON7-30-GP
TYCO-CON7-30-GP
NP1 NP2
GND GND
8
8
9
9
NP1 NP2
6 7
TP3901 AFTE14P-GPTP3901 AFTE14P-GP TP3902 AFTE14P-GPTP3902 AFTE14P-GP TP3903 AFTE14P-GPTP3903 AFTE14P-GP
B B
TP3904 AFTE14P-GPTP3904 AFTE14P-GP
BAT_IN#_1
1
BATA_SDA_1
1
BATA_SCL_1
1
BT+_F3901
1
Table 39.1- Surface Mount Zener ESD multi-source
Supplier
CHENMKO
DIODES
Description Lenovo P/N Wistron P/N
MMPZ5232BGP
N/A 83.5R603.R3F
N/AMMSZ5232BS-7-F
83.5R603.K3F
83.5R603.Q3FPANJIT MMSZ5232BS N/A
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
BATT_CONN
BATT_CONN
BATT_CONN
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
of
39 94Tuesday, January 18, 2011
of
39 94Tuesday, January 18, 2011
of
39 94Tuesday, January 18, 2011
-1
-1
-1
5
4
3
2
1
AD+
PU4001
PU4001
D
D
8
D
D
7
D
D
6
P1403EV8-GP
D D
C C
AD_IA27
B B
A A
P1403EV8-GP
84.P1403.B37
84.P1403.B37
PR4001
PR4001 10KR2F-2-GP
10KR2F-2-GP
1 2
DC_IN_D
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
12
PR4010
PR4010
49K9R2F-L-GP
49K9R2F-L-GP
CHG_AGND
PR4013
PR4013
1 2
0R0402-PAD
0R0402-PAD
PC4011
PC4011 SC220P50V2KX-3GP
SC220P50V2KX-3GP
5
PQ4001
PQ4001
BQ24745_ACOK
3D3V_AUX_S5
NEAR
S
S
1
S
S
2
S
S
3
GD
GD
45
AD+_G_1
1234
5
6
12
PC4007
PC4007
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SC150P50V2JN-3GP
SC150P50V2JN-3GP
PC4010
PC4010
1 2
12
PC4012
PC4012
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
BQ24745_EAO_RC
12
BQ24745_VREF
SRN100KJ-L-GP
SRN100KJ-L-GP
PR4018 0R2J-2-GPPR4018 0R2J-2-GP
CHG_AGND
12
PR4002
PR4002 100KR2J-1-GP
100KR2J-1-GP
AD+_G_2
12
PR4003
PR4003 49K9R2F-L-GP
49K9R2F-L-GP
AD_JK
12
3D3V_AUX_S5
12
PC4008
PC4008 SC1U10V3KX-3GP
SC1U10V3KX-3GP
CHG_AGND
BQ24745_FBO_RC BQ24745_FBO
PR4015
PR4015
1 2
1 2
PRN4001
PRN4001
1 2 3 4 5
1 2
200KR2F-L-GP
200KR2F-L-GP
PR4016
PR4016 7K5R2F-1-GP
7K5R2F-1-GP
PC4013SC56P50V2JN-2GP PC4013SC56P50V2JN-2GP
8
CHG_ON#
7 6
BQ24745_CHG_ON
PR4006
PR4006 316KR3F-2-GP
316KR3F-2-GP
AC_IN
12
AD+ total power R1 R2
65w
90w
AD+_TO_SYS
AD_JK
AK
PD4001
PD4001 1SS400GGP-GP
1SS400GGP-GP
12
SC1U25V5KX-1GP
SC1U25V5KX-1GP
PR4011
PR4011
1 2
0R0402-PAD
0R0402-PAD
BAT_SCL27,39
BAT_SDA27,39
PR4014
PR4014 4K7R2J-2-GP
4K7R2J-2-GP
1 2
12
PC4014
PC4014 SC1U10V3KX-3GP
SC1U10V3KX-3GP
AC_IN 27
PC4001
PC4001
BQ24745_DCIN BQ24745_ACIN
BQ24745_ACOK
CHG_AGND
BQ24745_IINP
BQ24745_EAI BQ24745_EAO BQ24745_VREF BQ24745_CHG_ON
4
CHG_AGND
CHG_AGND
R2
PR4008
PR4008 49K9R2F-L-GP
49K9R2F-L-GP
1 2
PU4003
PU4003
22
DCIN
2
ACIN
11
VDDSMB
13
ACOK
10
SCL
9
SDA
14
NC#14
8
VICM
6
FBO
5
EAI
4
EAO
3
VREF
7
CE
12
GND
BQ24745RHDR-GP
BQ24745RHDR-GP
187k
121k
BQ24745_VREF
12
R1
PR4007
PR4007 121KR2F-L-GP
121KR2F-L-GP
20100707
CHG_ICREF
CHG_AGND
1
ICREF
GND
29
BQ24745_CHG_ON
DY
DY
12
C4001
C4001 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
49.9k
49.9k
PC4002
PC4002
SCD1U50V3KX-GP
SCD1U50V3KX-GP
CSSP
CSSN
ICOUT
BOOT VDDP
UGATE
PHASE
LGATE
PGND CSOP CSON
NC#16
VFB
AD+ total power R1 R2
80w 49.9k137k
1 2
PR4004
PR4004 D01R3721F-GP-U
D01R3721F-GP-U
20100518 WAYNE
PG4001
BQ24745_CSSP
12
28
BQ24745_CSSN
27
BQ24745_ICOUT
26
BQ24745_BST
25
BQ24745_VDDP
21
24
BQ24745_LX1
23
20
19 18 17
16
BATT_SENSE
15
PQ4002
PQ4002
D
2N7002K-2-GP
2N7002K-2-GP
PG4001
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
12
SCD1U50V3KX-GP
SCD1U50V3KX-GP
1 2
PR40120R2J-2-GP PR40120R2J-2-GP
12
PC4015
PC4015 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
CHG_AGND
S
G
3
PG4002
PG4002
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
12
12
PC4003
PC4003
PC4004
PC4004 SCD1U50V3KX-GP
SCD1U50V3KX-GP
STOP_CHG#
SCD1U50V3KX-GP
SCD1U50V3KX-GP
BATT_SENSE 39
CHG_ON#
1 2
AC_IN to KBC
STOP_CHG# connects to KBC
3D3V_AUX_S5
CHG_AGND
PD4003
PD4003
K A
CH520S-30GP-GP-U
CH520S-30GP-GP-U
PC4017
PC4017
1 2
24745_LOW_G
SCD1U50V3KX-GP
SCD1U50V3KX-GP
12
PC4018
PC4018 SC10U25V6KX-1GP
SC10U25V6KX-1GP
CHG_ON# 27
12
DY
DY
PR4009
PR4009 10KR2F-2-GP
10KR2F-2-GP
PC4009
PC4009
1 2
SC1U10V3KX-3GP
SC1U10V3KX-3GP
24745_HIGH_G
PC4016
PC4016
12
DCBATOUT
STOP_CHG# 27
PU4004
PU4004
GD
GD
4 5
SIS412DN-T1-GE3-GP
SIS412DN-T1-GE3-GP
PU4005
PU4005
GD
GD
4 5
SIS412DN-T1-GE3-GP
SIS412DN-T1-GE3-GP
12
PC4019
PC4019 SC10U25V6KX-1GP
SC10U25V6KX-1GP
678
DDD
DDD
SSS
SSS
123
678
DDD
DDD
SSS
SSS
123
MAX8731A_CSIP MAX8731A_CSIN
2
AD+
12
PL4001
PL4001
1 2
IND-5D6UH-56-GP
IND-5D6UH-56-GP
12
PR4019
PR4019 2D2R3-1-U-GP
2D2R3-1-U-GP
DY
DY
12
PC4024
PC4024 SC470P50V2KX-3GP
SC470P50V2KX-3GP
DY
DY
12
PC4020
PC4020 SC10U25V6KX-1GP
SC10U25V6KX-1GP
PC4005
PC4005
DCBATOUT
BT+
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
PG4004
PG4004
12
BT+
PD4002
PD4002 SMF18A-GP
SMF18A-GP
83.SMF18.AAH
83.SMF18.AAH
A K
12
PC4006
PC4006
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
84.P1403.B37
84.P1403.B37
PR4005
PR4005 470KR2F-GP
470KR2F-GP
PU4002
PU4002
1 2 3 4 5
P1403EV8-GP
P1403EV8-GP
S
D
S
D D
D D
D
12
PC4023
PC4023
D01R3721F-GP-U
D01R3721F-GP-U
BT+_R
1 2
PR4017
PR4017
PG4003
PG4003
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
12
8 7 6
12
SC10U25V5KX-GP
SC10U25V5KX-GP
S
S S
S GD
GD
SC10U25V5KX-GP
SC10U25V5KX-GP
20100518 WAYNE
BT+
12
PC4021
PC4021 SC10U25V6KX-1GP
SC10U25V6KX-1GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
12
PC4025
PC4025 SC10U25V6KX-1GP
SC10U25V6KX-1GP
Charger_BQ24745
Charger_BQ24745
Charger_BQ24745
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
12
PC4022
PC4022 SCD1U50V3KX-GP
SCD1U50V3KX-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
40 94Tuesday, January 18, 2011
40 94Tuesday, January 18, 2011
40 94Tuesday, January 18, 2011
1
of
of
of
-1
-1
-1
5
SSID = PWR.Plane.Regulator_5v3p3v
4
3
2
1
DCBATOUT
PWR_5V_DCBATOUT
PG4104
PG4104
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4105
PG4105
SCD47U25V3KX-1GP
SCD47U25V3KX-1GP
3V_5V_EN9528EN2
3D3V_S5
12
12
DY
DY
PC4130
PC4130
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
GAP-CLOSE-PWR
GAP-CLOSE-PWR
GAP-CLOSE-PWR
GAP-CLOSE-PWR
GAP-CLOSE-PWR
GAP-CLOSE-PWR
GAP-CLOSE-PWR
GAP-CLOSE-PWR
SIS406DN-T1-GE3-GP
SIS406DN-T1-GE3-GP
PC4118
PC4118
1 2
SIS406DN-T1-GE3-GP
SIS406DN-T1-GE3-GP
DY
DY
PR4110
PR4110 100KR2J-1-GP
100KR2J-1-GP
3V_5V_POK 19
1 2
PG4122
PG4122
1 2
PG4124
PG4124
1 2
PG4125
PG4125
1 2
D D
12
C C
3D3V_PWR
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
B B
3D3V_PWR3D3V_S5
PG4106
PG4106
12
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4107
PG4107
12
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4108
PG4108
12
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4109
PG4109
12
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4110
PG4110
12
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4111
PG4111
12
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PC4119
PC4119
12
12
PTC4102
PTC4102
ST220U6D3VDM-20GP
ST220U6D3VDM-20GP
EC4101
EC4101 SCD1U25V2KX-GP
SCD1U25V2KX-GP
12
SANYO cap 220uF
6.3V, ESR=25mohm
PC4112
PC4112 SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
Close to VFB Pin (pin5)
IND-3D3UH-116-GP
IND-3D3UH-116-GP
68.3R31A.10V
68.3R31A.10V
PG4121
PG4121
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
12
SC470P50V2KX-3GP
SC470P50V2KX-3GP
12
PR4111
PR4111 6K65R2F-GP
6K65R2F-GP
12
PR4116
PR4116 10KR2F-2-GP
10KR2F-2-GP
DCBATOUT
12
PC4110
PC4110 SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
PL4101
PL4101
1 2
2D2R3-1-U-GP
2D2R3-1-U-GP
PC4102
PC4102
12
12
PWR_3D3V_DCBATOUT
PG4101
PG4101
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4102
PG4102
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4103
PG4103
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
12
DY
DY
PR4101
PR4101
DY
DY
12
DY
DY
PR4112
PR4112 0R2J-2-GP
0R2J-2-GP
PWR_3D3V_FB 2_R
PC4124
PC4124 SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
DY
DY
PWR_3D3V_DCBATOUT
678
D
DDD
DDD
PU4101
PU4101
SIS412DN-T1-GE3-GP
SIS412DN-T1-GE3-GP
SSS
GD
SSS
GD
123
4 5
SG
D
678
DDD
DDD
PU4102
PU4102 SIS412DN-T1-GE3-GP
SIS412DN-T1-GE3-GP
SSS
GD
SSS
GD
123
4 5
G
S
PC4115
PC4115
1 2
SCD47U25V3KX-1GP
SCD47U25V3KX-1GP
3V_5V_EN36
12
DY
DY
PC4131
PC4131
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
PWR_3D3V_BOO T2
1 2
PR4105 2D2R3J-2-GPPR4105 2D2R3J-2- GP
PWR_3D3V_U G ATE2
PWR_3D3V_PHASE2
PWR_3D3V_LGAT E2
PWR_3D3V_FB 2
PWR_3D3V_VOU T2
PR4109 0R2J-2-GPPR4109 0R2J- 2-GP
1 2
12
12
PWR_5V3D3V_VR EF
PR4137
PR4137
PR4138
PR4138
68KR2F-GP
68KR2F-GP
41K2R2F-GP
41K2R2F-GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
31
32
11
9528ILIM2
9528FS2
10
12
12
PC4122
PC4122
33
BD95280MUV-GP
BD95280MUV-GP
3D3V_PWR_2
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PC4125
PC4125 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
3
2
1
7
4
8
6
5
9
PG4119
PG4119
U4103
U4103
BOOT2
HG2
SW2
LG2
PGND2
FB2
VO2
EN2
ILIM2
NC#6
FS2
NC#5
REF2V
CTL
FIN
DCBATOUT
28
PWR_5V3D3V_VREG2
12
12
PC4101
PC4101 SC10U25V6KX-1GP
SC10U25V6KX-1GP
30
VIN
BOOT1
HG1
SW1
LG1
PGND1
FB1
VO1
EN1
ILIM1
NC#19
FS1
PGOOD
MCTL1
MCTL2
AGND
REG129REG2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PWR_5V3D3V_VREG1
12
PC4126
PC4126 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
22
23
24
26
25
14
27
21
17
19
15
20
18
16
13
G9306
G9306
1 2
12
PC4113
PC4113 SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
PWR_5V_BOOT 1
PWR_5V_UGAT E1
PWR_5V_PHASE1
PWR_5V_LGATE1
PWR_5V_FB1
PWR_5V_VOUT 1
9528EN1
PR4130 0R2J-2-GPPR4130 0R2J- 2-GP
9528ILIM1
9528FS1
9528MCTL1
9528MCTL2
12
75KR2F-GP
75KR2F-GP
5V_PWR_2
1 2
PR4135
PR4135
PWR_5V_BOOT 1_1PWR_3D3V_BOO T1
PR41062D2R3J-2-GP PR41062D2R3J-2-GP
12
12
PR4131
PR4131
41K2R2F-GP
41K2R2F-GP
PU4104
PU4104
PU4105
PU4105
5V_PWR
678
DDD
D
DDD
D
D
SSS
SSS
G
G
123
4 5
G
S
D
678
DDD
D
DDD
D
SSS
SSS
G
G
123
4 5
SG
5V_AUX_S5 5V_AUX_S5
9528MCTL1 9528MCTL2
PG4112
PG4112
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4113
PG4113
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4114
PG4114
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4115
PG4115
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4116
PG4116
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4118
PG4118
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4120
PG4120
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4123
PG4123
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
12
PC4114
PC4114 SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
1 2
IND-2D2UH-122-GP
IND-2D2UH-122-GP
12
68.2R21B.10J
DY
DY
PR4102
PR4102 2D2R3-1-U-GP
2D2R3-1-U-GP
DY
DY
12
PC4103
PC4103 SC470P50V2KX-3GP
SC470P50V2KX-3GP
12
DY
DY
PR4136
PR4136 0R2J-2-GP
0R2J-2-GP
12
PR4134
PR4134 0R2J-2-GP
0R2J-2-GP
PL4102
PL4102
5V_S5
12
DY
DY
PR4132
PR4132 0R2J-2-GP
0R2J-2-GP
12
PR4133
PR4133 0R2J-2-GP
0R2J-2-GP
12
12
PWR_5V_FB1_R
PWR_5V_DCBATOUT
12
PC4111
PC4111 SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
DY
DY
PR4114
PR4114 0R2J-2-GP
0R2J-2-GP
PC4128
PC4128 SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
DY
DY
Close to VFB Pin (pin2)
DY
DY
12
EC4102
EC4102 SCD1U25V2KX-GP
SCD1U25V2KX-GP
PG4117
PG4117
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
12
12
PR4115
PR4115 33KR2F-GP
33KR2F-GP
12
PR4119
PR4119 21K5R2F-GP
21K5R2F-GP
12
PC4120
PC4120 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Matsuki cap 220uF
6.3V, ESR=17mohm
5V_PWR
12
PTC4101
PTC4101 SE220U6D3VM-21-GP
SE220U6D3VM-21-GP
3D3V_PWR_2 3D3V_AUX_S5
PR4122 0R2J-2-GPPR4122 0R2J- 2-GP
A A
PR4139 0R2J-2-GPPR4139 0R2J- 2-GP
12
PR4123 0R2J-2-GP
PR4123 0R2J-2-GP
Table 41.1 - POSCAP multi-source
Supplier
SANYO
NEC-TOKIN
Descri pt ion L enovo P/N Wistron P/N
77.22271.27L
6TPE220MAP
V0J227M(25)12RE
N/A
77.C2271.00L
N/A
5
4
12
DY
DY
5V_AUX_S55V_PW R_2
12
<Core Design>
<Core Design>
<Core Design>
Wistron Corporat ion
Wistron Corporat ion
Wistron Corporat ion
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
Title
Title
Title
DC/DC 3D3V5V
DC/DC 3D3V5V
DC/DC 3D3V5V
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
3
2
Date: Sheet
Taipei Hsien 221, Taiw an, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
41 94Tuesday, January 18, 2011
41 94Tuesday, January 18, 2011
41 94Tuesday, January 18, 2011
-1
-1
-1
of
of
of
5
PR4242
PR4242
PC4218
PC4218
10R2J-2-GP
10R2J-2-GP
SC3300P50V2KX-1GP
SC3300P50V2KX-1GP
1 2
1 2
PWR_CPUCORE_TRBSTPWR_CPUCORE_TRBSTPWR_CPUCORE_TRBST
D D
Place close to VCC_CORE hot spot
1D05V_VTT
H_PROCHOT#5,27
H_CPU_SVIDDAT8 VR_SVID_ALERT#8
C C
H_CPU_SVIDCLK8
PR4203
PR4203
PR4266
PR4266 0R2J-2-GP
0R2J-2-GP
IMVP_PWRGD28,36
1 2
1 2
PR4233
PR4233
130R2F-1-GP
130R2F-1-GP
1 2
PR4243
PR4243 24K9R2F-L-GP
24K9R2F-L-GP
VSSSENSE8
VCCSENSE8
PR4245
PR4245
8K25R2F-1-GP
8K25R2F-1-GP
1D05V_VTT
12
PR4234
PR4234
12
75R2F-2-GP
75R2F-2-GP
H_PROCHOT_R#
12
PR4235
PR4235
75R2F-2-GP
75R2F-2-GP
1 2
0R2-PT5-LILY-GP
0R2-PT5-LILY-GP
56R2F-1-GP
56R2F-1-GP
PR4268
PR4268
12
3D3V_S0
D85V_PWRGD19,48
PC4201 SC1U10V2KX-1GPPC4201 SC1U10V2KX-1GP
1 2
5V_PWR
B B
Place close to VCC_GFXCORE hot spot
1 2
PR4201 2R3J-2-GPPR4201 2R3J-2-G P
PC4202
PC4202
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
DCBATOUT
PR4247
PR4247
8K25R2F-1-GP
8K25R2F-1-GP
PR4244
PR4244 1K21R2F-2-GP
1K21R2F-2-GP
1 2
12
PC4219
PC4219 SC3300P50V2KX-1GP
SC3300P50V2KX-1GP
PR4231
PR4231
12
0R0402-PAD-1-GP
0R0402-PAD-1-GP
PR4230
PR4230
12
0R0402-PAD-1-GP
0R0402-PAD-1-GP
12
PR4264
PR4264 NTC-100K-11-GP
NTC-100K-11-GP
12
PC4220
PC4220
SCD1U25V2KX-GP
SCD1U25V2KX-GP
3D3V_S0
12
PR4236
PR4236
10KR2F-2-GP
10KR2F-2-GP
PR4237
PR4237
1 2
10KR2F-2-GP
10KR2F-2-GP
PR4206
PR4206
1 2
0R2-PT5-LILY-GP
0R2-PT5-LILY-GP
1 2
1 2
PR4209 1KR2F-3-GPPR4209 1KR 2F-3-GP
PWR_CPUCORE_TSNA
12
12
PR4265
PR4265 NTC-100K-11-GP
NTC-100K-11-GP
PC4216 SC1KP50V2KX-1GPPC4216 SC1KP50V2KX-1GP
PWR_CPUCORE_VSP
PWR_CPUCORE_TSN
H_CPU_SVIDDAT
H_CPU_SVIDCLK
VR_SVID_ALERT#
PWR_CPUCORE_RDY
PWR_CPUCORE_RDYA
PWR_CPUCORE_EN
PWR_CPUCORE_VCC
PR4207
PR4207
1 2
10KR2F-2-GP
10KR2F-2-GP
PWR_CPUCORE_VRMP
GT1_24A_4.6m GT2_33A_3.9m
PR4259
PR4260
PR4215
PR4211
53.6K_1%
13.7K_1%
24.9K_1%
18.7K_1%
63.4K_1%
14.7K_1%
23.2K_1%
26.1K_1%
PWR_CPUCORE_DOUTPWR_CPUCORE_DOUTPW R_CPUCORE_DOUTPWR_CPUCORE_DOUT
1 2
1 2
PG4201
PG4201
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PU4201
PU4201
PWR_CPUCORE_ROSC
12
NCP6131S52MNR2G-GP-U
NCP6131S52MNR2G-GP-U
PC4221
PC4221
1 2
PR4221
PR4221
SCD1U25V2KX-GP
SCD1U25V2KX-GP
0R2J-2-GP
0R2J-2-GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
VSS_AXG_SENSE9
VCC_AXG_SENSE9
4
PC4223
PC4223 SC22P50V2JN-4GP
SC22P50V2JN-4GP
PC4222
PC4222
1 2
1 2
PR4249
PR4249 24D9R2F-L-GP
24D9R2F-L-GP
1 2
PR4250
PR4250 1KR2F-3-GP
1KR2F-3-GP
PWR_CPUCORE_DOUT
PWR_CPUCORE_TRBST
PWR_CPUCORE_VSN
52
50
51
53
VSN
GND
1
VSP
2
TSENSE
3
VRHOT#
4
SDIO
5
SCLK
6
ALERT#
7
VR_RDY
8
VR_RDYA
9
ENABLE
10
VCC
11
ROSC
12
VRMP
13
TSENSEA
DY
DY
PC4217
PC4217
TRBST
DIFFOUT
VSNA14VSPA
FBA16TRBSTA18COMPA19ILIMA20DROOPA21IOUTA
15
1 2
PWR_CPUCORE_VSPA
PWR_CPUCORE_VSNA
12
12
PWR_CPUCORE_FBAPWR_CPUCORE_FBAPWR_CPUCORE_FBAPWR_CPUCORE_FBA
PWR_CPUCORE_FBAPWR_CPUCORE_FBA
PR4239
PR4239
PR4238
PR4238
0R0402-PAD-1-GP
0R0402-PAD-1-GP
0R0402-PAD-1-GP
0R0402-PAD-1-GP
PC4206
PC4206 SC100P50V2JN-3GP
SC100P50V2JN-3GP
PR4218 1KR2F-3-GPP R4218 1KR2F-3-GP
1 2
SC100P50V2JN-3GP
SC100P50V2JN-3GP
PC4224
PC4224
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
1 2
1 2
PR4251
PR4251 6K19R2F-GP
6K19R2F-GP
PWR_CPUCORE_COMPPWR_CPUCORE_COMP
12
PR4254
PR4254 12K4R2F-GP
12K4R2F-GP
PWR_CPUCORE_FB
PWR_CPUCORE_ILIM
47
48
49
FB
COMP
DIFFOUTA
17
PWR_CPUCORE_TRBSTA
1
PWR_CPUCORE_DOUTAPWR_CPUCORE_DOUTAPWR_CPUCORE_DOUTA
PWR_CPUCORE_DOUTA
TP4202
TP4202
TPAD14-GP
TPAD14-GP
PR4217_R
1 2
1 2
PC4207 SC39P50V2JN-1GPPC4207 SC39P50V2JN-1G P
1 2
PR4219
PR4219 4K75R2F-1-GP
4K75R2F-1-GP
1 2
ILIM
PWR_CPUCORE_COMPAPWR_CPUCORE_COMPAPWR_CPUCORE_COMPA
PWR_CPUCORE_COMPA
PR4219_R
45
46
DROOP
0830
PWR_CPUCORE_ILIMA
12
PR4260
PR4260 14K7R2F-L-GP
14K7R2F-L-GP
PR4217
PR4217 10R2J-2-GP
10R2J-2-GP
1 2
1 2
PC4208
PC4208 SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
CSCOMP
0830
PWR_CPUCORE_CSCOMPPWR_CPUCORE_CSCOMPPWR_CPUCORE_CSCOMPPW R_CPUCORE_CSCOMPPWR_CPUCORE_CSCOMPPWR_CPUCORE_CSCOMPPWR_CPUCORE_CSCOMPPW R_CPUCORE_CSCOMPPWR_CPUCORE_CSCOMPPWR_CPUCORE_CSCOMPPWR_CPUCORE_CSCOMPPW R_CPUCORE_CSCOMPPWR_CPUCORE_CSCOMPPWR_CPUCORE_CSCOMPPWR_CPUCORE_CSCOMPPW R_CPUCORE_CSCOMPPWR_CPUCORE_CSCOMPPWR_CPUCORE_CSCOMP
44
43
42
IOUT
CSSUM
CSCOMPA22CSSUMA
24
23
PWR_CPUCORE_IOUTAPWR_CPUCORE_IOUTA
12
12
PR4215
PR4215
23K7R2F-GP
23K7R2F-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
PWR_CPUCORE_CSCOMPA
PR4258
PR4258 NTC-220K-5-GP
NTC-220K-5-GP PR4256
PR4256 75KR2J-GP
75KR2J-GP
PWR_CPUCORE_CSREF
PC4203
PC4203 SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
1 2
41
NC#4040NC#41
CSREF
CSN2
CSP2
CSN3
CSP3
CSN1
CSP1
DRON
PWM1/ADDR
PWM3/VBOOT
PWM2/ISHED
IMAX
PWMA/IMAXA
VBOOTA
CSPA25CSNA
26
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
PWR_CPUCORE_CSPA
PC4204
PC4204
PWR_CPUCORE_CSSUMAPW R_CPUCORE_CSSUMA
1 2
PR4261
PR4261 75KR2J-GP
75KR2J-GP
1 2
PR4263
PR4263 NTC-220K-5-GP
NTC-220K-5-GP
Place close to VCC_GFXCORE Inductor
3
Place close to VCC_CORE Inductor
1 2
1 2
1 2
PC4226
PC4226
1 2
SC470P50V2KX-3GP
SC470P50V2KX-3GP PC4225
PC4225
1 2
SC1200P50V2KX-1GP
SC1200P50V2KX-1GP
PWR_CPUCORE_CSSUMPWR_CPUCORE_CSSUMPWR_CPUCORE_CSSUMPWR_CPUCORE_CSSUMPWR_CPUCORE_CSSUMPWR_CPUCORE_CSSUMPWR_CPUCORE_CSSUMPWR_CPUCORE_CSSUMPWR_CPUCORE_CSSUMPWR_CPUCORE_CSSUMPWR_CPUCORE_CSSUMPWR_CPUCORE_CSSUMPW R_CPUCORE_CSSUMPWR_CPUCORE_CSSUM
PWR_CPUCORE_IOUT
5V_PWR
PR4214
PR4214 0R2J-2-GP
0R2J-2-GP
1 2
39
38
37
PC4215
PC4215
PWR_CPUCORE_CSP3
36
SCD047U25V2KX-GP
SCD047U25V2KX-GP
35
PC4213
PC4213
PWR_CPUCORE_CSP1
34
SCD047U25V2KX-GP
SCD047U25V2KX-GP
33
PWR_CPUCORE_DRON 43,44
32
31
PR4220
PR4220
1 2
30
PWR_CPUCORE_IMAX
29
28
27
PWR_CPUCORE_VBTA
PR4208
PR4208 10KR2F-2-GP
10KR2F-2-GP
1 2
DY
1 2
1 2
DY
PC4227
PC4227 SC1200P50V2KX-1GP
SC1200P50V2KX-1GP
PC4228
PC4228 SC330P50V2KX-3GP
SC330P50V2KX-3GP
1 2
PR4262
PR4262 165KR2F-L-GP
165KR2F-L-GP
PR4262_R
PC4211
PC4211
1 2
PR4257
PR4257 165KR2F-L-GP
165KR2F-L-GP
PR421210R2J-2-GP PR421210R2J-2-GP
12
PR421310R2J-2-GP PR421310R2J-2-GP
12
SCD1U25V2KX-GP
SCD1U25V2KX-GP
12
PC4205
PC4205
1 2
1 2
1 2
0R2J-2-GP
0R2J-2-GP
PR4210 41K2R2F-GPPR4210 41K2R2F-GP
12
5V_PWR
PR4246
PR4246 0R2J-2-GP
0R2J-2-GP
PWR_CPUCORE_CSNA
PC4212
PC4212
1 2
SCD047U25V2KX-GP
SCD047U25V2KX-GP
1 2
PR4253
PR4253 137KR3-GP
137KR3-GP
1 2
PR4252
PR4252 137KR3-GP
137KR3-GP
1 2
CSN1 43 CSN3 43
PR4216
PR4216 24K3R2F-1-GP
24K3R2F-1-GP
1 2
1 2
5V_PWR
12
PWR_CPUCORE_PWMA 44
PR4211
PR4211 26K1R2F-2-GP
26K1R2F-2-GP
1 2
For Discrete only, UMA need to DY
PR425971K5R3F-1-GP PR425971K5R 3F-1-GP
CSP3 43
CSP1 43
PR42286K98R2-GP PR42286K98R2-GP
PR42266K98R2-GP PR42266K98R2-GP
0830
1 2
1 2
CSPA 44
CSN3 43
CSP3 43
CSN1 43
CSP1 43
12
PR4205
PR4205 10KR2F-2-GP
10KR2F-2-GP
PR42290R 2J-2-GP PR42290R2J-2-GP
PR42236K98R 2-GP PR42236K98R2-G P
2
12
CSNA 44
CSPA 44
PR4204
PR4204 10KR2F-2-GP
10KR2F-2-GP
1
PWR_CPUCORE_PWM1 43
PWR_CPUCORE_PWM3 43
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporat ion
Wistron Corporat ion
Wistron Corporat ion
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
Title
Title
Title
DC/DC CPU CORE1 _NCP6131
DC/DC CPU CORE1 _NCP6131
DC/DC CPU CORE1 _NCP6131
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Taipei Hsien 221, Taiw an, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
-1
-1
-1
of
94Tuesday, January 18, 2011
42
of
94Tuesday, January 18, 2011
42
of
94Tuesday, January 18, 2011
42
5
DCBATOUT
12
PTC4301
PTC4301 SE100U25VM-L1-GP
SE100U25VM-L1-GP
79.10712.L02
79.10712.L02
D D
DCBATOUT
12
PTC4308
PTC4308 SE100U25VM-L1-GP
SE100U25VM-L1-GP
79.10712.L02
79.10712.L02
PWR_CPUCORE_PW M142 PWR_CPUCORE_DRON42,44
5V_PWR
4
PR4302
PR4302 2D2R3-1-U-GP
2D2R3-1-U-GP
PWR_VCORE1_EN
1 2
PR4301 49D9R2F-GPPR4301 49D9R2F-GP
12
PC4302
PC4302 SC1U10V2KX-1GP
SC1U10V2KX-1GP
1 2
PWR_VCORE1_BT1_R
PC4301
PC4301 SCD22U25V3KX-GP
SCD22U25V3KX-GP
PU4301
PU4301
1
BST
2 3
DRVH PWM EN VCC4DRVL
FLAG
9
1 2
8 7
SW
6
GND
5
NCP5911MNTBG-GP
NCP5911MNTBG-GP
3
PWR_VCORE1_HGPWR_VCORE1_BT1 PWR_VCORE1_PH
PWR_VCORE1_LG
2
1
DCBATOUT
6
DDD
C C
PWR_CPUCORE_PWM342 PWR_CPUCORE_DRON42,44
5V_PWR
B B
IRF6721SPBF-GP-U
IRF6721SPBF-GP-U
84.06721.030
84.06721.030
1 2
PR4304 49D9R2F-GPPR4304 49D9R2F-GP
PU4307
PU4307
PR4303
PR4303 2D2R3-1-U-GP
2D2R3-1-U-GP
PWR_VCORE3_EN
12
PC4307
PC4307 SC1U10V2KX-1GP
SC1U10V2KX-1GP
1
2345
6
DDD
D
DDD
D
S
G
S
G
1 2
12
PC4308
PC4308 SC4D7U25V6KX-3GP
SC4D7U25V6KX-3GP
PWR_VCORE3_BT3_R
PU4306
PU4306
1
BST
2
PWM
3
EN VCC4DRVL
PC4306
PC4306 SCD22U25V3KX-GP
SCD22U25V3KX-GP
1 2
8
DRVH
7
SW
6
GND
5
FLAG
9
NCP5911MNTBG-GP
NCP5911MNTBG-GP
12
PC4309
PC4309 SC4D7U25V6KX-3GP
SC4D7U25V6KX-3GP
PWR_VCORE3_HGPWR_VCORE3_BT3 PWR_VCORE3_PH
PWR_VCORE3_LG
DCBATOUT
12
PC4310
PC4310 SC4D7U25V6KX-3GP
SC4D7U25V6KX-3GP
PWR_VCORE1_HG PWR_VCORE1_PH
PR4312
PR4312
1 2
0R0402-PAD
0R0402-PAD
PR4313
PR4313
1 2
0R0402-PAD
0R0402-PAD
IRF6721SPBF-GP-U
IRF6721SPBF-GP-U
84.06721.030
84.06721.030
VCORE1_HG
VCORE1_LGPWR_VCORE1_LG
PU4313
PU4313
DDD
G
G
7
5
6
4
D
D
S
S
1
23
DDD
DDD
PU4312
PU4312 IRF6725MTRPBF-GP-U
IRF6725MTRPBF-GP-U
84.06725.030
84.06725.030
SSGD
SSGD
TP4303
TP4303
1
TPAD40-GP
TPAD40-GP
SC4D7U25V6KX-3GP
SC4D7U25V6KX-3GP
12
PC4303
PC4303
1
2345
12
PC4304
PC4304 SC4D7U25V6KX-3GP
SC4D7U25V6KX-3GP
PL4301
PL4301
1 2
L-D36UH-1-GP
L-D36UH-1-GP
PG4311
PG4311
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 2
12
PC4305
PC4305 SC4D7U25V6KX-3GP
SC4D7U25V6KX-3GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 2
PG4312
PG4312
12
CSN1 42 CSP1 42
PTC4303
PTC4303 SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
VCC_CORE
12
PTC4304
PTC4304 SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
VCC_CORE
VCORE3_HGPWR_VCORE3_HG
PR4309
PR4309
1 2
0R0402-PAD
PWR_VCORE3_PH
A A
PWR_VCORE3_LG
0R0402-PAD
PR4308
PR4308
1 2
0R0402-PAD
0R0402-PAD
VCORE3_LG
5
1
23
6
7
DDD
DDD
SSGD
SSGD
4
5
1
PU4308
PU4308 IRF6725MTRPBF-GP-U
IRF6725MTRPBF-GP-U
84.06725.030
84.06725.030
TP4301
TP4301 TPAD40-GP
TPAD40-GP
PG4313
PG4313
1 2
CSP342
PL4302
PL4302
1 2
L-D36UH-1-GP
L-D36UH-1-GP
PG4314
PG4314
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 2
CSN342
4
12
PTC4305
PTC4305 SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
12
PTC4306
PTC4306 SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
12
PTC4307
PTC4307 SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
3
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
DC/DC CPU CORE2 _NCP6131
DC/DC CPU CORE2 _NCP6131
DC/DC CPU CORE2 _NCP6131
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
43
43
43
1
-1
-1
of
of
of
-1
94Tuesday, January 18, 2011
94Tuesday, January 18, 2011
94Tuesday, January 18, 2011
5
DCBATOUT_VCC_GFXCOREDCBATOUT
PG4401
PG4401
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
D D
C C
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 2
PG4402
PG4402
1 2
PG4403
PG4403
1 2
PG4404
PG4404
1 2
PG4405
PG4405
1 2
PG4406
PG4406
1 2
VREG_SWA_HG VREG_SWA VREG_SWA_LG
4
1
2345
6
DDD
D
DDD
D
PU4401
PU4401
S
G
S
G
IRF6721SPBF-GP-U
IRF6721SPBF-GP-U
84.06721.030
84.06721.030
PR4403
PR4403
1 2
0R0402-PAD
0R0402-PAD
PR4404
PR4404
1 2
0R0402-PAD
0R0402-PAD
SWA_HG
SWA_LG
23
6
7
DDD
DDD
SSGD
SSGD
4
5
1
PU4403
PU4403 IRF6725MTRPBF-GP-U
IRF6725MTRPBF-GP-U
84.06725.030
84.06725.030
3
12
PC4401
PC4401 SC4D7U25V6KX-3GP
SC4D7U25V6KX-3GP
DCBATOUT_VCC_GFXCORE
12
PC4402
PC4402 SC4D7U25V6KX-3GP
SC4D7U25V6KX-3GP
PL4401 L-D36UH-1-GPPL4401 L-D36UH-1-GP
1 2
1 2
PG4407
PG4407
12
PC4403
PC4403 SC4D7U25V6KX-3GP
SC4D7U25V6KX-3GP
1 2
PG4408
PG4408
2
12
PTC4402
PTC4402 ST330U2VDM-4-GP
ST330U2VDM-4-GP
VCC_GFXCORE
12
PTC4403
PTC4403 ST330U2VDM-4-GP
ST330U2VDM-4-GP
1
TP4401
TP4401
1
TPAD40-GP
TPAD40-GP
B B
PWR_CPUCORE_PWMA42 PWR_CPUCORE_DRON42,43
A A
5
PR4402
PR4402
1 2
PR4401
PR4401 2D2R3-1-U-GP
2D2R3-1-U-GP
1 2
VREG_GFX_EN
49D9R2F-GP
49D9R2F-GP
VREG_GFX_BOOT_1
5V_PWR
12
PC4405
PC4405 SC1U10V2KX-1GP
SC1U10V2KX-1GP
4
1 2 3
PU4405
PU4405
BST
DRVH PWM EN
GND
VCC4DRVL
FLAG
9
NCP5911MNTBG-GP
NCP5911MNTBG-GP
PC4404
PC4404 SCD22U25V3KX-GP
SCD22U25V3KX-GP
1 2
8 7
SW
6 5
VREG_SWA_HGVREG_GFX_BOOT VREG_SWA
VREG_SWA_LG
3
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
CSNA 42 CSPA 42
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
DC/DC CPU CORE3 _NCP6131
DC/DC CPU CORE3 _NCP6131
DC/DC CPU CORE3 _NCP6131
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
44 94Tuesday, January 18, 2011
44 94Tuesday, January 18, 2011
44 94Tuesday, January 18, 2011
1
of
of
of
-1
-1
-1
5
4
3
2
1
DCBATOUT PWR_1D05V_DCBATOUT
D D
C C
B B
PG4501
PG4501
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4502
PG4502
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4503
PG4503
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4504
PG4504
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1.05VTT_PWRGD37,48 RUNPWROK19,36,37,46,47
PWR_1D05V_EN36
PR4502 0R2J-2-GPPR4502 0R2J-2-G P
1 2
12
PC4505
PC4505 SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
PR4501
PR4501 64K9R2F-1-GP
64K9R2F-1-GP
12
3D3V_S0
12
12
TPS51218 for 1D05V
PR4512
PR4512 10KR2J-3-GP
10KR2J-3-GP
PWR_1D05V_TRIP PWR_1D05V_EN
PWR_1D05V_CCM
PR4504
PR4504 470KR2F-GP
470KR2F-GP
PU4501
PU4501
1
PGOOD
2
TRIP
3
EN
4
VFB
5
CCM
TPS51218DSCR-GP-U1
TPS51218DSCR-GP-U1
GND VBST DRVH
V5IN DRVL
SW
11
PWR_1D05V_BOOT
10
PWR_1D05V_UGATE
9
PWR_1D05V_PHASEPWR_1D05V_VFB
8 7
PWR_1D05V_LGATE
6
PR4505
PR4505 2D2R3J-2-GP
2D2R3J-2-GP
1 2
5V_S5
12
Id=14.3A Qg=9.2~14nC Rdson=11~14mohm
PC4503
PC4503 SCD1U25V3KX-GP
PWR_1D05V_BOOT_R
PC4501
PC4501 SC1U10V2KX-1GP
SC1U10V2KX-1GP
Id=26.5A Qg=40.6~61nC, Rdson=2.6~3.2mohm
SCD1U25V3KX-GP
PWR_1D05V_DCBATOUT
678
DDD
DDD
PU4502
PU4502
SSS
GD
SSS
GD
123
4 5
12
678
DDD
D
DDD
D
SSS
SSS
G
G
123
4 5
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
SIR172DP-T1-GE3-GP
SIR172DP-T1-GE3-GP
PU4503
PU4503
12
PC4504
PC4504 SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
12
DY
DY
PR4503
PR4503 2D2R3-1-U-GP
2D2R3-1-U-GP
DY
DY
12
PC4502
PC4502 SC470P50V2KX-3GP
SC470P50V2KX-3GP
12
PC4506
PC4506 SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
Mag. 0.56uH 10*10*4 DCR=1.6~1.8mohm Idc=25A, Isat=40A
PL4501
PL4501
1 2
IND-D56UH-27-GP
IND-D56UH-27-GP
12
PR4506
PR4506
10R2F-L-GP
10R2F-L-GP
VTT_SENSE_L
PWR_1D05V_VFB
VSS_SENSE_L
PC4507
PC4507 SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
12
12
PR4507
PR4507 10KR2F-2-GP
10KR2F-2-GP
12
PR4508
PR4508 20K5R2F-GP
20K5R2F-GP
12
PR4509
PR4509 10R2F-L-GP
10R2F-L-GP
12
PC4508
PC4508 SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
Iomax=16A OCP>24A
12
PTC4502
PTC4502 SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
12
PTC4503
PTC4503 SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
1D05V_VTT
12
PC4509
PC4509 SCD1U25V3KX-GP
SCD1U25V3KX-GP
DY
VTT_SENSE_L
VSS_SENSE_L
DY
PR4510 0R2J-2-GP
PR4510 0R2J-2-GP
1 2
DY
DY
12
PC4510
PC4510 SC1000P50V3JN-GP-U
SC1000P50V3JN-GP-U
DY
DY
PR4511 0R2J-2-GP
PR4511 0R2J-2-GP
1 2
VCCIO_SENSE 8
VSSIO_SENSE 8
Vout=0.704V*(R1+R2)/R2
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet of
TPS51218_1D05V
TPS51218_1D05V
TPS51218_1D05V
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
45 94Tuesday, January 18, 2011
45 94Tuesday, January 18, 2011
45 94Tuesday, January 18, 2011
1
of
of
-1
-1
-1
5
4
3
2
1
DCBATOUT PWR_1D5V_DCBATOUT
D D
C C
PG4601
PG4601
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4602
PG4602
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4603
PG4603
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4604
PG4604
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
DY
DY
12
EC4601
EC4601 SCD1U25V2KX-GP
SCD1U25V2KX-GP
TPS51218 for 1D5V
3D3V_S0
12
PR4607
PR4607 10KR2J-3-GP
10KR2J-3-GP
PM_SLP_S4#19,27,82
PR4602 0R2J-2-GPPR4602 0R2J-2-G P
RUNPWROK19,36,37,45,47
1 2
12
PC4603
PC4603 SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
PR4601
PR4601 64K9R2F-1-GP
64K9R2F-1-GP
PWR_1D5V_TRIP
PWR_1D5V_EN
PWR_1D5V_CCM
12
12
PR4605
PR4605 470KR2F-GP
470KR2F-GP
PU4601
PU4601
1
PGOOD
2
TRIP
3
EN
4
VFB
5
CCM
TPS51218DSCR-GP-U1
TPS51218DSCR-GP-U1
GND
VBST
DRVH
V5IN
DRVL
SW
11
PWR_1D5V_BOOT
10
PWR_1D5V_UGATE
9
PWR_1D5V_PHASEPWR_1D5V_VFB
8 7
PWR_1D5V_LGATE
6
PR4606
PR4606
2D2R3J-2-GP
2D2R3J-2-GP
1 2
Id=14.3A Qg=9.2~14nC Rdson=11~14mohm
PWR_1D5V_BOOT_R
12
PC4601
PC4601 SC1U10V2KX-1GP
SC1U10V2KX-1GP
PWR_1D5V_DCBATOUT
PU4602
PU4602
PC4604
PC4604 SCD1U25V3KX-GP
SCD1U25V3KX-GP
12
5V_S5
PU4603
PU4603
Id=26.5A Qg=40.6~61nC, Rdson=2.6~3.2mohm
678
DDD
DDD
SSS
GD
SSS
GD
123
4 5
SIR172DP-T1-GE3-GP
SIR172DP-T1-GE3-GP
Mag. 0.56uH 10*10*4 DCR=1.6~1.8mohm Idc=25A, Isat=40A
12
678
DDD
D
DDD
D
SSS
SSS
G
G
12
123
4 5
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
12
PC4605
PC4605 SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
PL4601
PL4601
1 2
IND-D56UH-27-GP
IND-D56UH-27-GP
DY
DY
PR4603
PR4603 2D2R3-1-U-GP
2D2R3-1-U-GP
DY
DY
PC4602
PC4602 SC470P50V2KX-3GP
SC470P50V2KX-3GP
12
PC4606
PC4606 SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
12
PR4608
PR4608 11K5R2F-GP
11K5R2F-GP
PWR_1D5V_VFB
12
PR4609
PR4609 10KR2F-2-GP
10KR2F-2-GP
12
PC4607
PC4607 SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
12
PC4610
PC4610 SC1U16V3KX-5GP
SC1U16V3KX-5GP
12
PC4608
PC4608 SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
Iomax=16A OCP>24A
12
PTC4602
PTC4602 SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
1D5V_S3
12
PTC4603
PTC4603 SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
Vout=0.704V*(R1+R2)/R2
1D5V_S3
12
PC4615
B B
PC4615 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
PC4614
PC4614 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
RT9026 for 0D75V_S0
5V_S5
DY
DY
12
PC4612
PC4612 SC1U10V2KX-1GP
SC1U10V2KX-1GP
DDR_VREF_S3
PR4610 0R2J-2-GPPR4610 0R2J-2-GP
PM_SLP_S4#19,27,82
0D75V_EN37
A A
5
1 2
PR4611 0R2J-2-GPPR4611 0R2J-2-GP
1 2
12
PC4611
PC4611 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PWR_0D75V_S5
PWR_0D75V_S3 DDR_VREF_S3
12
PC4613
PC4613 SC1U10V2KX-1GP
SC1U10V2KX-1GP
4
RT9026PFP-GP
RT9026PFP-GP
12
PC4609
PC4609
SC4D7U10V3KX-GP
SC4D7U10V3KX-GP
VLDOIN
PGND
VTTSNS
GND
11
1D5V_S3
1 2 3
VTT
4 5
12
PC4616
PC4616 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
PU4604
PU4604
10
VDDQSNS
VIN
9
S5
8
GND
7
S3
6
VTTREF
0D75V_PWR
12
3
Iomax=1.2A OCP>1.8A
PG4621
PG4621
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4622
PG4622
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP PC4617
PC4617 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
0D75V_S0
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
TPS51128_1D5V & RT9026_0D75V
TPS51128_1D5V & RT9026_0D75V
TPS51128_1D5V & RT9026_0D75V
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
of
46 94Tuesday, January 18, 2011
of
46 94Tuesday, January 18, 2011
of
46 94Tuesday, January 18, 2011
-1
-1
-1
5
D D
3D3V_S5
PR4708
PR4708
RUNPWROK19,36,37,45,46
C C
12
PC4701
PC4701 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1 2
0R0402-PAD-1-GP
0R0402-PAD-1-GP
3D3V_S5
12
PC4702
PC4702 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
DY
DY
PR4701
PR4701 10KR2F-2-GP
10KR2F-2-GP
1 2
PWR_1D8V_GD
4
PWR_1D8V_FB PWR_1D8V_COMP
PC4703
PC4703 SC1500P50V2KX-2GP
SC1500P50V2KX-2GP
PWR_1D8V_C OMP_R
1 2
PC4704 SC47P50V2JN-3GPPC4704 SC47P50V2JN-3GP
1 2
RT8015B for 1D8V_S0
PU4701
PU4701 RT8015BGQW-GP
RT8015BGQW-GP
SHDN/RT
GND
PGND
LX#4 LX#3
GND
5 4 3 2 1
PWR_1D8V_LX
PWR_1D8V_RT
12
SCD1U25V2KX-GP
SCD1U25V2KX-GP
6
PVDD
7
VDD
8
PGOOD
9
FB
10
COMP
1 2
PR4702
PR4702 14KR2F-GP
14KR2F-GP
11
3
Mag.7*7*3 DCR=28~30mohm, Irating=6A Isat=13.5A
PL4701 IND-3D3UH-57GPPL4701 IND-3D3UH-57GP
12
PWR_1D8V_FB
PR4703
PR4703 820KR2F-GP
820KR2F-GP
PC4705
PC4705
Vo=0.8*(1+(R1/R2))
12
12
12
PR4707
PR4707 20KR2F-L-GP
20KR2F-L-GP
PR4706
PR4706 16KR2F-GP
16KR2F-GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
1D8V_PWR
12
PC4709
PC4709
2
1
Iomax=3A
1D8V_S0
PG4701
PG4701
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
PC4707
PC4707
PC4708
PC4708
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4702
PG4702
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4703
PG4703
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
G
DS
PQ4701
PQ4701 AO7401-GP
AO7401-GP
84.07401.031
84.07401.031
<Core Des ign>
<Core Des ign>
<Core Des ign>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
3
2
Date: Sheet
PWM_1D8V_RT8015B
PWM_1D8V_RT8015B
PWM_1D8V_RT8015B
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
47 94Tuesday, January 18, 2011
47 94Tuesday, January 18, 2011
47 94Tuesday, January 18, 2011
1
-1
-1
of
of
of
-1
B B
1 2
PWR_1D8V_RUN_EN
DY
DY
12
PC4710
PC4710 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
4
PR4709
PM_SLP_S3#19,27,36,37,82
A A
5
PR4709 0R2J-2-GP
0R2J-2-GP
5
4
3
2
1
DCBATOUT PWR_VCCSA_DCBATOUT
D D
C C
B B
PG4801
PG4801
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4802
PG4802
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4803
PG4803
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
D85V_PWRGD19,42
S-HR_20100614 V1.1 for CRB board
3D3V_S5
PR4814
PR4814 100KR2J-1-GP
100KR2J-1-GP
PR4815
PR4815 0R0402-PAD-1-GP
0R0402-PAD-1-GP
1 2
1 2
1.05VTT_PWRGD37,45
PR4801
PR4801
2D2R3J-2-GP
2D2R3J-2-GP
5V_S5
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
PC4802
PC4802
12
PR4805
PR4805 18K7R2F-GP
18K7R2F-GP
PR4806
PR4806 0R0402-PAD-1-GP
0R0402-PAD-1-GP
1 2
12
PC4801
PC4801
PWR_VCCSA_TON
PWR_VCCSA_VDD
PWR_VCCSA_GD PWR_VCCSA_CS
PWR_VCCSA_EN
DY
DY
12
PC4809
PC4809 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
RT8208A for VCCSA
PR4802 249KR2F-GPPR4802 249KR2F-GP
1 2
PU4801
PU4801
16
9 2
4
10
15 17
BOOT
TON VDDP
UGATE
VDD
PHASE LGATE
PGOOD CS
EM/DEM
VOUT
GND
RT8208BGQW-GP
RT8208BGQW-GP
G0
FB
G1
D1 D0
Freq=300KHz
PR4803
PR4803 2D2R3J-2-GP
PWR_VCCSA_BOOT
13
PWR_VCCSA_HG
12
PWR_VCCSA_PH
11
PWR_VCCSA_LG
8
PWR_VCCSA_G0
7
PWR_VCCSA_FB
3
PWR_VCCSA_G1
14
PWR_VCCSA_D1
5
PWR_VCCSA_D0
6 1
2D2R3J-2-GP
1 2
PR4804
PR4804
1 2
0R0402-PAD
0R0402-PAD
PR4807
PR4807
1 2
0R0402-PAD
0R0402-PAD
VCCSA_PWR
Vout=0.75*(1+R1/R2)
VCCSA_SEL VCCSA_PWR
L
H
0.9V
0.8V
PWR_VCCSA_BOOT_R
VCCSA_SEL 9 H_FC_C22 9
PWR_VCCSA_DCBATOUT
PU4802
PU4802
SIS412DN-T1-GE3-GP
SIS412DN-T1-GE3-GP
G
PC4807
PC4807 SCD1U25V3KX-GP
SCD1U25V3KX-GP
1 2
PU4803
PU4803
SIS412DN-T1-GE3-GP
SIS412DN-T1-GE3-GP
GS
Id=12.5A Qg=15.4~23nC Rdson=14.5~17.5mohm
678
DDD
DDD
GD
GD
4 5
678
DDD
DDD
GD
GD
4 5
D
SSS
SSS
S
123
D
SSS
SSS
123
PWR_VCCSA_FB
12
DY
DY
PR4811
PR4811 49K9R2F-L-GP
49K9R2F-L-GP
PWR_VCCSA_D1
12
PC4803
PC4803 SCD1U25V3KX-GP
SCD1U25V3KX-GP
Mag. 1.5uH 7*7*3 DCR=14~15mohm Idc=9A, Isat=18A
12
DY
DY
PR4816
PR4816 2D2R3-1-U-GP
2D2R3-1-U-GP
DY
DY
12
PC4811
PC4811 SC470P50V2KX-3GP
SC470P50V2KX-3GP
PWR_VCCSA_FB_R
12
12
PWR_VCCSA_D0
1 2
IND-1D5UH-53-GP
IND-1D5UH-53-GP
PR4808
PR4808 10KR2F-2-GP
10KR2F-2-GP
PR4812
PR4812 76K8R2F-GP
76K8R2F-GP
12
PC4804
PC4804 SC4D7U25V6KX-3GP
SC4D7U25V6KX-3GP
PL4801
PL4801
VCCSA_PWR
12
DY
DY
12
PC4810
PC4810 SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
12
PR4813
PR4813 143KR2F-L-1-GP
143KR2F-L-1-GP
DY
DY
PR4809
PR4809 0R2J-2-GP
0R2J-2-GP
12
PC4805
PC4805 SC4D7U25V6KX-3GP
SC4D7U25V6KX-3GP
Iomax=6A OCP>9A VCCSA=0.8V/0.9V
VCCSA_PWR
12
PTC4801
PTC4801 SE390U2D5VM-7GP
SE390U2D5VM-7GP
Matsuki cap 390uF
2.5V, ESR=10mohm
PR4810
PR4810 0R0402-PAD-1-GP
0R0402-PAD-1-GP
1 2
DY
DY
12
PC4812
PC4812 SCD1U25V2KX-GP
SCD1U25V2KX-GP
12
PC4806
PC4806 SC4D7U25V6KX-3GP
SC4D7U25V6KX-3GP
12
PC4808
PC4808 SCD1U25V3KX-GP
SCD1U25V3KX-GP
VCCSA_SENSE 9
VCCSA_PWR 0D85V_S0
PG4804
PG4804
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4805
PG4805
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4806
PG4806
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4807
PG4807
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4808
PG4808
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4809
PG4809
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4810
PG4810
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
A A
5
4
3
2
<Core Des ign>
<Core Des ign>
<Core Des ign>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
RT8208B_VCCSA
RT8208B_VCCSA
RT8208B_VCCSA
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
48 94Tuesday, January 18, 2011
48 94Tuesday, January 18, 2011
48 94Tuesday, January 18, 2011
1
of
of
of
-1
-1
-1
LCD / Inverter Connector
3D3V_S0
23
3D3V_S5
1
RN4901
RN4901 SRN2K2J-1-GP
SRN2K2J-1-GP
4
LVDS_DDC_DATA
LVDS_DDC_CLK
R4902
R4902
1 2
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
LCD_PRESENCE#
100KR2J-1-GP
100KR2J-1-GP
3D3V_AUX_S5
3D3V_S5
LCDVDD
1 2
FUSE-3A24V-1-GP
FUSE-3A24V-1-GP
69.43001.331
69.43001.331
2nd = 69.43001.371
C4901
C4901
3D3V_S0
FUSE-D75A32V-3-GP
FUSE-D75A32V-3-GP
3D3V_S0
F4902 FUSE-D5A32V-14-GPF4902 FUSE-D5A32V-14-GP
2nd = 69.43001.371
1 2
F4903
F4903
1 2
1 2
LVDS_DDC_DATA17
DCBATOUT_LCDDCBATOUT
F4901
F4901
BLON_OUT27 L_BKLT_CTRL17
LCD_PRESENCE#18
USB_PN1218 USB_PP1218
AUD_DMIC_DATA29 AUD_DMIC_CLK29
LID_CLOSE#27
R4901 330R2F-GPR4901 330R2F-GP
LVDSA_CLK17 LVDSA_CLK#17
LVDSA_DATA217 LVDSA_DATA2#17
LVDSA_DATA117 LVDSA_DATA1#17
LVDSA_DATA017 LVDSA_DATA0#17
LVDS_DDC_CLK17
TP4901TP4901
12
LCD_PRESENCE#
3D3V_CAM_S0
MIC_DET#
1
PANEL_LED_P PANEL_LED_N
LVDS_DDC_DATA LVDS_DDC_CLK
3D3V_DDC_S0
DCBATOUT_LCD
1.2A
C4902
C4902
1 2
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
LCD1
LCD1
1 2
3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
JAE-CON40-4-GP
JAE-CON40-4-GP
20.K0568.040
20.K0568.040
C4903
C4903
1 2
SCD1U25V3KX-GP
SCD1U25V3KX-GP
41
42
C4904
C4904
1 2
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
LCDVDD 3D3V_S0
U4901
LVDS_VDD_EN17
12
R4914
R4914 100KR2J-1-GP
100KR2J-1-GP
DY
DY
12
C4909
C4909 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
Layout 40 mil
12
C4908
C4908 SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
U4901
1
EN
2
2nd = 74.09724.09F
2nd = 74.09724.09F
IN#5 GND OUT3IN#4
G5285T11U-GP
G5285T11U-GP
74.05285.07F
74.05285.07F
5 4
12
C4907
C4907 SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
Q4901
Q4901
R1
R1
PANEL_LED27
1
R2
R2
LTC043ZUB-FS8-GP
LTC043ZUB-FS8-GP
3 2
PANEL_LED_N
Near LCD1
LID_CLOSE# AUD_DMIC_CLK AUD_DMIC_DATA 3D3V_DDC_S0
AFTP4901 AFTE14P-GPAFTP4901 AFTE14P-GP
1
AFTP4902 AFTE14P-GPAFTP4902 AFTE14P-GP
1
AFTP4903 AFTE14P-GPAFTP4903 AFTE14P-GP
1
AFTP4904 AFTE14P-GPAFTP4904 AFTE14P-GP
1
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
LCD CONNECTOR
LCD CONNECTOR
LCD CONNECTOR
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
49 94Tuesday, January 18, 2011
49 94Tuesday, January 18, 2011
49 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
5
4
3
2
1
CRT CONNECTOR
3D3V_S0
5V_CRT_S0
D D
C C
12
C5012
C5012
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
CRT_HSYNC17
CRT_DDCDATA_CON CRT_DDCCLK_CON
CRT_R CRT_G CRT_B
CRT_VSYNC_CON CRT_HSYNC_CON
CRT Hsync & Vsync level shift
R5004
R5004 R5001 10R2J-2-GPR5001 10R2J-2-GP
9
12 15
1 2 3
14 13
1 2 1 2
CRT1
CRT1
VCC_CRT
DDCDATA_ID1 DDCCLK_ID3
CRT_RED CRT_GREEN CRT_BLUE
VSYNC HSYNC
D-SUB-15-97-GP-U
D-SUB-15-97-GP-U
0R2J-2-GP
0R2J-2-GP
CRT_HSYNC_R
4
NC#4
11
NC#11
NP1
NP1
NP2
NP2
5
GND
6
GND
7
GND
8
GND
10
GND
16
GND
17
GND
U5001
U5001
1
1OE#
2
1A
3
2Y
4
GND
74AHCT2G125DP-GP
74AHCT2G125DP-GP
73.2G125.00B
73.2G125.00B
VCC
2OE#
Near CRT1
CRT_DDCCLK_CON CRT_DDCDATA_CON CRT_HSYNC_CON CRT_VSYNC_CON CRT_R CRT_G CRT_B 5V_CRT_S0
5V_S0
12
C5007
C5007 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
8 7 6
1Y
5
2A
R5002 10R2J-2-GPR5002 10R2J-2-GP
CRT_HSYNC1_2CRT_VSYNC1_2CRT_VSYNC_CON CRT_HSYNC_CON CRT_VSYNC_R
1 2 1 2
R5005 0R2J-2-GPR5005 0R2J-2-GP
1 1 1 1 1 1 1 1
3D3V_S0_DDC
AFTP5001 AFTE14P-GPAFTP5001 AFTE14P-GP AFTP5002 AFTE14P-GPAFTP5002 AFTE14P-GP AFTP5003 AFTE14P-GPAFTP5003 AFTE14P-GP AFTP5004 AFTE14P-GPAFTP5004 AFTE14P-GP AFTP5006 AFTE14P-GPAFTP5006 AFTE14P-GP AFTP5007 AFTE14P-GPAFTP5007 AFTE14P-GP AFTP5005 AFTE14P-GPAFTP5005 AFTE14P-GP AFTP5008 AFTE14P-GPAFTP5008 AFTE14P-GP
CRT_DDC_DATA17
CRT_DDC_CLK17
CRT_VSYNC 17
1 2
R500310KR2J-3-GP R500310KR2J-3-GP
SRN2K2J-1-GP
SRN2K2J-1-GP
R5006 0R2J-2-GPR5006 0R2J-2-GP
1 2
R5007 0R2J-2-GPR5007 0R2J-2-GP
1 2
CRT DDCDATA & DDCCLK level shift
3D3V_S0
1
RN5002
RN5002
4
DY
DY
12
C5008
C5008 SC100P50V2JN-3GP
SC100P50V2JN-3GP
Pull High 5V Design on CRT Board
23
3D3V_S0_DDC
Q5001
Q5001
5 6
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
DY
DY
12
C5009
C5009 SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
5V_CRT_S0
CRT_DDCDATA_CON
34 2 1
CRT_DDCCLK_CON
DY
DY
12
C5010
C5010 SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
12
F5001
F5001
5V_CRT_DDC
POLYSW-1D1A6V-GP
POLYSW-1D1A6V-GP
5V_S0
500mA
D5001
D5001 CH551H-30GP-GP
CH551H-30GP-GP
K A
4
RN5003
RN5003 SRN10KJ-5-GP
SRN10KJ-5-GP
1
2 3
CRT_DDCDATA_CON
CRT_HSYNC_CON CRT_VSYNC_CON CRT_DDCCLK_CON
DY
DY
12
C5011
C5011 SC100P50V2JN-3GP
SC100P50V2JN-3GP
5V_CRT_S0
D5002
D5002
2
B B
CRT_RED17
&575*%
CRT_GREEN17
CRT_BLUE17
A A
5
12
150R2F-1-GP
150R2F-1-GP
R5008
R5008
12
150R2F-1-GP
150R2F-1-GP
R5009
R5009
12
R5010
R5010
150R2F-1-GP
150R2F-1-GP
12
DY
DY
C5001
C5001
SC8P250V2CC-GP
SC8P250V2CC-GP
SC8P250V2CC-GP
SC8P250V2CC-GP
4
12
DY
DY
C5002
C5002
L5001 FCM1608CF-220T05-GPL5001 FCM1608CF-220T05-GP
1 2
L5002 FCM1608CF-220T05-GPL5002 FCM1608CF-220T05-GP
1 2
L5003 FCM1608CF-220T05-GPL5003 FCM1608CF-220T05-GP
1 2
12
DY
DY
C5003
C5003
SC8P250V2CC-GP
SC8P250V2CC-GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
12
C5004
C5004
12
SC10P50V2JN-4GP
SC10P50V2JN-4GP
C5005
C5005
3
CRT_R
CRT_G
CRT_B
12
C5006
C5006
SC10P50V2JN-4GP
SC10P50V2JN-4GP
1
2
1
2
1
2
1
CRT_HSYNC_CON CRT_RED
3
CH221GP-GP-U
CH221GP-GP-U D5003
D5003
CRT_VSYNC_CON
3
CH221GP-GP-U
CH221GP-GP-U D5004
D5004
CRT_DDCDATA_CON
3
CH221GP-GP-U
CH221GP-GP-U D5005
D5005
CRT_DDCCLK_CON
3
CH221GP-GP-U
CH221GP-GP-U
2
5V_CRT_S0
D5006
D5006
2
3
1
CH221GP-GP-U
CH221GP-GP-U D5007
D5007
2
1
2
1
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
CRT_GREEN
3
CH221GP-GP-U
CH221GP-GP-U D5008
D5008
CRT_BLUE
3
CH221GP-GP-U
CH221GP-GP-U
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CRT Connector
CRT Connector
CRT Connector
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
of
50 94
of
50 94
of
50 94
-1
-1
-1
A
B
C
D
E
3D3V_S0
12
Q5102
R5106
R5106 1MR2J-1-GP
1MR2J-1-GP
PCH_HDMI_DET17
4 4
3 3
Recommended Eq ualization: [PC1,PC0]=01, 4dB
3D3V_S0
R5112 4K7R2J-2-GP
R5112 4K7R2J-2-GP R5113 4K7R2J-2-GP
R5113 4K7R2J-2-GP
Q5102
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
DY
DY
12 12
DY
DY
D
12
DY
DY
R5111
R5111 5K1R2F-2-GP
5K1R2F-2-GP
HDMI_DETECT_R
12
R5105
R5105 100KR2J-1-GP
100KR2J-1-GP
HDMI_DATA2_R17 HDMI_DATA2_R#17
HDMI_DATA1_R17 HDMI_DATA1_R#17
HDMI_DATA0_R17 HDMI_DATA0_R#17
HDMI_CLK_R17 HDMI_CLK_R#17
3D3V_S0
R5101
R5101
1 2
0R2J-2-GP
0R2J-2-GP
R5109
R5109 4K7R2J-2-GP
4K7R2J-2-GP
HDMI_A_HPD_CN
12
12
DY
DY
C5101
C5101
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
REXT_HDMI
DY
DY
DDC_EN_PS8101
12
1 2
DY
DY
C5119
C5119
HDMI_OE#
DY
DY
R5110
R5110
499R2F-2-GP
499R2F-2-GP
3D3V_S0
12
D
DY
DY
G
3D3V_S0
12
DY
DY
C5102
C5102
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
38 39
41 42
44 45
47 48
PC0
3
PC1
4
6 10 25 32
71.P8101.003
71.P8101.003
2ND = 71.03360.A0K
2ND = 71.03360.A0K
DY
DY
R5102
R5102 20KR2J-L2-GP
20KR2J-L2-GP
HDMI_OE#
Q5101
Q5101 2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
S
12
DY
DY
C5121
C5121
DY
DY
U5101
U5101
IN_D1­IN_D1+
IN_D2­IN_D2+
IN_D3­IN_D3+
IN_D4­IN_D4+
PC0 PC1
REXT RT_EN# OE# DDC_EN
PS8101-GP
PS8101-GP
HDMI Connector
HDMI1
HDMI1
DY
DY
D5103
HDMI_TX2+ HDMI_TX2-
HDMI_TX1+ HDMI_TX1-
HDMI_TX0+ HDMI_TX0-
HDMI_TXC+ HDMI_TXC- HDMI_TXC-
TDMS_A_DAT TDMS_A_CLK
HDMI_TX2+ HDMI_TX2-
HDMI_TX1+ HDMI_TX1-
HDMI_TX0+ HDMI_TX0-
HDMI_TXC+ HDMI_TXC-
HDMI_DETECT_R
HDMI_A_HPD_CN TDMS_A_DAT TDMS_A_CLK
3D3V_S0
DY
DY
R5107 4K7R2J-2-GP
R5107 4K7R2J-2-GP
1 2
R5108 4K7R2J-2-GP
R5108 4K7R2J-2-GP
1 2
DY
DY
8101_NC35
2
11
15
VCC
VCC
GND
GND
1
5
12
8101_NC34
21
26
33
35
40
46
VCC
VCC
VCC
VCC
VCC
VCC
NC#3434NC#35
23
OUT_D1-
22
OUT_D1+
20
OUT_D2-
19
OUT_D2+
17
OUT_D3-
16
OUT_D3+
14
OUT_D4-
13
OUT_D4+
8
SDA
9
SCL
7
HPD
30
HPD_SINK
29
SDA_SINK
28
SCL_SINK
GND
GND
GND
GND
GND
GND36GND
GND
GND
18
24
27
31
37
43
49
D5103
1
L1#1
L1#8
2
L2#2
L2#7
G1
GND
GND
3
L3#3
L3#6
L4#44L4#5
RCLAMP0524P-GP
RCLAMP0524P-GP
D5104
D5104
1
L1#1
L1#8
2
L2#2
L2#7
G1
GND
GND
3
L3#3
L3#6
L4#44L4#5
RCLAMP0524P-GP
RCLAMP0524P-GP
PCH_HDMI_DATA 17 PCH_HDMI_CLK 17
R51142K2R2J-2-GP R51142K2R2J-2-GP
12
R51152K2R2J-2-GP R51152K2R2J-2-GP
12
8 7 G2 6 5
DY
DY
8 7 G2 6 5
HDMI_TX2+ HDMI_TX2-
HDMI_TX1+ HDMI_TX1-
HDMI_TX0+ HDMI_TX0-
HDMI_TXC+
HDMI_A_HPD_CN
5V_HDMI_S0
3
DY
DY
D5101
D5101
BAV99PT-GP-U
BAV99PT-GP-U
83.00099.K11
83.00099.K11
D5102
D5102
K A
CH551H-30GP-GP
CH551H-30GP-GP
2
1
5V_S0
5V_S0
5V_HDMI_S0
TP5101
TP5101 TPAD14-GP
TPAD14-GP
TP5102 TPAD14-GPTP5102 TPAD14- G P
HDMI_TX2+
HDMI_TX2­HDMI_TX1+
HDMI_TX1­HDMI_TX0+
HDMI_TX0­HDMI_TXC+
HDMI_TXC­HDMI_A_CEC
1
TDMS_A_CLK TDMS_A_DAT
HDMI_A_HPD_CN
1
20
1 2
3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19
21
SKT-HDMI23-26-GP-U
SKT-HDMI23-26-GP-U
22.10296.511
22.10296.511
22
23
2 2
HDMI Passive Level Shifter
HDMI DDC Passive Level Shifter
Close to HDMI Connector
HDMI_DATA2_R HDMI_DATA2_R#
HDMI_DATA1_R HDMI_DATA1_R#
HDMI_DATA0_R HDMI_DATA0_R#
HDMI_CLK_R HDMI_CLK_R#
1 1
A
2 3 1
2 3 1
2 3 1
2 3 1
RN5103SRN0J-6-GP RN5103SRN0J-6-GP
4
RN5104SRN0J-6-GP RN5104SRN0J-6-GP
4
RN5108SRN0J-6-GP RN5108SRN0J-6-GP
4
RN5107SRN0J-6-GP RN5107SRN0J-6-GP
4
RN5101
SRN680J-1-GP
RN5101
SRN680J-1-GP
123
HDMI_TX2+
HDMI_TX2-
HDMI_TX1+
HDMI_TX1­HDMI_TX0+
HDMI_TX0­HDMI_TXC+
HDMI_TXC-
678
4 5
B
3D3V_S0
123
RN5102
SRN680J-1-GP
RN5102
SRN680J-1-GP
12
DY
DY
R5104
R5104 100KR2J-1-GP
100KR2J-1-GP
678
4 5
D
Q5103
Q5103 2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
S
G
PCH_HDMI_DATA
PCH_HDMI_CLK
C
3D3V_S0
Q5104
Q5104
1
6
2
5
3 4
2N7002KDW-G P
2N7002KDW-G P
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
TDMS_A_DAT
TDMS_A_CLK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporat ion
Wistron Corporat ion
Wistron Corporat ion
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet
Date: Sheet
D
Date: Sheet
Taipei Hsien 221, Taiw an, R.O.C.
HDMI
HDMI
HDMI
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
E
-1
-1
51 94Tuesday, January 18, 2011
51 94Tuesday, January 18, 2011
51 94Tuesday, January 18, 2011
-1
of
of
of
A
4 4
3 3
B
C
D
E
BLANK
2 2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
1 1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
A
B
C
Date: Sheet
DISPLAY PORT CONNECTOR
DISPLAY PORT CONNECTOR
DISPLAY PORT CONNECTOR
D
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
52 94Tuesday, January 18, 2011
52 94Tuesday, January 18, 2011
52 94Tuesday, January 18, 2011
of
of
of
E
-1
-1
-1
5 4 3 2 1
A
D
C
BLANK
B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
BLANK
BLANK
BLANK
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
53 94Tuesday, January 18, 2011
53 94Tuesday, January 18, 2011
53 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
5 4 3 2 1
A
D
C
B
BLANK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
BLANK
BLANK
BLANK
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
54 94Tuesday, January 18, 2011
54 94Tuesday, January 18, 2011
54 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
A
4 4
3 3
B
C
D
E
2 2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
1 1
Title
Title
Title
FAN CONTROL
FAN CONTROL
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
A
B
C
Date: Sheet
D
FAN CONTROL
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
55 94Tuesday, January 18, 2011
55 94Tuesday, January 18, 2011
55 94Tuesday, January 18, 2011
of
of
of
E
-1
-1
-1
A
HDD Connector
B
C
D
E
C5606
C5606
3D3V_S0
R56100R3J-0-U-GP R56100R3J-0-U-GP R56110R3J-0-U-GP R56110R3J-0-U-GP
1 2 1 2
1 2 1 2
5V_S0
R56080R3J-0-U-GP R56080R3J-0-U-GP R56090R3J-0-U-GP R56090R3J-0-U-GP
C5610SCD01U16V2KX-3GP C5610SCD01U16V2KX-3GP
12
C5609SCD01U16V2KX-3GP C5609SCD01U16V2KX-3GP
12
C5603SCD01U16V2KX-3GP C5603SCD01U16V2KX-3GP C5602SCD01U16V2KX-3GP C5602SCD01U16V2KX-3GP
SATA_TXP0 21 SATA_TXN0 21
SATA_RXP0 21 SATA_RXN0 21
SATA Zero Power ODD
HDD1
HDD1
23
GND
4 4
HDD_DTCT#27
3 3
24
GND
NP1
NP1
NP2
NP2
S1
GND
S4
GND
S7
GND
P4
GND
P5
GND
P6
GND
P10
GND
P12
GND
P11
DAS/DSS
SKT-SATA7P-15P-65-GP
SKT-SATA7P-15P-65-GP
22.10300.B31
22.10300.B31
ODD Connector
P1
V33
P2
V33
P3
V33
P7
V5
P8
V5
P9
V5
P13
V12
P14
V12
P15
V12
S2
A+
S3
A-
S6
B+
S5
B-
SATA_RX- and SATA_RX+ Trace Length match within 20 mil
Mars: Exchange ODD and ESATA differential pair each other.
3D3V_S0_HDD
5V_S0_HDD
PN5601PWRNC PN5601PWRNC PN5602PWRNC PN5602PWRNC PN5603PWRNC PN5603PWRNC
SATA_TXP0_C SATA_TXN0_C
SATA_RXP0_C SATA_RXN0_C
C5615
C5615
1 2
DY
DY
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
C5614
C5614
1 2
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
1 2
C5613
C5613
DY
DY
1 2 1 2
12
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
R56030R5J-5-GP
R56030R5J-5-GP
5V_S0
RN5601
RN5601
4
SRN10KJ-5-GP
SRN10KJ-5-GP
SATA_TXN4 21
SATA_TXP4 21
SATA_RXN4 21 SATA_RXP4 21
3D3V_S0
1 23
12
C5601
C5601 SCD1U10V2KX-5GP
SUPPORT ZERO SATA ODD
20100926 V2.2
0707 Modify: Change Q5601 to DUAL 2N7002 for isolate MD/DA signal between PCH and ODD.
C
5V_S0
12
R5606
R5606 100KR2J-1-GP
100KR2J-1-GP
ODD_PWRGT#
SATA_ODD_DA#_C
5
6
Q5601
Q5601
SATA_ODD_PWRGT SATA_ODD_DA#
123 4
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
SCD1U10V2KX-5GP
D
DY
DY
R5602 0R3J-0-U-GP
R5602 0R3J-0-U-GP
5V_S0
12
C5604
C5604 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SATA_ODD_PWRGT22
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
1 2
-1 0114
12
R5601
R5601 100KR2J-1-GP
100KR2J-1-GP
SATA_ODD_PWRGT_T
D
Q5602
Q5602 2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
S
G
SATA HDD
SATA HDD
SATA HDD
S
Q5603
Q5603
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
ODD1
2 2
SATA_ODD_DA#18
SATA_ODD_PRSNT#22
R5605
R5605
1 2
DY
DY
12
SATA_ODD_DA#_C
0R2J-2-GP
0R2J-2-GP
DY
DY
R5604
R5604 10KR2J-3-GP
10KR2J-3-GP
ODD1
P4
MD
P1
DP
S1
GND
S4
GND
S7
GND
P5
GND
P6
GND
14
GND
15
GND
SKT-SATA7P-6P-56-GP
SKT-SATA7P-6P-56-GP
NP1 NP2
+5V +5V
A+
B+
A-
B-
P2 P3
S3 S2
S5 S6
NP1 NP2
ODD_PWR_5V
SATA_TXN4_C SATA_TXP4_C
SATA_RXN4_C SATA_RXP4_C
DY
DY
1 2
C5611 SCD01U16V2KX-3GPC5611 SCD01U16V2KX-3GP
1 2
C5612 SCD01U16V2KX-3GPC5612 SCD01U16V2KX-3GP
1 2
C5607 SCD01U16V2KX-3GPC5607 SCD01U16V2KX-3GP
1 2
C5608 SCD01U16V2KX-3GPC5608 SCD01U16V2KX-3GP
1 2
When the drive is powered on, the FET to the MD/DA pin drive is OFF. When the drive is powered off, the FET to the MD/DA pin is ON
1 1
SATA_ODD_PWRGT SATA_ODD_DA#
A
B
D
AO3419L-GP
AO3419L-GP
G
E
ODD_PWR_5V
56 94Tuesday, January 18, 2011
56 94Tuesday, January 18, 2011
56 94Tuesday, January 18, 2011
100 mil
12
C5605
C5605 SC1U10V2KX-1GP
SC1U10V2KX-1GP
of
of
of
-1
-1
-1
A
B
ESATA Connector
C
D
E
4 4
DY
DY
G2
RCLAMP0524P-GP
RCLAMP0524P-GP
SATA_TXP521 SATA_TXN521
SATA_RXP521
3 3
2 2
SATA_RXN521
USB_PP818 USB_PN818
5V_S5
12
C5704
C5704
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
USB_PWR_EN27,61 USB_OC#8_9 18,61
D5701
D5701
L1#1 L2#2 GND L3#3 L4#4
1 2 G1 3 4
USB_PP8 USB_PN8
U5701
U5701
1
GND
2
IN#2
3
IN
4
EN
8
OUT#8
7
OUT#7
6
OUT
5
OC#
GND
9
TPS2065DGN-GP
TPS2065DGN-GP
USB_PWR1
U1
C5707SCD01U16V2KX-3GP C5707SCD01U16V2KX-3GP
12
C5708SCD01U16V2KX-3GP C5708SCD01U16V2KX-3GP
12
C5705SCD01U16V2KX-3GP C5705SCD01U16V2KX-3GP
12
C5706SCD01U16V2KX-3GP C5706SCD01U16V2KX-3GP
12
S2 S3
S6 S5
U3 U2
SKT-ESATA-USB-S7-U4-5-GP-U
SKT-ESATA-USB-S7-U4-5-GP-U
Near ESATA1
USB_PWR1
USB_PP8 USB_PN8
ESATA1
ESATA1
VBUS
A+ A-
B+ B-
D+ D-
NP1 NP2
GND GND GND
GND CHASSIS#12 CHASSIS#13 CHASSIS#14 CHASSIS#15
1
AFTP5701 AFTE14P-GPAFTP5701 AFTE14P-GP
1
AFTP5702 AFTE14P-GPAFTP5702 AFTE14P-GP
1
AFTP5703 AFTE14P-GPAFTP5703 AFTE14P-GP
1
AFTP5704 AFTE14P-GPAFTP5704 AFTE14P-GP
NP1 NP2
S1 S4 S7 U4 12 13 14 15
8
L1#8
7
L2#7 GND
6
L3#6
5
L4#5
USB_PWR1
12
TC5701
C5703
C5703
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C5702
C5702
TC5701
ST150U6D3VBM-1-GP
ST150U6D3VBM-1-GP
WIDE PATT ERN (MIN 500MA) PLACE NEAR USB CONNECTOR
Table 57.1- USB2.0 PWR SW multi-source
Supplier
TI
Description Lenovo P/N Wistron P/N
TPS2065DGN4
ROHM
Table 57.2- 150U 6.3V POSCAP multi-source
Supplier
SANYO
Description Lenovo P/N Wistron P/N
6TPE150MAZB 77.21571.111
54Y9024BA
54Y9024AABD8012FVJ
N/ATEPSLB20J157M
N/A
74.02065.079
74.08012.07G
77.C1571.09LNEC-TOKIN
HPC
<Core Design>
<Core Design>
DY
DY
D5702
D5702
1 1
USB_PP8 USB_PN8
A
1
ESD I/O1
2
GND
3
ESD I/O2
IP4223CZ6-GP
IP4223CZ6-GP
ESD I/O4 ESD I/O3
VP
6 5 4
B
5V_S5
C
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
TNCB0J157MTRZTF N/A 80.15715.12L
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
ESATA CONNECTOR
ESATA CONNECTOR
ESATA CONNECTOR
A4
A4
A4
D
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
57 94Tuesday, January 18, 2011
57 94Tuesday, January 18, 2011
57 94Tuesday, January 18, 2011
E
-1
-1
-1
of
of
of
5
4
3
2
1
JACK SENSENEAR HEADPHONE CONN
R5804 5D1R2J-1-GPR5804 5D1R2J-1-GP
AUD_PORTA_L29
AUD_PORTA_R29
D D
TP5808
TP5808
MIC_JACK_3
1
12
AFTE14P-GP
AFTE14P-GP
D5803
D5803
RSB5D6SMT2R-GP
RSB5D6SMT2R-GP
AU_GND
C C
7
MIC_JACK3
NP1
NP1
NP2
NP2
HP_L_JACK
HP_R_JACK
1
AGND
HP_JACK_SYS
8
DGND
9
DGND
AUDIO-JK244-GP
AUDIO-JK244-GP
confirm HPMIC1 is NO type's connector
R5805 5D1R2J-1-GPR5805 5D1R2J-1-GP
HPMIC1
HPMIC1
4
VCC3MA
2 3
5
6
NC#6
1 2
1 2
TP5809
TP5809 AFTE14P-GP
AFTE14P-GP
1
HP_L_JACK_R HP_R_JACK_R
HP_JACK_SYS
AUD_5V
R5810
R5810 1KR2J-1-GP
1KR2J-1-GP
1 2
C5812 SC1U10V2KX-1GPC5812 SC1U10V2KX-1GP
1 2
HP_L_JACK_R
HP_R_JACK_R
HP_JACK_SYS
AU_GND
12
12
D5802
D5802
D5801
D5801
RSB5D6SMT2R-GP
RSB5D6SMT2R-GP
RSB5D6SMT2R-GP
RSB5D6SMT2R-GP
AU_GND
R5814
R5814 100KR2J-1-GP
100KR2J-1-GP
1 2
1 1
1
TP5805AFTE14P-GP TP5805AFTE14P-GP TP5806AFTE14P-GP TP5806AFTE14P-GP
TP5807AFTE14P-GP TP5807AFTE14P-GP
MIC_JACK_3
R5803 10KR2J-3-G PR5803 10KR2J-3-GP
1 2
12
AU_GND
C5813
C5813 SC1U10V2KX-1GP
SC1U10V2KX-1GP
R5808 10KR2F- 2-GPR5808 10KR2F -2-GP
1 2
D
Q5801
Q5801 2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
S
G
D
Q5804
Q5804 2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
S
G
AU_GND
AUD_SENSE_A 29
HP_JACK_SYS
R5802 39K2R2F- L-GPR5802 39K2R2F -L-GP
1 2
D
Q5803
Q5803 2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
S
G
AU_GND
AUD_SENSE_A 29
EC5808 SCD01U25V2KX-3GPEC5808 SCD 01U25V2KX-3GP
1 2
AU_GND
MIC_JACK_3
R5817 0R2J-2-GPR5817 0R2J-2-GP
1 2
R5815 0R2J-2-GPR5815 0R2J-2-GP
AUD_PORTC_R_C29
AUD_PORTC_L_C29
1 2
R5816 0R2J-2-GPR5816 0R2J-2-GP
1 2
R5801
R5801 2K2R2J-2-GP
2K2R2J-2-GP
12
AU_GND
R5811
R5811 1KR2J-1-GP
1KR2J-1-GP
1 2
12
C5808
C5808 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
AUD_LDO_OUT_3D3V
DY
DY
EC5809 SCD01U25V2KX-3GP
EC5809 SCD01U25V2KX-3GP
1 2
EC5806 SCD01U25V2KX-3GPEC5806 SCD 01U25V2KX-3GP
1 2
EC5807 SCD01U25V2KX-3GPEC5807 SCD 01U25V2KX-3GP
1 2
AU_GND
AU_GND
AU_GND
INTERNAL STEREO SPEAKERS
Port G
AUD_SPK_L+_L29
B B
A A
5
4
AUD_SPK_L-_L29
Only needed if speaker connector is physically far from audio codec. W hen in doubt, it's always a good idea to have population option.
AUD_SPK_R-_L29 AUD_SPK_R+_L29
3
SC47P50V2JN-3GP
SC47P50V2JN-3GP
Place these EMI components close to speaker connector.
SC47P50V2JN-3GP
SC47P50V2JN-3GP
EC5803
EC5803
EC5801
EC5801
12
SC47P50V2JN-3GP
SC47P50V2JN-3GP
12
SC47P50V2JN-3GP
SC47P50V2JN-3GP
EC5802
EC5802
EC5804
EC5804
12
12
1 1
1 1
2
TP5801AFTE14P-GP TP5801AFTE14P-GP TP5802AFTE14P-GP TP5802AFTE14P-GP
1 2
3 4
ACES-CON4-29-GP
ACES-CON4-29-GP
TP5803AFTE14P-GP TP5803AFTE14P-GP TP5804AFTE14P-GP TP5804AFTE14P-GP
SPK1
SPK1
5
6
Table 58.1 - Bi-direction ESD multi-source
Supplier
ROHM
ON SEMI
Descri pt ion L enovo P/N Wi stron P/N
83.RSB56.BAF
RSB5.6SM T2R
ESD5B5.0ST1G
N/A
83.ESD5B.0AF
N/A
83.0005V.0AFNXP N/APESD5V0S1BB
<Core Design>
<Core Design>
<Core Design>
Wistron Corporat ion
Wistron Corporat ion
Wistron Corporat ion
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A2
A2
A2
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiw an, R.O.C.
Audio Jack
Audio Jack
Audio Jack
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
58 94
58 94
58 94
of
of
of
-1
-1
-1
5
4
3
2
1
D D
C C
B B
<Core Design>
<Core Design>
A A
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
BLANK
BLANK
BLANK
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
59 94Tuesday, January 18, 2011
59 94Tuesday, January 18, 2011
59 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
5
SSID = Flash.ROM
4
3
2
1
SPI FLASH ROM (4M byte) for PCH
3D3V_SPI
D D
678
RN6001
RN6001 SRN4K7J-10-GP
SRN4K7J-10-GP
123
4 5
SPI_CS0#_R21,27
SPI_SO_R21,27
C C
R6001 33R2J-2-GPR6001 33R2J-2-GP
1 2
DY
DY
12
EC6002
EC6002 SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SPI_SO SPI_WP#
SPI_HOLD_0#
U6001
U6001
1
CE#
2
SO
3
WP# VSS4SI
SST25VF032B-80-4I-S2AF-GP
SST25VF032B-80-4I-S2AF-GP
VDD
HOLD#
SCK
8 7 6 5
3D3V_SPI
DY
DY
12
EC6003
EC6003 SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
DY
DY
12
C6001
C6001 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
DY
12
EC6001
EC6001 SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
3D3V_SPI
12
C6002
C6002 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SPI_CLK_R 21,27 SPI_SI_R 21,27
3D3V_SPI 3D3V_S0 3D3V_S5
20100622 V1.2
DY
R6011 0R2J-2-GP
R6011 0R2J-2-GP R6010 0R2J-2-GPR6010 0R2J-2-GP
DY
12 12
the same page 23 VCCSPI power
Table 60.1- SPI Serial Flash Memory multi-source
Supplier
B B
WINBOND
NUMONYX
Description Lenovo P/N Wistron P/N
MX25L3206EM2I-12G
W25Q32BVSSIG 72.25Q32.A01
N/A
N/A
72.25320.C01MXIC
M25PX32-VMW6F N/A 72.25P32.C01
Table 6 0.2 - Schot tky Barrier Diode multi-source
2
1
RTC_PWR
4
3D3V_AUX_S5
R6002 1KR2J-1-GPR6002 1KR2J-1-GP
1 2
TP6002TPAD14-GP TP6002TPAD14-GP
+RTC_VCC
1
+RTC_VCC
TP6001TP6001
1
RTC1
RTC1
3 1 2
4
ACES-CON2-31-GP
ACES-CON2-31-GP
3
Supplier
CHENMKO
CHENMKO
Description Lenovo P/N Wistron P/N
CH715FGP
BAS40CWGP
N/A
N/A
83.R0304.D81
83.00040.R81
83.00040.E81PANJIT N/ABAS40CW
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
2
Date: Sheet
Flash/RTC
Flash/RTC
Flash/RTC
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Taipei Hsien 221, Taiwan, R.O.C.
of
60 94
of
60 94
of
60 94
1
-1
-1
-1
Q6001
RTC_AUX_S5
Q6001
SSID = RBATT
3
C6003
C6003
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
A A
5
1 2
CH715FGP-GP-U
CH715FGP-GP-U
Width=20mils
5
4
3
2
1
USB Connector
WIDE PATTERN (MIN 500M A) PLACE NEAR USB CONNECTOR
R6101 0R3J-0-U-GPR6101 0R3J-0-U-GP
D D
USB_PN918 USB_PP918
C C
USB_PN118 USB_PP118
B B
1 2
1
DY
DY
TR6101
TR6101 ACM2012-900-1GP
ACM2012-900-1GP
3 4
2
R6102 0R3J-0-U-GPR6102 0R3J-0-U-GP
1 2
WIDE PATTERN (MIN 500M A) PLACE NEAR USB CONNECTOR
R6103 0R3J-0-U-GPR6103 0R3J-0-U-GP
1 2
34
2
DY
DY
TR6102
TR6102 ACM2012-900-1GP
ACM2012-900-1GP
1
R6104 0R3J-0-U-GPR6104 0R3J-0-U-GP
1 2
USB_PWR2
12
C6101
C6101
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
USB_PWR3
12
C6103
C6103
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Left Rear USB Connector
USBPN9_TVS USBPP9_TVS
12
12
C6102
C6102
SC470P50V2KX-3GP
SC470P50V2KX-3GP
TC6101
TC6101
ST150U6D3VBM-1-GP
ST150U6D3VBM-1-GP
Left Front USB Connector
USBPN1_TVS USBPP1_TVS
12
12
C6104
C6104
SC470P50V2KX-3GP
SC470P50V2KX-3GP
TC6102
TC6102
ST150U6D3VBM-1-GP
ST150U6D3VBM-1-GP
Near USB2
USB_PWR3
USBPN1_TVS USBPP1_TVS
Near USB1
USB_PWR2
USBPN9_TVS USBPP9_TVS
1 1
1 1
1 1
1 1
USB1
USB1
6 1
2 3 4 5
SKT-USB6-21-GP
SKT-USB6-21-GP
22.10321.Z61
22.10321.Z61
USB2
USB2
6 1
2 3 4 5
SKT-USB6-21-GP
SKT-USB6-21-GP
22.10321.Z61
22.10321.Z61
AFTP6101 AFTE14P-GPAFTP6101 AFTE14P-GP AFTP6102 AFTE14P-GPAFTP6102 AFTE14P-GP
AFTP6103 AFTE14P-GPAFTP6103 AFTE14P-GP AFTP6104 AFTE14P-GPAFTP6104 AFTE14P-GP
AFTP6107 AFTE14P-GPAFTP6107 AFTE14P-GP AFTP6105 AFTE14P-GPAFTP6105 AFTE14P-GP
AFTP6108 AFTE14P-GPAFTP6108 AFTE14P-GP AFTP6106 AFTE14P-GPAFTP6106 AFTE14P-GP
USB_PWR_EN27,57
5V_S5
USB_PWR2 USB_PW R3
12
C6105
C6105
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
USBPP1_TVS USBPN1_TVS
1 2 3
U6102
U6102
1
ESD I/O1
2
GND
3
ESD I/O2
IP4223CZ6-GP
IP4223CZ6-GP
U6101
U6101
GND IN
OUT1
EN1
OUT2
EN24OC2#
GND
9
DY
DY
ESD I/O4 ESD I/O3
8
OC1#
7 6 5
TPS2066DGN-GP-U
TPS2066DGN-GP-U
6 5
VP
4
USBPN9_TVSUSBPP9_TVS
Table 61.1- USB2.0 PWR SW multi-source
Supplier
TI
Description Lenovo P/N Wistron P/N
TPS2066DGN
TI
5V_S5
41R0511AA
N/ATPS2066DGN-1
USB_OC#8_9 18,57
USB_OC#0_1 18
74.02066.A71
74.02066.B71
Table 61.2- 150U 6.3V POSCAP multi-source
Supplier
SANYO
Description Lenovo P/N Wistron P/N
N/ATEPSLB20J157M
6TPE150MAZB 77.21571.111
N/A
77.C1571.09LNEC-TOKIN
HPC TNCB0J157MTRZTF N/A 80.15715.12L
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
USB Connector
USB Connector
USB Connector
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
61 94Tuesday, January 18, 2011
61 94Tuesday, January 18, 2011
61 94Tuesday, January 18, 2011
1
of
of
of
-1
-1
-1
5 4 3 2 1
A
D
C
B
BLANK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
BLANK
BLANK
BLANK
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
62 94Tuesday, January 18, 2011
62 94Tuesday, January 18, 2011
62 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
5 4 3 2 1
A
D
Bluetooth Connector
3D3V_S0
C
F6301
BT1
BT1
15 NP1
1
WIFI_BUSY65
BLUETOOTH_EN27
TP1702TPAD14-GP TP1702TPAD14-GP
LED_BDC_IN
1
3 5 7
9 11 13
HRS-CONN14D-1-GP
HRS-CONN14D-1-GP
2 4
6 8 10 12 14 NP2 16
3D3V_BT_S0
BT_BUSY 65BDC_PRESENCE#18
USB_PP3 18
USB_PN3 18
F6301 POLYSW-D5A6V-1-GP
POLYSW-D5A6V-1-GP
1 2
12
C6301
C6301 SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
B
BDC_PRESENCE# WIFI_BUSY BLUETOOTH_EN BT_BUSY 3D3V_BT_S0
1
TP1106TP1106
1
TP1107TP1107
1
TP1108TP1108
1
TP1109TP1109
1
TP1110TP1110
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A
Title
Title
Title
Bluetooth
Bluetooth
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
Bluetooth
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
63 94Tuesday, January 18, 2011
63 94Tuesday, January 18, 2011
63 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
5 4 3 2 1
A
D
C
BLANK
B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
FingerPrint
FingerPrint
FingerPrint
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
64 94Tuesday, January 18, 2011
64 94Tuesday, January 18, 2011
64 94Tuesday, January 18, 2011
-1
-1
-1
of
of
of
A
B
C
D
E
HALF MINI CARD FOR WLAN
3D3V_S0
4 4
DY
DY
R6511 0R2J-2-GP
R6511 0R2J-2-GP
PCIE_WAKE#19,82
PCIE_CLK_WLAN_RQ3#20
R6501 0R2-PT5-LILY-GPR6501 0R2-PT5-LILY-GP
E51_RXD27 E51_TXD27
3 3
5V_S5
1 2
R6502 0R2-PT5-LILY-GPR6502 0R2-PT5-LILY-GP
1 2
R6503 0R3J-0-U-GP
R6503 0R3J-0-U-GP
1 2
DY
DY
1 2
WIFI_BUSY63
CLK_PCIE_WLAN#20 CLK_PCIE_WLAN20
BT_BUSY63
E51_RXD_R E51_TXD_R
PCIE_RXN420 PCIE_RXP420
PCIE_TXN420 PCIE_TXP420
+5V_MINI_DEBUG
WLAN1
WLAN1
53
NP1
1 3
5 7
9 11 13 15
17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
NP2
54
TCN-CONN52A-2-GP
TCN-CONN52A-2-GP
3D3V_S0
2 4
6
LPC_AD0_C
8
LPC_AD1_C
10
LPC_AD2_C
12
LPC_AD3_C
14
LPC_FRAME#_C
16
18 20 22 24 26 28 30 32 34 36 38 40 42 44
CLK_PCI_LPC_C
46 48 50 52
1D5V_S0
1 2
DY
DY
1 2
DY
DY
1 2
DY
DY
1 2
DY
DY
1 2
DY
DY
PLT_RST#_WLAN
PCH_SMBCLK_WLAN PCH_SMBDATA_WLAN
WLAN_LED#
R6508 0R2J-2-GP
R6508 0R2J-2-GP
R6510 0R2-PT5-LILY-GPR6510 0R2-PT5-LILY-GP
1 2
1 12
DY
DY
R6504~R6509 close to Debug connector
R65050R2J-2-GP
R65050R2J-2-GP R65040R2J-2-GP
R65040R2J-2-GP R65070R2J-2-GP
R65070R2J-2-GP R65060R2J-2-GP
R65060R2J-2-GP R65090R2J-2-GP
R65090R2J-2-GP
R6512 0R2-PT5-LILY-GPR6512 0R2-PT5-LILY-GP
1 2
R6513 0R2-PT5-LILY-GPR6513 0R2-PT5-LILY-GP
1 2
USB_PN11 18 USB_PP11 18
TP6501TP6501
LPC_AD0 21,27,71 LPC_AD1 21,27,71 LPC_AD2 21,27,71 LPC_AD3 21,27,71
LPC_FRAME# 21,27,71
3D3V_S0
CLK_PCI_LPC 18,71
WIFI_RF_EN 27 PLT_RST# 5,18,27,32,36,66,71,80,82,83
PCH_SMBCLK 14,15,20,66
PCH_SMBDATA 14,15,20,66
2 2
5V_S5
12
C6501
C6501 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 1
A
12
C6505
C6505 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C6506
C6506 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C6507
C6507 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
B
3D3V_S01D5V_S0
12
C6502
C6502 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C6503
C6503 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C
12
C6504
C6504 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
MINI CARD SLOT 1
MINI CARD SLOT 1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
D
MINI CARD SLOT 1
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
65 94Tuesday, January 18, 2011
65 94Tuesday, January 18, 2011
65 94Tuesday, January 18, 2011
E
-1
-1
-1
of
of
of
A
B
C
D
E
Mini Card Connector(WWAN)
Place near MINI Card CONN
3D3V_S0
4 4
12
TC6601
TC6601 ST220U6D3VDM-20GP
ST220U6D3VDM-20GP
12
C6606
C6606 SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
3 3
3D3V_S0
12
C6608
C6608 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C6601
C6601 SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
1D5V_S0
12
C6607
C6607 SC33P50V2JN-3GP
SC33P50V2JN-3GP
12
C6609
C6609 SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
12
C6602
C6602 SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
Place near Pin 24
1D5V_S0
12
C6610
C6610 SC33P50V2JN-3GP
SC33P50V2JN-3GP
12
C6603
C6603 SC33P50V2JN-3GP
SC33P50V2JN-3GP
SATA_RXP121 SATA_RXN121
SATA_TXN121 SATA_TXP121
DY
DY
12
C6604
C6604 SC33P50V2JN-3GP
SC33P50V2JN-3GP
C6612 SCD01U16V2KX-3GPC6612 SCD01U16V2KX-3GP
1 2
C6613 SCD01U16V2KX-3GPC6613 SCD01U16V2KX-3GP
1 2
C6614 SCD01U16V2KX-3GPC6614 SCD01U16V2KX-3GP
1 2
C6615 SCD01U16V2KX-3GPC6615 SCD01U16V2KX-3GP
1 2
WWAN_IN18
mSATA_DTCT#22,27
3D3V_WW AN
SATA_RXP1_C SATA_RXN1_C
SATA_TXN1_C SATA_TXP1_C
WWAN1
WWAN1
53
NP1
1 3
5 7
9 11 13 15
17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
NP2
54
TCN-CONN52A-2-GP
TCN-CONN52A-2-GP
2 4
6 8 10 12 14 16
18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
1D5V_S0 3D3V_WWAN
UIM_PWR UIM_DATA UIM_CLK_SIM UIM_RESET UIM_VPP
PLT_RST#
PCH_SMBCLK_WW AN PCH_SMBDATA_WW AN
USB_PN4_R USB_PP4_R
3G_LED#
3D3V_S0
1
UIM_CLK_SIM
3G_EN 27 PLT_RST# 5,18,27,32,36,65,71,80,82,83
R6604 0R2-PT5-LILY-GPR6604 0R2-PT5-LILY-GP
1 2
R6609 0R2-PT5-LILY-GPR6609 0R2-PT5-LILY-GP
1 2
R6603 0R0402-PADR6603 0R0402-PAD
1 2
R6601 0R0402-PADR6601 0R0402-PAD
1 2
TP6602 TPAD14-GPTP6602 TPAD14-GP
R6602
R6602
0R0402-PAD
0R0402-PAD
12
UIM_CLK
DY
DY
12
C6605
C6605 SC100P50V2JN-3GP
SC100P50V2JN-3GP
PCH_SMBCLK 14,15,20,65
PCH_SMBDATA 14,15,20,65
USB_PN4 18 USB_PP4 18
10A2.7A
1 2
R6605
R6605 0R3J-0-U-GP
12
DY
DY
R6608
R6608 10KR2J-3-GP
10KR2J-3-GP
0R3J-0-U-GP
DY
12
12
DY
DY
C6611
C6611
SCD1U10V2KX-5GP
2 2
3G_POWERON27
1 1
A
SCD1U10V2KX-5GP
B
DY
DY
R6606
R6606
100KR2J-1-GP
100KR2J-1-GP
DY
DY
Q6601
Q6601
R1
R1
B
R2
R2
PDTC115EE-1-GP
PDTC115EE-1-GP
C E
54
TPCF8102-GP
TPCF8102-GP
12
R6607
R6607 10KR2J-3-GP
10KR2J-3-GP
DY
DY
6
7
321
8
DY
U6601
U6601
3D3V_S03D3V_S5 3D3V_WW AN
SIM Connector
SIM1
SIM1
UIM_PWR
12
C6616
C6616
DY
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C
DY
TP6601TP6601
D
UIM_RESET UIM_CLK
UIM_VPP UIM_DATA
CD
1
1
VCC
2
RST
3
CLK
5
GND
6
VPP
7
I/O
8
GND
9
GND
10
CD
NP1
NP1
NP2
NP2
CARD-PUSH-7P-2-GP
CARD-PUSH-7P-2-GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
MINI CARD SLOT 2
MINI CARD SLOT 2
MINI CARD SLOT 2
Taipei Hsien 221, Taiwan, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
66 94Tuesday, January 18, 2011
66 94Tuesday, January 18, 2011
66 94Tuesday, January 18, 2011
E
of
of
of
-1
-1
-1
5 4 3 2 1
A
D
C
B
BLANK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
BLANK
BLANK
BLANK
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
67 94Tuesday, January 18, 2011
67 94Tuesday, January 18, 2011
67 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
5 4 3 2 1
A
D
C
B
BLANK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
BLANK
BLANK
BLANK
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
68 94Tuesday, January 18, 2011
68 94Tuesday, January 18, 2011
68 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
A
B
C
D
E
Touch Pad Connector Track Point Connector
5V_S0
TP6917 AFTE14P-GPTP6917 AFTE14P-GP TP6915 AFTE14P-GPTP6915 AFTE14P-GP
4 4
TP6916 AFTE14P-GPTP6916 AFTE14P-GP TP6920 AFTE14P-GPTP6920 AFTE14P-GP TP6919 AFTE14P-GPTP6919 AFTE14P-GP TP6918 AFTE14P-GPTP6918 AFTE14P-GP TP6914 AFTE14P-GPTP6914 AFTE14P-GP TP6913 AFTE14P-GPTP6913 AFTE14P-GP TP6912 AFTE14P-GPTP6912 AFTE14P-GP TP6911 AFTE14P-GPTP6911 AFTE14P-GP TP6910 AFTE14P-GPTP6910 AFTE14P-GP TP6908 AFTE14P-GPTP6908 AFTE14P-GP
3 3
2 2
Table 69.1- Transistor multi-source
Supplier
1 1
ROHM
Panasonic
3D3V_FP_FUSE
1
USB_PN2
1
USB_PP2
1
PALM_LED_N
1
PALM_LED_P
1
PAD_DETECT#
1
TP4DATAPAD_R
1
TP4CLKPAD_R
1
5V_TP_FUSE
1
PAD_RESET#
1
TPCLK_R
1
TPDATA_R
1
TPAD1
TPAD1
21 1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22
PTWO-CON20-2-GP-U
PTWO-CON20-2-GP-U
20.K0392.020
20.K0392.020
PALM_LED27
TPDATA_R TPCLK_R
5V_TP_FUSE
TP4CLKPAD_R TP4DATAPAD_R
PALM_LED_P
PALM_LED_N
5V_S0
12
F6902
F6902
FUSE-D5A32V-14-GP
FUSE-D5A32V-14-GP
1
Q6901
Q6901
R1
R1
1
R2
R2
LTC043ZUB-FS8-GP
LTC043ZUB-FS8-GP
RN6901 SRN0J-6-GPRN6901 SRN0J-6-GP
1 2 3
RN6902 SRN0J-6-GPRN6902 SRN0J-6-GP
1 2 3
330R2F-GP
330R2F-GP
TP6921AFTE14P-GP TP6921AFTE14P-GP
3 2
Description Lenovo P/N Wistron P/N
PDTC143ZU
LTC043ZUB
DRC5143Z0L
A
N/A
N/A
N/A
84.00143.E1KNXP
84.00043.011
84.05143.011
3D3V_S5
4
4
R6906
R6906
12
PALM_LED_N
5V_S0
R6901
R6901
1 2
100KR2J-1-GP
100KR2J-1-GP
USB_PP2 18 USB_PN2 18
R6902
R6902
1 2
100KR2J-1-GP
100KR2J-1-GP
100KR2J-1-GP
100KR2J-1-GP
3D3V_FP_FUSE
C6902
C6902 SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
1 2
B
R6904
R6904
1 2
R6903
R6903
1 2
100KR2J-1-GP
100KR2J-1-GP
1 2
FUSE-D5A32V-14-GP
FUSE-D5A32V-14-GP
DY
DY
1 2
C6903
C6903 SC4P50V2CN-GP
SC4P50V2CN-GP
R6905
R6905
1 2
100KR2J-1-GP
100KR2J-1-GP
TP4CLKPAD TP4DATAPAD
F6901
F6901
TPDATA 27 TPCLK 27
PAD_RESET# 27
PAD_DETECT# 27
3D3V_S0
12
R6908
R6908 10KR2F-2-GP
10KR2F-2-GP
TRP1
TRP1
ACES-CON10-26-GP
ACES-CON10-26-GP
20.K0585.010
20.K0585.010
11 1
2 3 4 5 6 7 8 9 10 12
TP4DATAPAD TP4_RESET
TP4MIDDLE TP4RIGHT TP4LEFT TP4CLKPAD
TRP1_PWR
1
TP6907 AFTE14P-GPTP6907 AFTE14P-GP TP6906 AFTE14P-GPTP6906 AFTE14P-GP TP6905 AFTE14P-GPTP6905 AFTE14P-GP TP6904 AFTE14P-GPTP6904 AFTE14P-GP TP6903 AFTE14P-GPTP6903 AFTE14P-GP TP6902 AFTE14P-GPTP6902 AFTE14P-GP TP6901 AFTE14P-GPTP6901 AFTE14P-GP
R6907
R6907
1 2
0R0402-PAD
0R0402-PAD
TP6909AFTE14P-GP TP6909AFTE14P-GP
TP4_RESET 27
5V_S0
TRP1_PWR
1
TP4CLKPAD
1
TP4LEFT
1
TP4RIGHT
1
TP4MIDDLE
1
TP4_RESET
1
TP4DATAPAD
1
KeyBoard Connector
KB1
KB1
31
32
ACES-CON30-8-GP
ACES-CON30-8-GP
20.K0524.030
20.K0524.030
2nd = 20.K0385.030
2nd = 20.K0385.030
C
KROW1
1
KROW7
2
KROW6
3
KCOL9
4
KROW4
5
KROW5
6
KCOL0
7
KROW2
8
KROW3
9
KCOL5
10
KCOL1
11
KROW0
12
KCOL2
13
KCOL4
14
KCOL7
15
KCOL8
16
KCOL6
17
KCOL3
18
KCOL12
19
KCOL13
20
KCOL14
21
KCOL11
22
KCOL10
23
KCOL15
24 25
TP4LEFT
26
TP4MIDDLE
27
TP4RIGHT
28
KCOL16
29
KCOL17
30
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
D
Date: Sheet
KROW[0..7] 27
KCOL[0..17] 27
TP6949 AFTE14P-GPTP6949 AFTE14P-GP TP6948 AFTE14P-GPTP6948 AFTE14P-GP
TP6947 AFTE14P-GPTP6947 AFTE14P-GP TP6946 AFTE14P-GPTP6946 AFTE14P-GP TP6945 AFTE14P-GPTP6945 AFTE14P-GP TP6944 AFTE14P-GPTP6944 AFTE14P-GP TP6943 AFTE14P-GPTP6943 AFTE14P-GP TP6942 AFTE14P-GPTP6942 AFTE14P-GP TP6941 AFTE14P-GPTP6941 AFTE14P-GP TP6940 AFTE14P-GPTP6940 AFTE14P-GP TP6939 AFTE14P-GPTP6939 AFTE14P-GP TP6938 AFTE14P-GPTP6938 AFTE14P-GP TP6937 AFTE14P-GPTP6937 AFTE14P-GP TP6936 AFTE14P-GPTP6936 AFTE14P-GP TP6935 AFTE14P-GPTP6935 AFTE14P-GP TP6934 AFTE14P-GPTP6934 AFTE14P-GP TP6933 AFTE14P-GPTP6933 AFTE14P-GP TP6932 AFTE14P-GPTP6932 AFTE14P-GP TP6950 AFTE14P-GPTP6950 AFTE14P-GP TP6929 AFTE14P-GPTP6929 AFTE14P-GP TP6927 AFTE14P-GPTP6927 AFTE14P-GP TP6928 AFTE14P-GPTP6928 AFTE14P-GP TP6931 AFTE14P-GPTP6931 AFTE14P-GP TP6930 AFTE14P-GPTP6930 AFTE14P-GP TP6924 AFTE14P-GPTP6924 AFTE14P-GP TP6922 AFTE14P-GPTP6922 AFTE14P-GP TP6923 AFTE14P-GPTP6923 AFTE14P-GP TP6926 AFTE14P-GPTP6926 AFTE14P-GP TP6925 AFTE14P-GPTP6925 AFTE14P-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
TOUCH PAD CONNECTOR
TOUCH PAD CONNECTOR
TOUCH PAD CONNECTOR
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
KROW1
1
KROW7
1
KROW6
1
KCOL9
1
KROW4
1
KROW5
1
KCOL0
1
KROW2
1
KROW3
1
KCOL5
1
KCOL1
1
KROW0
1
KCOL2
1
KCOL4
1
KCOL7
1
KCOL8
1
KCOL6
1
KCOL3
1
KCOL12
1
KCOL13
1
KCOL14
1
KCOL11
1
KCOL10
1
KCOL15
1
TP4LEFT
1
TP4MIDDLE
1
TP4RIGHT
1
KCOL16
1
KCOL17
1
of
69 94Tuesday, January 18, 2011
of
69 94Tuesday, January 18, 2011
of
69 94Tuesday, January 18, 2011
E
-1
-1
-1
5 4 3 2 1
A
D
C
BLANK
B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
BLANK
BLANK
BLANK
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
70 94Tuesday, January 18, 2011
70 94Tuesday, January 18, 2011
70 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
5 4 3 2 1
A
Golden Finger for Debug Board
D
C
B
TP80 TPAD30TP80 TPAD30
PLT_RST#
R7106
R7106
1 2
0R0402-PAD
0R0402-PAD
EXT_FWH#
PLT_RST# LPC_FRAME#_R
CLK_PCI_LPC
PLT_RST#_DEBUG LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R
3D3V_S0
GFDB1
GFDB1
TOP BOTTOM
TOP BOTTOM
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
GF-26P-GP-U1
GF-26P-GP-U1
ZZ.80648.026
ZZ.80648.026
5V_S0
14
14
15
15
16
02 Do not mirror
02 Do not mirror
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
For EMI
12
C7101
C7101
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
EXT_FWH# LPC_AD0_R LPC_AD1_R LPC_AD2_R LPC_AD3_R PLT_RST#_DEBUG
LPC_FRAME#_R
R7101 0R2J-2-GP
R7101 0R2J-2-GP
1 2
DY
DY
R7102 0R2J-2-GP
R7102 0R2J-2-GP
1 2
DY
DY
R7103 0R2J-2-GP
R7103 0R2J-2-GP
1 2
DY
DY
R7104 0R2J-2-GP
R7104 0R2J-2-GP
1 2
DY
DY
R7105 0R2J-2-GP
R7105 0R2J-2-GP
1 2
DY
DY
(BOTTOM VIEW)
TOP VIEW
(14)
1
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
2
(25)(15)
....
....
12
CLK_PCI_LPC 18,65
LPC_FRAME# 21,27,65 PLT_RST# 5,18,27,32,36,65,66,80,82,83
(26)
13
3D3V_S0
LPC_AD021,27,65 LPC_AD121,27,65 LPC_AD221,27,65 LPC_AD321,27,65
LPC_FRAME#21,27,65
PLT_RST#5,18,27,32,36,65,66,80,82,83
CLK_PCI_LPC18,65
A
DY
DY
DB1
DB1
1 2 3 4 5 6 7 8 9
10 11 12
MLX-CON10-7-GP
MLX-CON10-7-GP
20.D0183.110
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
DEBUG CONN
DEBUG CONN
DEBUG CONN
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
71 94Tuesday, January 18, 2011
71 94Tuesday, January 18, 2011
71 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
5 4 3 2 1
A
D
C
B
BLANK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
BLANK
BLANK
BLANK
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
72 94Tuesday, January 18, 2011
72 94Tuesday, January 18, 2011
72 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
5 4 3 2 1
A
D
C
B
BLANK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
BLANK
BLANK
BLANK
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
73 94Tuesday, January 18, 2011
73 94Tuesday, January 18, 2011
73 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
5
4
3
2
1
Please apply Shield GND for SD_CLK signal between R5U220 and SD Card Slot to decrease external noise.
D D
+3.3V_RUN_CARD
Card Reader Connector
+3.3V_RUN_CARD
12
DY
DY
R7401
+3.3V_RUN_CARD
C C
SD_D032 SD_D132 SD_D232 SD_D332
B B
SD_D0 SD_D1 SD_D2 SD_D3 SD_CLK
DY
DY
12
EC7401
EC7401 SC12P50V2JN-3GP
SC12P50V2JN-3GP
SD_D0 SD_D1 SD_D2 SD_D3
DY
DY
12
EC7402
EC7402 SC12P50V2JN-3GP
SC12P50V2JN-3GP
CDR1
CDR1
4
VDD
7
DAT0
8
DAT1
9
DAT2
1
CD/DAT3
NP1
NP1
NP2
NP2
CARD-PUSH-14P-1-GP
CARD-PUSH-14P-1-GP
20.I0078.011
20.I0078.011
DY
DY
12
EC7403
EC7403 SC12P50V2JN-3GP
SC12P50V2JN-3GP
CMD
CLK
CD
WP
EMPTY
VSS VSS
GND
CD/WP/GND
2 5 10 12 14
3 6
13 11
DY
DY
12
EC7404
EC7404 SC12P50V2JN-3GP
SC12P50V2JN-3GP
R7401 10KR2J-3-GP
10KR2J-3-GP
SD_CLK
SD_CMD 32
SD_CLK 32
SD_DET# 32
SD_WP 32
DY
DY
12
EC7405
EC7405 SC12P50V2JN-3GP
SC12P50V2JN-3GP
12
C7402
C7402 SC47U6D3V5MX-1-GP
SC47U6D3V5MX-1-GP
+3.3V_RUN_CARD trace = 40mil C7402 lose CDR1
12
C7403
C7403 SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
CARD Reader CONN
CARD Reader CONN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A4
A4
A4
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
5
4
3
Date: Sheet
2
CARD Reader CONN
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
-1
-1
74 94
74 94
74 94
of
of
of
1
-1
5
4
3
2
1
SSID = ExpressCard
+1.5V_CARD Max. 650mA, Average 500mA. +3.3V_CARD Max. 1300mA, Average 1000mA +3.3V_CARDAUX Max. 275mA
D D
C C
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
New Card
New Card
New Card
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Taipei Hsien 221, Taiwan, R.O.C.
of
75 94
of
75 94
of
75 94
1
-1
-1
-1
5 4 3 2 1
A
D
C
B
BLANK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
BLANK
BLANK
BLANK
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
76 94Tuesday, January 18, 2011
76 94Tuesday, January 18, 2011
76 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
A
4 4
3 3
B
C
D
E
BLANK
2 2
<Core Design>
<Core Design>
<Core Design>
1 1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
A
B
C
Date: Sheet
D
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
TPM
TPM
TPM
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
77 94Tuesday, January 18, 2011
77 94Tuesday, January 18, 2011
77 94Tuesday, January 18, 2011
of
of
of
E
-1
-1
-1
5 4 3 2 1
A
D
C
B
BLANK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
Date: Sheet
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
BLANK
BLANK
BLANK
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
78 94Tuesday, January 18, 2011
78 94Tuesday, January 18, 2011
78 94Tuesday, January 18, 2011
of
of
of
-1
-1
-1
5
4
3
2
1
D D
3D3V_S5
VCC3M_Q VCC3_ACC
R7901 10R2J-2-GPR7901 10R2J-2-GP
EBC
Q7901
Q7901 PDTA114EE-3-GP-U
PDTA114EE-3-GP-U
R2
R2
R1
R1
GSENSE_ON#27
C C
GSENSE_TST27
12
R7903
R7903 100KR2J-1-GP
100KR2J-1-GP
ANALOG_AGND
12
DY
DY
R7902
R7902 100KR2J-1-GP
100KR2J-1-GP
12
R7904
R7904 0R0402-PAD-1-GP
0R0402-PAD-1-GP
G-Sensor
1 2
14
U7901
U7901
2
ST
VDD
3
GND
5
GND
6
GND
7
GND
1
NC#1
4
NC#4
NC#99NC#16
LIS34ALTR-GP
LIS34ALTR-GP
15
RES VOUTZ
VOUTY VOUTX
NC#11 NC#13
12
C7901
C7901
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP
ANALOG_AGND
8 10 12
11 13 16
12
C7902
C7902
GSENSE_Z_R
GSENSE_Y_R
GSENSE_X_R
DY
DY
12
C7903
C7903 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
ANALOG_AGND
12
C7904
C7904 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
ANALOG_AGND
12
C7905
C7905 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
ANALOG_AGND
DY
DY
R7905 56KR2J-L1-GP
R7905 56KR2J-L1-GP
1 2
12
R7906 56KR2J-L1-GPR7906 56KR2J-L1-GP
1 2
R7907 56KR2J-L1-GPR7907 56KR2J-L1-GP
1 2
12
12
DY
DY
C7906
C7906 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C7907
C7907 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
GSENSE_X
C7908
C7908 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
GSENSE_Z 27
GSENSE_Y 27
GSENSE_X 27
Table 79.1- Transistor multi-source
Supplier
B B
R7902
R7903
All other
LIS34AL
KXTC8-2850
NO_ASM
ASM
ASM
No Accel
ASM
ASM
NO_ASM
Layout Comment : (1) Place C7904, C7905, Q7901, R7901, R7902,
C7901, C7902, R7903, R508 close to U7901. (2) Avoid routing under DCDC switching area.
NXP
ON
ROHM
Panasonic
Table 79.2- Accelerometer multi-source
Description Lenovo P/N Wistron P/N
PDTA114EE
DTA114EET1G
LTA014EEB
DRA9114E0L
N/A
N/A
N/A
N/A
84.00114.H1K
84.DT114.B11
84.00014.01H
84.09114.A11
Supplier De scription Lenovo P/N Wistron P/ N
ST
ROHM-KIONIX
LIS34ALTR-GP
KXTC8-2850-GP
41R0828AA
N/A
74.00034.0BZ
74.KXTC8.0BZ
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
G-Sensor
G-Sensor
G-Sensor
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Taipei Hsien 221, Taiwan, R.O.C.
of
79 94
of
79 94
of
79 94
1
-1
-1
-1
5
4
3
2
1
D D
3D3V_S0
C C
Q8001
Q8001
R1
R1
B
PDTC115TE-GP
PDTC115TE-GP
C E
3D3V_S5
12
R8001
R8001 4K7R2J-2-GP
4K7R2J-2-GP
PROT_EEPROM
PLT_RST# 5,18,27,32,36,65,66,71,82,83
RFID
U8001
U8001
1
NC#1
2
NC#2
3
PROT#
4
GND
BUL08-1FVJ-WGE2-GP
BUL08-1FVJ-WGE2-GP
VCC
WP
SCL
SDA
3D3V_S5
8 7 6 5
SMB_CLK 20,82 SMB_DATA 20,82
12
C8001
C8001
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
Table 80.1- Transistor multi-source
B B
Supplier
ROHM
Panasonic
Table 80.2- EEPROM multi-source
Supplier
A A
ROHM
NXP
SANYO
Description Lenovo P/N Wistron P/N
PDTC115TE
LTC015EEB
DRC9115T0L
N/A
N/A
N/A
84.00115.E1KNXP
84.00015.01H
84.09115.A11
Description Lenovo P/N Wistron P/N
BUL08-1FVJ-WGE2
PCA24S08ADP
LE26CAP08TT-TLM-H 72.26C08.00R
5
N/A
N/A
N/A
72.BUL08.A0Q
72.24S08.A0Q
4
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
RFID
RFID
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet
Date: Sheet
3
Date: Sheet
2
RFID
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
80 94Tuesday, January 18, 2011
80 94Tuesday, January 18, 2011
80 94Tuesday, January 18, 2011
1
-1
-1
-1
of
of
of
5
D D
C C
4
3
2
1
BLANK
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
of
81 94Tuesday, January 18, 2011
of
81 94Tuesday, January 18, 2011
of
81 94Tuesday, January 18, 2011
1
-1
-1
-1
5
4
3
2
1
TO EXP BOARD CONN
D D
1D5V_S0
5V_S5
650mA
2A
PLT_RST#5,18,27,32,36,65,66,71,80,83
SMB_CLK20,80 SMB_DATA20,80
R8202 0R2J-2-GP
R8202 0R2J-2-GP
PM_SLP_S4#19,27,46
C C
EXC_PWR_SHDN_R#27
B B
A A
5
1 2
DY
DY
R8203 0R2J-2-GPR8203 0R2J-2-GP
1 2
PCIE_WAKE#19,65
PM_SLP_S3#19,27,36,37,47
PCIE_CLK_NEW_RQ5#20
KBC_PWRBTN#27
4
3D3V_S0
GF1
GF1
TOPBOTTOM
3D3V_S5
275mA
1.3A
EXC_PWR_SHDN#
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
02 Do not mirror
02 Do not mirror
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
GF-MINIPCI52P-GP
GF-MINIPCI52P-GP
ZZ.00PAD.U71
ZZ.00PAD.U71
TOPBOTTOM
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
DC BOARD CONN
3D3V_S0
TP2
TP2 TPAD30
TPAD30
AD_JK
TP8201 AFTE14P-GPTP8201 AFTE14P-GP TP8202 AFTE14P-GPTP8202 AFTE14P-GP TP8203 AFTE14P-GPTP8203 AFTE14P-GP TP8204 AFTE14P-GPTP8204 AFTE14P-GP TP8205 AFTE14P-GPTP8205 AFTE14P-GP
AD+3D3V_LAN_S5
42 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11
41
ACES-CONN40A-9-GP
ACES-CONN40A-9-GP
20.F1844.040
20.F1844.040
1 1 1 1 1
DCCN1
DCCN1
9 7 5 3
1
AC_IN_LED_P AC_IN_LED_N ACDC_ID2 AD_OFF AD+
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4
2
3
3D3V_AUX_S5
AC_IN_LED_P
AC_IN_LED_N
12
R8201
R8201 620R2J-GP
620R2J-GP
USB_PN13 18 USB_PP13 18
USB_PN10 18 USB_PP10 18
USB_AO_SEL0 27
CLK_PCIE_NEW# 20
CLK_PCIE_NEW 20
PCIE_RXN8 20
PCIE_RXP8 20
USB_AO_SEL1 27
PCIE_TXN8 20 PCIE_TXP8 20
USB_PWR_EN2 27
USB_OC#10_11 18
LAN_XI 20
PCIE_WAKE# 19,65 PLT_RST# 5,18,27,32,36,65,66,71,80,83
PCIE_CLK_LAN_RQ0# 20
CLK_PCIE_LAN# 20
CLK_PCIE_LAN 20
PCIE_TXN2 20 PCIE_TXP2 20
PCIE_RXP2 20 PCIE_RXN2 20
AD_OFF 27
ACDC_ID2 27
Q8201
Q8201
3
R1
R1
2
R2
R2
LTC043ZUB-FS8-GP
LTC043ZUB-FS8-GP
1
AC_IN_LED 27
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
IO Board Connector
IO Board Connector
IO Board Connector
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Taipei Hsien 221, Taiwan, R.O.C.
of
82 94
of
82 94
of
82 94
1
-1
-1
-1
5
4
3
2
1
PEG_TXP[0..15]4 PEG_TXN[0..15]4
PEG_TXP0 PEG_TXN0
1 2
1 2
DY
DY
R8320
R8320 0R2J-2-GP
0R2J-2-GP
PEG_TXP1 PEG_TXN1
PEG_TXP2 PEG_TXN2
PEG_TXP3 PEG_TXN3
PEG_TXP4 PEG_TXN4
PEG_TXP5 PEG_TXN5
PEG_TXP6 PEG_TXN6
PEG_TXP7 PEG_TXN7
PEG_TXP8 PEG_TXN8
PEG_TXP9 PEG_TXN9
PEG_TXP10 PEG_TXN10
PEG_TXP11 PEG_TXN11
PEG_TXP12 PEG_TXN12
PEG_TXP13 PEG_TXN13
PEG_TXP14 PEG_TXN14
PEG_TXP15 PEG_TXN15
PWRGOOD
10KR2F-2-GP
10KR2F-2-GP
VGA_RST#
D D
C C
B B
CLK_PCIE_VGA20 CLK_PCIE_VGA#20
PX
PX
R8317
R8317
PCIE_RST#27,85
VGA1A
VGA1A
AA38
Y37
Y35
W36
W38
V37
V35 U36
U38 T37
T35 R36
R38 P37
P35 N36
N38
M37
M35
L36
L38 K37
K35
J36
J38
H37
H35
G36
G38
F37
F35 E37
AB35 AA36
AJ21 AK21 AH16
AA30
DY
DY
12
C8333
C8333
MADISON-PRO-2-GP
MADISON-PRO-2-GP
SC47P50V2JN-3GP
SC47P50V2JN-3GP
PCIE_RX0P PCIE_RX0N
PCIE_RX1P PCIE_RX1N
PCIE_RX2P PCIE_RX2N
PCIE_RX3P PCIE_RX3N
PCIE_RX4P PCIE_RX4N
PCIE_RX5P PCIE_RX5N
PCIE_RX6P PCIE_RX6N
PCIE_RX7P PCIE_RX7N
PCIE_RX8P PCIE_RX8N
PCIE_RX9P PCIE_RX9N
PCIE_RX10P PCIE_RX10N
PCIE_RX11P PCIE_RX11N
PCIE_RX12P PCIE_RX12N
PCIE_RX13P PCIE_RX13N
PCIE_RX14P PCIE_RX14N
PCIE_RX15P PCIE_RX15N
CLOCK
CLOCK
PCIE_REFCLKP PCIE_REFCLKN
NC#AJ21 NC#AK21 PWRGOOD
PERST#
PCI EXPRESS INTERFACE
PCI EXPRESS INTERFACE
PX
PX
1 OF 8
1 OF 8
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
CALIBRATION
CALIBRATION
PCIE_CALRP PCIE_CALRN
Y33 Y32
W33 W32
U33 U32
U30 U29
T33 T32
T30 T29
P33 P32
P30 P29
N33 N32
N30 N29
L33 L32
L30 L29
K33 K32
J33 J32
K30 K29
H33 H32
Y30 Y29
PEG_C_RXP0 PEG_C_RXN0
PEG_C_RXP1 PEG_C_RXN1
PEG_C_RXP2 PEG_C_RXN2
PEG_C_RXP3 PEG_C_RXN3
PEG_C_RXP4 PEG_C_RXN4
PEG_C_RXP5 PEG_C_RXN5
PEG_C_RXP6 PEG_C_RXN6
PEG_C_RXP7 PEG_C_RXN7
PEG_C_RXP8 PEG_C_RXN8
PEG_C_RXP9 PEG_C_RXN9
PEG_C_RXP10 PEG_C_RXN10
PEG_C_RXP11 PEG_C_RXN11
PEG_C_RXP12 PEG_C_RXN12
PEG_C_RXP13 PEG_C_RXN13
PEG_C_RXP14 PEG_C_RXN14
PEG_C_RXP15 PEG_C_RXN15
PCIE_CALRP PCIE_CALRN
dGPU reset for PX/SG transitions
R8321
R8321
3D3V_VGA_S0
5 4
Y
1 2
PLT_RST#5,18,27,32,36,65,66,71,80,82
A A
DY
DY
R8319 0R2J-2-GP
1D5V_VGA_PWOK86 1D8V_S0_VGA_PG93
R8319 0R2J-2-GP
PX
PX
R8325
R8325
0R2-PT5-LILY-GP
0R2-PT5-LILY-GP
5
12 12
PLT_RST#
1D8V_S0_VGA_PG_1
DY
DY
12
C8334
C8334 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
U8301
U8301
1
B
VCC
2
A
3
GND
74LVC1G08GW-1-GP
74LVC1G08GW-1-GP
4
PEG_RXP[0..15] 4 PEG_RXN[0..15] 4
C8301 SCD1U6D3V1KX-GP
C8301 SCD1U6D3V1KX-GP
1 2
PX
PX
C8302 SCD1U6D3V1KX-GP
C8302 SCD1U6D3V1KX-GP
1 2
PX
PX
C8303 SCD1U6D3V1KX-GP
C8303 SCD1U6D3V1KX-GP
1 2
PX
PX
C8304 SCD1U6D3V1KX-GP
C8304 SCD1U6D3V1KX-GP
1 2
PX
PX
C8305 SCD1U6D3V1KX-GP
C8305 SCD1U6D3V1KX-GP
1 2
PX
PX
C8306 SCD1U6D3V1KX-GP
C8306 SCD1U6D3V1KX-GP
1 2
PX
PX
C8308 SCD1U6D3V1KX-GP
C8308 SCD1U6D3V1KX-GP
1 2
PX
PX
C8307 SCD1U6D3V1KX-GP
C8307 SCD1U6D3V1KX-GP
1 2
PX
PX
C8309 SCD1U6D3V1KX-GP
C8309 SCD1U6D3V1KX-GP
1 2
PX
PX
C8310 SCD1U6D3V1KX-GP
C8310 SCD1U6D3V1KX-GP
1 2
PX
PX
C8311 SCD1U6D3V1KX-GP
C8311 SCD1U6D3V1KX-GP
1 2
PX
PX
C8312 SCD1U6D3V1KX-GP
C8312 SCD1U6D3V1KX-GP
1 2
PX
PX
C8313 SCD1U6D3V1KX-GP
C8313 SCD1U6D3V1KX-GP
1 2
PX
PX
C8314 SCD1U6D3V1KX-GP
C8314 SCD1U6D3V1KX-GP
1 2
PX
PX
C8316 SCD1U6D3V1KX-GP
C8316 SCD1U6D3V1KX-GP
1 2
PX
PX
C8315 SCD1U6D3V1KX-GP
C8315 SCD1U6D3V1KX-GP
1 2
PX
PX
C8318 SCD1U6D3V1KX-GP
C8318 SCD1U6D3V1KX-GP
1 2
PX
PX
C8317 SCD1U6D3V1KX-GP
C8317 SCD1U6D3V1KX-GP
1 2
PX
PX
C8320 SCD1U6D3V1KX-GP
C8320 SCD1U6D3V1KX-GP
1 2
PX
PX
C8319 SCD1U6D3V1KX-GP
C8319 SCD1U6D3V1KX-GP
1 2
PX
PX
C8321 SCD1U6D3V1KX-GP
C8321 SCD1U6D3V1KX-GP
1 2
PX
PX
C8322 SCD1U6D3V1KX-GP
C8322 SCD1U6D3V1KX-GP
1 2
PX
PX
C8323 SCD1U6D3V1KX-GP
C8323 SCD1U6D3V1KX-GP
1 2
PX
PX
C8324 SCD1U6D3V1KX-GP
C8324 SCD1U6D3V1KX-GP
1 2
PX
PX
C8325 SCD1U6D3V1KX-GP
C8325 SCD1U6D3V1KX-GP
1 2
PX
PX
C8326 SCD1U6D3V1KX-GP
C8326 SCD1U6D3V1KX-GP
1 2
PX
PX
C8328 SCD1U6D3V1KX-GP
C8328 SCD1U6D3V1KX-GP
1 2
PX
PX
C8327 SCD1U6D3V1KX-GP
C8327 SCD1U6D3V1KX-GP
1 2
PX
PX
C8330 SCD1U6D3V1KX-GP
C8330 SCD1U6D3V1KX-GP
1 2
PX
PX
C8329 SCD1U6D3V1KX-GP
C8329 SCD1U6D3V1KX-GP
1 2
PX
PX
C8332 SCD1U6D3V1KX-GP
C8332 SCD1U6D3V1KX-GP
1 2
PX
PX
C8331 SCD1U6D3V1KX-GP
C8331 SCD1U6D3V1KX-GP
1 2
PX
PX
R8316 1K27R2F-L-GP
R8316 1K27R2F-L-GP
1 2
PX
PX
R8318
DY
DY
R8318
1 2
DGPU_HOLD_RST#18
PX
PX
VGA_RST#
0R2J-2-GP
0R2J-2-GP
2KR2F-3-GP
2KR2F-3-GP
VGA_RST# 85
PEG_RXP0 PEG_RXN0
PEG_RXP1 PEG_RXN1
PEG_RXP2 PEG_RXN2
PEG_RXP3 PEG_RXN3
PEG_RXP4 PEG_RXN4
PEG_RXP5 PEG_RXN5
PEG_RXP6 PEG_RXN6
PEG_RXP7 PEG_RXN7
PEG_RXP8 PEG_RXN8
PEG_RXP9 PEG_RXN9
PEG_RXP10 PEG_RXN10
PEG_RXP11 PEG_RXN11
PEG_RXP12 PEG_RXN12
PEG_RXP13 PEG_RXN13
PEG_RXP14 PEG_RXN14
PEG_RXP15 PEG_RXN15
1V_VGA_S0
PX
PX
R8328 0R2J-2-GP
R8328 0R2J-2-GP
1 2
DY
DY
U8302
U8302
1
B
2
A
3
GND
74LVC1G08GW-1-GP
74LVC1G08GW-1-GP
VCC
5 4
Y
CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET
DESCRIPTION OF DEFAULT SETTINGS
Transmitter Power Savings Enable 0: 50% Tx output swing 1: Full Tx output swing
PCIE TRANSMITTER DE-EMPHASIS ENABLED 0:Tx de-emphasis disabled 1:Tx de-emphasis enabled
0:Advertises the PCIe device as 2.5GT/s capable at power on. 1:Advertises the PCIe device as 5.0GT/s capable at power on.
optional input allow the system to request a fast power reduction by setting GPIO5 to low.
0:VGA Controller capacity enabled 1:The device won't be recognized as the system's VGA controller
BIOS_ROM_EN=1, Config[2:0] defines t he ROM type BIOS_ROM_EN=0, Config[2: 0] defines the primary memory aperture size
0:Disable external BIOS ROM device
VIP Device Strap Enable indicates to the software driver tha t it sense whether or not a VIP device is connected on the VIP Host interface.
1:Enable external BIOS ROM device
RESERVED RESERVED
AUD[1:0]:11-Audio for both DisplayPort and HDMI
3D3V_VGA_S0
PE_GPIO0
H
L
H
2
3D3V_VGA_S0
3
STRAPS
TX_PWRS_ENB
GPIO8_ROMSO
VGA_DIS
GPIO21_BB_EN
BIOS_ROM_EN
VIP_DEVICE_STRAP_EN
RSVD
AUD[1]
PIN STRAPS
TX_PWRS_ENB85 TX_DEEMPH_EN85 BIF_GEN2_EN_A85
GPIO8_ROMSO85
VGA_DIS85
CONFIG085 CONFIG185 CONFIG285
BIOS_ROM_EN85 GPIO5_AC_BATT85
GPIO21_BB_EN85
VGA_RST#
PIN GPIO0 GPIO1TX_DEEMPH_EN GPIO2BIF_GEN2_EN_A 0 GPIO5GPIO5_AC_BATT GPIO8 RESERVED
GPIO[13:11]ROMIDCFG[2:0]
GPIO21 RESERVED
GPIO_22_ROMCSB
V2SYNC
H2SYNC 0
GENERICC 0RSVD
HSYNC X VSYNC XAUD[0]
PX
PX
R8301 3KR2J-2-GP
R8301 3KR2J-2-GP
1 2
PX
PX
R8302 3KR2J-2-GP
R8302 3KR2J-2-GP
1 2
PX
PX
R8303 10KR2J-3-GP
R8303 10KR2J-3-GP
1 2
R8304 10KR2J-3-GP
R8304 10KR2J-3-GP
1 2
DY
DY
R8305 10KR2J-3-GP
R8305 10KR2J-3-GP
1 2
DY
DY
PX
PX
R8306 10KR2J-3-GP
R8306 10KR2J-3-GP
1 2
R8307 10KR2J-3-GP
R8307 10KR2J-3-GP
1 2
DY
DY
R8308 10KR2J-3-GP
R8308 10KR2J-3-GP
1 2
DY
DY
R8313 10KR2J-3-GP
R8313 10KR2J-3-GP
1 2
DY
DY
R8314 10KR2J-3-GP
R8314 10KR2J-3-GP
1 2
DY
DY
R8315 10KR2J-3-GP
R8315 10KR2J-3-GP
1 2
DY
DY
dGPU mode
IGPU
IGPU with BACO
RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 3K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE
RECOMMEND
PLATFORM SETTING
X X
1 1
0 ? 0 0GPIO9
XXX
0
X
X
0
0
0
0 0 1 (256MB)
0
0
0
0
0
1
1
3D3V_VGA_S0
R8324 10KR2J-3-GP
R8324 10KR2J-3-GP
JTAG_TMS_VGA85
JTAG_TRST#_VGA85
TESTEN84
JTAG_TCK_VGA20,85
TESTEN Vancouver need to 5.1K ohm Mannhatton need to 1K ohm
1 2
DY
DY
R8322 10KR2J-3-GP
R8322 10KR2J-3-GP
1 2
DY
DY
R8326 10KR2J-3-GP
R8326 10KR2J-3-GP
PX
PX
R8327 5K11R2F-L1-GP
R8327 5K11R2F-L1-GP
R8323 10KR2J-3-GP
R8323 10KR2J-3-GP
DY
DY
1 2
1 2
DY
DY
12
JTAG SIGNAL OPTION
Signal
Normal mode
Debug mode
"1"(PU)TESTEN "1"(PU)
"0"(PD) "1"(PU)JTAG_TRST#
JTAG_TCK
JTAG_TMS
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
GPU_PCIE/STRAPPING(1/5)
GPU_PCIE/STRAPPING(1/5)
GPU_PCIE/STRAPPING(1/5)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
"1"(PU)
CLK
"1"(PU)"1"(PU)
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
pilot run mode
"0"(PD)
NC
NC
NC
of
83 94
of
83 94
of
83 94
-1
-1
-1
5
3 OF 8
VGA1C
VGA1C
DDR2
C37 C35 A35 E34
G32
D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10
G13
H13 J13 H11
G10
G8 K9
K10
G9 A8 C8 E8 A6 C6 E6 A5
L18 L20
L27 N12
AG12
M12 M27
AH12
MADISON-PRO-2-GP
MADISON-PRO-2-GP
DDR2 GDDR3/GDDR5
GDDR3/GDDR5 DDR3
DDR3
DQA0_0/DQA_0 DQA0_1/DQA_1 DQA0_2/DQA_2 DQA0_3/DQA_3 DQA0_4/DQA_4 DQA0_5/DQA_5 DQA0_6/DQA_6 DQA0_7/DQA_7 DQA0_8/DQA_8 DQA0_9/DQA_9 DQA0_10/DQA_10 DQA0_11/DQA_11 DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19 DQA0_20/DQA_20 DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24 DQA0_25/DQA_25 DQA0_26/DQA_26 DQA0_27/DQA_27 DQA0_28/DQA_28 DQA0_29/DQA_29 DQA0_30/DQA_30 DQA0_31/DQA_31 DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34 DQA1_3/DQA_35 DQA1_4/DQA_36 DQA1_5/DQA_37 DQA1_6/DQA_38 DQA1_7/DQA_39 DQA1_8/DQA_40 DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46 DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49 DQA1_18/DQA_50 DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54 DQA1_23/DQA_55 DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59 DQA1_28/DQA_60 DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63
MVREFDA MVREFSA
MEM_CALRN0 MEM_CALRN1 MEM_CALRN2
MEM_CALRP1 MEM_CALRP0 MEM_CALRP2
MAA1_7/MAA_A15_BA1
MEMORY INTERFACE A
MEMORY INTERFACE A
GDDR5/DDR2/GDDR3
GDDR5/DDR2/GDDR3
EDCA0_0/QSA_0/RDQSA_0 EDCA0_1/QSA_1/RDQSA_1 EDCA0_2/QSA_2/RDQSA_2 EDCA0_3/QSA_3/RDQSA_3 EDCA1_0/QSA_4/RDQSA_4 EDCA1_1/QSA_5/RDQSA_5 EDCA1_2/QSA_6/RDQSA_6 EDCA1_3/QSA_7/RDQSA_7
DDBIA0_0/QSA_0#/WDQSA_0 DDBIA0_1/QSA_1#/WDQSA_1 DDBIA0_2/QSA_2#/WDQSA_2 DDBIA0_3/QSA_3#/WDQSA_3 DDBIA1_0/QSA_4#/WDQSA_4 DDBIA1_1/QSA_5#/WDQSA_5 DDBIA1_2/QSA_6#/WDQSA_6 DDBIA1_3/QSA_7#/WDQSA_7
MDA[0..31]88 MDB[0..31]90
MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6
D D
MDA[32..63]89
C C
B B
MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17
MDA18
MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63
MVREFDA MVREFSA
MEM_CALRN0 MEM_CALRN1 MEM_CALRN2
MEM_CALRP1 MEM_CALRP0 MEM_CALRP2
3 OF 8
DDR2
DDR2 GDDR5/GDDR3
GDDR5/GDDR3 DDR3
DDR3
MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8
MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12
MAA1_5/MAA_13_BA2 MAA1_6/MAA_14_BA0
WCKA0_0/DQMA_0
WCKA0#_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0#_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1#_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1#_1/DQMA_7
ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0#
CLKA1
CLKA1# RASA0#
RASA1# CASA0#
CASA1#
CSA0#_0 CSA0#_1
CSA1#_0 CSA1#_1
CKEA0 CKEA1
WEA0# WEA1#
MAA0_8 MAA1_8
GDDR5
GDDR5
PX
PX
4
G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17
A32 C32 D23 E22 C14 A14 E10 D9
C34 D29 D25 E20 E16 E12 J10 D7
A34 E30 E26 C20 C16 C12 J11 F8
J21 G19
H27 G27
J14 H14
K23 K19
K20 K17
K24 K27
M13 K16
K21 J20
K26 L15
H23 J19
MAA0 88,89 MAA1 88,89 MAA2 88,89 MAA3 88,89 MAA4 88,89 MAA5 88,89 MAA6 88,89 MAA7 88,89 MAA8 88,89 MAA9 88,89 MAA10 88,89 MAA11 88,89 MAA12 88,89 A_BA2 88,89 A_BA0 88,89 A_BA1 88,89
DQMA0 88 DQMA1 88 DQMA2 88 DQMA3 88 DQMA4 89 DQMA5 89 DQMA6 89 DQMA7 89
QSAP_0 88 QSAP_1 88 QSAP_2 88 QSAP_3 88 QSAP_4 89 QSAP_5 89 QSAP_6 89 QSAP_7 89
QSAN_0 88 QSAN_1 88 QSAN_2 88 QSAN_3 88 QSAN_4 89 QSAN_5 89 QSAN_6 89 QSAN_7 89
ODTA0 88 ODTA1 89
CLKA0 88 CLKA0# 88
CLKA1 89 CLKA1# 89
RASA0# 88 RASA1# 89
CASA0# 88 CASA1# 89
CSA0#_0 88
CSA1#_0 89
CKEA0 88 CKEA1 89
WEA0# 88 WEA1# 89
MDB[32..63]91
TESTEN83
1
23
4
MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8
MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63
MVREFDB MVREFSB
CLKTESTA
CLKTESTB
DY
DY
RN8401
RN8401 SRN4K7J-8-GP
SRN4K7J-8-GP
3
VGA1D
VGA1D
C5
DQB0_0/DQB_0
C3
DQB0_1/DQB_1
E3
DQB0_2/DQB_2
E1
DQB0_3/DQB_3
F1
DQB0_4/DQB_4
F3
DQB0_5/DQB_5
F5
DQB0_6/DQB_6
G4
DQB0_7/DQB_7
H5
DQB0_8/DQB_8
H6
DQB0_9/DQB_9
J4
DQB0_10/DQB_10
K6
DQB0_11/DQB_11
K5
DQB0_12/DQB_12
L4
DQB0_13/DQB_13
M6
DQB0_14/DQB_14
M1
DQB0_15/DQB_15
M3
DQB0_16/DQB_16
M5
DQB0_17/DQB_17
N4
DQB0_18/DQB_18
P6
DQB0_19/DQB_19
P5
DQB0_20/DQB_20
R4
DQB0_21/DQB_21
T6
DQB0_22/DQB_22
T1
DQB0_23/DQB_23
U4
DQB0_24/DQB_24
V6
DQB0_25/DQB_25
V1
DQB0_26/DQB_26
V3
DQB0_27/DQB_27
Y6
DQB0_28/DQB_28
Y1
DQB0_29/DQB_29
Y3
DQB0_30/DQB_30
Y5
DQB0_31/DQB_31
AA4
DQB1_0/DQB_32
AB6
DQB1_1/DQB_33
AB1
DQB1_2/DQB_34
AB3
DQB1_3/DQB_35
AD6
DQB1_4/DQB_36
AD1
DQB1_5/DQB_37
AD3
DQB1_6/DQB_38
AD5
DQB1_7/DQB_39
AF1
DQB1_8/DQB_40
AF3
DQB1_9/DQB_41
AF6
DQB1_10/DQB_42
AG4
DQB1_11/DQB_43
AH5
DQB1_12/DQB_44
AH6
DQB1_13/DQB_45
AJ4
DQB1_14/DQB_46
AK3
DQB1_15/DQB_47
AF8
DQB1_16/DQB_48
AF9
DQB1_17/DQB_49
AG8
DQB1_18/DQB_50
AG7
DQB1_19/DQB_51
AK9
DQB1_20/DQB_52
AL7
DQB1_21/DQB_53
AM8
DQB1_22/DQB_54
AM7
DQB1_23/DQB_55
AK1
DQB1_24/DQB_56
AL4
DQB1_25/DQB_57
AM6
DQB1_26/DQB_58
AM1
DQB1_27/DQB_59
AN4
DQB1_28/DQB_60
AP3
DQB1_29/DQB_61
AP1
DQB1_30/DQB_62
AP5
DQB1_31/DQB_63
Y12
MVREFDB
AA12
MVREFSB
AD28
TESTEN
AK10
CLKTESTA
AL10
CLKTESTB
MADISON-PRO-2-GP
MADISON-PRO-2-GP
DDR2
DDR2 GDDR3/GDDR5
GDDR3/GDDR5 DDR3
DDR3
4 OF 8
4 OF 8
DDR2
DDR2 GDDR5/GDDR3
GDDR5/GDDR3 DDR3
DDR3
MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8
MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12
WCKB0_0/DQMB_0
WCKB0#_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0#_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1#_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1#_1/DQMB_7
MEMORY INTERFACE B
MEMORY INTERFACE B
GDDR5/DDR2/GDDR3
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0 EDCB0_1/QSB_1/RDQSB_1 EDCB0_2/QSB_2/RDQSB_2 EDCB0_3/QSB_3/RDQSB_3 EDCB1_0/QSB_4/RDQSB_4 EDCB1_1/QSB_5/RDQSB_5 EDCB1_2/QSB_6/RDQSB_6 EDCB1_3/QSB_7/RDQSB_7
DDBIB0_0/QSB_0#/WDQSB_0 DDBIB0_1/QSB_1#/WDQSB_1 DDBIB0_2/QSB_2#/WDQSB_2 DDBIB0_3/QSB_3#/WDQSB_3 DDBIB1_0/QSB_4#/WDQSB_4 DDBIB1_1/QSB_5#/WDQSB_5 DDBIB1_2/QSB_6#/WDQSB_6 DDBIB1_3/QSB_7#/WDQSB_7
ADBIB0/ODTB0 ADBIB1/ODTB1
GDDR5
GDDR5
PX
PX
MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1
CLKB0
CLKB0#
CLKB1
CLKB1# RASB0#
RASB1# CASB0#
CASB1#
CSB0#_0 CSB0#_1
CSB1#_0 CSB1#_1
CKEB0 CKEB1
WEB0# WEB1#
MAB0_8 MAB1_8
DRAM_RST#
P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9
H3 H1 T3 T5 AE4 AF5 AK6 AK5
F6 K3 P3 V5 AB5 AH1 AJ9 AM5
G7 K1 P1 W4 AC4 AH3 AJ8 AM3
T7 W7
L9 L8
AD8 AD7
T10 Y10
W10 AA10
P10 L10
AD10 AC10
U10 AA11
N10 AB11
T8 W8
AH11
DRAM_RST
2
MAB0 90,91 MAB1 90,91 MAB2 90,91 MAB3 90,91 MAB4 90,91 MAB5 90,91 MAB6 90,91 MAB7 90,91 MAB8 90,91 MAB9 90,91 MAB10 90,91 MAB11 90,91 MAB12 90,91 B_BA2 90,91 B_BA0 90,91 B_BA1 90,91
DQMB0 90 DQMB1 90 DQMB2 90 DQMB3 90 DQMB4 91 DQMB5 91 DQMB6 91 DQMB7 91
QSBP_0 90 QSBP_1 90 QSBP_2 90 QSBP_3 90 QSBP_4 91 QSBP_5 91 QSBP_6 91 QSBP_7 91
QSBN_0 90 QSBN_1 90 QSBN_2 90 QSBN_3 90 QSBN_4 91 QSBN_5 91 QSBN_6 91 QSBN_7 91
ODTB0 90 ODTB1 91
CLKB0 90 CLKB0# 90
CLKB1 91 CLKB1# 91
RASB0# 90 RASB1# 91
CASB0# 90 CASB1# 91
CSB0#_0 90
CSB1#_0 91
CKEB0 90 CKEB1 91
WEB0# 90 WEB1# 91
MAB13 90,91MAA13 88,89
PX
PX
R8418 10R2J-2-GP
R8418 10R2J-2-GP
1 2
12
PX
PX
R8420
R8420 5K1R2J-4-GP
5K1R2J-4-GP
Vancouver
Mannhatton
1D5V_VGA_S0
12
DY
DY
R8401
R8401 2K2R2J-2-GP
2K2R2J-2-GP
PX
PX
R8402 51R2J-2-GP
R8402 51R2J-2-GP
1 2
PX
PX
12
C8401
C8401 SC120P50V2JN-1GP
SC120P50V2JN-1GP
DY
DY
R8419
R8419 0R2J-2-GP
0R2J-2-GP
1 2
1
MEM_RST 88,89,90,91
This basic topology should be used for DRAM_RST for
**
PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC
Madison: MEM_CALRP[0,2] signals are used. Park: MEM_CALRP1 and MEM_CALRN1 are used
1D5V_VGA_S0
PX
PX
R8403
R8403
PX
PX
R8405
R8405
PX
PX
R8406
R8406
A A
1 2
1 2
1 2
MEM_CALRN0
243R2F-2-GP
243R2F-2-GP
MEM_CALRN1
243R2F-2-GP
243R2F-2-GP
MEM_CALRN2
243R2F-2-GP
243R2F-2-GP
5
PX
PX
R8407
R8407
PX
PX
R8408
R8408
PX
PX
R8409
R8409
1 2
1 2
1 2
MEM_CALRP1
243R2F-2-GP
243R2F-2-GP
MEM_CALRP0
243R2F-2-GP
243R2F-2-GP
MEM_CALRP2
243R2F-2-GP
243R2F-2-GP
DDR3/GDDR3 Memory Stuff Option(Mad/Park)
12
PX
PX
Ra Ra
R8410
R8410 40D2R2F-GP
40D2R2F-GP
12
PX
PX
R8414
R8414
Rb Rb RbRb
100R2F-L1-GP-U
100R2F-L1-GP-U
MVDDQ
Ra
Rb
4
GDDR5
1.5V
40.2R
100R
PX
PX
12
C8402
C8402 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
GDDR3
1.8V/1.5V
40.2R
100R
12
PX
PX
R8411
R8411 40D2R2F-GP
40D2R2F-GP
MVREFSAMVREFDA
12
PX
PX
R8415
R8415 100R2F-L1-GP-U
100R2F-L1-GP-U
DDR3
1.5V
40.2R
100R
PX
PX
12
C8403
C8403 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
PX
PX
R8412
R8412
Ra Ra
40D2R2F-GP
40D2R2F-GP
MVREFDB MVREFSB
12
PX
PX
R8416
R8416 100R2F-L1-GP-U
100R2F-L1-GP-U
3
PX
PX
12
C8404
C8404 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1D5V_VGA_S01D5 V_VGA_S01D5V_VGA_S01D5V_VGA_ S0
12
12
PX
PX
R8413
R8413 40D2R2F-GP
40D2R2F-GP
PX
PX
R8417
R8417 100R2F-L1-GP-U
100R2F-L1-GP-U
PX
PX
12
C8405
C8405 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
DDR3/GDDR3/GDDR5.These Capacitors and Resistor values are an example only. The Series R and || Cap values will depend on the DRAM load and will have to be calculated for different Memory ,DRAM Load and board to pass Reset Signal Spec.
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Ta iwan, R.O.C.
Taipei Hsien 221, Ta iwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Ta iwan, R.O.C.
GPU Memory(2/5)
GPU Memory(2/5)
GPU Memory(2/5)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
84 94
84 94
84 94
-1
-1
-1
of
of
of
5
DVPDATA [3:2:1:0] for VRAM type selection H/W strap Should provide VRAM Table for VBios request
DVPDATA [3:0] 0111 2Gbit Hynix-H5TQ2G63BFR-12C (800MHz) (Whistler-LP 2G / Seymour-XT 1G) 1111 2Gbit Samsung-K4W2G1646C-HC12 (800MHz) (Whistler-LP 2G / Seymour-XT 1G) 0011 1Gbit Hynix-H5TQ1G63BFR-12C (800MHz) (Whistler-LP 1G) 1011 1Gbit Samsung-K4W1G1646E-HC12 (800MHz) (Whistler-LP 1G)
D D
DY
DY
Q8501
Q8501 2N7002KDW-G P
2N7002KDW-G P
R8522 0R2J-2-GP
R8522 0R2J-2-GP
VGA_RST#83 PCIE_RST#27,83
3D3V_VGA_S0
PX
PX
R8520
R8520
C C
JTAG_TCK_VGA20,83
Voltage Swing:1.8V
B B
R8521
R8521 124R2F-U-GP
124R2F-U-GP
1D8V_VGA_S0
12
DY
DY
R8508 0R2J-2-GP
R8508 0R2J-2-GP
12
DY
DY
GPIO17_VGA
12
10KR2J-3-GP
10KR2J-3-GP
DY
DY
1 2
PX
PX
L8501
L8501
1 2
BLM18PG471SN1D-GP
BLM18PG471SN1D-GP
PLACE VREFG DIVIDER AND CAP CLOSE TO ASI C
A A
PX
PX
C8524
C8524
12
SC10P50V2JN-4GP
SC10P50V2JN-4GP
XTALIN
XTALIN
5
THERMTRIP_VGA
THERMTRIP_R
5
6
123 4
Q5801_2
DY
DY
12
C8526
C8526 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
DY
DY
R8519
R8519 150R2F-1-GP
150R2F-1-GP
(1.8V@75mA DPLL_PVDD)
DY
DY
12
C8505
C8505 SC4D7U6D3V3KX-G P
SC4D7U6D3V3KX-G P
1V_VGA_S0
PX
PX
L8506
L8506 BLM18PG471SN1D-GP
BLM18PG471SN1D-GP
PX
PX
R8504
R8504
1 2
PX
PX
X8501
X8501
1 2
XTAL-27MHZ-65-GP-U
XTAL-27MHZ-65-GP-U
12
DY
DY
R8523
R8523 10KR2J-3-GP
10KR2J-3-GP
H_THERMTRIP# 5,22,36
PX
PX
12
C8515
C8515 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
1D8V_VGA_S0
10MR2J-L-GP
10MR2J-L-GP
XTALOUT
PX
PX
12
C8516
C8516 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
(1.0V@125mA DPLL_VDDC) (1.1V@150mA DPLL_VDDC For M96/M92)
12
12
DY
DY
C8517
C8517
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
L8504
L8504
PX
PX
1 2
BLM15BD121SS1D-GP
BLM15BD121SS1D-GP
PX
PX
C8525
C8525
12
SC10P50V2JN-4GP
SC10P50V2JN-4GP
PX
PX
C8518
C8518
MEM_ID0 MEM_ID1 MEM_ID2 MEM_ID3
TX_DEEMPH_EN83 BIF_GEN2_EN_A83 SMBD_THERM27,28 SMBC_THERM27,28 GPIO5_AC_BATT83
DPLL_PVDD
12
PX
PX
C8519
C8519
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
12
C8520
C8520 SC4D7U6D3V3KX-G P
SC4D7U6D3V3KX-G P
12
12
TX_PWRS_ENB83
4
VGA1B
VGA1B
TXCAP_DPA3P
PX
PX
DPA
DPA
DPB
DPB
DPC
DPC
DPD
DPD
DAC1
DAC1
DAC2
DAC2
DDC/AUX
DDC/AUX
DDCCLK_AUX3P
DDCDATA_AUX3N
DDCCLK_AUX4P
DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N
DDCCLK_AUX7P
DDCDATA_AUX7N
TXCAM_DPA3N
TXCBP_DPB3P TXCBM_DPB3N
TXCCP_DPC3P
TXCCM_DPC3N
TXCDP_DPD3P
TXCDM_DPD3N
1D8V_VGA_S0
12
12
SAMSUNG
SAMSUNG
VRAM_2G
VRAM_2G
R8513
R8513
R8511
R8511
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
12
Hynix
Hynix
VRAM_1G
VRAM_1G
R8518
R8518
R8512
R8512
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
RN8501 SRN0J-6-GP
RN8501 SRN0J-6-GP
GPIO8_ROMSO83
VGA_DIS83 CONFIG083
CONFIG183 CONFIG283
PWRCNTL_092
PWRCNTL_192
GPIO21_BB_EN83 BIOS_ROM_EN83 PEG_CLKREQ#20
JTAG_TRST#_VGA83
JTAG_TCK_VGA20,83 JTAG_TMS_VGA83
1D8V_VGA_S0
12
PX
PX
R8515
R8515 499R2F-2-GP
499R2F-2-GP
12
PX
PX
PX
PX
12
R8516
R8516
C8514
C8514
249R2F-GP
249R2F-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DPLL_VDDC
TP8516 TPAD14- GPTP8516 TPAD14-G P
TP8517TP 8517 TP8529TP 8529
TP8511 TPAD14- GPTP8511 TPAD14-G P
(1.8V@20mA TSVDD)
PX
PX
12
C8521
C8521 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
Clock Input Configuraiton - GDDR3/DDR3 a) 27MHz crystal connected to XTALIN or XTALOUT or b) 27MHz (1.8V) oscillator connected to XTALIN or c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only)
4
PX
PX
R8505
R8505 10KR2J-3-GP
10KR2J-3-GP
12
DY
DY
R8510
R8510 10KR2J-3-GP
10KR2J-3-GP
PX
PX
1 2 3
TP8506TP 8506 TP8502TP 8502 TP8507TP 8507
TP8501TP 8501
TP8503TP 8503
TP8512TP 8512 TP8513TP 8513 TP8509TP 8509 TP8514TP 8514 TP8515TP 8515
TP8521TP 8521
GPU_VREFG
DPLL_PVDD
1
1 1
1
12
12
PX
PX
R8501
R8501 10KR2J-3-GP
10KR2J-3-GP
12
DY
DY
R8503
R8503 10KR2J-3-GP
10KR2J-3-GP
GPIO_VGA_03_DATA
4
GPIO_VGA_04_CLK
VPIO14_VGA
1
GPIO16_SSIN
1
GPIO17_VGA
GPIO18_VGA
1
THERMTRIP_VGA
JTAG_TDI_VGA
1
JTAG_TDO_VGA
1
GENERICC
1
GENERICD
1
GENERICE_HPD4
1
GENERICF
1
GENERICG
1
HDMI_HPD_GPU
1
VGA_DPLUS VGA_DMINUS
VGA_TS_FDO
TSVDD
PX
PX
C8522
C8522 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
XTALIN XTALOUT
XO_IN
AR8
DVPCNTL_MVP_0
AU8
DVPCNTL_MVP_1
AP8
DVPCNTL_0
AW8
DVPCNTL_1
AR3
DVPCNTL_2
AR1
DVPCLK
AU1
DVPDATA_0
AU3
DVPDATA_1
AW3
DVPDATA_2
AP6
DVPDATA_3
AW5
DVPDATA_4
AU5
DVPDATA_5
AR6
DVPDATA_6
AW6
DVPDATA_7
AU6
DVPDATA_8
AT7
DVPDATA_9
AV7
DVPDATA_10
AN7
DVPDATA_11
AV9
DVPDATA_12
AT9
DVPDATA_13
AR10
DVPDATA_14
AW10
DVPDATA_15
AU10
DVPDATA_16
AP10
DVPDATA_17
AV11
DVPDATA_18
AT11
DVPDATA_19
AR12
DVPDATA_20
AW12
DVPDATA_21
AU12
DVPDATA_22
AP12
DVPDATA_23
AK26
SCL
AJ26
SDA
GENERAL PURPOSE I/O
GENERAL PURPOSE I/O
AH20
GPIO_0
AH18
GPIO_1
AN16
GPIO_2
AH23
GPIO_3_SMBDATA
AJ23
GPIO_4_SMBCLK
AH17
GPIO_5_AC_BATT
AJ17
GPIO_6
AK17
GPIO_7_BLON
AJ13
GPIO_8_ROMSO
AH15
GPIO_9_ROMSI
AJ16
GPIO_10_ROMSCK
AK16
GPIO_11
AL16
GPIO_12
AM16
GPIO_13
AM14
GPIO_14_HPD2
AM13
GPIO_15_PWRCNTL_0
AK14
GPIO_16_SSIN
AG30
GPIO_17_THERMAL_INT
AN14
GPIO_18_HPD3
AM17
GPIO_19_CTF
AL13
GPIO_20_PWRCNTL_1
AJ14
GPIO_21_BB_EN
AK13
GPIO_22_ROMCS#
AN13
GPIO_23_CLKREQ#
AM23
JTAG_TRST#
AN23
JTAG_TDI
AK23
JTAG_TCK
AL24
JTAG_TMS
AM24
JTAG_TDO
AJ19
GENERICA
AK19
GENERICB
AJ20
GENERICC
AK20
GENERICD
AJ24
GENERICE_HPD4
AH26
GENERICF
AH24
GENERICG
AK24
HPD1
AH13
VREFG
AM32
DPLL_PVDD
AN32
DPLL_PVSS
AN31
DPLL_VDDC
AV33
XTALIN
AU34
XTALOUT
AW34
XO_IN
AW35
XO_IN2
AF29
DPLUS
AG29
DMINUS
AK32
TS_FDO
AL31
TS_A
AJ32
TSVDD
AJ33
TSVSS
MADISON-PRO-2-GP
MADISON-PRO-2-GP
MUTI GFX
MUTI GFX
I2C
I2C
PLL/CLOCK
PLL/CLOCK
THERMAL
THERMAL
2 OF 8
2 OF 8
TX0P_DPA2P
TX0M_DPA2N
TX1P_DPA1P
TX1M_DPA1N
TX2P_DPA0P
TX2M_DPA0N
TX3P_DPB2P
TX3M_DPB2N
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
TX0P_DPC2P TX0M_DPC2N
TX1P_DPC1P TX1M_DPC1N
TX2P_DPC0P TX2M_DPC0N
TX3P_DPD2P TX3M_DPD2N
TX4P_DPD1P TX4M_DPD1N
TX5P_DPD0P TX5M_DPD0N
HSYNC VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
COMP
H2SYNC V2SYNC
VDD2DI
VSS2DI
A2VDD
A2VDDQ
A2VSSQ
R2SET
DDC1CLK
DDC1DATA
AUX1P AUX1N
DDC2CLK
DDC2DATA
AUX2P AUX2N
DDC6CLK
DDC6DATA
3
AU24 AV23
AT25 AR24
AU26 AV25
AT27 AR26
AR30 AT29
AV31 AU30
AR32 AT31
AT33 AU32
AU14 AV13
AT15 AR14
AU16 AV15
AT17 AR16
AU20 AT19
AT21 AR20
AU22 AV21
AT23 AR22
AD39
R
AD37
R#
AE36
G
AD35
G#
AF37
B
AE38
B#
AC36 AC38
GPU_RSET
AB34 AD34
AE34 AC33
AC34
AC30
R2
AC31
R2#
AD30
G2
AD31
G2#
AF30
B2
AF31
B2#
AC32
C
AD32
Y
AF32
AD29 AC29
AG31 AG32
AG33 AD33 AF33
R2SET
AA29
AM26 AN26
AM27 AL27
AM19 AL19
AN20 AM20
AL30 AM30
AL29 AM29
AN21 AM21
AJ30 AJ31
AK30 AK29
3
R8526 0R0402-PADR8526 0R0402-PAD
VGA_CRT_RED
VGA_CRT_GREEN
VGA_CRT_BLUE
+3.3V tolerant
VGA_CRT_HSYNC VGA_CRT_VSYNC
PX
PX
R8514 499R2F- 2-GP
R8514 499R2F- 2-GP
1 2
AVDD
VDD1DI
VDD2DI
1 2
R8517
R8517
1 2
715R2F-GP
715R2F-GP
PX
PX
VGA_CRT_DDCCLK VGA_CRT_DDCDATA
DDC1/DDC2/DDC6 have 5V-tolerant
1
1
1
1 1
AVSSQ
A2VDD
2
LVDS Interface
VGA1G
VGA1G
LVDS CONTROL
LVDS CONTROL
LVTMDP
LVTMDP
PX
PX
MADISON-PRO-2-GP
SRN150F-1-GP
SRN150F-1-GP
R8506
R8506
1 2
0R0402-PAD
0R0402-PAD
PX
PX
RN8502
RN8502
1 2 3 4 5
MADISON-PRO-2-GP
8 7 6
2
TP8522TP 8522
TP8523TP 8523
TP8524TP 8524
VGA_CRT_RED
TP8525TP 8525
VGA_CRT_GREEN
TP8526TP 8526
VGA_CRT_BLUE
AVSSQ
A2VDDQ
TP8527TP 8527
1
TP8528TP 8528
1
7 OF 8
7 OF 8
VARY_BL
DIGON
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
TXOUT_U3P
TXOUT_U3N
TXCLK_LP_DPE3P TXCLK_LN_DPE3N
TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N
TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N
TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N
TXOUT_L3P TXOUT_L3N
VGA_LBKLT_CTL
AK27
VGA_LCDVDD_EN
AJ27
AK35 AL36
AJ38 AK37
AH35 AJ36
AG38 AH37
AF35 AG36
AP34 AR34
AW37 AU35
AR37 AU39
AP35 AR35
AN36 AP37
1D8V_VGA_S0
R8502 0R0402-PA DR8502 0R0402-PAD
R8524 0R0402-PA DR8524 0R0402-PAD
R8507 0R0402-PA DR8507 0R0402-PAD
R8525 0R0402-PA DR8525 0R0402-PAD
3D3V_VGA_S0
(3.3V@130mA A2VDD)
R8509 0R0402-PA DR8509 0R0402-PAD
1
23
PX
PX
RN8503
RN8503 SRN10KJ-5-GP
SRN10KJ-5-GP
4
(1.8V@65mA AVDD)
1 2
(1.8V@100mA VDD1DI)
1 2
(1.8V@50mA VDD2DI)
1 2
(1.8V@1.5mA A2VDDQ)
1 2
1 2
AVDD
PX
PX
12
C8503
C8503 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AVSSQ
VDD1DI
PX
PX
12
C8506
C8506 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VDD2DI
DY
DY
12
C8508
C8508 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
A2VDDQ
DY
DY
12
C8510
C8510 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
A2VDD
DY
DY
12
C8513
C8513 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
GPU_DP/LVDS/CRT/GPIO(3/5)
GPU_DP/LVDS/CRT/GPIO(3/5)
GPU_DP/LVDS/CRT/GPIO(3/5)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A2
A2
A2
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
1
Wistron Corporat ion
Wistron Corporat ion
Wistron Corporat ion
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
85 94
85 94
85 94
of
of
of
-1
-1
-1
1D5V_VGA_S0
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
D D
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C C
B B
A A
For DDR3/GDDR5, MVDDQ = 1.5V
12
12
PX
PX
PX
PX
C8604
C8604
C8601
C8601
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
PX
PX
PX
PX
C8618
C8618
C8619
C8619
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8603
C8603
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1D8V_VGA_S0
5
12
PX
PX
C8605
C8605
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8620
C8620
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8635
C8635
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
PX
PX
L8601
L8601 BLM15BD121SS1D-GP
BLM15BD121SS1D-GP
PX
PX
L8602
L8602 BLM15BD121SS1D-GP
BLM15BD121SS1D-GP
(For M97, Broadway, Madis on and Park SPV10 = 1.0V)
1V_VGA_S0 SPV10
PX
PX
L8605
L8605 BLM15BD121SS1D-GP
BLM15BD121SS1D-GP
12
12
PX
PX
C8606
C8606
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8621
C8621
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
1 2
PX
PX
L8603
L8603
1 2
BLM15BD121SS1D-GP
BLM15BD121SS1D-GP
PX
PX
L8604
L8604
1 2
BLM15BD121SS1D-GP
BLM15BD121SS1D-GP
(M97, Broadway and Madison: 1.8V@150mA MPV18) (Park: 1.8V@75mA MPV18)
1 2
5
12
PX
PX
PX
PX
C8607
C8607
C8608
C8608
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
PX
PX
PX
PX
C8622
C8622
C8623
C8623
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
(1.8V@110mA VDD_CT)
PX
PX
12
C8650
C8650 SC4D7U6D3V3KX-G P
SC4D7U6D3V3KX-G P
3D3V_VGA_S0
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
(1.8V@40mA PCIE_PVDD)
12
PX
PX
C8675
C8675
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
(120mA SPV10)
12
PX
PX
C8678
C8678
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
(1.8V@75mA SPV18)
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
PX
PX
C8691
C8691
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
PX
PX
C8688
C8688
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8665
C8665
12
PX
PX
C8676
C8676
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
12
PX
PX
C8692
C8692
PX
PX
C8609
C8609
PX
PX
C8624
C8624
PX
PX
C8679
C8679
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PX
PX
12
C8652
C8652 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8666
C8666
12
PX
PX
C8677
C8677
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SPV18
PX
PX
C8689
C8689
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
MPV18
12
PX
PX
C8664
C8664
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
PX
PX
C8610
C8610
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8625
C8625
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
PX
PX
C8667
C8667
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PCIE_PVDD
TP8602 TPAD14- GPTP8602 TPAD14-G P
PX
PX
C8680
C8680
12
PX
PX
C8690
C8690
12
PX
PX
C8611
C8611
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8626
C8626
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PX
PX
C8654
C8654 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8668
C8668
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8673
C8673
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SPV18
VGA_SENSE92
FB_VDDCI
1
GND_SENSE92
PX
PX
C8612
C8612
PX
PX
C8627
C8627
VDDC_CT
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
MPV18
4
VGA1E
VGA1E
MEM I/O
MEM I/O
AC7
VDDR1
AD11
VDDR1
AF7
VDDR1
AG10
VDDR1
AJ7
VDDR1
AK8
VDDR1
AL9
VDDR1
G11
VDDR1
G14
VDDR1
G17
VDDR1
G20
VDDR1
G23
VDDR1
G26
VDDR1
G29
VDDR1
H10
VDDR1
J7
VDDR1
J9
VDDR1
K11
VDDR1
K13
VDDR1
K8
VDDR1
L12
VDDR1
L16
VDDR1
L21
VDDR1
L23
VDDR1
L26
VDDR1
L7
VDDR1
M11
VDDR1
N11
VDDR1
P7
VDDR1
R11
VDDR1
U11
VDDR1
U7
VDDR1
Y11
VDDR1
Y7
VDDR1
LEVEL
LEVEL TRANSLATION
TRANSLATION
AF26
VDD_CT
AF27
VDD_CT
AG26
VDD_CT
AG27
VDD_CT
I/O
I/O
AF23
VDDR3
AF24
VDDR3
AG23
VDDR3
AG24
VDDR3
AF13
VDDR4
AF15
VDDR4
AG13
VDDR4
AG15
VDDR4
AD12
VDDR4
AF11
VDDR4
AF12
VDDR4
AG11
VDDR4
12
PX
PX
C8674
C8674
M20
NC_VDDRHA
M21
NC_VSSRHA
V12
NC_VDDRHB
U12
NC_VSSRHB
PLL
PLL
AB37
PCIE_PVDD
H7
MPV18
H8
MPV18
AM10
SPV18
AN9
SPV10
AN10
SPVSS
VOLTAGE
VOLTAGE SENESE
SENESE
AF28
FB_VDDC
AG28
FB_VDDCI
AH29
FB_GND
MADISON-PRO-2-GP
MADISON-PRO-2-GP
4
PX
PX
PCIE
PCIE
PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR
PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC
CORE
CORE
VDDC/BIF_VDDC
VDDC/BIF_VDDC
ISOLATED
ISOLATED CORE I/O
CORE I/O
5 OF 8
5 OF 8
AA31 AA32 AA33 AA34 V28 W29 W30 Y31
G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28
AA15
VDDC
AA17
VDDC
AA20
VDDC
AA22
VDDC
AA24
VDDC
AA27
VDDC
AB16
VDDC
AB18
VDDC
AB21
VDDC
AB23
VDDC
AB26
VDDC
AB28
VDDC
AC17
VDDC
AC20
VDDC
AC22
VDDC
AC24
POWER
POWER
VDDC
AC27
VDDC
AD18
VDDC
AD21
VDDC
AD23
VDDC
AD26
VDDC
AF17
VDDC
AF20
VDDC
AF22
VDDC
AG16
VDDC
AG18
VDDC
AG21
VDDC
AH22
VDDC
AH27
VDDC
AH28
VDDC
M26
VDDC
N24
VDDC
N27 R18
VDDC
R21
VDDC
R23
VDDC
R26
VDDC
T17
VDDC
T20
VDDC
T22
VDDC
T24
VDDC
T27 U16
VDDC
U18
VDDC
U21
VDDC
U23
VDDC
U26
VDDC
V17
VDDC
V20
VDDC
V22
VDDC
V24
VDDC
V27
VDDC
Y16
VDDC
Y18
VDDC
Y21
VDDC
Y23
VDDC
Y26
VDDC
Y28
VDDC
AA13
VDDCI
AB13
VDDCI
AC12
VDDCI
AC15
VDDCI
AD13
VDDCI
AD16
VDDCI
M15
VDDCI
M16
VDDCI
M18
VDDCI
M23
VDDCI
N13
VDDCI
N15
VDDCI
N17
VDDCI
N20
VDDCI
N22
VDDCI
R12
VDDCI
R13
VDDCI
R16
VDDCI
T12
VDDCI
T15
VDDCI
V15
VDDCI
Y13
VDDCI
(1.8V@504mA PCIE_VDDR)
12
12
PX
PX
C8613
C8613
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
(1.0V@1920mA PCIE_VDDC)
12
12
PX
PX
C8628
C8628
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8636
C8636
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
PX
PX
C8645
C8645
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
BIF_VDDC
55mA in BACO mode
PX
PX
12
C8651
C8651 SC22U4V3MX-GP
SC22U4V3MX-GP
(GDDR3/DDR3 1.12V@4A VDDCI)
(GDDR5 1.12V@16A VDDCI)
12
PX
PX
C8681
C8681
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
PX
PX
C8655
C8655
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
PX
PX
C8614
C8614
C8615
C8615
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
PX
PX
C8629
C8629
C8630
C8630
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8637
C8637
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
PX
PX
C8646
C8646
C8647
C8647
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PX_EN Mode
0 Normal
BACO1
12
12
PX
PX
PX
PX
C8682
C8682
C8683
C8683
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
PX
PX
PX
PX
C8656
C8656
C8657
C8657
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
3
1D8V_VGA_S0
12
12
PX
PX
PX
PX
C8617
C8617
C8616
C8616
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
PX
PX
C8639
C8639
12
12
PX
PX
C8632
C8632
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8640
C8640
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
PX
PX
C8649
C8649
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
PX
PX
C8631
C8631
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
PX
PX
C8638
C8638
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8648
C8648
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
BIF_VDDC
VGA_Core
1V_VGA
12
12
PX
PX
PX
PX
C8684
C8684
C8685
C8685
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8658
C8658
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8659
C8659
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PX
PX
C8633
C8633
PX
PX
C8669
C8669
12
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PX
PX
C8686
C8686
PX
PX
C8660
C8660
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PX
PX
C8641
C8641
SC22U4V3MX-GP
SC22U4V3MX-GP
VGA_CORE
1V_VGA_S0
12
12
PX
PX
PX
PX
C8602
C8602
C8634
C8634
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
VGA_CORE
12
12
PX
PX
C8671
C8671
12
PX
PX
PX
PX
C8643
C8643
C8644
C8644
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C8672
C8672
SC22U4V3MX-GP
SC22U4V3MX-GP
BIF_VDDC
3D3V_VGA_S0
PX
PX
C8642
C8642
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
PX
PX
C8670
C8670
SC22U4V3MX-GP
SC22U4V3MX-GP
BACO mode
12
PX
PX
C8687
C8687
SC22U4V3MX-GP
SC22U4V3MX-GP
12
PX
PX
C8661
C8661
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VGA_CORE
12
12
PX
PX
PX
PX
C8663
C8663
C8662
C8662
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
PX
PX
R8603
R8603
1KR2J-1-GP
1KR2J-1-GP
2
U8601
U8601
AO3400A-GP
AO3400A-GP
DS
PX
PX
G
84.03400.B37
84.03400.B37
PX_EN87
1D5V_VGA_PWOK
2
BIF_VDDC_CORE
PX_EN##
1D5V_VGA_PWOK83
8209A_EN/DEM_VGA92,93
G
1D5V_VGA_S0
84.03400.B37
84.03400.B37
PX
PX
Q8601
Q8601
S
2N7002K-2-GP
2N7002K-2-GP
1 2
DY
DY
R8608
R8608 2K2R2J-2-GP
2K2R2J-2-GP
D S
DGPU_PWROK22,92,93
1
PX
PX
U8602
12
PX
PX
R8604
R8604 1KR2J-1-GP
1KR2J-1-GP
PX
PX
1D5V_VGA_PWOK _R
3D3V_VGA_S0
5
VCC
4
Y
DY
DY
Q8603
Q8603
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
U8602
AO3418-GP
AO3418-GP
BIF_VDDC_1V
DS
84.03418.031
84.03418.031
G
PX_EN#
1D5V_VGA_PWOK _R
PX_EN##
3D3V_VGA_S03D3V_S5
12
DY
DY
R8606
R8606 10KR2J-3-GP
10KR2J-3-GP
D
GPU_POWER(4/5)
GPU_POWER(4/5)
GPU_POWER(4/5)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
Wistron Corporat ion
Wistron Corporat ion
Wistron Corporat ion
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
U8603
U8603 AO3400A-GP
AO3400A-GP
PX
PX
G
D
DY
DY
12
C8693
C8693 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
Q8604
Q8604 MMBT3904-4-GP
MMBT3904-4-GP
BIF_VDDC
VGA_CORE 1V_VGA_S0
3D3V_VGA_S0
1 2
R8601 0R2J- 2-GP
R8601 0R2J- 2-GP
DY
DY
U8605
U8605
1
B
2
A
3
GND
74LVC1G08GW-1- GP
74LVC1G08GW-1- GP
12
DY
DY
R8607
R8607 10KR2J-3-GP
10KR2J-3-GP
C
B
E
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A2
A2
A2 Date: Sheet
Date: Sheet
Date: Sheet
U8604
U8604 AO3418-GP
AO3418-GP
D S
84.03418.031
84.03418.031
PX
PX
Q8602
Q8602
6
2N7002KDW-G P
2N7002KDW-G P
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
1D5V_VGA_PWOK 83
86 94
86 94
86 94
PX
PX
G
PX_EN#
2345 1
-1
-1
-1
of
of
of
5
6 OF 8
GND
GND
6 OF 8
GND/PX_EN
VSS_MECH VSS_MECH VSS_MECH
A3
GND
A37
GND
AA16
GND
AA18
GND
AA2
GND
AA21
GND
AA23
GND
AA26
GND
AA28
GND
AA6
GND
AB12
GND
AB15
GND
AB17
GND
AB20
GND
AB22
GND
AB24
GND
AB27
GND
AC11
GND
AC13
GND
AC16
GND
AC18
GND
AC2
GND
AC21
GND
AC23
GND
AC26
GND
AC28
GND
AC6
GND
AD15
GND
AD17
GND
AD20
GND
AD22
GND
AD24
GND
AD27
GND
AD9
GND
AE2
GND
AE6
GND
AF10
GND
AF16
GND
AF18
GND
AF21
GND
AG17
GND
AG2
GND
AG20
GND
AG22
GND
AG6
GND
AG9
GND
AH21
GND
AJ10
GND
AJ11
GND
AJ2
GND
AJ28
GND
AJ6
GND
AK11
GND
AK31
GND
AK7
GND
AL11
GND
AL14
GND
AL17
GND
AL2
GND
AL20
GND
AL21 AL23
GND
AL26
GND
AL32
GND
AL6
GND
AL8
GND
AM11
GND
AM31
GND
AM9
GND
AN11
GND
AN2
GND
AN30
GND
AN6
GND
AN8
GND
AP11
GND
AP7
GND
AP9
GND
AR5
GND
B11
GND
B13
GND
B15
GND
B17
GND
B19
GND
B21
GND
B23
GND
B25
GND
B27
GND
B29
GND
B31
GND
B33
GND
B7
GND
B9
GND
C1
GND
C39
GND
E35
GND
E5
GND
F11
GND
F13
GND
VSS_MECH1
A39
VSS_MECH2
AW1
VSS_MECH3
AW39
PX
PX
PX_EN_R
R8708 0R2J-2-GP
R8708 0R2J-2-GP
1 2
12
PX
PX
R8709
R8709 10KR2J-3-GP
10KR2J-3-GP
PX_EN is tri-state before internal PWRGOOD is asserted and PERSTb is de-asserted.
TP8701TP 8701
1
TP8702TP 8702
1
TP8703TP 8703
1
VGA1F
VGA1F
AB39
PCIE_VSS
E39
PCIE_VSS
F34
PCIE_VSS
F39
PCIE_VSS
G33
PCIE_VSS
G34
PCIE_VSS
H31
PCIE_VSS
H34
PCIE_VSS
H39
PCIE_VSS
J31
PCIE_VSS
J34
PCIE_VSS
K31
PCIE_VSS
K34
PCIE_VSS
K39
PCIE_VSS
D D
C C
B B
L31
PCIE_VSS
L34
PCIE_VSS
M34
PCIE_VSS
M39
PCIE_VSS
N31
PCIE_VSS
N34
PCIE_VSS
P31
PCIE_VSS
P34
PCIE_VSS
P39
PCIE_VSS
R34
PCIE_VSS
T31
PCIE_VSS
T34
PCIE_VSS
T39
PCIE_VSS
U31
PCIE_VSS
U34
PCIE_VSS
V34
PCIE_VSS
V39
PCIE_VSS
W31
PCIE_VSS
W34
PCIE_VSS
Y34
PCIE_VSS
Y39
PCIE_VSS
F15
GND
F17
GND
F19
GND
F21
GND
F23
GND
F25
GND
F27
GND
F29
GND
F31
GND
F33
GND
F7
GND
F9
GND
G2
GND
G6
GND
H9
GND
J2
GND
J27
GND
J6
GND
J8
GND
K14
GND
K7
GND
L11
GND
L17
GND
L2
GND
L22
GND
L24
GND
L6
GND
M17
GND
M22
GND
M24
GND
N16
GND
N18
GND
N2
GND
N21
GND
N23
GND
N26
GND
N6
GND
R15
GND
R17
GND
R2
GND
R20
GND
R22
GND
R24
GND
R27
GND
R6
GND
T11
GND
T13
GND
T16
GND
T18
GND
T21
GND
T23
GND
T26
GND
U15
GND
U17
GND
U2
GND
U20
GND
U22
GND
U24
GND
U27
GND
U6
GND
V11
GND
V16
GND
V18
GND
V21
GND
V23
GND
V26
GND
W2
GND
W6
GND
Y15
GND
Y17
GND
Y20
GND
Y22
GND
Y24
GND
Y27
GND
U13
GND
V13
GND
MADISON-PRO-2-GP
MADISON-PRO-2-GP
PX
PX
4
PX_EN 86
PX
PX
1 2
R8710
R8710 0R2J-2-GP
0R2J-2-GP
1 2
R8704
R8704 0R2J-2-GP
0R2J-2-GP
PX
PX
(1.8V@130mA DPA_VDD18)
PX
PX
12
C8707
C8707 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
(1.8V@130mA DPD_VDD18)
PX
PX
12
C8719
C8719 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DPA_VDD181D8V_VGA_S0
DPD_VDD18
0831
PX
PX
12
C8708
C8708 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PX
PX
C8720
C8720 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
3
0831
DPD_VDD18
1V_VGA_S0
(1.0V@110mA DPC_VDD10)
DPD_VDD18
1V_VGA_S0
(1.0V@110mA DPD_VDD10)
R8701
R8701
PX
PX
DPCD_CALR D PAB_CALR
1 2
150R2F-1-GP
1 2
DPF_VDD10
PX
PX
C8730
C8730 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
150R2F-1-GP
DPF_VDD18
DPF_VDD10
DPF_VDD18
PX
PX
C8726
C8726 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
LVDS mode
(1.8V@200mA DPE_VDD18)
LVDS mode
(1.0V@120mA DPE_VDD10)
LVDS mode
(1.8V@200mA DPF_VDD18)
1D8V_VGA_S0
PX
PX
R8713
R8713
1 2
0R0603-PAD
0R0603-PAD
LVDS mode
(1.0V@120mA DPF_VDD10)
1V_VGA_S0
For M97/M96, DPF_VDD18 can be shared with DPE_VDD18 For M97/M96, DPF_VDD10 can be shared with DPE_VDD10 For dual link DVI using DPA AND DPB, DPA_VDDxx and DPB_VDDxx can be shared respectively
PX
PX
R8714
R8714
1 2
0R0402-PAD
0R0402-PAD
12
DPEF_CALR
PX
PX
R8705
R8705 150R2F-1-GP
150R2F-1-GP
1 2
VGA1H
VGA1H
AP20 AP21
AP13 AT13
AN17 AP16 AP17 AW14 AW16
AP22 AP23
AP14 AP15
AN19 AP18 AP19 AW20 AW22
AW18
AH34
AJ34
AL33
AM33
AN34 AP39 AR39 AU37
AF34 AG34
AK33 AK34
AF39 AH39 AK39
AL34
AM34
AM39
MADISON-PRO-2-GP
MADISON-PRO-2-GP
DPC_VDD18 DPC_VDD18
DPC_VDD10 DPC_VDD10
DPC_VSSR DPC_VSSR DPC_VSSR DPC_VSSR DPC_VSSR
DPD_VDD18 DPD_VDD18
DPD_VDD10 DPD_VDD10
DPD_VSSR DPD_VSSR DPD_VSSR DPD_VSSR DPD_VSSR
DPCD_CALR
DP E/F POWER
DP E/F POWER
DPE_VDD18 DPE_VDD18
DPE_VDD10 DPE_VDD10
DPE_VSSR DPE_VSSR DPE_VSSR DPE_VSSR
DPF_VDD18 DPF_VDD18
DPF_VDD10 DPF_VDD10
DPF_VSSR DPF_VSSR DPF_VSSR DPF_VSSR DPF_VSSR
DPEF_CALR
For dual link DVI using DPC AND DPD, DPC_VDDxx and DPD_VDDxx can be shared respectively
For dual link LVDS, DPE_VDDxx and DPF_VDDxx can be shared respectively
2
PX
PX
DP A/B POWERDP C/D POWER
DP A/B POWERDP C/D POWER
DPAB_CALR
DP PLL POWER
DP PLL POWER
8 OF 8
8 OF 8
DPA_VDD18 DPA_VDD18
DPA_VDD10 DPA_VDD10
DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR
DPB_VDD18 DPB_VDD18
DPB_VDD10 DPB_VDD10
DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR
DPA_PVDD
DPA_PVSS
DPB_PVDD
DPB_PVSS
DPC_PVDD DPC_PVSS
DPD_PVDD DPD_PVSS
DPE_PVDD
DPE_PVSS
DPF_PVDD
DPF_PVSS
DPA_VDD18
AN24 AP24
AP31 AP32
AN27 AP27 AP28 AW24 AW26
DPA_VDD18
AP25 AP26
AN33 AP33
AN29 AP29 AP30 AW30 AW32
AW28
150R2F-1-GP
150R2F-1-GP
AU28 AV27
AV29 AR28
AU18 AV17
AV19 AR18
(1.8V@20mA DPE_PVDD)
AM37 AN38
DPF_PVDD_1
AL38
0R2J-2-GP
0R2J-2-GP
AM35
DPF_PVSS
0R2J-2-GP
0R2J-2-GP
DPA_VDD10
12
C8702
C8702 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PX
PX
0831
(1.0V@110mA DPA_VDD10)
(1.0V@110mA DPB_VDD10)
PX
PX
R8703
R8703
1 2
DPA_VDD18
DPA_VDD18
DPD_VDD18
DPD_VDD18
DPF_VDD18
PX
PX
R8706
R8706
1 2
PX
PX
R8707
R8707
1 2
12
C8703
C8703 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PX
PX
0831
DPA_VDD10
(1.8V@20mA DPA_PVDD)
(1.8V@20mA DPB_PVDD)
(1.8V@20mA DPC_PVDD)
(1.8V@20mA DPD_PVDD)
(1.8V@20mA DPF_PVDD)
1
R8715
R8715
1 2
0R0402-PAD
0R0402-PAD
1V_VGA_S0
0831
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporat ion
Wistron Corporat ion
Wistron Corporat ion
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A2
A2
A2
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Taipei Hsien 221, Taiw an, R.O.C.
GPU_DPPWR/GND(5/5)
GPU_DPPWR/GND(5/5)
GPU_DPPWR/GND(5/5)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
87 94
87 94
87 94
of
of
of
-1
-1
-1
5
4
3
2
1
1D5V_VGA_S0 1D5V_VGA_S0
C8811
C8807
C8807
12
C8806
D D
C C
B B
C8806
WTL
WTL
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
CLKA084 CLKA0#84
56R2F-1-GP
56R2F-1-GP
C8802
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
C8802
12
C8809
C8809
WTL
WTL
WTL
WTL
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
R8804
R8804
WTL
WTL
GPU_CLKA0_T
12
C8808
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
R8803
R8803
56R2F-1-GP
56R2F-1-GP
WTL
WTL
12
WTL
WTL
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
WTL
WTL
C8810
C8810
12
WTL
WTL
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
R8801 243R2F-2-GP
R8801 243R2F-2-GP
MAA1084,89 MAA1184,89 MAA1284,89 MAA1384,89
A_BA084,89 A_BA184,89 A_BA284,89
C8811
C8808
C8812
C8812
12
C8813
C8813
WTL
WTL
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C8801
C8801
12
WTL
WTL
1 2
WTL
WTL
MAA084,89 MAA184,89 MAA284,89 MAA384,89 MAA484,89 MAA584,89 MAA684,89 MAA784,89 MAA884,89 MAA984,89
CKEA084
DQMA284 DQMA184 DQMA084
WEA0#84 CASA0#84 RASA0#84
12
12
WTL
WTL
WTL
WTL
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8804
C8804
12
WTL
WTL
VRAM_ZQ1 VRAM_ZQ2
VRAM1
VRAM1
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
NC#M7
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ2G63BFR-12C-GP
H5TQ2G63BFR-12C-GP
72.52G63.00U
72.52G63.00U
2nd = 72.42164.C0U
2nd = 72.42164.C0U
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7 NC#L9 NC#L1 NC#J9 NC#J1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
WTL
WTL
VRAM2
MDA2 MDA29
E3
MDA7
F7
MDA1
F2
MDA3
F8
MDA6
H3
MDA4
H8
MDA0
G2
MDA5
H7
MDA20 MDA13
D7
MDA19
C3
MDA23
C8
MDA16
C2
MDA22
A7
MDA17
A2
MDA21
B8
MDA18
A3 C7
B7 F3
G3 K1
L2 T2
T7 L9 L1 J9 J1
J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1
G1 F9 E8 E2 D8 D1 B9 B1 G9
MDA[0..31] 84
QSAP_2 84 QSAN_2 84
QSAP_0 84 QSAN_0 84
ODTA0 84
CSA0#_0 84 MEM_RST 84,89,90,91
12
C8822
C8822
WTL
WTL
C8823
C8823
WTL
WTL
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C8815
C8815
WTL
WTL
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8814
C8814
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C8817
C8817
WTL
WTL
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C8819
C8819
12
12
WTL
WTL
VRAM1_2_VREFVRAM1_2_VREF
C8816
C8816
12
C8818
C8818
WTL
WTL
WTL
WTL
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C8820
C8820
12
WTL
WTL
1 2
R8802 243R2F-2-GP
R8802 243R2F-2-GP
WTL
WTL
MAA084,89 MAA184,89 MAA284,89 MAA384,89 MAA484,89 MAA584,89 MAA684,89 MAA784,89 MAA884,89
MAA984,89 MAA1084,89 MAA1184,89 MAA1284,89 MAA1384,89
A_BA084,89 A_BA184,89 A_BA284,89
CLKA084 CLKA0#84
CKEA084
DQMA384
WEA0#84 CASA0#84 RASA0#84
12
WTL
WTL
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8821
C8821
12
WTL
WTL
VRAM2
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
NC#M7
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ2G63BFR-12C-GP
H5TQ2G63BFR-12C-GP
72.52G63.00U
72.52G63.00U
2nd = 72.42164.C0U
2nd = 72.42164.C0U
DQSU#
RESET#
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
DQSU
DQSL
DQSL#
ODT
CS#
NC#T7
NC#L9 NC#L1
NC#J9 NC#J1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
WTL
WTL
E3
MDA27
F7
MDA28
F2
MDA31
F8
MDA25
H3
MDA26
H8
MDA30
G2
MDA24
H7 D7
MDA14
C3
MDA10
C8
MDA15
C2
MDA11
A7
MDA9
A2
MDA8
B8
MDA12
A3 C7
B7 F3
G3 K1
L2 T2
T7 L9 L1 J9 J1
J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1
G1 F9 E8 E2 D8 D1 B9 B1 G9
MDA[0..31] 84
QSAP_1 84 QSAN_1 84
QSAP_3 84 QSAN_3 84
ODTA0 84
CSA0#_0 84 MEM_RST 84,89,90,91
1D5V_VGA_S0
12
R8805
R8805 2K1R2F-GP
2K1R2F-GP
WTL
WTL
VRAM1_2_VREF
12
R8806
R8806 2K1R2F-GP
2K1R2F-GP
WTL
WTL
A A
5
WTL
WTL
12
C8803
C8803 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
4
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
3
2
Date: Sheet
GPU-VRAM1,2 (1/4)
GPU-VRAM1,2 (1/4)
GPU-VRAM1,2 (1/4)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Taipei Hsien 221, Taiwan, R.O.C.
of
88 94
of
88 94
of
88 94
1
-1
-1
-1
5
K8 K2
12
SC1U6D3V2KX-GP
D D
C C
CLKA184 CLKA1#84
12
GPU_CLKA1_T
12
SC1U6D3V2KX-GP
12
WTL
WTL
WTL
R8907
R8907 56R2F-1-GP
56R2F-1-GP
WTL
WTL
C8903
C8903 SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
WTL
R8908
R8908 56R2F-1-GP
56R2F-1-GP
12
WTL
WTL
C8910
C8910
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
R8903 243R2F-2-GP
R8903 243R2F-2-GP
WTL
WTL
C8913
C8913
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
WTL
WTL
C8905
C8905
1 2
WTL
WTL
MAA084,88 MAA184,88 MAA284,88 MAA384,88 MAA484,88 MAA584,88 MAA684,88 MAA784,88 MAA884,88 MAA984,88 MAA1084,88 MAA1184,88 MAA1284,88 MAA1384,88
A_BA084,88 A_BA184,88 A_BA284,88
CKEA184
DQMA584 DQMA484
WEA1#84 CASA1#84 RASA1#84
12
WTL
WTL
C8912
C8912
12
WTL
WTL
C8907
C8907
VRAM_ZQ3 VRAM_ZQ4
N1 R9 B2 D9
G7
R1 N9
A8 A1 C1 C9 D2 E9 F1 H9 H2
H1
M8
L8
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3
M7
M2
N8
M3
J7
K7 K9
D3 E7
L3 K3
J3
4
VRAM3
VRAM3
VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VREFDQ VREFCA ZQ
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7
BA0 BA1 BA2
CK CK#
CKE
DMU DML
WE# CAS# RAS#
H5TQ2G63BFR-12C-GP
H5TQ2G63BFR-12C-GP
RESET#
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
NC#T7 NC#L9 NC#L1 NC#J9 NC#J1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
CS#
3
MDA35
E3
MDA38
F7
MDA33
F2
MDA37
F8
MDA34
H3
MDA39
H8
MDA32
G2
MDA36
H7
MDA45
D7
MDA43
C3
MDA47
C8
MDA40
C2
MDA44
A7
MDA41
A2
MDA46
B8
MDA42
A3 C7
B7 F3
G3 K1
L2 T2
T7 L9 L1 J9 J1
J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1
G1 F9 E8 E2 D8 D1 B9 B1 G9
QSAP_5 84 QSAN_5 84
QSAP_4 84 QSAN_4 84
ODTA1 84
CSA1#_0 84 MEM_RST 84,88,90,91
VRAM3_4_VREFVRAM3_4_VREF
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
WTL
WTL
WTL
C8922
C8922
WTL
C8915
C8915
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
WTL
WTL
C8916
C8916
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
R8904 243R2F-2-GP
R8904 243R2F-2-GP
WTL
WTL
MAA084,88 MAA184,88 MAA284,88 MAA384,88 MAA484,88 MAA584,88 MAA684,88 MAA784,88 MAA884,88 MAA984,88 MAA1084,88 MAA1184,88 MAA1284,88 MAA1384,88
A_BA084,88 A_BA184,88 A_BA284,88
CLKA184 CLKA1#84
CKEA184
DQMA684 DQMA784
WEA1#84 CASA1#84 RASA1#84
2
1D5V_VGA_S01D5V_VGA_S0
12
WTL
WTL
C8914
C8914
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
WTL
WTL
C8918
C8918
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VRAM4
VRAM4
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
NC#M7
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ2G63BFR-12C-GP
H5TQ2G63BFR-12C-GP
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9 NC#L1 NC#J9 NC#J1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
1
MDA61
E3
MDA60
F7
MDA63
F2
MDA57
F8
MDA59
H3
MDA58
H8
MDA62
G2
MDA56
H7
MDA50
D7
MDA55
C3
MDA49
C8
MDA53
C2
MDA48
A7
MDA54
A2
MDA51
B8
MDA52
A3 C7
B7 F3
G3 K1
L2 T2
T7 L9 L1 J9 J1
J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1
G1 F9 E8 E2 D8 D1 B9 B1 G9
QSAP_6 84 QSAN_6 84
QSAP_7 84 QSAN_7 84
ODTA1 84
CSA1#_0 84 MEM_RST 84,88,90,91
MDA[32..63] 84MDA[32..63] 84
B B
1D5V_VGA_S0
12
WTL
WTL
R8901
R8901 2K1R2F-GP
2K1R2F-GP
VRAM3_4_VREF
12
WTL
WTL
R8902
R8902 2K1R2F-GP
2K1R2F-GP
A A
5
WTL
WTL
12
C8901
C8901 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
4
1D5V_VGA_S0
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
WTL
WTL
C8902
C8902
12
WTL
WTL
C8906
C8906
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
WTL
WTL
C8909
C8909
12
WTL
WTL
C8908
C8908
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
3
12
WTL
WTL
C8911
C8911
1D5V_VGA_S0
12
WTL
WTL
C8919
C8919
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
WTL
WTL
C8917
C8917
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
12
WTL
WTL
C8921
C8921
12
WTL
WTL
C8920
C8920
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
2
12
WTL
WTL
C8923
C8923
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
GPU-VRAM3,4 (2/4)
GPU-VRAM3,4 (2/4)
GPU-VRAM3,4 (2/4)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Taipei Hsien 221, Taiwan, R.O.C.
1
of
89 94
of
89 94
of
89 94
-1
-1
-1
5
K8 K2
PX
PX
PX
12
C9022
C9022
SC1U6D3V2KX-GP
D D
C C
SC1U6D3V2KX-GP
20090902
CLKB084 CLKB0#84
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
B B
R9007
R9007
56R2F-1-GP
56R2F-1-GP
C9003
C9003
12
PX
PX
GPU_CLKB0_T
12
PX
PX
R9008
R9008
56R2F-1-GP
56R2F-1-GP
PX
PX
1D5V_VGA_S0
12
PX
12
C9023
C9023
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PX
PX
12
C9005
C9005
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
R9004 243R2F-2-GP
R9004 243R2F-2-GP
PX
PX
MAB084,91 MAB184,91 MAB284,91 MAB384,91 MAB484,91 MAB584,91 MAB684,91 MAB784,91 MAB884,91
MAB984,91 MAB1084,91 MAB1184,91 MAB1284,91 MAB1384,91
B_BA084,91 B_BA184,91 B_BA284,91
CKEB084
DQMB384 DQMB184
WEB0#84 CASB0#84 RASB0#84
12
PX
PX
R9001
R9001 2K1R2F-GP
2K1R2F-GP
12
PX
PX
R9002
R9002 2K1R2F-GP
2K1R2F-GP
PX
PX
12
C9010
C9010
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PX
PX
12
C9007
C9007
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VRAM_ZQ5 VRAM_ZQ6
VRAM5_6_VREF
N1 R9 B2 D9
G7
R1 N9
A8 A1 C1 C9 D2 E9 F1 H9 H2
H1
M8
L8
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3
M7
M2
N8
M3
J7
K7 K9
D3 E7
L3 K3
J3
PX
PX
12
C9001
C9001 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
4
VRAM5
VRAM5
VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VREFDQ VREFCA ZQ
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7
BA0 BA1 BA2
CK CK#
CKE
DMU DML
WE# CAS# RAS#
H5TQ2G63BFR-12C-GP
H5TQ2G63BFR-12C-GP
72.52G63.00U
72.52G63.00U
2nd = 72.42164.C0U
2nd = 72.42164.C0U
PX
PX
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
RESET#
NC#T7 NC#L9 NC#L1 NC#J9 NC#J1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
CS#
3
MDB14
E3
MDB13
F7
MDB12
F2
MDB15
F8
MDB11
H3
MDB8
H8
MDB9
G2
MDB10
H7
MDB26 MDB1
D7
MDB27
C3
MDB30
C8
MDB24 MDB4
C2
MDB31
A7
MDB25 MDB7
A2
MDB29
B8
MDB28
A3 C7
B7 F3
G3 K1
L2 T2
T7 L9 L1 J9 J1
J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1
G1 F9 E8 E2 D8 D1 B9 B1 G9
MDB[0..31] 84
PX
PX
PX
12
C9017
C9017
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
QSBN_3 84 QSBN_0 84 QSBP_1 84
QSBN_1 84 ODTB0 84
CSB0#_0 84 MEM_RST 84,88,89,91
PX
PX
PX
12
C9002
C9002
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PX
12
C9006
C9006
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PX
PX
12
C9009
C9009
VRAM5_6_VREFVRAM5_6_VREF
CLKB084 CLKB0#84
PX
PX
12
C9008
C9008
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C9021
C9021
PX
12
C9019
C9019
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PX
PX
12
C9013
C9013
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
R9006 243R2F-2-GP
R9006 243R2F-2-GP
MAB084,91 MAB184,91 MAB284,91 MAB384,91 MAB484,91 MAB584,91 MAB684,91 MAB784,91 MAB884,91
MAB984,91 MAB1084,91 MAB1184,91 MAB1284,91 MAB1384,91
B_BA084,91 B_BA184,91 B_BA284,91
CKEB084
DQMB084 DQMB284
WEB0#84 CASB0#84 RASB0#84
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
PX
PX
1D5V_VGA_S01D5V_VGA_S0
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
2
1D5V_VGA_S01D5V_VGA_S0
PX
PX
C9020
C9020
PX
PX
C9014
C9014
PX
PX
12
C9012
C9012
VRAM6
VRAM6
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
NC#M7
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ2G63BFR-12C-GP
H5TQ2G63BFR-12C-GP
72.52G63.00U
72.52G63.00U
2nd = 72.42164.C0U
2nd = 72.42164.C0U
PX
PX
PX
PX
12
C9011
C9011
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C9015
C9015
DQSU#
DQSL#
RESET#
NC#T7
NC#L9 NC#L1 NC#J9 NC#J1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
DQSU
DQSL
ODT
CS#
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
12
PX
PX
C9016
C9016
E3 F7 F2 F8 H3 H8 G2 H7
D7 C3 C8 C2 A7 A2 B8 A3
C7 B7
F3 G3
K1
L2 T2
T7 L9 L1 J9 J1
J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1
G1 F9 E8 E2 D8 D1 B9 B1 G9
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
MDB16 MDB18 MDB20 MDB19 MDB22 MDB17 MDB23 MDB21
MDB5 MDB2
MDB3 MDB0
MDB6
PX
PX
C9018
C9018
1
MDB[0..31] 84
QSBP_0 84QSBP_3 84
QSBP_2 84 QSBN_2 84
ODTB0 84
CSB0#_0 84 MEM_RST 84,88,89,91
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
GPU-VRAM5,6 (3/4)
GPU-VRAM5,6 (3/4)
GPU-VRAM5,6 (3/4)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Taipei Hsien 221, Taiwan, R.O.C.
of
90 94
of
90 94
of
90 94
1
-1
-1
-1
5
4
3
2
1
PX
PX
C9122
C9122
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PX
PX
C9115
C9115
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
PX
PX
CKEB184
DQMB784 DQMB684
WEB1#84 CASB1#84 RASB1#84
PX
PX
12
C9108
C9108
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1D5V_VGA_S01D5V_VGA_S0
PX
PX
12
C9123
C9123
PX
PX
12
C9116
C9116
PX
PX
12
C9109
C9109
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VRAM8
VRAM8
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
NC#M7
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ2G63BFR-12C-GP
H5TQ2G63BFR-12C-GP
72.52G63.00U
72.52G63.00U
2nd = 72.42164.C0U
2nd = 72.42164.C0U
PX
PX
1D5V_VGA_S01D5V_VGA_S0
PX
PX
12
C9110
C9110
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
C7
DQSU
B7
DQSU#
F3
DQSL
G3
DQSL#
K1
ODT
L2
CS#
T2
RESET#
T7
NC#T7
L9
NC#L9
L1
NC#L1
J9
NC#J9
J1
NC#J1
J8
VSS
M1
VSS
M9
VSS
J2
VSS
P9
VSS
G8
VSS
B3
VSS
T1
VSS
A9
VSS
T9
VSS
E1
VSS
P1
VSS
G1
VSSQ
F9
VSSQ
E8
VSSQ
E2
VSSQ
D8
VSSQ
D1
VSSQ
B9
VSSQ
B1
VSSQ
G9
VSSQ
PX
PX
12
C9114
C9114
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
PX
PX
C9117
C9117
MDB53 MDB51 MDB55 MDB49 MDB54 MDB48 MDB52 MDB50
MDB61 MDB62 MDB58 MDB59 MDB63 MDB56 MDB57 MDB60
PX
PX
12
C9118
C9118
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
MDB[32..63] 84
QSBP_7 84 QSBN_7 84
QSBP_6 84 QSBN_6 84
ODTB1 84
CSB1#_0 84 MEM_RST 84,88,89,90
PX
PX
12
C9119
C9119
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
PX
PX
C9120
C9120
VRAM7
VRAM7
K8
VDD
K2
VDD
N1
VDD
PX
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
PX
PX
CKEB184
DQMB484 DQMB584
WEB1#84 CASB1#84 RASB1#84
PX
12
C9113
C9113
PX
PX
12
C9106
C9106
VRAM_ZQ7 VRAM_ZQ8
VRAM7_8_VREF
PX
PX
12
C9111
C9111
D D
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
20100712 V1.5 20100712 V1.5
C C
CLKB184 CLKB1#84
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
B B
R9107
R9107
56R2F-1-GP
56R2F-1-GP
C9103
C9103
12
PX
PX
GPU_CLKB1_T
12
PX
PX
R9108
R9108
56R2F-1-GP
56R2F-1-GP
PX
PX
12
PX
PX
12
C9112
C9112
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PX
PX
12
C9105
C9105
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
R9103 243R2F-2-GP
R9103 243R2F-2-GP
MAB084,90 MAB184,90 MAB284,90 MAB384,90 MAB484,90 MAB584,90 MAB684,90 MAB784,90 MAB884,90
MAB984,90 MAB1084,90 MAB1184,90 MAB1284,90 MAB1384,90
B_BA084,90 B_BA184,90 B_BA284,90
1D5V_VGA_S0
12
PX
PX
R9101
R9101 2K1R2F-GP
2K1R2F-GP
12
PX
PX
R9102
R9102 2K1R2F-GP
2K1R2F-GP
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
NC#M7
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ2G63BFR-12C-GP
H5TQ2G63BFR-12C-GP
72.52G63.00U
72.52G63.00U
2nd = 72.42164.C0U
2nd = 72.42164.C0U
PX
PX
PX
PX
12
C9101
C9101 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7 NC#L9 NC#L1 NC#J9 NC#J1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
MDB40
E3
MDB43
F7
MDB47
F2
MDB44
F8
MDB41
H3
MDB45
H8
MDB42
G2
MDB46
H7
MDB36
D7
MDB35
C3
MDB39
C8
MDB32
C2
MDB37
A7
MDB33
A2
MDB38
B8
MDB34
A3 C7
B7 F3
G3 K1
L2 T2
T7 L9 L1 J9 J1
J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1
G1 F9 E8 E2 D8 D1 B9 B1 G9
MDB[32..63] 84
QSBP_4 84 QSBN_4 84
QSBP_5 84 QSBN_5 84
ODTB1 84
CSB1#_0 84 MEM_RST 84,88,89,90
PX
PX
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VRAM7_8_VREFVRAM7_8_VREF
CLKB184 CLKB1#84
PX
PX
12
C9102
C9102
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C9121
C9121
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
R9104 243R2F-2-GP
R9104 243R2F-2-GP
MAB084,90 MAB184,90 MAB284,90 MAB384,90 MAB484,90 MAB584,90 MAB684,90 MAB784,90 MAB884,90
MAB984,90 MAB1084,90 MAB1184,90 MAB1284,90 MAB1384,90
B_BA084,90 B_BA184,90 B_BA284,90
PX
PX
12
C9107
C9107
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
GPU-VRAM7,8 (4/4)
GPU-VRAM7,8 (4/4)
GPU-VRAM7,8 (4/4)
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
Taipei Hsien 221, Taiwan, R.O.C.
of
91 94
of
91 94
of
91 94
1
-1
-1
-1
5
4
3
2
1
SSID = PWR.Plane.Regulator_GFX
DCBATOUT PWR_DCBATOUT_VGA_CORE
PG9201
PG9201
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9202
PG9202
D D
C C
B B
MADSION PRO
Setting Vref Vout & Rfb-Top
VOUT (Target)
A A
WHIST => R9211 NO_ASM. SEYMR => whole ASM
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9203
PG9203
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9204
PG9204
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
12
SC1U10V2KX-1GP
SC1U10V2KX-1GP
DGPU_PWR_EN93
1.150
1.050
1.000
0.900
PX
PX
R9201
R9201 10R2F-L-GP
10R2F-L-GP
PX
PX
C9202
C9202
12
PX
PX
PR9205
PR9205 6K34R2F-GP
6K34R2F-GP
1 2
Vref (V)
0.75
VOUT (compute)
1.150
1.050
1.000
0.900
5
5V_PWR
12
PWR_VGA_CORE_VDD
PWR_VGA_CORE_PGOOD PWR_VGA_CORE_CS
8209A_EN/DEM_VGA86,93
K A
R9208 R9210 10K 50K
PWR_VGA_CORE_TON
PX
PX
C9201
C9201 SC1U10V2KX-1GP
SC1U10V2KX-1GP
D9201
D9201
CH551H-30GP-GP
CH551H-30GP-GP
DY
DY
PX
PX
PU9201
PU9201
PWR_VGA_CORE_BOOT
16
TON
9
VDDP
2
VDD
4
PGOOD
10
CS
15
EM/DEM
17
GND
RT8208BGQW-GP
RT8208BGQW-GP
RT8208B:74.08208.A73
3D3V_VGA_S0
12
PX
PX
R9212
R9212 10KR2F-2-GP
10KR2F-2-GP
DY
DY
12
C9211
C9211 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
R9211
13
BOOT
UGATE PHASE
LGATE
VOUT
8209A_EN/DEM_VGA 86,93
12 11 8
7
G0
3
FB
14
G1
5
D1
6
D0
1
PWR_VGA_CORE_UGATE PWR_VGA_CORE_PHASE PWR_VGA_CORE_LGATE
PWR_VGA_CORE_FB PWR_VGA_CORE_D1
PWR_VGA_CORE_D0 PWR_VGA_CORE_VOUT
R9209 50K 75K VID1
VID0
0 0
0 1 01
1
1
PX
PR9203 249KR2F-GP
PR9203 249KR2F-GP
NVVDD_ALTV1
PX
1 2
PX
PX
PR9204
PR9204
1 2
2R3J-2-GP
2R3J-2-GP
PWRCNTL_0 85 PWRCNTL_1 85
PWR_VGA_CORE_PGOOD
NVVDD_ALTV0 +VGA_CORE
H
H
4
PWR_DCBATOUT_VGA_CORE
6
DDD
DDD
PX
PX
G
G
PX
PX
PC9203
PWR_VGA_CORE_BOOT_C
3D3V_VGA_S0
12
12
L
PC9203
1 2
PR9201
SCD1U25V3KX-GP
SCD1U25V3KX-GP
PR9201
1 2
0R0402-PAD
0R0402-PAD
PR9202
PR9202
1 2
0R0402-PAD
0R0402-PAD
6
7
4
5
Vout=0.75V*(R1+R2)/R2
PX
PX
R9213
R9213 10KR2J-3-GP
10KR2J-3-GP
R9214
R9214
1 2
0R0402-PAD
0R0402-PAD
PX
PX
C9212
C9212 SC100P50V2JN-3GP
SC100P50V2JN-3GP
VGA_SENSE86
GND_SENSE86
1.12V or 1V
DGPU_PWROK 22,86,93
PX
PX
PR9207
PR9207
1 2
0R0402-PAD
0R0402-PAD
PX
PX
PR9212
PR9212
1 2
0R0402-PAD
0R0402-PAD
OUT=[R9208+(R9210//R9209)}/(R9210//R9209)
H
0.9V
OUT=(R9208+R9210)/R9210
3
1
2345
D
D
PU9202
PU9202 IRF6721SPBF-GP-U
IRF6721SPBF-GP-U
84.06721.030
84.06721.030
S
S
1
23
DDD
DDD
PX
PX
PU9204
PU9204 IRF6725MTRPBF-GP-U
IRF6725MTRPBF-GP-U
84.06725.030
84.06725.030
SSGD
SSGD
1
PX
PX
12
PC9207
PC9207 SC10U25V5KX-GP
SC10U25V5KX-GP
TP9201
TP9201 TPAD40-GP
TPAD40-GP
DY
DY
12
PC9201
PC9201 SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
PX
PX
12
PC9205
PC9205 SC10U25V5KX-GP
SC10U25V5KX-GP
Design Current = 21.94A
24.14A<OCP< 28.53A
PX
PL9201 L-D36UH-1-GP
PL9201 L-D36UH-1-GP
PX
1 2
PWR_VGA_CORE_VOUT
PX
PX
PR9208
PR9208 10KR2F-2-GP
10KR2F-2-GP
PWR_VGA_CORE_FB
12
PX
PX
R9209
R9209 33KR2F-GP
33KR2F-GP
PWR_VGA_CORE_D0
PG9205
PG9205
12
12
12
12
PWR_GND_SENSE_1
12
PX
PX
12
PC9210
PC9210 SC10U25V5KX-GP
SC10U25V5KX-GP
VGA_CORE_PWR
PX
PX
12
PC9206
PC9206
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PX
PX
PR9206
PR9206 10R2J-2-GP
10R2J-2-GP
12
DY
DY
PC9208
PC9208
SC10P50V2JN-4GP
SC10P50V2JN-4GP
PX
PX
R9210
R9210 49K9R2F-L-GP
49K9R2F-L-GP
PX
PX
PR9213
PR9213 10R2J-2-GP
10R2J-2-GP
2
PX
PX
12
PC9211
PC9211 SC10U25V5KX-GP
SC10U25V5KX-GP
PX
PX
12
PTC9202
PTC9202
SE470UF2VDM-GP
SE470UF2VDM-GP
12
DY
DY
PC9209
PC9209
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
PWR_VGA_CORE_D1
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
VGA_CORE VGA_CORE_PWR VGA_CORE
PG9206
PG9206
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9207
PG9207
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9208
PG9208
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9209
PG9209
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9210
PG9210
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9211
PG9211
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9212
PG9212
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9213
PG9213
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9214
PG9214
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9215
PG9215
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9227
PG9227
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PX
PX
12
PTC9203
PTC9203
SE470UF2VDM-GP
SE470UF2VDM-GP
3D3V_AUX_S5
DY
DY
PR9214
PR9214 100KR2J-1-GP
100KR2J-1-GP
1 2
PWR_VGA_CORE_EN_R#
DY
DY
PQ9201
PQ9201 2N7002KDW-GP
2N7002KDW-GP
8209A_EN/DEM_VGA PQ9206_3
DY
DY
R9211
R9211 49K9R2F-L-GP
49K9R2F-L-GP
RT8208B_+VGA_CORE
RT8208B_+VGA_CORE
RT8208B_+VGA_CORE
LLW-1 / LGG-1
LLW-1 / LGG-1
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
LLW-1 / LGG-1
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
5
6
123 4
Wistron Corporation
Wistron Corporation
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
PG9216
PG9216
1 2
PG9217
PG9217
1 2
PG9218
PG9218
1 2
PG9219
PG9219
1 2
PG9220
PG9220
1 2
PG9221
PG9221
1 2
PG9222
PG9222
1 2
PG9223
PG9223
1 2
PG9224
PG9224
1 2
PG9225
PG9225
1 2
PG9226
PG9226
1 2
VGA_CORE_PWR
DY
DY
PR9215
PR9215 100R2J-2-GP
100R2J-2-GP
1 2
of
92 94
of
92 94
of
92 94
-1
-1
-1
5
+3VS to 3.3V_DELAY Transfer
3D3V_S0
D D
DGPU_PWR_EN#18 8209A_EN/DEM_VGA86,92
C C
3D3V_S0
12
PX
PX
R9302
R9302 100KR2J-1-GP
100KR2J-1-GP
3.3V_ALW_1
PX
PX
R9308
R9308 10KR2F-2-GP
10KR2F-2-GP
1 2
PX
PX
Q9305
Q9305
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
DY
DY
R9301 0R5J-5-GP
R9301 0R5J-5-GP
1 2
S
D
D
D
G
G
PX
PX
Q9302
Q9302
G
DMP2130L-7-GP
DMP2130L-7-GP
84.02130.031
84.02130.031
2ND = 84.03413.A31
2ND = 84.03413.A31
5
6
PX
PX
Q9301
Q9301 2N7002KDW-GP
2N7002KDW-GP
123 4
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
3.3V_RUN_VGA_1
20100629 V1.3
DGPU_PWR_EN
D
DGPU_PWR_EN 92
3D3V_VGA_S0
12
PX
PX
R9304
R9304 100R2J-2-GP
100R2J-2-GP
4
20100629 V1.3
DGPU_PWR_EN92
Reserved PD9301 connect DGPU_PWR_EN to PWR_1D5V_EN for power down sequence.
9025_PGOOD_1V
DIS mode:R9309,R9311 follow Old Sequence PX_Muxless :R9310,C9308,R9320,C9304 value need fine tune for BACO sequecne
DY
DY
D9301
D9301
K A
CH551H-30GP-GP
CH551H-30GP-GP
DY
DY
R9309 0R2J-2-GP
R9309 0R2J-2-GP
1 2
PX
PX
R9320
R9320
1 2
0R2-PT5-LILY-GP
0R2-PT5-LILY-GP
RUN_ENABLE
12
PX
PX
12
C9301
C9301 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
PX
PX
R9305
R9305 330KR2J-L1-GP
330KR2J-L1-GP
PX
PX
C9304
C9304 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3
PX
PX
Q9303
Q9303 NDS0610-G-GP
NDS0610-G-GP
G
12
PX
PX
R9306
R9306 100KR2J-1-GP
100KR2J-1-GP
DIS_EN_1D5_RUN
D
G
PX
PX
U9301
U9301
D
D
8
D
D
7
D
D
6
D
D
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
S
1D5V_VGA_S0
S
S
1
S
S
2
S
S
3
G
G
45
RUNON_R
DS
12
PX
PX
R9307
R9307
330KR2J-L1-GP
330KR2J-L1-GP
PX
PX
Q9304
Q9304 2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
12
RUNON_R_1
1 2
PX
PX
R9303
R9303
20KR2F-L-GP
20KR2F-L-GP
PX
PX
C9302
C9302 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
RUNON_R_1
PX
PX
12
C9303
C9303 SCD1U25V2KX-GP
SCD1U25V2KX-GP
1D5V_S3 1D5V_VGA_S0
DIS_EN_1D5_RUN_R
PX
PX
12
TC9302
TC9302 ST100U6D3VBM-5GP
ST100U6D3VBM-5GP
77.C1071.081
77.C1071.081
2nd = 77.21071.07L
2nd = 77.21071.07L
2
DGPU_PWROK22,86,92
PX
PX
12
TC9301
TC9301
ST330U2D5VDM-13GP
ST330U2D5VDM-13GP
77.C3371.10L
77.C3371.10L
2nd = 79.33719.20D
2nd = 79.33719.20D
20100805 V1.8
DY
DY
U9304
U9304
1
VCC
2
ON
3
DIS2
G1/G2
4
GND
S/DIS1
SLG55221-130010VTR-GP
SLG55221-130010VTR-GP
74.55221.0E3
74.55221.0E3
NC#9
20100629 V1.3
DIS_EN_1D5_RUN
5V_S5
9 8
PG
D
7 6 5
SLG_RUN_ENABLE_VGA
1
1D5V_VGA_S0
12
PX
PX
R9321
R9321 470R2J-2-GP
470R2J-2-GP
DIS_FBVDD
PX
PX
D
Q9306
Q9306 2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
S
G
Discharge Circuit
RUNON_R_1
1D5V_VGA_S05V_S5
12
DY
DY
R9322
R9322 0R2J-2-GP
0R2J-2-GP
RT9025 for 1V_VGA
1D5V_S3
PX
PX
PX
C9308
C9308
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
9025_PGOOD_1V
PX
12
C9306
C9306 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
3D3V_VGA_S0
12
PX
PX
R9313
R9313 2K2R2J-2-GP
2K2R2J-2-GP
PX
PX
12
C9305
C9305 SC10U6D3V5KX-1GP
D9302
D9302
K A
CH551H-30GP-GP
CH551H-30GP-GP
DY
DY
1 2
1 2
PX
PX
R9310
R9310 10KR2F-2-GP
10KR2F-2-GP
SC10U6D3V5KX-1GP
9025_EN
0R2J-2-GP
0R2J-2-GP
Reserved PD9302 connect DGPU_PWR_EN to PWR_1V_EN for power down sequence.
DY
3D3V_VGA_S0
DY
R9311
R9311
DGPU_PWR_EN92
20100629 V1.3
DGPU_PWROK22,86,92
DIS mode:R9309,R9311 follow Old Sequence
B B
PX_Muxless :R9310,C9308,R9320,C9304 value need fine tune for BACO sequecne
5V_S5
PX
PX
12
C9307
C9307 SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
PX
PX
U9302
U9302
VDD4NC#5
3
VIN
2
EN
1
PGOOD
RT9025-25PSP-GP
RT9025-25PSP-GP
G9301
G9301
GAP-CLOSE-PWR
GAP-CLOSE-PWR
G9302
G9302
GAP-CLOSE-PWR
GAP-CLOSE-PWR
G9303
G9303
GAP-CLOSE-PWR
GAP-CLOSE-PWR
Iomax=1.5A
1V_VGA_S0
12
12
12
12
PX
PX
R9312
R9312 5K1R2F-2-GP
5K1R2F-2-GP
9025_FB
12
PX
PX
R9314
R9314 20KR2F-L-GP
20KR2F-L-GP
1DV_M92_PWR
SC100P50V2JN-3GP
SC100P50V2JN-3GP
PX
PX
12
C9309
C9309
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
PX
PX
PX
PX
12
12
C9311
C9311
C9310
C9310
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
9
5
GND
6
VOUT
7
ADJ
8
GND
Vo=0.8*(1+(R1/R2))
RT9025 for 1D8V_VGA
3D3V_S5
PX
R9315
R9315
PX
PX
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3D3V_VGA_S0
PX
PX
R9319
R9319
1 2
PX
12
C9313
C9313 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
DY
C9315
C9315
12
PX
PX
R9317
R9317 10KR2F-2-GP
10KR2F-2-GP
9025_PGOOD_VGA
12
DY
DY
12
C9312
C9312 SC10U6D3V5KX-1GP
20100629 V1.3
Reserved PD9303 connect DGPU_PWR_EN to PWR_1D8V_EN for power down sequence.
DGPU_PWR_EN92
A A
5
SC10U6D3V5KX-1GP
DY
DY
D9303
D9303
K A
CH551H-30GP-GP
9025_PGOOD_1V 9025_EN_VGA
1D8V_S0_VGA_PG83
CH551H-30GP-GP
1 2
0R2-PT5-LILY-GP
0R2-PT5-LILY-GP
0R2-PT5-LILY-GP
0R2-PT5-LILY-GP
5V_S5
PX
PX
12
C9314
C9314 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PX
PX
U9303
U9303
VDD4NC#5
3
VIN
2
EN
1
PGOOD
RT9025-25PSP-GP
RT9025-25PSP-GP
Iomax=1A OCP>1.35A
1D8V_VGA_S0
G9304
G9304
9
5
GND
6
VOUT
7
ADJ
8
GND
Vo(cal.)=1.8069V
12
9025_ADJ_VGA
12
PX
PX
R9316
R9316 18KR2F-GP
18KR2F-GP
PX
PX
R9318
R9318 14K3R2F-GP
14K3R2F-GP
DY
DY
12
C9316
C9316 SC100P50V2JN-3GP
SC100P50V2JN-3GP
PX
PX
12
C9317
C9317 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1D8V_LDO_VGA
DY
DY
12
C9318
C9318 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
GAP-CLOSE-PWR
GAP-CLOSE-PWR
G9305
G9305
GAP-CLOSE-PWR
GAP-CLOSE-PWR
12
12
Vo=0.8*((R1+R2)/R2)
4
3
2
Table 93.1- Adjustable LDO Regulator multi-source
Supplier
GMT
RICHTEK
Description Lenovo P/N Wistron P/N
G9661-25ADJF11U
N/A 74.09661.07D
N/ART9025-25GSP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev C
C
C
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C .
DISCRETE VGA POWER
DISCRETE VGA POWER
DISCRETE VGA POWER
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
93 94
93 94
93 94
74.09025.A3D
of
of
of
-1
-1
-1
5
VGACPU
H4
H2
H1
H1 HOLET157B276R134-GP
HOLET157B276R134-GP
1
ZZ.SCREW.091
ZZ.SCREW.091
D D
H14
H14 HOLE237R95-GP
HOLE237R95-GP
1
ZZ.00PAD.921
ZZ.00PAD.921
H21
H21 HOLE197R67X146
HOLE197R67X146
1
KN1.PAD.01
KN1.PAD.01
C C
H2 HOLET157B276R134-GP
HOLET157B276R134-GP
1
ZZ.SCREW.091
ZZ.SCREW.091
H8
H8 HOLE237R95-GP
HOLE237R95-GP
1
ZZ.00PAD.921
ZZ.00PAD.921
H15
H15 STF217R113H119-GP
STF217R113H119-GP
1
34.4C408.001
34.4C408.001
H22
H22 HOLE197R67X146
HOLE197R67X146
1
KN1.PAD.01
KN1.PAD.01
H3
H3 HOLET157B276R134-GP
HOLET157B276R134-GP
1
ZZ.SCREW.091
ZZ.SCREW.091
H9
H9 HT85X105B85R26-S-GP
HT85X105B85R26-S-GP
1
ZZ.SCREW.191
ZZ.SCREW.191
H16
H16 STF256R117H221-GP
STF256R117H221-GP
1
34.4B804.001
34.4B804.001
H23
H23 GNDPADSR197
GNDPADSR197
1
ZZ.NDPAD.XXX
ZZ.NDPAD.XXX
H4 HOLET157B276R134-GP
HOLET157B276R134-GP
1
ZZ.SCREW.091
ZZ.SCREW.091
H10
H10 HT85X105B85R26-S-GP
HT85X105B85R26-S-GP
1
ZZ.SCREW.191
ZZ.SCREW.191
H17
H17 STF256R117H221-GP
STF256R117H221-GP
1
34.4B804.001
34.4B804.001
H24
H24 GNDPADSR197
GNDPADSR197
1
ZZ.NDPAD.XXX
ZZ.NDPAD.XXX
H11
H11 HOLE237R95-GP
HOLE237R95-GP
ZZ.00PAD.921
ZZ.00PAD.921
H18
H18 HOLE315R95-GP
HOLE315R95-GP
ZZ.00PAD.911
ZZ.00PAD.911
H25
H25 GNDPADSR197
GNDPADSR197
1
ZZ.NDPAD.XXX
ZZ.NDPAD.XXX
H5
H5 HOLET157B276R134-GP
HOLET157B276R134-GP
1
ZZ.SCREW.091
ZZ.SCREW.091
1
1
ZZ.NDPAD.XXX
ZZ.NDPAD.XXX
H12
H12 HT6BE6R24-U-45-GP
HT6BE6R24-U-45-GP
H26
H26 GNDPADSR197
GNDPADSR197
1
1
4
H6
H6 HOLET157B276R134-GP
HOLET157B276R134-GP
1
ZZ.SCREW.091
ZZ.SCREW.091
H13
H13 HT6BE75R24-U-45- G P
HT6BE75R24-U-45- G P
1
ZZ.00PAD.971
ZZ.00PAD.971
H20
H20 HOLE315R95-GP
HOLE315R95-GP
1
ZZ.00PAD.911
ZZ.00PAD.911
1
S1
S1 SPRING-62-GP
SPRING-62-GP
1
S2
S2 SPRING-71-GP
SPRING-71-GP
3
2
1
EMI CAP
DCBATOUT
12
EC9701
EC9701 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
3D3V_S5
12
EC9704
EC9704 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
B B
5V_S5
12
EC9715
EC9715 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
1D5V_S3
12
EC9746
EC9746 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
A A
12
EC9702
EC9702 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9705
EC9705 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9716
EC9716 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9747
EC9747 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
12
12
12
5
EC9703
EC9703 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
EC9706
EC9706 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
EC9729
EC9729 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
EC9748
EC9748 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
3D3V_S0
12
12
12
12
EC9708
EC9708 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
EC9707
EC9707 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
EC9730
EC9730 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
EC9749
EC9749 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9709
EC9709 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
1D5V_VGA_S0
12
EC9711
EC9711 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9731
EC9731 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9750
EC9750 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9710
EC9710 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9719
EC9719 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9732
EC9732 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9751
EC9751 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
1D05V_VTT
12
EC9712
EC9712 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9720
EC9720 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9733
EC9733 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
4
12
EC9721
EC9721 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
1D5V_S0
12
EC9713
EC9713 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
5V_S0
12
EC9734
EC9734 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9722
EC9722 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9714
EC9714 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9735
EC9735 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9723
EC9723 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9736
EC9736 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9724
EC9724 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9737
EC9737 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
3
1D8V_S0
12
EC9725
EC9725 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9738
EC9738 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9717
EC9717 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9726
EC9726 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9739
EC9739 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9718
EC9718 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
12
EC9727
EC9727 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
EC9740
EC9740 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9728
EC9728 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9741
EC9741 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
2
12
EC9742
EC9742 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9743
EC9743 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9744
EC9744 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
12
EC9745
EC9745 SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporat ion
Wistron Corporat ion
Wistron Corporat ion
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.
Taipei Hsien 221, Taiw an, R.O.C.
Title
Title
Title
UNUSED PARTS/EMI Capacitors
UNUSED PARTS/EMI Capacitors
UNUSED PARTS/EMI Capacitors
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A2
A2
A2
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Tuesday, January 18, 2011
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiw an, R.O.C.
LLW-1 / LGG-1
LLW-1 / LGG-1
LLW-1 / LGG-1
1
94 94
94 94
94 94
-1
-1
-1
of
of
of
Loading...