Wistron LLW-1, LGG-1 Schematic

5

4

3

2

1

LLW-1/LGG-1 Schematics

D D

Sandy Bridge Cougar Point

C C

2010-11-08

REV : SB

DY:None Installed UMA:UMA platform installed only

B B

PX:Discrete(both Robson and Whistler) SKU installed RBS:Robson SKU installed only WTL:Whistler SKU installed only SAMSUNG:Use SAMSUNG VRAM Hynix:Use Hynix VRAM VRAM_1G:Use 1G VRAM VRAM_2G:Use 2G VRAM

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, November 09, 2010

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

LLW-1 / LGG-1

1

1 94

SB

PCB Layer Stackup

ThermalSensor

EMC2103

RFID I2C/SM Bus Switch

AUDIO COMBO Jack 58

28

80

SM Bus

SIM Slot

USB 2.0

Camera

##OnMainBoard

66

HD AUDIO CODEC CX20671

USB 2.0

PORT2

PORT1

VRAM

2GB/1GB

14" HD 1366*768

VGA connector

HDMI connector

SATA CONN

ODD CONN

Mini PCI-E WWAN Card

eSATA Combo CN

eSATA

PORT3

CH1

61

CH9

61

CH12

49

LLW-1 / LGG-1 Block Diagram

AMD GPU

Whistler-LP 1G/2G Seymour-XT 1G

PEG x16

Intel CPU

Sandy Bridge

DDR3 1333MHz

DMI x4

Intel

PCH

USB 2.0 (14 ports)

AC97 2.3/Azalia Interface

Serial ATA 150MB/s

ACPI 2.0

LPC I/F PCI Rev 2.3 PCI Express

INT. RTC

17~25

CH2

USB 2.0

CH3

83~87

4~10

FDI

XDP Conn.

Channel A

DDR3 1333

Channel B

DDR3 1333

USB 2.0 CH11

PCI Express 4

PCI Express 2

11

Project Code: PCB(Raw Card):10282

UNBUFFERED DDR3 SODIMM

204-PIN DDR3 SODIMM

UNBUFFERED DDR3 SODIMM

Mini PCI-E WLAN Card

PCI Express 2

CONNCONN

82

PCI Express 3

USB 2.0 CH13

USB 2.0 CH10 USB 2.0 CH10

Media Card Reader

R5U220

PCI Express 8PCI Express 8

82

LPC Bus / 33MHz

KBC Nuvoton NPCE795

27

G-Sensor

SPI FLASH

79

Int.KB/Track point Touch Pad

60

14

15

65

LOM

RTL8111E

32

USB 2.0 CH13

NEW CARD

USB 2.0 PORT4

LPC Debug Board Conn

71

69

88~91

49

50

51

29

56

66

57

USB 2.0

FingerPrint

Bluetooth

DDR3 800MHz

LVDS

VGA Port

Display Port

SATA Port 0

SATA Port 4

SATA

USB 2.0 CH4

Azalia bus

SATA Port5

CH8

69

63

L1: TOP L5: VCC L2: GND L3: Signal L4: Signal

L6: Signal L7: GND L8: BOTTOM

Battery Charger/Selector

BQ24745

OUTPUTSINPUTS

DCBATOUT BT+

System DC/DC

BD95280

PWR_3D3V_DCBATOUT

PWR_5V_DCBATOUT

3D3V_S5 5V_S5

CPU DC/DC

NCP6131

DCBATOUT

DCBATOUT_VCC_GFXCOREVCC_GFXCORE

42~44

VCC_CORE

1D05V_VTT

TPS51218

PWR_1D05V_DCBATOUT

1D05V_VTT

1D5V_S3

TPS51218

PWR_1D5V_DCBATOUT 1D5V_S3

0D75V

RJ45

RT9026

1D5V_S3

DDR_VREF_S3

0D75V_S0

1D8V_S0

RT8015

3D3V_S5

1D8V_S0

VCCSA

RT8208B

PWR_VCCSA_DCBATOUT

0D85V_S0

GFX CORE

RT8208B

PWR_DCBATOUT_VGA_COREVGA_CORE

1V_VGA

RT9025

1V_VGA_S01D5V_S3

1D8V_VGA

RT9025

3D3V_S5 1D8V_VGA_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Block Diagram

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

LLW-1 / LGG-1

2 94Tuesday, November 09, 2010

40

41

45

46

47

48

92

93

SB

A

PCH Strapping

Name Schematics Notes

SPKR

INIT3_3V# Weak internal pull-up. Leave as "No Connect". GNT3#/GPIO55

4 4

GNT2#/GPIO53 GNT1#/GPIO51

SPI_MOSI

NV_ALE

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Connect to Vcc3_3 with 8.2-kΩ

No Reboot Mode with TCO Disabled:

- 10-kΩ weak pull-up resistor.

GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.

Enable Danbury:

Disable Danbury:

Enable Danbury:

Disable Danbury:

Huron River Schematic Checklist Rev.0_7

Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

Left floating, no pull-down required.

Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]

Leave floating (internal pull-down)

B

C

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[2]

PCI-Express Static Lane Reversal

CFG[4]

CFG[6:5]

CFG[7]

PCI-Express Port Bifurcation Straps

PEG DEFER TRAINING

1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded DisplayPort. Enabled - An external Display Port device is

0:

connectd to the EMBEDDED display Port

11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled

1:

PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

0:

D

Huron River Schematic Checklist Rev.0_7

Default Value

1

0

11

1

E

NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.

Low (0) - Flash Descriptor Security will be overridden. Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features.

HAD_DOCK_EN# /GPIO[33]

3 3

High (1) - Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions.

HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. HDA_SYNC

GPIO15

GPIO8

2 2

GPIO27

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no

confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality

Note : This is an un-muxed signal. This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1-kohm pull-up on this signal to +3.3VA rail.

GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled.

Default = Do not connect (floating)

High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.

POWER PLANE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_S5

VOLTAGE DESCRIPTION

5V

3.3V

1.8V

1.5V

1.05V

0.95 - 0.85V

0.75V

0.35V to 1.5V

0.4 to 1.25V

1.8V

3.3V 1V

5V

1.5V

0.75V

6V-14.1V 6V-14.1V 5V 5V

3.3V

3.3V3D3V_LAN_S5

3.3V

Voltage Rails

ACTIVE IN

S0

CPU Core Rail Graphics Core Rail

S3

AC Brick Mode only

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

USB Table

Pair Device

X

PCIE Routing

LANE1 LANE2 LANE3

1 1

LANE5 LANE6 LANE7 LANE8 NEW CARD

RESERVED

LAN CARD READER MiniCard WLANLANE4

RESERVED RESERVED RESERVED

SATA Table

SATA

Pair

0 1 2 3 4 5

Device

HDD mSATA

N/A N/A

ODD ESATA

0

USB2

1

FINGERPRINT

2

BLUETOOTH

3

Mini Card2 (WWAN)

4

X

5

X

6

X

7

ESATA1

8

USB1

9

USB Ext. port 4

10

Mini Card1 (WLAN)

11

CAMERA

12

New Card

13

SMBus ADDRESSES

2

I C / SMBus Addresses

Device

EC SMBus 1 Battery Capacity Board

EC SMBus 2 PCH MXM LCD Thermal Sensor

PCH SMBus CK505 Clock Generator SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot

Address Hex Bus Ref Des

HURON RIVER ORB

KBC_SDA1/KBC_SCL1 KBC_SDA1/KBC_SCL1

KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2

PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Table of Content

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

LLW-1 / LGG-1

3 94Tuesday, November 09, 2010

SB

5

4

3

2

1

SSID = CPU

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

1 OF 9

CPU1A

D D

C C

B B

NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Lane reversal does not apply to FDI sideband signals.

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

DMI_TXN[3..0]19

DMI_TXP[3..0]19

DMI_RXN[3..0]19

DMI_RXP[3..0]19

FDI_TXN[7:0]19

FDI_TXP[7:0]19

FDI_FSYNC019 FDI_FSYNC119

FDI_INT19 FDI_LSYNC019

FDI_LSYNC119

1D05V_VTT

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2

R403 10KR2J-3-GP

1 2

DY

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DP_COMP eDP_HPD

B27 B25 A25 B24

B28 B26 A24 B23

G21 E22 F21 D21

G22 D22 F20 C21

A21 H19 E19 F18 B21 C20 D18 E17

A22 G19 E20 G18 B20 C19 D19 F17

H20

H17

A18 A17 B16

C15 D15

C17 F16 C16 G15

C18 E16 D16 F15

J18 J17

J19

SANDY

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI0_FSYNC FDI1_FSYNC

FDI_INT FDI0_LSYNC

FDI1_LSYNC

EDP_COMPIO EDP_ICOMPO EDP_HPD

EDP_AUX EDP_AUX#

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3

SANDY

DMI

Intel(R) FDI

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11

PCI EXPRESS* - GRAPHICS

PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

1 OF 9

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_IRCOMP_R

PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0

PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0

PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0

PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

1 2

PEG_RXN[0..15]

C401 SCD1U6D3V1KX-GP

1 2

PX

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

PX PX

PX

C402 SCD1U6D3V1KX-GP

C402 SCD1U6D3V1KX-GP C403 SCD1U6D3V1KX-GP

C403 SCD1U6D3V1KX-GP C404 SCD1U6D3V1KX-GP

C404 SCD1U6D3V1KX-GP C405 SCD1U6D3V1KX-GP

C405 SCD1U6D3V1KX-GP C406 SCD1U6D3V1KX-GP

C406 SCD1U6D3V1KX-GP C407 SCD1U6D3V1KX-GP

C407 SCD1U6D3V1KX-GP C408 SCD1U6D3V1KX-GP

C408 SCD1U6D3V1KX-GP C409 SCD1U6D3V1KX-GP

C409 SCD1U6D3V1KX-GP C410 SCD1U6D3V1KX-GP

C410 SCD1U6D3V1KX-GP C411 SCD1U6D3V1KX-GP

C411 SCD1U6D3V1KX-GP C412 SCD1U6D3V1KX-GP

C412 SCD1U6D3V1KX-GP C413 SCD1U6D3V1KX-GP

C413 SCD1U6D3V1KX-GP C414 SCD1U6D3V1KX-GP

C414 SCD1U6D3V1KX-GP C415 SCD1U6D3V1KX-GP

C415 SCD1U6D3V1KX-GP C416 SCD1U6D3V1KX-GP

C416 SCD1U6D3V1KX-GP C417 SCD1U6D3V1KX-GP

C417 SCD1U6D3V1KX-GP C418 SCD1U6D3V1KX-GP

C418 SCD1U6D3V1KX-GP C419 SCD1U6D3V1KX-GP

C419 SCD1U6D3V1KX-GP C420 SCD1U6D3V1KX-GP

C420 SCD1U6D3V1KX-GP C421 SCD1U6D3V1KX-GP

C421 SCD1U6D3V1KX-GP C422 SCD1U6D3V1KX-GP

C422 SCD1U6D3V1KX-GP C423 SCD1U6D3V1KX-GP

C423 SCD1U6D3V1KX-GP C424 SCD1U6D3V1KX-GP

C424 SCD1U6D3V1KX-GP C425 SCD1U6D3V1KX-GP

C425 SCD1U6D3V1KX-GP C426 SCD1U6D3V1KX-GP

C426 SCD1U6D3V1KX-GP C427 SCD1U6D3V1KX-GP

C427 SCD1U6D3V1KX-GP C428 SCD1U6D3V1KX-GP

C428 SCD1U6D3V1KX-GP C429 SCD1U6D3V1KX-GP

C429 SCD1U6D3V1KX-GP C430 SCD1U6D3V1KX-GP

C430 SCD1U6D3V1KX-GP C431 SCD1U6D3V1KX-GP

C431 SCD1U6D3V1KX-GP C432 SCD1U6D3V1KX-GP

C432 SCD1U6D3V1KX-GP

1D05V_VTT

PEG_RXN[0..15] 83

PEG_RXP[0..15]

NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect

PEG Static Lane Reversal

PEG_RXP[0..15] 83

PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0

PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0

PEG_TXN[0..15] 83

PEG_TXP[0..15] 83

Table 4.1- Central Processing Unit slot multi-source

Supplier

FOXCONN

TYCO

A A

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

Description Lenovo P/N Wistron P/N

PZ98827-364B-41F

N/A 62.10055.421

N/A2-2013620-3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (PCIE/DMI/FDI)

LLW-1 / LGG-1

Tuesday, November 09, 2010

LLW-1 / LGG-1

4 94

62.10040.771

SB

SSID = CPU

5

1D05V_VTT

R501 62R2J-GPR501 62R2J-GP

1 2

D D

H_PROCHOT#

12

C502

C502 SC47P50V2JN-3GP

SC47P50V2JN-3GP

H_SNB_IVB#18

4

CPU1B

SANDY

C26

SNB_IVB#

SKTOCC#_R

1

TP501TPAD14-GP TP501TPAD14-GP

1

TP502TPAD14-GP TP502TPAD14-GP

H_CATERR#

AN34

AL33

SKTOCC#

CATERR#

MISCTHERMALPWR MANAGEMENT

3

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

2 OF 9

BCLK

BCLK#

A28 A27

A16 A15

CLK_DP_P_R CLK_DP_N_R

CLK_EXP_P 20 CLK_EXP_N 20

CLK_DP_P_R 20 CLK_DP_N_R 20

2

Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted.

RN502

CLK_DP_P_R CLK_DP_N_R

RN502

1 2 3

SRN1KJ-11-GP-U

DY

1

1D05V_VTT

4

H_PECI22,27

R513

H_PROCHOT#27,42

Connect EC to PROCHOT# through inverting OD buffer.

R506

1 2

H_CPUPW RGD_R

10KR2J-3-GP

C C

H_THERMTRIP#22,36,85

H_PM_SYNC19

H_CPUPW RGD22,36

PM_DRAM_PWRGD19,37

VDDPWRGOOD37

12

R502

R502 1KR2J-1-GP

1KR2J-1-GP

1 2

R504 0R2J-2-GPR504 0R2J-2-GP

R505

1D05V_VTT3D3V_S0

B B

D

Q501

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.031

S

G

PLT_RST#18,27,32,36,65,66,71,80,82,83

G

H_PROCHOT#_R

56R2F-1-GP

H_CPUPW RGD_R

DY

VDDPWRGOOD XDP_TMS

1 2

12

D

0R2J-2-GP

BUF_PLT_RST#

R509

R509 75R2F-2-GP

75R2F-2-GP

R512

R512 43R2J-GP

43R2J-GP

1 2

Q502

Q502 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.031

S

AN33

AL32

AN32

AM34

AP33

AR33

BUF_PLT_RST#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

V8

SM_DRAMPWROK

RESET#

SANDY

DDR3

JTAG & BPM

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

MISC

R8

SM_RCOMP_0

AK1

SM_RCOMP_1

A5

SM_RCOMP_2

A4

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils.

AP29

PRDY#

AP27

PREQ#

AR26

TCK

AR27

TMS

AP30

TRST#

AR28

TDI

AP26

TDO

AL35

DBR#

XDP_BPM0

AT28

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

XDP_BPM1

AR29

XDP_BPM2

AR30

XDP_BPM3

AT30

XDP_BPM4

AP32

XDP_BPM5

AR31

XDP_BPM6

AT31

XDP_BPM7

AR32

XDP_DBRESET# XDP_PREQ# XDP_PRDY# XDP_TDO XDP_TDI XDP_TRST# XDP_TCLK XDP_TMS

R508 140R2F-GPR508 140R2F-GP R507 25D5R2F-GPR507 25D5R2F-GP R510 200R2F-L-GPR510 200R2F-L-GP

XDP_PRDY# XDP_PREQ#

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

1 1 1 1 1 1 1 1

1 2 1 2 1 2

TP503TP503 TP504TP504 TP505TP505 TP506TP506 TP507TP507 TP508TP508 TP509TP509 TP510TP510

XDP_DBRESET# 11,19 XDP_PREQ# 11 XDP_PRDY# 11

1

TP511TP511

1

TP512TP512

1

TP513TP513

1

TP514TP514

1

TP515TP515

SM_DRAMRST# 37

R503

R503 4K99R2F-L-GP

4K99R2F-L-GP

1 2

XDP_TDI XDP_TDO

XDP_TCLK

XDP_TRST#

R511 51R2J-2-GPR511 51R2J-2-GP

1 2

XDP_DBRESET#

Table 5.1- N-Channel MOSFET multi-source

Supplier

PANJIT

Description Lenovo P/N Wistron P/N

2N7002K

DIODES

1D05V_VTT

RN501

4 5 3

6

2

7

1

8

SRN51J-1-GP

R516 1KR2J-1-GPR516 1KR2J-1-GP

1 2

N/A 84.2N702.J31

N/A2N7002K

3D3V_S0

84.2N702.031

84.07002.I31NXP N/A2N7002BK

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (Thermal/CLK/PM)

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

LLW-1 / LGG-1

5 94Tuesday, November 09, 2010

SB

5

4

3

2

1

SSID = CPU

4 OF 9

3 OF 9

CPU1C

SANDY

M_A_DQ[63:0]14 M_B_DQ[63:0]15

D D

C C

B B

M_A_DQ[63:0]

M_A_BS014 M_A_BS114 M_A_BS214

M_A_CAS#14 M_A_RAS#14 M_A_WE#14

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AK8 AK9

AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9 AF9

C5

SA_DQ0

D5

SA_DQ1

D3

SA_DQ2

D2

SA_DQ3

D6

SA_DQ4

C6

SA_DQ5

C2

SA_DQ6

C3

SA_DQ7

F10

SA_DQ8

F8

SA_DQ9 SA_DQ10

G9

SA_DQ11

F9

SA_DQ12

F7

SA_DQ13

G8

SA_DQ14

G7

SA_DQ15

K4

SA_DQ16

K5

SA_DQ17

K1

SA_DQ18

J1

SA_DQ19

J5

SA_DQ20

J4

SA_DQ21

J2

SA_DQ22

K2

SA_DQ23

M8

SA_DQ24 SA_DQ25

N8

SA_DQ26

N7

SA_DQ27 SA_DQ28

M9

SA_DQ29

N9

SA_DQ30

M7

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37

AJ5

SA_DQ38

AJ6

SA_DQ39

AJ8

SA_DQ40 SA_DQ41

AJ9

SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55

V6

SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

3 OF 9

SA_CLK0

SA_CLK#0

SA_CKE0

SA_CLK1

SA_CLK#1

SA_CKE1

SA_CLK2

SA_CLK#2

SA_CKE2

SA_CLK3

SA_CLK#3

SA_CKE3

SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3

SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DIM0_CLK_DDR0 14 M_A_DIM0_CLK_DDR#0 14 M_A_DIM0_CKE0 14

M_A_DIM0_CLK_DDR1 14 M_A_DIM0_CLK_DDR#1 14 M_A_DIM0_CKE1 14

M_A_DIM0_CS#0 14 M_A_DIM0_CS#1 14

M_A_DIM0_ODT0 14 M_A_DIM0_ODT1 14

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQS#[7:0] 14

M_A_DQS[7:0] 14

M_A_A[15:0] 14

M_B_DQ[63:0]

M_B_BS015 M_B_BS115 M_B_BS215

M_B_CAS#15 M_B_RAS#15 M_B_WE#15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12

AH12

AT11 AN14 AR14

AT14

AT12 AN15 AR15

AT15

AA9 AA7

AA10

AB8 AB9

CPU1D

SANDY

C9

SB_DQ0

A7

SB_DQ1 SB_DQ2

C8

SB_DQ3

A9

SB_DQ4

A8

SB_DQ5

D9

SB_DQ6

D8

SB_DQ7

G4

SB_DQ8

F4

SB_DQ9

F1

SB_DQ10

G1

SB_DQ11

G5

SB_DQ12

F5

SB_DQ13

F2

SB_DQ14

G2

SB_DQ15

J7

SB_DQ16

J8

SB_DQ17 SB_DQ18

K9

SB_DQ19

J9

SB_DQ20

J10

SB_DQ21

K8

SB_DQ22

K7

SB_DQ23

M5

SB_DQ24

N4

SB_DQ25

N2

SB_DQ26

N1

SB_DQ27

M4

SB_DQ28

N5

SB_DQ29

M2

SB_DQ30

M1

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54

R6

SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

4 OF 9

SB_CLK0

SB_CLK#0

SB_CKE0

SB_CLK1

SB_CLK#1

SB_CKE1

SB_CLK2

SB_CLK#2

SB_CKE2

SB_CLK3

SB_CLK#3

SB_CKE3

SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_B_DIM0_CLK_DDR0 15 M_B_DIM0_CLK_DDR#0 15 M_B_DIM0_CKE0 15

M_B_DIM0_CLK_DDR1 15 M_B_DIM0_CLK_DDR#1 15 M_B_DIM0_CKE1 15

M_B_DIM0_CS#0 15 M_B_DIM0_CS#1 15

M_B_DIM0_ODT0 15 M_B_DIM0_ODT1 15

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQS#[7:0] 15

M_B_DQS[7:0] 15

M_B_A[15:0] 15

SANDY

A A

5

4

3

SANDY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDR)

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, November 09, 2010

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

LLW-1 / LGG-1

1

6 94

SB

5

4

3

2

1

SSID = CPU

CFG011

TP701TP701

D D

TP714TP714 TP715TP715

TP702TP702

TP703TP703 TP704TP704 TP705TP705 TP706TP706 TP707TP707 TP708TP708 TP709TP709 TP710TP710 TP711TP711 TP712TP712

VCC_VALIDATION_SENSE

1

VSS_VALIDATION_SENSE

1

M3 - Processor Generated SO-DIMM VREF_DQ

DY

R708 0R2J-2-GP

M_VREF_DQ_DIMM014,37

C C

B B

M_VREF_DQ_DIMM115

M_VREF_CA_DIMM014 M_VREF_CA_DIMM115

1 2

R709 0R2J-2-GP

1 2

DY

DY DY

DY

R707 0R2J-2-GP

1 2

R706 0R2J-2-GP

1 2

DY

12

R711

R711 1KR2F-3-GP

1KR2F-3-GP

CFG0 CFG1

1

CFG2 CFG3

1

CFG4 CFG5 CFG6 CFG7 CFG8

1

CFG9

1

CFG10

1

CFG11

1

CFG12

1

CFG13

1

CFG14

1

CFG15

1

CFG16

1

CFG17

1

B4:VREF_DQ CHA

M_VREF_DQ_DIMM0_C M_VREF_CA_DIMM0_CM_VREF_CA_DIMM0_C

D1:VREF_DQ CHB

12

R712

R712 1KR2F-3-GP

1KR2F-3-GP

3D3V_S5

20 mils

12

R710

R710 10KR2J-3-GP

10KR2J-3-GP

H_VCCP_SEL

AK28 AK29 AL26 AL27 AK26 AL29

AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27

AK31 AN29

AJ31

AH31

AJ33

AH33

AJ26

F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29

B18 A19

B4 D1

J20

J15

CPU1E

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

RSVD#AJ31 RSVD#AH31 RSVD#AJ33 RSVD#AH33

RSVD#AJ26

RSVD#B4 RSVD#D1

RSVD#F25 RSVD#F24 RSVD#F23 RSVD#D24 RSVD#G25 RSVD#G24 RSVD#E23 RSVD#D23 RSVD#C30 RSVD#A31 RSVD#B30 RSVD#B29 RSVD#D30 RSVD#B31 RSVD#A30 RSVD#C29

RSVD#J20 RSVD#B18 RSVD#A19

RSVD#J15

SANDY

RESERVED

5 OF 9

RSVD#L7 RSVD#AG7 RSVD#AE7 RSVD#AK2

RSVD#W8

RSVD#AT26

RSVD#AM33

RSVD#AJ27

RSVD#T8

RSVD#J16 RSVD#H16

RSVD#G16

RSVD#AR35

RSVD#AT34 RSVD#AT33 RSVD#AP35

RSVD#AR34

RSVD#B34 RSVD#A33 RSVD#A34 RSVD#B35 RSVD#C35

RSVD#AJ32 RSVD#AK32

RSVD#AH27

RSVD#AN35 RSVD#AM35

RSVD#AT2 RSVD#AT1 RSVD#AR1

L7 AG7 AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

AN35 AM35

AT2 AT1 AR1

VCC_DIE_SENSE

PCIE_CLK_XDP_P 11,20 PCIE_CLK_XDP_N 11,20

1

CFG2

TP716TP716

12

PX

R702

R702 1KR2J-1-GP

1KR2J-1-GP

PEG Static Lane Reversal

CFG2

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

CFG7

12

DY

R705

R705 1KR2J-1-GP

1KR2J-1-GP

CFG5 CFG6

A A

12

DY

R701

R701 1KR2J-1-GP

1KR2J-1-GP

12

DY

R704

R704 1KR2J-1-GP

1KR2J-1-GP

5

PEG DEFER TRAINING

1: PEG Train immediately following xxRESETB de assertion

CFG7

0: PEG Wait for BIOS for training

PCIE Port Bifurcation Straps

CFG[6:5]

11: x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

4

3

CFG4

12

DY

R703

R703 1KR2J-1-GP

1KR2J-1-GP

Display Port Presence Strap CFG4

2

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

Title

CPU (RESERVED)

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, November 09, 2010

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

LLW-1 / LGG-1

1

7 94

SB

5

SSID = CPU

PROCESSOR CORE POWER

D D

C C

B B

A A

VCC_CORE

12

C801

SC10U6D3V3MX-GP

12

C815

SC10U6D3V3MX-GP

12

C816

SC10U6D3V5KX-1GP

12

C837

SC10U6D3V5KX-1GP

53A

12

C803

C802

SC10U6D3V3MX-GP

12

C818

C817

SC10U6D3V3MX-GP

12

C821

C822

SC10U6D3V5KX-1GP

12

C836

C835

SC10U6D3V5KX-1GP

VCC Output Decoupling Recommendation: 4 x 470 uF at Bottom Socket Edge 8 x 22 uF at Top Socket Cavity 8 x 22 uF at Top Socket Edge 8 x 22 uF at Bottom Socket Cavity

5

12

C811

C804

SC10U6D3V3MX-GP

12

C820

C819

SC10U6D3V3MX-GP

12

C823

SC10U6D3V5KX-1GP

12

C834

SC10U6D3V5KX-1GP

12

C824

C825

SC10U6D3V5KX-1GP

12

C832

C833

SC10U6D3V5KX-1GP

12

C826

SC10U6D3V5KX-1GP

12

C831

SC10U6D3V5KX-1GP

4

POWER

CPU1F

VCC_CORE

AG35

VCC

AG34

VCC

AG33

VCC

AG32

VCC

AG31

VCC

AG30

VCC

AG29

VCC

AG28

VCC

AG27

VCC

AG26

VCC

AF35

VCC

AF34

VCC

AF33

VCC

AF32

VCC

AF31

VCC

AF30

VCC

AF29

VCC

AF28

VCC

AF27

VCC

AF26

VCC

AD35

VCC

AD34

VCC

AD33

VCC

AD32

VCC

AD31

VCC

AD30

VCC

AD29

VCC

AD28

VCC

AD27

VCC

AD26

VCC

AC35

VCC

AC34

VCC

AC33

VCC

AC32

VCC

12

C827

SC10U6D3V5KX-1GP

12

C828

SC10U6D3V5KX-1GP

4

AC31 AC30 AC29 AC28 AC27 AC26

AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

SANDY

POWER

SANDY

CORE SUPPLY

SENSE LINES SVID

3

PEG AND DDR

VCCIO_SENSE VSSIO_SENSE

3

6 OF 9

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE

VSS_SENSE

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

VCCIO Output Decoupling Recommendation: 2 x 330 uF (3 x 330 uF for 2012 capable designs) 5 x 22 uF & 5 x 0805 no-stuff at Bottom 7 x 22 uF & 2 x 0805 no-stuff at Top

12

C806

C805

SC10U6D3V5KX-1GP

No-stuff sites outside the socket may be removed. No-stuff sites inside the socket cavity need to remain.

12

C812

SC10U6D3V5KX-1GP

For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7 For CRB VIDALERT# need to pull high 75 ohm close to CPU

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

R803 43R2J-GPR803 43R2J-GP

R801, R802 need to close to CPU

VCCIO_SENSE 45 VSSIO_SENSE 45

12

C813

SC10U6D3V5KX-1GP

1 2

VCC_CORE

SC10U6D3V5KX-1GP

12

R801

R801 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R802

R802 100R2F-L1-GP-U

100R2F-L1-GP-U

2

1D05V_VTT

12

C807

12

C814

12

C808

SC10U6D3V5KX-1GP

12

C829

SC10U6D3V5KX-1GP

C809

12

C830

H_CPU_SVIDDAT

C810

SC10U6D3V5KX-1GP

12

C842

SC10U6D3V5KX-1GP

12

C839

C838

SC10U6D3V5KX-1GP

1D05V_VTT

12

C844

C843

SC10U6D3V5KX-1GP

R804 130R2F-1-GPR804 130R2F-1-GP

1 2

12

C840

SC10U6D3V5KX-1GP

12

C845

SC10U6D3V5KX-1GP

1D05V_VTT

1

12

C841

S-HS_20100610 V1.0

VR_SVID_ALERT# 42

H_CPU_SVIDCLK 42

H_CPU_SVIDDAT 42

VCCSENSE 42 VSSSENSE 42

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_CORE)

Size Document Number Rev

Size Document Number Rev Custom

Custom

Tuesday, November 09, 2010

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

LLW-1 / LGG-1

1

8 94

SB

5

VAXG Output Decoupling Recommendation:

SSID = CPU

VCC_GFXCORE

2 x 470 uF at Bottom Socket Edge 2 x 22 uF at Top Socket Cavity 4 x 22 uF at Top Socket Edge 2 x 22 uF at Bottom Socket Cavity 4 x 22 uF at Bottom Socket Edge

PROCESSOR VAXG: 24A

D D

12

C901

SC10U6D3V5KX-1GP

12

C907

SC10U6D3V5KX-1GP

C C

Disabling Guidelines for External Graphics Designs: Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed. Can be left floating (Gfx VR keeps VAXG rail from floating)

B B

if the VR is stuffed

12

C903

C902

SC10U6D3V5KX-1GP

12

C918

C908

SC10U6D3V5KX-1GP

1D8V_S0

SC10U6D3V5KX-1GP

VCCPLL Output Decoupling Recommendation: 1 x 330 uF 2 x 1 uF 1 x 10 uF

4

12

C904

SC10U6D3V5KX-1GP

12

C919

SC10U6D3V5KX-1GP

C905

C920

C906

SC10U6D3V5KX-1GP

12

C921

SC10U6D3V5KX-1GP

PROCESSOR VCCPLL: 1.2A

12

C925

SC10U6D3V5KX-1GP

C923

12

C922

SC1U10V2KX-1GP

3

POWER

CPU1G

AT24

VAXG

AT23

VAXG

AT21

VAXG

AT20

VAXG

AT18

VAXG

AT17

VAXG

AR24

VAXG

AR23

VAXG

AR21

VAXG

AR20

VAXG

AR18

VAXG

AR17

VAXG

AP24

VAXG

AP23

VAXG

AP21

VAXG

AP20

VAXG

AP18

VAXG

AP17

VAXG

AN24

VAXG

AN23

VAXG

AN21

VAXG

AN20

VAXG

AN18

VAXG

AN17

VAXG

AM24

VAXG

AM23

VAXG

AM21

VAXG

AM20

VAXG

AM18

VAXG

AM17

VAXG

AL24

VAXG

AL23

VAXG

AL21

VAXG

AL20

VAXG

AL18

VAXG

AL17

VAXG

AK24

VAXG

AK23

VAXG

AK21

VAXG

AK20

VAXG

AK18

VAXG

AK17

VAXG

AJ24

VAXG

AJ23

VAXG

AJ21

VAXG

AJ20

VAXG

AJ18

VAXG

AJ17

VAXG

AH24

VAXG

AH23

VAXG

AH21

VAXG

AH20

VAXG

AH18

VAXG

AH17

VAXG

B6

VCCPLL

A6

VCCPLL

A2

12

C924

VCCPLL

SANDY

POWER

SANDY

GRAPHICS

1.8V RAIL

SENSE

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

VAXG_SENSE

VSSAXG_SENSE

LINES

SM_VREF

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCSA_SENSE

FC_C22

VCCSA_VID1

7 OF 9

AK35 AK34

VCC_AXG_SENSE 42 VSS_AXG_SENSE 42

Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation.

+V_SM_VREF_CNT should have 10 mil trace width

+V_SM_VREF_CNT

AL1

Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

12

SC10U6D3V5KX-1GP

C909

SC10U6D3V5KX-1GP

+V_SM_VREF_CNT 37

PROCESSOR VDDQ: 10A

12

C910

PROCESSOR VCCSA: 6A

12

C916

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

RN901

RN901 SRN1KJ-7-GP

SRN1KJ-7-GP

VCCSA_SENSE

H_FC_C22 VCCSA_SEL

0D85V_S0

1

23

4

SC10U6D3V5KX-1GP

12

R902

R902 10R2J-2-GP

10R2J-2-GP

H_FC_C22 48 VCCSA_SEL 48

2

R906,R907 close to CPU

1D5V_S0

12

SC10U6D3V5KX-1GP

C911

12

C915

C912

SC10U6D3V5KX-1GP

0D85V_S0

12

C917

SC10U6D3V5KX-1GP

R902 need be close to pin H23.

VCCSA_SENSE 48

12

C914

C913

SC10U6D3V5KX-1GP

VDDQ Output Decoupling Recommendation: 1 x 330 uF 6 x 10 uF

TC903

TC903 ST330U2VDM-4-GP

ST330U2VDM-4-GP

79.33719.20L

VCCSA Output Decoupling Recommendation: 1 x 330 uF 2 x 10 uF at Bottom Socket Cavity 1 x 10 uF at Bottom Socket Edge

VCC_GFXCORE

VCC_AXG_SENSE VSS_AXG_SENSE

S-HR_20100609 V1.0

1

12

R906

R906 100R2F-L1-GP-U

100R2F-L1-GP-U

R907

R907 100R2F-L1-GP-U

100R2F-L1-GP-U

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_GFXCORE)

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, November 09, 2010

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

LLW-1 / LGG-1

1

9 94

SB

5

4

3

2

1

SSID = CPU

9 OF 9

8 OF 9

CPU1H

AT35

VSS

AT32

VSS

AT29

VSS

AT27

VSS

AT25

VSS

AT22

VSS

D D

C C

B B

AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

M34

H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26

L33 L30 L27

K35 K32 K29 K26 J34 J31

F34 F31 F29

CPU1I

SANDY

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

P9

VSS

P8

VSS

P6

VSS

P5

VSS

P3

VSS

P2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L9

VSS

L8

VSS

L6

VSS

L5

VSS

L4

VSS

L3

VSS

L2

VSS

L1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H9

VSS

H8

VSS

H7

VSS

H6

VSS

H5

VSS

H4

VSS

H3

VSS

H2

VSS

H1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

9 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

SANDY

A A

5

4

3

SANDY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, November 09, 2010

Date: Sheet of

2

Date: Sheet of

CPU (VSS)

LLW-1 / LGG-1

Taipei Hsien 221, Taiwan, R.O.C.

10 94

1

SB

5

4

3

2

1

D D

12

DY

R1110

R1110 200R2J-L1-GP

200R2J-L1-GP

PCH_TCK21

PCH_TMS21 PCH_TDI21

PCH_TDO21

XDP_DBRESET#5,19

PCIE_CLK_XDP_N7,20

PCIE_CLK_XDP_P7,20

XDP_PRDY#5

XDP_PREQ#5

C C

1

TP1101TP1101

1

TP1102TP1102

1

CFG07

TP1103TP1103

1

TP1104TP1104

1

TP1105TP1105

PM_RSMRST#19

R1124 1KR2J-1-GP

1 2

DY

R1123 1KR2J-1-GP

1 2

DY

12

DY

R1116

R1116 100R2J-2-GP

100R2J-2-GP

12

DY

R1111

R1111 200R2J-L1-GP

200R2J-L1-GP

12

DY

R1117

R1117 100R2J-2-GP

100R2J-2-GP

12

DEBUG Interface for Processor.

CPU XDP SFF 26pin IF Pin 1 OBSFN_A0 (PREQ#, I/O) Pin 2 OBSFN_A1 (PRDY#, I/O) Pin 3 GND Pin 4 OBSDATA_A0 (Open, I/O)

B B

A A

Pin 5 OBSDATA_A1 (Open, I/O) Pin 6 GND Pin 7 OBSDATA_A2 (Open, I/O) Pin 8 OBSDATA_A3 (Open, I/O) Pin 9 GND Pin 10 HOOK0 (PWRGD, In) Pin 11 HOOK1 (BP_PWRGD_RST#, Out) Pin 12 HOOK2 (CFG0, Out) Pin 13 HOOK3 (vr_READYSYS_PWROK,Out) Pin 14 HOOK4 (BCLK, In) Pin 15 HOOK5 (BCLK#, In) Pin 16 VCCOBS_AB (VCCP Voltage of CPU, In) Pin 17 HOOK6 (RESET#, Out) Pin 18 HOOK7 (DBR#, Out) Pin 19 GND Pin 20 TDO, In Pin 21 TRST#, Out Pin 22 TDI, Out Pin 23 TMS, Out Pin 24 TCK1 (Open) Pin 25 GND Pin 26 TCK0 ,Out

TABLE

PCH PIN

TDO

TMS

TDI

TCK

TRST#

REF DES

R1110 R1116 R2 R1112 R1118 R91 R1111 R1117 R90 R541 R953 R535 R103

PCH ES1 JTAG

Enable EnableDisable Disable

DY DY DY DY DY DY 51 Ohms

200 Ohms

DY DY 200 Ohms 100 Ohms

DY DY 51 Ohms 51 Ohms 20K Ohms 10K Ohms

DY DY

20K Ohms 10K Ohms

DY DY

PCH ES2 JTAG

200 Ohms 100 Ohms

200 Ohms

100 Ohms100 Ohms

DY DY 200 Ohms 100 Ohms

51 Ohms 51 Ohms

DY

DY DY

DY DY DYDY

DY DY

PRODUCTION

Enable Disable

DY DY

51 Ohms

DY

DY 51 Ohms 51 Ohms

DY

DY DY DY DY DY DY DY DY DY

51 Ohms

DY DY DY

3D3V_S53D3V_S5

DY

R1112

R1112 200R2J-L1-GP

200R2J-L1-GP

DY

R1118

R1118 100R2J-2-GP

100R2J-2-GP

XDP1102

28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2

1

27

MLX-CON26-8-GP

DY

DEBUG Interface for PCH.

PCH XDP SFF 26pin IF Pin 1 OBSFN_A0 (Open), I/O) Pin 2 OBSFN_A1 (Open, I/O) Pin 3 GND Pin 4 OBSDATA_A0 (Open, I/O) Pin 5 OBSDATA_A1 (Open, I/O) Pin 6 GND Pin 7 OBSDATA_A2 (Open, I/O) Pin 8 OBSDATA_A3 (Open, I/O) Pin 9 GND Pin 10 HOOK0 (RSMRST#, In) Pin 11 HOOK1 (BP_PWRGD_RST#, Out) Pin 12 HOOK2 (Open) Pin 13 HOOK3 (Open) Pin 14 HOOK4 (Open) Pin 15 HOOK5 (Open) Pin 16 VCCOBS_AB (3.3VSUS, In) Pin 17 HOOK6 (RSMRST#, Out) Pin 18 HOOK7 (DBR#, Out) Pin 19 GND Pin 20 TDO (JTAG, In) Pin 21 TRST# (Open) Pin 22 TDI (JTAG, Out) Pin 23 TMS (JTAG, Out) Pin 24 TCK1 (Open) Pin 25 GND Pin 26 TCK0 (JTAG, Out)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

LOGIC

5

4

3

2

Title

XDP CONN

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

LLW-1 / LGG-1

1

SB

11 94Tuesday, November 09, 2010

SB

5

D D

C C

4

3

2

1

BLANK

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

LLW-1 / LGG-1

12 94Tuesday, November 09, 2010

1

SB

A

4 4

3 3

B

C

D

E

BLANK

2 2

Wistron Corporation

1 1

Title

CLOCK GEN

Size Document Number Rev

A4

Date: Sheet of

A

B

C

Date: Sheet of

D

CLOCK GEN

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

LLW-1 / LGG-1

13 94Tuesday, November 09, 2010

E

SB

5

SSID = MEMORY

DDR_VREF_S3

20100706

12

R1405

R1405 0R2J-2-GP

0R2J-2-GP

D D

M_VREF_CA_DIMM0

12

SCD1U10V2KX-5GP

DDR_VREF_S3

12

M_VREF_DQ_DIMM0

12

C C

SCD1U10V2KX-5GP

B B

A A

C1423

20100706

R1404

R1404 0R2J-2-GP

0R2J-2-GP

C1411

SC2D2U10V3KX-1GP

12

SC2D2U10V3KX-1GP

0D75V_S0

SC1U6D3V2KX-GP

DY

C1425

DY

C1412

12

C1419

C1424

SCD1U10V2KX-5GP

12

C1413

SCD1U10V2KX-5GP

Place these caps close to VTT1 and VTT2.

12

DY

C1420

SC1U6D3V2KX-GP

5

12

C1421

M_A_A[15:0] 6

M_A_BS26 M_A_BS06

M_A_BS16

M_A_DQ[63:0]6

12

DY

C1422

C1418

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

M_A_DQS#[7:0] 6 M_A_DQS[7:0] 6

M_A_DIM0_ODT06 M_A_DIM0_ODT16

M_VREF_CA_DIMM07 M_VREF_DQ_DIMM07,37

DDR3_DRAMRST#15,37

M_VREF_CA_DIMM0 M_VREF_DQ_DIMM0

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

0D75V_S0

H =9.2mm

4

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

2nd = 62.10017.T11

3rd = 62.10017.T61

DDR3-204P-82-GP

62.10017.U01

NP1 NP2

RAS#

WE#

CAS# CS0#

CS1# CKE0

CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

SCL

EVENT#

VDDSPD

SA0 SA1

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199 197

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6

M_A_DIM0_CS#0 6 M_A_DIM0_CS#1 6

M_A_DIM0_CKE0 6 M_A_DIM0_CKE1 6

M_A_DIM0_CLK_DDR0 6 M_A_DIM0_CLK_DDR#0 6

M_A_DIM0_CLK_DDR1 6 M_A_DIM0_CLK_DDR#1 6

TS#_DIMM0_1 15

SA0_DIM0 SA1_DIM0

3

PCH_SMBDATA 15,20,65,66 PCH_SMBCLK 15,20,65,66

1D5V_S3

79.33719.20L

3

12

C1401

C1401 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1D5V_S3

ST330U2VDM-4-GP

SCD1U10V2KX-5GP

3D3V_S0

12

DY

12

C1402

C1402 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

TC1401

SC10U6D3V5KX-1GP

C1414

SCD1U10V2KX-5GP

2

SA0_DIM0 SA1_DIM0

12

R1401

R1401 10KR2J-3-GP

10KR2J-3-GP

12

R1402

R1402 10KR2J-3-GP

10KR2J-3-GP

Thermal EVENT

TS#_DIMM0_1

R1403 10KR2J-3-GPR1403 10KR2J-3-GP

1 2

1

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

3D3V_S0

SODIMM A DECOUPLING

12

C1403

SC10U6D3V5KX-1GP

12

C1415

SCD1U10V2KX-5GP

C1404

C1416

DY

C1405

SC10U10V5ZY-1GP

12

C1417

SCD1U10V2KX-5GP

2

C1407

C1406

SC10U6D3V5KX-1GP

Layout Note: Place these Caps near SO-DIMMA.

SC10U10V5ZY-1GP

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

12

DY

C1409

C1408

SC10U6D3V5KX-1GP

Tuesday, November 09, 2010

12

DY

C1410

SC10U6D3V5KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DDR3-SODIMM1

LLW-1 / LGG-1

1

14 94

SB

5

SSID = MEMORY

M_B_A[15:0] 6

D D

C1521

M_B_DQ[63:0]6

M_VREF_CA_DIMM17

M_VREF_DQ_DIMM17

DDR3_DRAMRST#14,37

M_B_BS26 M_B_BS06

M_B_BS16

M_B_DQS#[7:0] 6 M_B_DQS[7:0] 6

M_B_DIM0_ODT06 M_B_DIM0_ODT16

M_VREF_CA_DIMM1 M_VREF_DQ_DIMM1

DDR_VREF_S3

R1504

R1504 0R2J-2-GP

0R2J-2-GP

1 2

M_VREF_CA_DIMM1

12

C1523

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

C C

DDR_VREF_S3

R1503

R1503 0R2J-2-GP

0R2J-2-GP

1 2

M_VREF_DQ_DIMM1

12

C1515

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

B B

0D75V_S0

SC1U6D3V2KX-GP

A A

DY

C1524

12

DY

C1516

12

DY

C1518

12

C1522

SCD1U10V2KX-5GP

12

C1517

SCD1U10V2KX-5GP

Place these caps close to VTT1 and VTT2.

12

C1519

SC1U6D3V2KX-GP

5

DY

C1520

12

SC1U6D3V2KX-GP

4

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

0D75V_S0

H = 5.2mm

4

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

2nd = 62.10017.T01

3rd = 62.10017.T51

DDR3-204P-83-GP

62.10017.T91

NP1 NP2

RAS#

WE#

CAS# CS0#

CS1# CKE0

CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA SCL

EVENT#

VDDSPD

SA0 SA1

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199 197

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

SA0_DIM1 SA1_DIM1

1D5V_S3

3

M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6

M_B_DIM0_CS#0 6 M_B_DIM0_CS#1 6

M_B_DIM0_CKE0 6 M_B_DIM0_CKE1 6

M_B_DIM0_CLK_DDR0 6 M_B_DIM0_CLK_DDR#0 6

M_B_DIM0_CLK_DDR1 6 M_B_DIM0_CLK_DDR#1 6

PCH_SMBDATA 14,20,65,66 PCH_SMBCLK 14,20,65,66

TS#_DIMM0_1 14

3

12

C1501

C1501 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

Layout Note: Place these Caps near SO-DIMMB.

1D5V_S3

2

3D3V_S0

DY

12

C1502

C1502 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

SODIMM B DECOUPLING

12

DY

C1503

SC10U10V5ZY-1GP

12

C1511

SCD1U10V2KX-5GP

2

DY

C1504

C1512

1

3D3V_S0

12

R1501

R1501 10KR2J-3-GP

10KR2J-3-GP

SA1_DIM1 SA0_DIM1

12

R1502

R1502 10KR2J-3-GP

10KR2J-3-GP

12

C1505

SC10U6D3V5KX-1GP

12

C1513

SCD1U10V2KX-5GP

12

C1506

SC10U6D3V5KX-1GP

12

C1514

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Tuesday, November 09, 2010

Date: Sheet of

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

SO-DIMMB is placed farther from the Processor than SO-DIMMA

12

DY

C1508

C1507

SC10U10V5ZY-1GP

C1509

SC10U6D3V5KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DDR3-SODIMM2

LLW-1 / LGG-1

12

DY

C1510

SC10U6D3V5KX-1GP

1

15 94

SB

5

D D

4

3

2

1

C C

B B

A A

5

(Blanking)

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM2

Size Document Number Rev

Size Document Number Rev A4

A4

Tuesday, November 09, 2010

Date: Sheet of

3

Date: Sheet of

2

DDR3-SODIMM2

LLW-1 / LGG-1

16 94

SB

1

5

D D

3D3V_S0

RN1701

1 2 3

SRN2K2J-1-GP

RN1702

1 2 3

SRN100KJ-6-GP

4

L_CTRL_DATA L_CTRL_CLK

L_BKLT_EN LVDS_VDD_EN

L_DDC_DATA(PAGE17): This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display

Place near PCH

C C

Impedance:90 ohm

Close to PCH side

CRT_RED CRT_GREEN CRT_BLUE

B B

678

RN1705

RN1705 SRN150F-1-GP

SRN150F-1-GP

123

4 5

4

12

R1701

R1701 2K37R2F-GP

2K37R2F-GP

3

4 OF 10

PCH1D

L_BKLT_EN27 LVDS_VDD_EN49

L_BKLT_CTRL49 LVDS_DDC_CLK49

LVDS_DDC_DATA49

TP1701TPAD14-GP TP1701TPAD14-GP

LVDSA_CLK#49 LVDSA_CLK49

LVDSA_DATA0#49 LVDSA_DATA1#49 LVDSA_DATA2#49

LVDSA_DATA049 LVDSA_DATA149 LVDSA_DATA249

CRT_DDC_CLK50

CRT_DDC_DATA50

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG LVDS_VBG

1

CRT_BLUE50

CRT_GREEN50

CRT_RED50

CRT_HSYNC50

CRT_VSYNC50

DAC_IREF_R

12

R1702

R1702 1KR2D-1-GP

1KR2D-1-GP

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

LVDS

CRT

Digital Display Interface

4 OF 10

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

DDBP_DATA2# DDBP_DATA2 DDBP_DATA1# DDBP_DATA1 DDBP_DATA0# DDBP_DATA0 DDBP_CLK# DDBP_CLK

2

3D3V_S0

4

RN1706

RN1706 SRN2K2J-1-GP

SRN2K2J-1-GP

1

2 3

PCH_HDMI_CLK 51 PCH_HDMI_DATA 51

C1708 SCD1U10V2KX-5GPC1708 SCD1U10V2KX-5GP

1 2

C1707 SCD1U10V2KX-5GPC1707 SCD1U10V2KX-5GP

1 2

C1706 SCD1U10V2KX-5GPC1706 SCD1U10V2KX-5GP

1 2

C1705 SCD1U10V2KX-5GPC1705 SCD1U10V2KX-5GP

1 2

C1704 SCD1U10V2KX-5GPC1704 SCD1U10V2KX-5GP

1 2

C1703 SCD1U10V2KX-5GPC1703 SCD1U10V2KX-5GP

1 2

C1702 SCD1U10V2KX-5GPC1702 SCD1U10V2KX-5GP

1 2

C1701 SCD1U10V2KX-5GPC1701 SCD1U10V2KX-5GP

1 2

DDI Port B Detect:(SDVO_CTRL_ DATA) 1: Port B detected 0: Port B not detected

Close to level shifter side

Impedance:90 ohm

1

PCH_HDMI_DET 51 HDMI_DATA2_R# 51

HDMI_DATA2_R 51

HDMI_DATA1_R# 51

HDMI_DATA1_R 51

HDMI_DATA0_R# 51

HDMI_DATA0_R 51

HDMI_CLK_R# 51

HDMI_CLK_R 51

Impedance:100 ohm

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, November 09, 2010

Date: Sheet of

PCH (LVDS/CRT/DDI)

LLW-1 / LGG-1

Taipei Hsien 221, Taiwan, R.O.C.

17 94

1

SB

5

4

3

2

1

SSID = PCH

3D3V_S0 3D3V_S0

RN1801

D D

SATA_ODD_DA# INT_PIRQD# INT_PIRQB# BDC_PRESENCE#

R1801 4K7R2J-2-GP

A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3 Low = A16 swap

C C

R1802 1KR2J-1-GP

1 2

R1803 1KR2J-1-GP

1 2

RN1801

1 2 3 4 5 6

SRN8K2J-2-GP-U

DY

12

override/Top-Block Swap Override enabled High = Default

DY

10

LCD_PRESENCE#

9 8 7

PCI_GNT3#

BBS_BIT1 BBS_BIT0

WWAN_IN INT_PIRQA# INT_PIRQC#

USB_OC#0_1 USB_OC#12_13 USB_OC#8_9 USB_OC#6_7 USB_OC#2_3

BBS_BIT0 21

BOOT BIOS Strap

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

0 0 LPC 0 1 Reserved

01

B B

A A

11

5

Reserved

SPI(Default)

CLK_PCI_LPC65,71 CLK_PCI_FB20 CLK_PCI_KBC27

3D3V_S5 3D3V_S5

RN1802

1 2 3 4 5 6

SRN8K2J-2-GP-U

DGPU_HOLD_RST# DGPU_PW R_EN#

DGPU_HOLD_RST#83

DGPU_PW R_EN#93

TP1804TP1804

LCD_PRESENCE#49 SATA_ODD_DA#56 BDC_PRESENCE#63 WWAN_IN66

R1804 22R2J-2-GPR1804 22R2J-2-GP R1805 22R2J-2-GPR1805 22R2J-2-GP R1806 22R2J-2-GPR1806 22R2J-2-GP

DY

EC1802

EC1802 SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

1 2

KBC CLK EMI

4

10

PCH_GPIO14

9 8

USB_OC#10_11

7

LAN_PW R_ON

RN1803

1 2 3

SRN10KJ-5-GP

3D3V_S0

R1814

R1814 8K2R2J-3-GP

8K2R2J-3-GP

1 2

DGPU_PW M_SELECT#

1

TP1801TP1801

TP1806TP1806

1 2 1 2 1 2

DY

EC1801

EC1801 SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

1 2

PLT_RST#5,27,32,36,65,66,71,80,82,83

4

DGPU_SELECT# DGPU_PW R_EN#

1

LCD_PRESENCE# SATA_ODD_DA# BDC_PRESENCE#

1

CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R

12

DY

R1816

R1816 100KR2J-1-GP

100KR2J-1-GP

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

BBS_BIT1 PCI_GNT3#

PCI_PME# PCI_PLTRST#

3D3V_S0

DY

PCH1E

Cougar

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

H3

AH12

AM4 AM5

Y13 K24

L24 AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

K40 K38

H38

G38

C46 C44 E40

D47 E42 F46

G42 G40

C42 D44

K10

C6

H49 H43

J48 K42 H40

DY

5

4

73.01G08.L04

2ND = 73.7SZ08.DAH

R1807 0R2J-2-GPR1807 0R2J-2-GP

12

C1801

C1801 SC220P50V2KX-3GP

SC220P50V2KX-3GP

Cougar

TP1

Point

TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PME# PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

COUGAR-GP-U2-NF

U1801

B

VCC

A

Y

GND

74LVC1G08GW-1-GP

1 2

3

5 OF 10

AY7

RSVD

AV7

RSVD

AU3

RSVD

BG4

RSVD

AT10

RSVD

BC8

RSVD

AU2

RSVD

AT4

RSVD

AT3

RSVD

AT1

RSVD

AY3

RSVD

AT5

RSVD

AV3

RSVD

AV1

RSVD

BB1

RSVD

BA3

RSVD

BB5

NVRAM

RSVD

PCI

USB

1 2 3

PCI_PLTRST#

12

RSVD RSVD RSVD RSVD RSVD RSVD

RSVD

DF_TVS

RSVD RSVD RSVD

RSVD RSVD

RSVD

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

USBP8N

USBP8P

USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

DY

C1802

C1802 SC220P50V2KX-3GP

SC220P50V2KX-3GP

BB3 BB7 BE8 BD4 BF6

NV_ALE

AV5

NV_CLE

AY1 AV10 AT8 AY5

BA2 AT12

BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_RBIAS

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

OC[3:0]# for Device 29 (Ports 0-7) OC[7:4]# for Device 26 (Ports 8-13)

R1811 22D6R2F-L1-GPR1811 22D6R2F-L1-GP

1 2

USB_OC#0_1 USB_OC#2_3 LAN_PW R_ON USB_OC#6_7 USB_OC#8_9 USB_OC#10_11 USB_OC#12_13 PCH_GPIO14

2

USB_PN1 61 USB_PP1 61 USB_PN2 69 USB_PP2 69 USB_PN3 63 USB_PP3 63 USB_PN4 66 USB_PP4 66

USB_PN8 57 USB_PP8 57 USB_PN9 61 USB_PP9 61 USB_PN10 82 USB_PP10 82 USB_PN11 65 USB_PP11 65 USB_PN12 49 USB_PP12 49 USB_PN13 82 USB_PP13 82

USB_OC#0_1 61 LAN_PW R_ON 31 USB_OC#8_9 57,61

USB_OC#10_11 82

Danbury Technology: Disabled when Low. Enable when High.

Title

Size Document Number Rev

A3

Date: Sheet of

NV_CLE

DMI & FDI Termination Voltage

NV_CLE

Pair

0 1 2 3 4 5 6 7 8 9 10 11 12 13

PCH (PCI/USB/NVRAM)

+V_NVRAM_VCCQ

12

R1808

R1808 2K2R2J-2-GP

2K2R2J-2-GP

R1809

1 2

1KR2J-1-GP

H_SNB_IVB# 5

Set to Vss when LOW Set to Vcc when HIGH

+V_NVRAM_VCCQ

NV_ALE

USB

Device X USB2

FINGERPRINT

BLUETOOTH Mini Card2 (WWAN) X X X ESATA1 USB1 USB Ext. port 4 Mini Card1 (WLAN) CAMERA

New Card

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

LLW-1 / LGG-1

18 94Tuesday, November 09, 2010

1

12

DY

R1810

R1810 1KR2J-1-GP

1KR2J-1-GP

SB

5

4

3

2

1

SSID = PCH

D D

Signal Routing Guideline: DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

PWROKSYS_PWROK

DY

R1926

R1926 10KR2J-3-GP

10KR2J-3-GP

1 2

C C

R1904

R1904 100KR2J-1-GP

100KR2J-1-GP

1 2

S0_PWR_GOOD27,36 D85V_PW RGD42,48

XDP_DBRESET#5,11

SYS_PWROK36

R1924 0R2J-2-GPR1924 0R2J-2-GP R1927 0R2J-2-GPR1927 0R2J-2-GP

RUNPWROK36,37,45,46,47

PM_DRAM_PWRGD5,37

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

SUS_PW R_ACK27

B B

A A

PM_PWRBTN#27

AC_PRESENT27

3D3V_S5

DY

RN1901

8 7 6

SRN10KJ-6-GP

R1921 10KR2J-3-GPR1921 10KR2J-3-GP R1922 10KR2J-3-GP

R1922 10KR2J-3-GP R1920 10KR2J-3-GPR1920 10KR2J-3-GP

Need Check!!

R1908 10KR2J-3-GPR1908 10KR2J-3-GP

5

1D05V_VTT

1 2 1 2

1 2 3 45

12 12 12

12

DMI_RXN[3..0]4 DMI_RXP[3..0]4

DMI_TXN[3..0]4 DMI_TXP[3..0]4

R1901 49D9R2F-GPR1901 49D9R2F-GP

1 2

R1902 750R2F-GPR1902 750R2F-GP

1 2

3D3V_S0

R1903 0R2J-2-GP

1 2

R1925 0R2J-2-GP

1 2

R1905 10KR2J-3-GPR1905 10KR2J-3-GP

1 2

R1923 0R2J-2-GP

1 2

R1906 0R2J-2-GPR1906 0R2J-2-GP

1 2

R1907 0R2J-2-GP

1 2

PM_RSMRST#11

AC_PRESENT SUS_PW R_ACK

PCIE_WAKE# PM_PWRBTN# PM_SLP_LAN#

PM_RSMRST#

PEG_B_CLK_RQ# 20

DMI_RXN34 DMI_RXN24 DMI_RXN14 DMI_RXN04

DMI_RXP34 DMI_RXP24 DMI_RXP14 DMI_RXP04

DMI_TXN34 DMI_TXN24 DMI_TXN14 DMI_TXN04

DMI_TXP34 DMI_TXP24 DMI_TXP14 DMI_TXP04

DMI_COMP_R

RBIAS_CPY

DY

DY DY

DY

BATLOW #20

PM_RI#20

SUSACK#SUS_PW R_ACK

SYS_RESET#

PWROK

MEPWROK

PM_RSMRST#

SUS_PW R_ACK

AC_PRESENT

PCIE_WAKE# CRB : 1K CEKLT: 10K

PM_RSMRST# CRB : PL 10K ANNIE : PL 100K

4

PCH1C

BC24

DMI0RXN

Cougar

BE20 BG18 BG20

BE24 BC20

BJ18 BJ20

AW24 AW20

BB18 AV18

AY24 AY20 AY18 AU18

BJ24 BG25 BH21

C12

K3

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

COUGAR-GP-U2-NF

Cougar

DMI1RXN

Point

DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP DMI_IRCOMP DMI2RBIAS

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPWRDNACK/GPIO30

PWRBTN#

ACPRESENT/GPIO31

BATLOW#/GPIO72

RI#

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5

DMI

System Power Management

3D3V_AUX_S5

FDI_RXP6

FDI

FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#/GPIO29

R1909 100KR2J-1-GPR1909 100KR2J-1-GP

1 2

12

R1916

R1916 10KR2J-3-GP

10KR2J-3-GP

3V_5V_POK_#

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

DSWODVREN

A18

PCH_DPW ROK

E22

PCIE_WAKE#

B9

PM_CLKRUN#

N3

PM_SUS_STAT#

G8

SUS_CLK

N14

PM_SLP_S5#

D10

SLP_S4#_R

H4

SLP_S3#_R

F4

PM_SLP_A#

G10

PM_SLP_SUS#

G16

H_PM_SYNC

AP14

PM_SLP_LAN#

K14

Q1901

34 2

5

1

6

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

3

FDI_TXN[7:0] 4 FDI_TXP[7:0] 4

FDI_TXN7 4 FDI_TXN6 4 FDI_TXN5 4 FDI_TXN4 4 FDI_TXN3 4 FDI_TXN2 4 FDI_TXN1 4 FDI_TXN0 4

FDI_TXP7 4 FDI_TXP6 4 FDI_TXP5 4 FDI_TXP4 4 FDI_TXP3 4 FDI_TXP2 4 FDI_TXP1 4 FDI_TXP0 4

FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4

DY

R1911 10KR2J-3-GP

1 2

R1910 0R2J-2-GPR1910 0R2J-2-GP

1 2

PCIE_WAKE# 65,82

PM_CLKRUN# 27

1

R1913 0R2J-2-GPR1913 0R2J-2-GP

1 2

1

R1914 0R2J-2-GPR1914 0R2J-2-GP

1 2

R1915 0R2J-2-GPR1915 0R2J-2-GP

1 2

1

PM_RSMRST#

3V_5V_POK 41

For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)

2.DPWROK and RSMRST# will rise at the same time (connected on board)

3.SLP_SUS# and SUSACK# are left as ‘no connect’

4.SUSWARN# used as SUSPWRDNACK/GPIO30

RTC_AUX_S5

PM_RSMRST#

TP1901 TPAD14-GPTP1901 TPAD14-GP

PCH_SUSCLK_KBC 27

TP1902 TPAD14-GPTP1902 TPAD14-GP

PM_SLP_S4# 27,46,82

PM_SLP_S3# 27,36,37,47,82

TP1903TPAD14-GPTP1903TPAD14-GP

TP1904TPAD14-GPTP1904TPAD14-GP

H_PM_SYNC 5

TP1905TPAD14-GPTP1905TPAD14-GP

R1912 1KR2J-1-GPR1912 1KR2J-1-GP

1 2

RSMRST#_KBC 27

2

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

RTC_AUX_S5

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1 2

DSWODVREN

PM_CLKRUN#

Title

Size Document Number Rev

A3

Date: Sheet of

R1918 330KR2J-L1-GP

1 2

DY

R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (DMI/FDI/PM)

LLW-1 / LGG-1

19 94Tuesday, November 09, 2010

1

3D3V_S0

SB

5

SSID = PCH

PCH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1#/GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2#/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4#/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5#/GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

COUGAR- GP-U2-NF

3D3V_S5

Cougar

Cougar Point

Point

LAN

Card Reader

WLAN

NEW CARD

RN2001

1 2 3 4 5

SRN10KJ-6-G P

RN2002

1 2 3 4 5

SRN10KJ-6-G P

8 7 6

1 2 3

PCIE_CLK_RQ1#

PEG_B_CLK_RQ #19

PCIE_RXN1 PCIE_RXP1 PCIE_TXN1_C PCIE_TXP1_C

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN3_C PCIE_TXP3_C

PCIE_TXN4_C PCIE_TXP4_C

PCIE_TXN8_C PCIE_TXP8_C

CLK_PCH_SR C0_N

4

CLK_PCH_SR C0_P

PCIE_CLK_LAN_R Q0#

CLK_PCH_SR C2_N CLK_PCH_SR C2_P

4

PCIE_CLK_CR_R Q2#

CLK_PCH_SR C3_N

4

CLK_PCH_SR C3_P

PCIE_CLK_WLA N_RQ3#

PCIE_CLK_RQ4#

CLK_PCH_SR C5_N

4

CLK_PCH_SR C5_P

PCIE_CLK_NEW _RQ5#

PCIE_CLK_RQ6#

PCIE_CLK_RQ7#

TP2004TPAD14-GP TP2004TPAD14-GP

1

TP2005TPAD14-GP TP2005TPAD14-GP

1

TP2006TPAD14-GP TP2006TPAD14-GP

1

TP2007TPAD14-GP TP2007TPAD14-GP

PCIE_RXN282

PCIE_RXP282 PCIE_TXN282 PCIE_TXP282

D D

PCIE_RXN332

PCIE_RXP332 PCIE_TXN332 PCIE_TXP332

PCIE_RXN465

PCIE_RXP465 PCIE_TXN465 PCIE_TXP465

PCIE_RXN882

PCIE_RXP882 PCIE_TXN882 PCIE_TXP882

LAN CLK

PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW. PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN

C C

CARD READER CLK

PCIE_CLK_LAN_R Q0#82

PCIE_CLK_CR_R Q2#32

WLAN CLK

PCIECLKRQ1# and PCIECLKRQ2#

3D3V_S0

support S0 power only

B B

PCIE_CLK_WLA N_RQ3#65

RN2018

PCIE_CLK_RQ1#

1

4

PCIE_CLK_CR_R Q2#

2 3

SRN10KJ-5-G P

PCIE_CLK_NEW _RQ5#82

PL 10K FOR Integrated CLOCK GEN mode.

CLK_BUF_RE F14 CLK_BUF_CP YCLK_N CLK_BUF_CP YCLK_P

1

C2001 SCD 1U10V2KX-5GPC 2001 SCD1U 10V2KX-5GP

1 2

C2002 SCD 1U10V2KX-5GPC 2002 SCD1U 10V2KX-5GP

1 2

C2003 SCD 1U10V2KX-5GPC 2003 SCD1U 10V2KX-5GP

1 2

C2004 SCD 1U10V2KX-5GPC 2004 SCD1U 10V2KX-5GP

1 2

C2005 SCD 1U10V2KX-5GPC 2005 SCD1U 10V2KX-5GP

1 2

C2006 SCD 1U10V2KX-5GPC 2006 SCD1U 10V2KX-5GP

1 2

C2009 SCD 1U10V2KX-5GPC 2009 SCD1U 10V2KX-5GP

1 2

C2010 SCD 1U10V2KX-5GPC 2010 SCD1U 10V2KX-5GP

1 2

CLK_PCIE_LAN#82 CLK_PCIE_LAN82

CLK_PCIE_CR#32 CLK_PCIE_CR32

CLK_PCIE_WLA N#65 CLK_PCIE_WLA N65

CLK_PCIE_NEW #82 CLK_PCIE_NEW82

RN2009

1 2 3 4 5 6

SRN10KJ-L3-G P

need very close to PCH

RN2012 SRN0J-6-GPRN2012 SRN0J-6-GP

RN2013 SRN0J-6-GPRN20 13 SRN0J-6-GP

RN2014 SRN0J-6-GPRN2014 SRN0J-6-GP

RN2015 SRN0J-6-GPRN2015 SRN0J-6-GP

PCIE_CLK_XDP_N7,11 PCIE_CLK_XDP_P7,11

10

CLK_BUF_EXP_N

9

CLK_BUF_EXP_P

8

CLK_BUF_DO T96_N

7

CLK_BUF_DO T96_P

2 3 1

1 2 3

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

PCI-E*

CLOCKS

PCIE_CLK_WLA N_RQ3#

PCIE_CLK_RQ7#

PCIE_CLK_NEW _RQ5#

PCIE_CLK_LAN_R Q0#

PCIE_CLK_RQ4#

EC_SWI#

4

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SML1CLK/GPIO58

SML1DATA/GPIO75

Link

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N

CLKIN_SATA_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67

FLEX CLOCKS

BATLOW# 19

PM_RI# 19

2 OF 10

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKIN_DMI_N

CLKIN_DMI_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

E12

SMB_CLK

H14

SMB_DATA

C9

DRAMRST_C NTRL_PCH

A12

SML0_CLK

C8

SML0_DATA

G12

PCH_GPIO74

C13

SML1_CLK

E14

SML1_DATA

M16

CL_CLK

M7

CL_DATA

T11

CL_RST#

P10

PEG_CLKREQ#_ R

M10

CLKOUT_PEG _A_N

AB37

CLKOUT_PEG _A_P

AB38

CLKOUT_DM I_N

AV22

CLKOUT_DM I_P

AU22

CLKOUT_DP _N

AM12

CLKOUT_DP _P

AM13

CLK_BUF_EXP_N

BF18

CLK_BUF_EXP_P

BE18

CLK_BUF_CP YCLK_N

BJ30

CLK_BUF_CP YCLK_P

BG30

CLK_BUF_DO T96_N

G24

CLK_BUF_DO T96_P

E24

CLK_BUF_CK SSCD_N

AK7

CLK_BUF_CK SSCD_P

AK5

CLK_BUF_RE F14

K45

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

JTAG_TCK

K43

CLK_48_USB30

F47

LAN_25M

H47

DGPU_PRSN T#

K49

EC_SWI# 27

SMB_CLK 80,82 SMB_DATA 80,82

DRAMRST_C NTRL_PCH 37

SML1_CLK 27 SML1_DATA 27

1

TP2001 TPAD14 -GPTP2001 TPAD 14-GP

1

TP2002 TPAD14 -GPTP2002 TPAD 14-GP

1

TP2003 TPAD14 -GPTP2003 TPAD 14-GP

PX

R2003 0R2J-2-GP

1 2

RN2016 SRN0J-6-GPRN2016 SRN0J-6-G P

1 2 3

RN2010 SRN0J-6-GPRN2010 SRN0J-6-G P

1 2 3

RN2017 SRN0J-6-GP

1 2 3

DY

2 3 1

R2007 90D9R2F-1-G PR2007 90D9R2F-1-GP

1 2

DY

22R2J-2-GP

1 2

1

1 2

DY

22R2J-2-GP

TP2008 TPAD14 -GPTP2008 TPAD 14-GP

22R2J-2-GP

R2001

R2015

4

CLK_PCIE_VGA# 83 CLK_PCIE_VGA 83

4

CLK_EXP_N 5 CLK_EXP_P 5

4

CLK_DP_N_R 5 CLK_DP_P_R 5

RN2011

4

SRN10KJ-5-G P

CLK_PCI_FB 18

+VCCDIFFC LKN

JTAG_TCK_VG A 83,85

For VGA_ 27M

LAN_XI 82

3

PEG_CLKREQ#_ R

SMB_DATA

SMB_CLK

PEG_CLKREQ# 85

3D3V_S5 3D3V_S5

12

R2004

R2004 10KR2J-3-GP

10KR2J-3-GP

12

DY

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

RN2007

2 3 1

SRN2K2J-1-G P

6

XTAL25_IN

XTAL25_OUT

3D3V_S0 3D3V_S0

12

R2012

R2012 10KR2J-3-GP

10KR2J-3-GP

12

DY

R2010

R2010 10KR2J-3-GP

10KR2J-3-GP

SMB_CLK SMB_DATA

SML0_DATA SML0_CLK

SML1_CLK SML1_DATA

PCIE_CLK_RQ6# PCH_GPIO74

DRAMRST_C NTRL_PCH

4

2nd = 84.DM601.03F

84.2N702.A3F

2N7002KDW -GP

1 2345

Q2001

DY

R2008 0R2J-2-GP

1 2

R2008 and C2008 CO-LAY

R2006

R2006 1M1R2J-GP

1M1R2J-GP

1 2

12

UMA

R2013

R2013 10KR2J-3-GP

10KR2J-3-GP

UMA_DIS# DGPU_PRSN T#

12

PX

R2011

R2011 10KR2J-3-GP

10KR2J-3-GP

1

4

23 23

1

4 2 3

1

4

1

4

2 3

1 2

R2009

CRB : 1K CEKLT: 10K

PCH_SMBDAT A 14,15,65,66

PCH_SMBCLK 14,15,65,66

C2008

12

X2001

SC12P50V2JN-3G P

XTAL-25MHZ- 96GP

1 2

C2007

12

SC12P50V2JN-3G P

UMA_DISCRETE# UMA: 1 1 DIS :0 1 SG(PX) : 0 0 Optimus(Muxless) : 1 0

UMA_DIS# 22

RN2003

RN2003 SRN2K2J-1-G P

SRN2K2J-1-G P RN2004

RN2004 SRN2K2J-1-G P

SRN2K2J-1-G P RN2005

RN2005 SRN2K2J-1-G P

SRN2K2J-1-G P RN2006

RN2006 SRN10KJ-5-G P

SRN10KJ-5-G P

1KR2J-1-GP

2

1

Table 20.1- Dual N-Channel MOSFET multi-source

Supplier

PANJIT

A A

DIODES

Description Lenovo P/N Wi stron P/N

2N7002KDW

N/A 84.2N702.A3F

84.DM601.03F

N/ADMN601DWK-7

84.2N702.E3FNXP N/A2N7002BKS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

PCH (PCI-E/SMBUS/CLOCK/CL)

Size Document Number Rev

A2

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

LLW-1 / LGG-1

1

SB

20 94Tuesd ay, November 0 9, 2010

SB

5

SSID = PCH

RTC_X1

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

1 2

D D

12

C2101

SC15P50V2JN-2-GP

C C

X-32D768KHZ-40GPU

HDA_CODEC_SYNC29 HDA_CODEC_SDOUT29

HDA_CODEC_RST#29 HDA_CODEC_BITCLK29

X2101

1

2 3

4

RTC_X2

12

C2102

C2102 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

RN2102

2 3 1

SRN33J-5-GP-U

12 12

4

RTC_AUX_S5

HDA_SYNC

R212233R2J-2-GP R212233R2J-2-GP

HDA_SDOUT

R212333R2J-2-GP R212333R2J-2-GP

HDA_RST# HDA_BITCLK

RN2104

2 3 1

SRN20KJ-GP-U

SC1U6D3V2KX-GP

Flash Descriptor Security Overide

+3VS_+1.5VS_HDA_IO

DY

R2115 1KR2J-1-GP

3D3V_S0

R2106 1KR2J-1-GP

+3VS_+1.5VS_HDA_IO

B B

This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310

DY

1 2

DY

1 2

R2103 1KR2J-1-GPR2103 1KR2J-1-GP

1 2

HDA_SDOUT

NO REBOOT STRAP

HDA_SPKR

HDA_SYNC

HDA_SDOUT

HDA_SPKR

Low = Default High = Enable

No Reboot Strap

Low = Default High = No Reboot

PLL ODVR VOLTAGE

HDA_SYNC

Low = 1.8V (Default) High = 1.5V

For EMI

HDA_BITCLK HDA_RST#

DY

12

EC2101

A A

EC2101

SCD1U10V2KX-5GP

12

5

HDA_CODEC_SDOUT SPI_CS0#_R

DY

EC2102

EC2102 SC22P50V2JN-4GP

SC22P50V2JN-4GP

DY

EC2103

EC2103 SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

1 2

4

12

C2104

DY

EC2105

EC2105 SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

1 2

4

3

SRTC_RST#

12

C2103

C2103 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

RTC_RST#

21

G2101

G2101 GAP-OPEN

GAP-OPEN

ME_UNLOCK27

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

INTVRMEN- Integrated SUS

1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs

RTC_AUX_S5

R2104 1M1R2J-GPR2104 1M1R2J-GP

1 2

R2105 330KR2F-L-GPR2105 330KR2F-L-GP

1 2

HDA_SPKR29

HDA_SDIN029

R2107 1KR2J-1-GPR2107 1KR2J-1-GP

1 2

PCH_TCK11 PCH_TMS11 PCH_TDI11

PCH_TDO11

SPI_CLK_R27,60 SPI_CS0#_R27,60

SPI_SI_R27,60

SPI_SO_R27,60

PCH1A

RTC_X1 RTC_X2 RTC_RST# SRTC_RST#

SM_INTRUDER# PCH_INTVRMEN

HDA_BITCLK HDA_SYNC

HDA_RST#

HDA_SDOUT

PCH_GPIO33

1

TP2105TPAD14-GP TP2105TPAD14-GP

PCH_TCK

SPI_CS0#_R

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

COUGAR-GP-U2-NF

PSW_CLR#22 MFG_MODE22 S_GPIO22

3

Cougar

Cougar Point

Point

RTCIHDA

JTAG

SPI

SRN10KJ-6-GP

PCH_GPIO33

PCH_TCK

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ1#/GPIO23

SATA0RXN

SATA1RXN

SATA 6G

SATA2RXN

SATA3RXN

SATA4RXN

SATA

SATA5RXN

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATA0GP/GPIO21 SATA1GP/GPIO19

RN2103

1 2 3 4 5

R2125 1KR2J-1-GP

R2102 51R2J-2-GPR2102 51R2J-2-GP

C38 A38 B37 C37

D36 E36

LDRQ0#

K36 V5

SERIRQ

AM3 AM1

SATA0RXP

AP7

SATA0TXN

AP5

SATA0TXP

AM10 AM8

SATA1RXP

AP11

SATA1TXN

AP10

SATA1TXP

AD7 AD5

SATA2RXP

AH5

SATA2TXN

AH4

SATA2TXP

AB8 AB10

SATA3RXP

AF3

SATA3TXN

AF1

SATA3TXP

Y7 Y5

SATA4RXP

AD3

SATA4TXN

AD1

SATA4TXP

Y3 Y1

SATA5RXP

AB3

SATA5TXN

AB1

SATA5TXP

Y11 Y10

AB12 AB13

AH1

P3

SATALED#

V14 P1

3D3V_S0 3D3V_S0

8 7 6

DY

12

1 2

2

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

SATA_COMP

SATA3_COMP

RBIAS_SATA3

BBS_BIT0

2

Table 21.1 Project_ID

LPC_AD[0..3]

LPC_FRAME# 27,65,71

LW_GG_SEL

INT_SERIRQ 22,27

SATA_RXN0 56 SATA_RXP0 56 SATA_TXN0 56 SATA_TXP0 56

SATA_RXN1 66 SATA_RXP1 66 SATA_TXN1 66 SATA_TXP1 66

SATA_RXN4 56 SATA_RXP4 56 SATA_TXN4 56 SATA_TXP4 56

SATA_RXN5 57 SATA_RXP5 57 SATA_TXN5 57 SATA_TXP5 57

R2112 37D4R2F-GPR2112 37D4R2F-GP

R2113 49D9R2F-GPR2113 49D9R2F-GP

R2114 750R2F-GPR2114 750R2F-GP

1

3D3V_S0

GG

LW_GG_SEL

HighLW

LOW

LPC_AD[0..3] 27,65,71

LW_GG_SEL

12

LW

R2109

R2109 10KR2J-3-GP

10KR2J-3-GP

12

GG

R2110

R2110 10KR2J-3-GP

10KR2J-3-GP

HDD

mSATA

ODD ESATA

1D05V_VTT

1 2

SATA_LED# 22 SATA_DET#0 22

BBS_BIT0 18

0827

BBS_BIT0

Title

PCH (SPI/RTC/LPC/SATA/IHDA)

Size Document Number Rev

A3

Date: Sheet of

1D05V_VTT

R2108 10KR2J-3-GPR2108 10KR2J-3-GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

LLW-1 / LGG-1

21 94Tuesday, November 09, 2010

1

SB

5

4

3

2

1

SSID = PCH

Note: For PCH debug with XDP, need to NO STUFF R2218

R2218 100R2J-2-GPR2218 100R2J-2-GP

3D3V_S0

R2202 200KR2F-L-GPR2202 200KR2F-L-GP

SRN10KJ-5-GP

3D3V_S0

PCH_GPIO12 PCH_GPIO57

PCH_GPIO15

PCH_GPIO24

1 2

RN2203

1 2 3

R2223

1 2

10KR2J-3-GP

R2201 1KR2J-1-GPR2201 1KR2J-1-GP

R2221 10KR2J-3-GPR2221 10KR2J-3-GP

4

FFS_INT2_R

RN2204

4

SRN10KJ-5-GP

1 2

D D

3D3V_S0

GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.

C C

B B

SATA_ODD_PRSNT#

H_A20GATE H_RCIN#

23 1

SATA_ODD_PRSNT#56

PSW_CLR#21

3D3V_S5

S_GPIO21

EC_SCI#27

R2213 0R2J-2-GPR2213 0R2J-2-GP

1 2

DGPU_PW ROK92,93

TP2202

TPAD14-GP

mSATA_DTCT#27,66

TP2204

TPAD14-GP

GAP-OPEN

21

G2201

MFG_MODE21

PCH_TEMP_ALERT#27

TP2212TPAD14-GP TP2212TPAD14-GP

TP2209TPAD14-GP TP2209TPAD14-GP TP2210TPAD14-GP TP2210TPAD14-GP

TP2211TPAD14-GP TP2211TPAD14-GP

1 2

EC_SMI# DGPU_HPD_INTR# EC_SCI# ICC_EN# PCH_GPIO12 PCH_GPIO15

GPIO16

PCH_GPIO22 PCH_GPIO24

1

mSATA_DTCT# PLL_ODVR_EN

NC_FP_DET#

1

DMI_OVRVLTG FDI_OVRVLTG

GFX_CRB_DET FFS_INT2_R PCH_TEMP_ALERT# PCH_GPIO57

PCH_NCTF_1

1

PCH_NCTF_2

1

PCH_NCTF_3

1

PCH_NCTF_4

1

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24/MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49

D6

GPIO57

A4

NCTF_VSS#A4

A44

NCTF_VSS#A44

A45

NCTF_VSS#A45

A46

NCTF_VSS#A46

A5

NCTF_VSS#A5

A6

NCTF_VSS#A6

B3

NCTF_VSS#B3

B47

NCTF_VSS#B47

BD1

NCTF_VSS#BD1

BD49

NCTF_VSS#BD49

BE1

NCTF_VSS#BE1

BE49

NCTF_VSS#BE49

BF1

NCTF_VSS#BF1

BF49

NCTF_VSS#BF49

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49

GPIO

NCTF

D1,D49,E1,E49,F1,F49

BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48

6 OF 10

TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71

A20GATE

PROCPWRGD

THRMTRIP#

CPU/MISC

INIT3_3V#

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NCTF_VSS#BG2

NCTF_VSS#BG48

NCTF_VSS#BH3

NCTF_VSS#BH47

NCTF_VSS#BJ4 NCTF_VSS#BJ44 NCTF_VSS#BJ45 NCTF_VSS#BJ46

NCTF_VSS#BJ5

NCTF_VSS#BJ6

NCTF_VSS#C2

NCTF_VSS#C48

NCTF_VSS#D1

NCTF_VSS#D49

NCTF_VSS#E1

NCTF_VSS#E49

NCTF_VSS#F1

NCTF_VSS#F49

PECI

RCIN#

NC_1

C40

UMA_DIS#

B41

VRAM_SIZE1

C41

VRAM_SIZE2

A40

H_A20GATE

P4

H_PECI_R

AU16 P5 AY11

PCH_THERMTRIP_R

AY10

INIT3_3V#

T14

AH8 AK11 AH10

TS_VSS

AK10 P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

TP2207TP2207

1

TP2208TP2208

1

1 1

R2222

1 2

0R0402-PAD

SATA_ODD_PWRGT 56 UMA_DIS# 20

TP2206

TPAD14-GP

TP2205

TPAD14-GP

H_A20GATE 27

R2203 0R2J-2-GP

1 2

DY

H_RCIN# 27

H_CPUPW RGD 5,36

R2204 390R2J-1-GPR2204 390R2J-1-GP

1 2

TP2201

TPAD14-GP

12

DY

12

R2214

R2211

3D3V_S0

TPAD14-GP

12

R2207

R2207 10KR2J-3-GP

10KR2J-3-GP

DY

12

R2208

R2208 10KR2J-3-GP

10KR2J-3-GP

R2209

R2209 10KR2J-3-GP

10KR2J-3-GP

DMI_OVRVLTG

R2210

R2210 10KR2J-3-GP

10KR2J-3-GP

3D3V_S5

12

DY

FDI_OVRVLTG

ICC_EN#

1

3D3V_S0

0827

10KR2J-3-GP

1KR2J-1-GP

H_PECI 5,27

H_THERMTRIP# 5,36,85

FDI TERMINATION VOLTAGE OVERRIDE

GPIO37 (FDI_OVRVLTG)

DMI TERMINATION VOLTAGE OVERRIDE

GPIO36

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

Integrated Clock Chip Enable

ICC_EN#

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

INTERNAL GFX EXTERNAL GFX

R2205 DY 10K

R2206 100K DY

3D3V_S0

12

R2205

R2205 10KR2J-3-GP

10KR2J-3-GP

DY

GFX_CRB_DET

12

R2206

R2206 100KR2J-1-GP

100KR2J-1-GP

R2224

PCH_THERMTRIP_R

R2224

DY

56R2F-1-GP

12

1D05V_VTT

20100723 V1.62

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

HIGH (R2211 DY)- DISABLED [DEFAULT]

LOW (R2211)- ENABLED

3D3V_S0

RN2201

INT_SERIRQ21,27

SATA_LED#21

A A

SATA_DET#021

5

PCH_GPIO22 PCH_TEMP_ALERT#

EC_SMI# EC_SCI# DGPU_HPD_INTR#

1 2 3 4 5

SRN10KJ-6-GP

SRN10KJ-6-GP RN2202

RN2202

SRN10KJ-6-GP

8 7 6

mSATA_DTCT#

12

DY

R2225

R2225 10KR2J-3-GP

10KR2J-3-GP

4

NC_FP_DET#

12

R2220

R2220 10KR2J-3-GP

10KR2J-3-GP

3

0827

PLL_ODVR_EN

R2215

10KR2J-3-GP

R2212

1KR2J-1-GP

DY

3D3V_S5

12

2

PLL ON DIE VR ENABLE

ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

PCH (GPIO/CPU)

LLW-1 / LGG-1

22 94Tuesday, November 09, 2010

1

SB

5

4

3

2

1

SSID = PCH

3D3V_S03D3V_DAC_S0

1D05V_VTT

D D

12

C2301

SC10U6D3V5KX-1GP

1D05V_VTT

C C

12

SC10U6D3V5KX-1GP

C2305

12

C2306

SC1U6D3V2KX-GP

6A

12

SC1U6D3V2KX-GP

TP2301TPAD14-GP TP2301TPAD14-GP

12

SC1U6D3V2KX-GP

C2302

C2307

12

SC1U6D3V2KX-GP

1D05V_VTT

1

12

SC1U6D3V2KX-GP

C2303

C2308

12

C2304

SC1U6D3V2KX-GP

VCCAPLLEXP

12

C2309

SC1U6D3V2KX-GP

20100625 V1.2

1D05V_VTT

L2302

DY

12

VCCAPLLEXP

C2324

C2324 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

0.266A (Totally VCC3_3 current)

0.159A(Totally current of VCCVRM)

1D5V_S0_1D8V_S0

0.042A (Totally current of VCCDMI)

TP2302TPAD14-GP TP2302TPAD14-GP

1D05V_VTT

3D3V_S0

12

C2310

C2310 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

R2302 0R3J-0-U-GPR2302 0R3J-0-U-GP

VCCFDIPLL

1

+1.05VS_VCC_DMI

VCCAFDI_VRM

1 2

IND-1UH-100-GP

B B

PCH1G

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO

BJ22

VCCAPLLEXP

AN16

VCCIO

AN17

VCCIO

AN21

VCCIO

AN26

VCCIO

AN27

VCCIO

AP21

VCCIO

AP23

VCCIO

AP24

VCCIO

AP26

VCCIO

AT24

VCCIO

AN33

VCCIO

AN34

VCCIO

BH29

VCC3_3

AP16

VCCVRM

BG6

VCCAFDIPLL

AP17

VCCIO

AU20

VCCDMI

COUGAR-GP-U2-NF

POWER

Cougar

Cougar Point

Point

VCC CORE

VCCIO

FDI

CRTLVDS

DMI

NAND / SPI HVCMOS

7 OF 10

VCCADAC

VSSADAC

VCCALVDS VSSALVDS

VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS

VCC3_3

VCCVRM

VCCDMI

VCCCLKDMI

VccDFTERM

VCCSPI

+VCCA_DAC_1_2

U48

U47

+3VS_VCCA_LVD

AK36 AK37

AM37 AM38 AP36 AP37

V33

V34

AT16

+1.05VS_VCC_DMI

AT20

AB36

+1.05VS_VCC_DMI_CCI

AG16

AG17

AJ16

AJ17

V1

12

C2313

C2313 SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

R2303 0R2J-2-GP

DY

1 2

+1.8VS_VCCTX_LVDS

12

DY

R2309

R2309 0R2J-2-GP

0R2J-2-GP

C2319

C2319 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2321

C2321 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2316

C2316 SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

1 2

0.02A

+V_NVRAM_VCCQ 1D8V_S0

0.19A

12

C2322

C2322 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

0.02A

12

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2314

C2314 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

1D5V_S0_1D8V_S0

1D05V_VTT

R23060R2J-2-GP R23060R2J-2-GP

1D05V_VTT

R23070R2J-2-GP R23070R2J-2-GP

(1uFx1)

L2301

1 2

0.001A

0.06A

12

C2317

C2317 SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

R23080R2J-2-GP R23080R2J-2-GP

12

VCCSPI

12

HCB1608KF-181-GP

C2315

C2315 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

1 2

12

C2318

C2318 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

3D3V_S5 3D3V_S0

12

R2313

R2313 0R2J-2-GP

0R2J-2-GP

R23040R3J-0-U-GP R23040R3J-0-U-GP

12

The same BIOS SPI ROM power

3D3V_S0

R23050R5J-5-GP R23050R5J-5-GP

SC1U10V2KX-1GP

12

DY

R2314

R2314 0R2J-2-GP

0R2J-2-GP

1D8V_S0

12

C2311

DY

R23120R2J-2-GP

1 2

R23120R2J-2-GP

3.3V CRT LDO

U2301

1

VIN

2

VOUT GND EN3NC#4

G9091-330T11U-GP

3D3V_DAC_S05V_S0

5 4

12

C2312

SC1U6D3V2KX-GP

Table 23.1- LDO Regulator multi-source

Supplier

VCCVRM(Internal PLL and VRMs): A.1.5V for Mobile B.1.8 V for Desktop co-operate with R2103

A A

5

4

1D5V_S0 1D5V_S0_1D8V_S0

1 2

R23100R3J-0-U-GP R23100R3J-0-U-GP

3

2

GMT

RICHTEK

Title

Size Document Number Rev

Date: Sheet of

Description Lenovo P/N Wistron P/N

G9091-330T11U

N/A 74.09091.J3F

N/ART9198-33GBR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (POWER1)

A3

LLW-1 / LGG-1

1

23 94Tuesday, November 09, 2010

74.09198.Q7F

SB

5

4

3

2

1

SSID = PCH

+VCCSUS1

3D3V_AUX_S5

DY

R2418 0R3J-0-U-GP

1 2

12

D D

1D05V_VTT

3D3V_S0

C C

1D05V_VTT

2nd = 68.10010.10T

B B

2nd = 68.10010.10T

1D05V_VTT

A A

1D05V_VTT

DY

R2417 0R2J-2-GP

R2417 0R2J-2-GP R2419

R2419 0R3J-0-U-GP

0R3J-0-U-GP

DY

R2420 0R2J-2-GP

1 2

68.1001A.10B

R2404 0R2J-2-GPR2404 0R2J-2-GP

R2405 0R2J-2-GPR2405 0R2J-2-GP

12

L2404

1 2

DY

R2401 0R3J-0-U-GP

R2402

1R2F-GP

1 2

L2404

DY

2nd = 68.10010.10T

12

1 2

68.1001A.10B

2nd = 68.10010.10T

L2402

IND-10UH-66-GP

L2403

IND-10UH-66-GP

12

+VCCPDSW

DY

C2438

C2438 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

IND-10UH-66-GP

68.1001A.10B

DY

12

C2442

C2442 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

L2401

IND-10UH-66-GP

0.08A

+1.05VS_VCCA_A_DPL

DY

12

C2444

C2444 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

0.08A

+1.05VS_VCCA_B_DPL

DY

12

C2445

C2445 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

+VCCDIFFCLK

12

C2412

C2412 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+V1.05S_SSCVCC

12

C2413

C2413 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

5

12

SC1U10V2KX-1GP

VCCACLK

+VCCAPLL_CPY_PCH

DCPSUS

+V3.3S_VCC_CLKF33

12

C2401

SC10U6D3V3MX-GP

12

DCPSUSBYP

DY

C2441

12

C2409

C2409 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2410

C2410 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1D05V_VTT

DY

C2439

1 2

SCD1U10V2KX-5GP

DY

C2440

C2440 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

1D05V_VTT

12

SC10U6D3V5KX-1GP

12

C2402

SC1U10V2KX-1GP

R2406 0R3J-0-U-GPR2406 0R3J-0-U-GP

1D05V_VTT

C2403

C2414

C2414 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

0.002A

3D3V_S5

R2403 0R3J-0-U-GPR2403 0R3J-0-U-GP

TPAD14-GP

1D05V_VTT

1 2

TP2404

TP2401TPAD14-GP TP2401TPAD14-GP

TP2405TPAD14-GP TP2405TPAD14-GP

TP2402TPAD14-GP TP2402TPAD14-GP

1.01A (Total current of VCCASW)

12

C2406

SC1U6D3V2KX-GP

(22uFx2_0603)

(1uFx3)

1D5V_S0_1D8V_S0

12

C2404

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

+VCCRTCEXT

0.16A (Totally current of VCCVRM

12

C2411

C2411 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+VCCDIFFCLKN

0.055A

12

0.095A

C2415 SCD1U10V2KX-5GPC2415 SCD1U10V2KX-5GP

12

TP2406TPAD14-GP TP2406TPAD14-GP

0.001A

6uA

12

C2420

C2420 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

4

12

C2418

C2418 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2421

C2421 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2417

C2417 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

RTC_AUX_S5

VCCACLK

1

+VCCPDSW

DCPSUSBYP

1

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

1

+VCCSUS1

1

12

C2408

C2407

C2408

SC1U6D3V2KX-GP

+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL

+VCCDIFFCLK

+V1.05S_SSCVCC

+VCCSST

DCPSUS

1

12

C2419

C2419 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

PCH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3

BH23

VCCAPLLDMI2

AL29

VCCIO

AL24

DCPSUS

AA19

VCCASW

AA21

VCCASW

AA24

VCCASW

AA26

VCCASW

AA27

VCCASW

AA29

VCCASW

AA31

VCCASW

AC26

VCCASW

AC27

VCCASW

AC29

VCCASW

AC31

VCCASW

AD29

VCCASW

AD31

VCCASW

W21

VCCASW

W23

VCCASW

W24

VCCASW

W26

VCCASW

W29

VCCASW

W31

VCCASW

W33

VCCASW

N16

DCPRTC

Y49

VCCVRM

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO

AF33

VCCDIFFCLKN

AF34

VCCDIFFCLKN

AG34

VCCDIFFCLKN

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS

V19

DCPSUS

BJ8

V_PROC_IO

A22

VCCRTC

COUGAR-GP-U2-NF

12

C2422

C2422 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

POWER

Cougar

Cougar Point

Point

Clock and Miscellaneous

CPURTC

3

PCI/GPIO/LPCMISC

SATA USB

HDA

10 OF 10

VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCCIO

V5REF_SUS

DCPSUS

VCCSUS3_3

V5REF

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCC3_3 VCC3_3 VCC3_3

VCC3_3

VCCIO

VCCIO VCCIO

VCCIO

VCCAPLLSATA

VCCVRM

VCCIO VCCIO VCCIO

VCCASW

VCCSUSHDA

1D05V_VTT

N26 P26 P28 T27 T29

3D3V_S5

T23 T24 V23 V24 P24

1D05V_VTT

T26

+5VA_PCH_VCC5REFSUS

M26

+VCCA_USBSUS

AN23

+V3.3A_VCCPSUS

AN24

+5VS_PCH_VCC5REF

P34

N20

+V3.3A_VCCPSUS

N22 P20 P22

AA16 W16 T34

AJ2

AF13

AH13 AH14

AF14 AK1

AF11

AC16 AC17 AD17

T21

V21

T19

P32

12

+V1.05S_VCCAPLL_SATA3

+V1.05S_VCC_SATA

1D05V_VTT

+3VS_+1.5VS_HDA_IO

0.01A

12

C2423

C2423 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2424

C2424 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S5

C2430

C2430 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

12

C2429

C2429 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1D05V_VTT

1D5V_S0_1D8V_S0

12

C2435

C2435 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2433

C2433 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2425

C2425 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

DY

12

C2428

C2428 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

3D3V_S0

12

C2431

C2431 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2432

C2432 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1 2

2

TP2403 TPAD14-GPTP2403 TPAD14-GP

1

C2443

C2443 SC1U10V2KX-1GP

SC1U10V2KX-1GP

0.001A

1 2

DY

1 2

12

C2434

C2434 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

DY

R24120R3J-0-U-GP R24120R3J-0-U-GP

3D3V_S5

AK

D2401

D2401 CH751H-40-1-GP

CH751H-40-1-GP

12

C2426

C2426 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

5V_S5

R240810R2J-2-GP R240810R2J-2-GP

0.001A

3D3V_S0

AK

D2402

D2402 CH751H-40-1-GP

CH751H-40-1-GP

3D3V_S5

R24100R3J-0-U-GP R24100R3J-0-U-GP

3D3V_S5

12

DY

C2436

SC1U10V3ZY-6GP

1D05V_VTT

R24110R3J-0-U-GP

1D05V_VTT

Title

Size Document Number Rev

A3

Date: Sheet of

12

1 2

C2427

C2427 SC1U10V2KX-1GP

SC1U10V2KX-1GP

DY

U2401

VIN

VOUT GND EN3NC#4

G9091-150T11U-GP

R2414 0R3J-0-U-GPR2414 0R3J-0-U-GP

1 2

R2415 0R3J-0-U-GP

1 2

DY

R2413 0R3J-0-U-GP

1 2

DY

PCH (POWER2)

LLW-1 / LGG-1

5V_S0

R240710R2J-2-GP R240710R2J-2-GP

1D5V_S5

5 4

12

DY

C2437

SC1U10V3ZY-6GP

1D5V_S0 1D5V_S5+3VS_+1.5VS_HDA_IO 3D3V_S5

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

24 94Tuesday, November 09, 2010

1

12

DY

C2416

SC10U6D3V5KX-1GP

SB

5

4

3

2

1

SSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS

AA17

VSS

AA2

VSS

AA3

VSS

AA33

VSS

AA34

VSS

AB11

VSS

AB14

VSS

AB39

VSS

AB4

VSS

AB43

VSS

AB5

VSS

AB7

VSS

AC19

VSS

AC2

VSS

AC21

VSS

AC24

VSS

AC33

VSS

AC34

VSS

AC48

VSS

AD10

VSS

AD11

VSS

AD12

VSS

AD13

VSS

AD19

VSS

AD24

VSS

AD26

VSS

AD27

VSS

AD33

VSS

AD34

VSS

AD36

VSS

AD37

VSS

AD38

VSS

AD39

VSS

AD4

VSS

AD40

VSS

AD42

VSS

AD43

VSS

AD45

VSS

AD46

VSS

AD8

VSS

AE2

VSS

AE3

VSS

AF10

VSS

AF12

VSS

AD14

VSS

AD16

VSS

AF16

VSS

AF19

VSS

AF24

VSS

AF26

VSS

AF27

VSS

AF29

VSS

AF31

VSS

AF38

VSS

AF4

VSS

AF42

VSS

AF46

VSS

AF5

VSS

AF7

VSS

AF8

VSS

AG19

VSS

AG2

VSS

AG31

VSS

AG48

VSS

AH11

VSS

AH3

VSS

AH36

VSS

AH39

VSS

AH40

VSS

AH42

VSS

AH46

VSS

AH7

VSS

AJ19

VSS

AJ21

VSS

AJ24

VSS

AJ33

VSS

AJ34

VSS

AK12

VSS

AK3

VSS

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

8 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS

AY42

VSS

AY46

VSS

AY8

VSS

B11

VSS

B15

VSS

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

F45

VSS

BB12

VSS

BB16

VSS

BB20

VSS

BB22

VSS

BB24

VSS

BB28

VSS

BB30

VSS

BB38

VSS

BB4

VSS

BB46

VSS

BC14

VSS

BC18

VSS

BC2

VSS

BC22

VSS

BC26

VSS

BC32

VSS

BC34

VSS

BC36

VSS

BC40

VSS

BC42

VSS

BC48

VSS

BD46

VSS

BD5

VSS

BE22

VSS

BE26

VSS

BE40

VSS

BF10

VSS

BF12

VSS

BF16

VSS

BF20

VSS

BF22

VSS

BF24

VSS

BF26

VSS

BF28

VSS

BD3

VSS

BF30

VSS

BF38

VSS

BF40

VSS

BF8

VSS

BG17

VSS

BG21

VSS

BG33

VSS

BG44

VSS

BG8

VSS

BH11

VSS

BH15

VSS

BH17

VSS

BH19

VSS

H10

VSS

BH27

VSS

BH31

VSS

BH33

VSS

BH35

VSS

BH39

VSS

BH43

VSS

BH7

VSS

D3

VSS

D12

VSS

D16

VSS

D18

VSS

D22

VSS

D24

VSS

D26

VSS

D30

VSS

D32

VSS

D34

VSS

D38

VSS

D42

VSS

D8

VSS

E18

VSS

E26

VSS

G18

VSS

G20

VSS

G26

VSS

G28

VSS

G36

VSS

G48

VSS

H12

VSS

H18

VSS

H22

VSS

H24

VSS

H26

VSS

H30

VSS

H32

VSS

H34

VSS

F3

VSS

COUGAR-GP-U2-NF

3

Cougar

Cougar Point

Point

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

PCH (VSS)

LLW-1 / LGG-1

1

SB

25 94Tuesday, November 09, 2010

SB

5

D D

C C

4

3

2

1

BLANK

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

LLW-1 / LGG-1

26 94Tuesday, November 09, 2010

1

SB

SSID = KBC

3D3V_AUX_KBC

R2771

R2771 2D2R3-1-U- GP

2D2R3-1-U- GP

1 2

12

C2701

SC2D2U10V3KX-1GP

R2714

1 2

R2729

1 2

R2727

1 2

12

UMA

R2713

R2713 10KR2J-3-GP

10KR2J-3-GP

DISCRETE_ID

12

PX

R2741

R2741 10KR2J-3-GP

10KR2J-3-GP

12

R2740

R2740 10KR2J-3-GP

10KR2J-3-GP

AD_OFF

R2770 1KR2J-1-GPR2770 1KR2J-1-GP

C2701

PAD_DETEC T#

HDD_DTC T#

D D

3D3V_AUX_KBC

3D3V_S0

3D3V_AUX_S5

3D3V_AUX_KBC

C C

EC_AGND

5

R2702 0R3J-0-U- GPR2702 0R3J-0-U-G P

12

C2705

C2704

DY

SCD1U10V2KX-5GP

EC_AGND

ACDC_ID2

10KR2J-3-GP

100KR2J-1-GP

1

TP2708TP2708

10KR2J-3-GP

TP2705TP2705

KB_ID1

12

C2707

C2706

SCD1U10V2KX-5GP

DY

C2714 SCD 1U10V2KX-5GP

1 2

AD_IA40 ACDC_ID282

GSENSE_Z79

USB_AO_SEL182 GSENSE_TST79 3G_EN66

SUS_PWR _ACK19 GSENSE_X79

TP2707TP2707

FAN_ID28

GSENSE_Y79

PAD_DETEC T#69 AD_OFF82 BEEP_ENABLE29 S5_ENABLE36 3G_POWER ON66

BAT_IN#39

LID_CLOSE#49 RSMRST#_KBC19

PM_SLP_S4#19,46,82

ME_UNLOCK21 HDD_DTC T#56

EC_ENABLE

1

RTC_AUX_S5

WIFI_RF_EN65 BLUETOOTH _EN63 S0_PWR_GO OD19,36

USB_PWR _EN57,61 AC_PRESENT19

NOTE: C2712 must place close to VCORF pin.

R2725 0R5J-5-GPR2725 0R5J -5-GP

12

C2709

C2708

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

EC_AGND

PCB_VER_AD

VGA_THRM

1

KBC_PWR BTN_EC# PAD_DETEC T#

AC_IN_KBC

KB_ID1

DISCRETE_ID

KBC_VCORF

12

C2712

C2712 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

EC_SWI#20

B B

EC_SCI#22

R2712

AC_IN_KBC

1 2

0R0402-PAD

12

DY

R2706

R2706 100KR2J-1-GP

100KR2J-1-GP

3D3V_AUX_S5

12

R2717

R2717 22KR2J-GP

22KR2J-GP

A A

FAN_ID

AC_IN 40

3D3V_S0

SML1_CLK

SML1_DATA

3D3V_AUX_S53D3V_AUX_KBC

1 2

3D3V_AUX_KBC _VCC

12

C2710

SCD1U10V2KX-5GP

104

97 98 99

100 101

105 106

79 95 96

108

93 94

114

6

109

14 15 80 17 20 21 23 26 73 74 75 82 83 84

91 110 112 107

44

NPCE795GA0D X-GP

71.00795.A0G

DY

R2715 0R2J-2-GP

1 2

D2701

1

2

BAS16GP-GP

DY

R2716 0R2J-2-GP

1 2

D2704

1

2

BAS16GP-GP

Q2703

2345 1

6

2N7002KDW -GP

VBAT

U2701A

VREF GPIO90/AD0

GPIO91/AD1 GPIO92/AD2 GPIO93/AD3

GPIO94/DA0 GPIO95/DA1 GPIO96/DA2

GPIO2 GPIO3/AD6 GPIO4/AD5 GPIO5/AD4 PSL_IN2_GPI6# GPIO7/AD7 GPIO16 GPIO24 GPIO30 GPIO34/CIRRXL GPIO36 GPIO41 GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO46/CIRRXM/TRST# GPIO51 PSL_IN1_GPI70 PSL_OUT_GPIO71 VBKUP GPIO75 GPO76/SHBM GPIO77 GPIO81 GPO82/IOX_LDSH/TEST# GPI/O84/IOX_SCLK/XORTR# GPIO97

VCORF

3

2nd = 84.DM601.03F

5

4

115

VCC19VCC46VCC76VCC88VCC

GND18GND45GND78GND89GND

GND

5

116

NOTE: Pleae place R2711 close to AGND pin.

ECSWI#_KBC

ECSCI#_KBC

SMBC_THER M SMBD_THER M

84.2N702.A3F

4

SCD1U10V2KX- 5GP

102

4

VDD

AVCC

LRESET#

LFRAME#

GPIO11/CLKRUN#

GPIO65/SMI#

ECSCI#/GPIO54

GPIO10/LPCPD#

GPIO67/PWUREQ#

GPIO85/GA20

KBRST#/GPIO86

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1

GPIO17/SCL1 GPIO22/SDA1 GPIO73/SCL2 GPIO74/SDA2 GPIO23/SCL3 GPIO31/SDA3 GPIO47/SCL4 GPIO53/SDA4

F_SDI/F_SDIO1

F_SDIO/F_SDIO0

AGND

103

R2711

EC_AGND

12

0R2J-2-GP

EC_AGND

3D3V_S0

RN48

23 1

4

SRN10KJ-5-G P

SMBC_THER M 28,85

SMBD_THER M 28,85

3D3V_S0

12

C2702

1 OF 2

SERIRQ

F_CS0#

F_SCK

LCLK LAD3

LAD2 LAD1 LAD0

SC220P50V2KX-3GP

SC220P50V2KX-3GP R2735

R2735

PLT_RST#_EC

1 2

7 2 3

LPC_AD3

1

LPC_AD2

128

LPC_AD1

127

LPC_AD0

126 125 8 9

ECSCI#_KBC

29 124

ECSWI#_KBC

123 121 122

27 25 11 10 71 72

70 69 67 68 119

GSENSOR_ID

120

PROCHOT _EC

24 28

EC_SPI_CS#_C

90

EC_SPI_CLK_C

92

EC_SPI_DI_C

86

EC_SPI_DO_C

87

NOTE: Locate resistors R2719 and R2722 close to the NPCE791L.

NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connection.

EC_GPIO47 High Active

PROCHOT _EC

12

R2732

R2732 100KR2J-1-GP

100KR2J-1-GP

C2703

C2703 SC2D2U10V3KX- 1GP

SC2D2U10V3KX- 1GP

C2711

DY

1 2

0R2J-2-GP

CLK_PCI_KBC 18 LPC_FRAME# 21,65,71

INT_SERIRQ 21,22 PM_CLKRUN # 19 L_BKLT_EN 17

PCH_TEMP_ALE RT# 22

H_A20GATE 22 H_RCIN# 22

BLON_OUT 49 PCIE_RST# 83,85 GSENSE_ON# 79 USB_AO_SEL0 82

TPDATA 69 TPCLK 69

BAT_SCL 39,40 BAT_SDA 39,40 SML1_CLK 20 SML1_DATA 20

USB_PWR _EN2 82

CHG_ON# 40

R2737 0R2J-2-GPR 2737 0R 2J-2-GP R2722 33R2J-2-GPR2722 33R2J -2-GP

Q2702

G

S

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.031

KBC_PWR BTN#82

PLT_RST# 5,18,32,36,65,66,71 ,80,82,83

LPC_AD[0..3] 21,65,71

NOTE: PWM Signal :

1. If unused, select altrnative GPIO function and enable internal pull-down.

2. Please measure and make sure that the rise time of VCC_POR is less than 10us.

<------ TP <------ BATTERY / CHARGER

<------PCH / eDP

33R2J-2-GPR2736 33R2J -2-GPR2736

12

33R2J-2-GPR2719 33R2J -2-GPR2719

12 12 12

H_PROCHO T#_EC

D

SPI_CS0#_R 21,60 SPI_CLK_R 21,60

SPI_SO_R 21,60

SPI_SI_R 21,60

3D3V_AUX_S5

G2701

G2701 GAP-OPEN

GAP-OPEN

2 1

3

3D3V_AUX_KBC

R2724

R2724 10KR2J-3-GP

10KR2J-3-GP

BOM Ctrl

PCB_VER_AD

R2733 0R2J-2-GPR273 3 0R2J-2-GP

12

1 2

12

R2726

R2726 100KR2J-1-GP

100KR2J-1-GP

EC_AGND

1D05V_VTT

NOTE: Please be aware that the SPI interface trace length between PCH and EC should not exceed 6500mils,. The mismatch of SPI interface signals between EC and SPI flash should not exceed 500mils.

1 2

R2704

R2704 10KR2J-3-GP

10KR2J-3-GP

R2703 470R2J-2-GPR2703 470R2 J-2-GP

R2774

R2774 100KR2J-1-GP

100KR2J-1-GP

12

H_PROCHO T# 5,42

DY

12

C2717

C2717 SC220P50V2KX-3GP

SC220P50V2KX-3GP

3

mSATA_DTC T#22,66

PM_PWRBT N#19

TP2711TP2711

TP2710TP2710

H_PECI5,22

R2701 and C2716 Need very close to EC

KBC_PWR BTN_EC#

R2700

R2700 1MR2J-1-GP

1MR2J-1-GP

mSATA_DTC T#_C

1 2

TP4_RESET69

PM_SLP_S3#19,36 ,37,47,82

PANEL_LED49

KBC_BEEP29

1

STOP_CHG#40

1

PAD_RESET#69

AC_IN_LED82 PALM_LED69

E51_RxD65 E51_TxD65

AMP_MUTE#29

PCH_SUSCL K_KBC19

R2721 43R2J-GPR2721 43R2J-GP R2720 0R2J-2-GPR272 0 0R2J-2-GP

PURE_HW _SHUTDO WN#28,36

1 2 1 2

BRIGHTNESS FAN1_PWM

ECRST#

AMP_MUTE#

PECI

EC_VTT

12

C2716

C2716 SCD1U16V2KX- 3GP

SCD1U16V2KX- 3GP

R2723 10KR2J-3-GPR2723 10KR2J-3-G P

EC GPIO standard PH/PL

BAT_SCL BAT_SDA

BAT_IN#

R2701 100KR2J-1-GPR2701 100KR2J-1-GP

S5_ENABLE LID_CLOSE#

ECRST#

R2709 10KR2J-3-GPR2709 10KR2J-3-GP

AMP_MUTE# PCIE_RST#

E51_RxD

R2708 10KR2J-3-GP

BLUETOOTH _EN

R2707 10KR2J-3-GP

2

U2701B

31

GPIO56/TA1

117

GPIO20/TA2/IOX_DIN_DIO

63

GPIO14/TB1

64

GPIO1/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

81

GPIO66/G_PWM

66

GPIO33/H_PWM

22

GPIO45/E_PWM

16

GPIO40/F_PWM

85

VCC_POR#

113

GPIO87/CIRRXM/SIN_CR

111

GPI/O83/SOUT_CR/TRIST#

30

GPIO55/CLKOUT/IOX_DIN_DIO

77

GPIO0/EXTCLK

13

PECI

12

VTT

NPCE795GA0D X-GP

71.00795.A0G

12

RN2701

23 1

4

SRN4K7J-8-G P

12

RN2705

1

4

23

SRN10KJ-5-G P

12

RN2702

1

4

23

SRN10KJ-5-G P

DY

1 2

DY

1 2

2

KBSOUT0/JENK#

KBSOUT1/TCK KBSOUT2/TMS

KBSOUT4/JEN0#

KBSOUT5/TDO

KBSOUT6/RDY#

KBSOUT9/SDP_VIS# KBSOUT10/P80_CLK

KBSOUT11/P80_DAT

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

KBSOUT15/GPIO61/XOR_OUT

GPIO60/KBSOUT16 GPIO57/KBSOUT17

ECRST#

E

Q2701

B

MMBT3906-4-GP

C

84.T3906.A11

2nd = 84.03906.F11

3D3V_AUX_KBC

3D3V_S0

2 OF 2

KBSOUT3/TDI

KBSOUT7 KBSOUT8

KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7

20100709

GSENSOR_ID

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

54 55 56 57 58 59 60 61

DY

12

C2715

C2715 SC1U6D3V2KX- GP

SC1U6D3V2KX- GP

1

3D3V_S0

12

R2718

G Sensor ID:

100KR2J-1-GP

High: ST Low:ADI

12

DY

R2710

R2710 100KR2J-1-GP

100KR2J-1-GP

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

KCOL[0..17] 69

KROW[0..7] 69

TP2709TP2709

mSATA_DTC T#_C

1

10KR2J-3-GP

Prevent BIOS data loss solution

3D3V_AUX_S5

12

DY

R2705

R2705 10KR2J-3-GP

10KR2J-3-GP

U2702

1

GND

PURE_HW _SHUTDO WN#

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Tuesday, Novem ber 09, 2010

Date: Sheet of

VCC

2

RESET#

G690L293T73UF-G P

74.00690.I7B

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

KBC Nuvoton NPCE795

LLW-1 / LGG-1

1

3D3V_AUX_S5

3

27 94

R2728

12

SB

5

4

3

2

1

SSID = Thermal

Close to SO-DIMM side.

SA 0905 change to 390p

3

D D

2nd = 84.M3904.A11

C C

Close to VGA side.

THER_VGA_DXP

2

C

PX

B

Q2805

MMBT3904WT1G-GP

2nd = 84.M3904.A11

B B

Q2805

84.03904.R11

E

THER_VGA_DXN

1

TP2802

TP2802 TPAD14-GP

TPAD14-GP

E

B

Q2803

C

MMBT3904WT1G-GP

84.03904.R11

2

E

UMA

B

Q2802

C

THER_UMA_DXP

MMBT3904WT1G-GP

84.03904.R11

2nd = 84.M3904.A11

R2811 0R2J-2-GP

1 2

PX

12

C2808

C2808 SC390P50V2KX-GP

SC390P50V2KX-GP

R2812 0R2J-2-GP

1 2

THERM_SCI#

SMBC_THERM27,85 SMBD_THERM27,85

pin6, ALERT# OD pin7, SYS_SHDN# OD

12

C2802

C2802 SC390P50V2KX-GP

SC390P50V2KX-GP

R2813 0R2J-2-GP

UMA

12

C2805

C2805 SC390P50V2KX-GP

SC390P50V2KX-GP

R2814 0R2J-2-GP

between CPU, VGA and DIMM on bottom side

PX

R2802 0R0402-PADR2802 0R0402-PAD

1 2

Thermal sensor

UMA

1 2

UMA

1 2

C2803

1 2

SCD1U10V2KX-5GP

REMOTE2+ REMOTE2-

2103_VDD

H_THERMDA H_THERMDC

THERM_SYS_SHDN# SHDN_SEL THERM_SCI#_R

2200p close to smsc2103 chip

3D3V_S0

12

R2801

R2801 68R2-GP

68R2-GP

U2801

3

VDD

2

DP1

1

DN1

16

DP2/DN3

15

ND2/DP3

7

SYS_SHDN#

6

ALERT#

9

SMCLK

8

SMDATA

EMC2103-2-AP-GP

74.02103.A73

REMOTE2-THER_UMA_DXN

12

C2806

C2806 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

REMOTE2+

GPIO1 GPIO2

TACH

PWM

TRIP_SET

SHDN_SEL

GND GND

T8

1

C

Q2801

B

E

MMBT3904WT1G-GP

84.03904.R11

2nd = 84.M3904.A11

CPU TEMP: H_THERMDA and H_THERMDC routing 10mil trace width and spacing. Locate Capacity near Thermal diode.

3D3V_S0

12

R2804

R2804 6K8R2J-GP

6K8R2J-GP

SHDN_SEL

SHDN --> 2N3904 ON External diode

4 5

10 11

14 13

12 17

2103_4 2103_5

TRIP_SET

TP2801TPAD14-GPTP2801TPAD14-GP

1

TP2803TPAD14-GPTP2803TPAD14-GP

1

R2803 2K05R2F-GPR2803 2K05R2F-GP

1 2

T8 = 105

2200p close to smsc2103 chip

12

C2809

C2809 SC390P50V2KX-GP

SC390P50V2KX-GP

CPU backside or inside the socket

FAN_TACH

RN2801

2 3 1

SRN10KJ-5-GP

D2802

CH551H-30GP-GP

20100709_EMI

3D3V_S0

4

KA

FAN_TACH FAN_PW M

SA 0905

H_THERMDA

12

C2804

C2804 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

H_THERMDC

12

C2801

SC4D7U6D3V3KX-GP

FAN_ID27

R2806 0R0402-PADR2806 0R0402-PAD

1 2

DY

12

EC2801

EC2801 SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

5V_S0

12

FAN_PW M_CFAN_PW M

DY

12

EC2802

EC2802 SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

R2805

R2805 10KR2J-3-GP

10KR2J-3-GP

ACES-CON6-35-GP

5V_S0 FAN_PW M_C FAN_TACH FAN_ID

FAN1

8 6

5 4 3 2

1 7

1

TP2101TP2101

1

TP2102TP2102

1

TP2103TP2103

1

TP2104TP2104

3D3V_AUX_S5

DY

D2803

D2803 BAT54PT-GP

BAT54PT-GP

83.00054.T81

2ND = 83.BAT54.D81

3rd = 83.BAT54.S81

PURE_HW _SHUTDOWN#27,36

A A

5

4

12

DY

R2810

R2810 10KR2J-3-GP

10KR2J-3-GP

3

1

2

DY

12

C2807

C2807 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

Q2804

D

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.031

S

G

3

THERM_SYS_SHDN#

R2808 0R2J-2-GP

R2808 0R2J-2-GP R2809 0R2J-2-GPR2809 0R2J-2-GP

3D3V_S0

DY

1 2 1 2

12

R2807

R2807 100KR2J-1-GP

100KR2J-1-GP

3D3V_S0

IMVP_PWRGD 36,42

Table 28.1- General Purpose Transistors multi-source

Supplier

PANJIT

Title

THERMAL SENSOR SMSC EMC2103

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Description Lenovo P/N Wistron P/N

MMBT3904WT1G

MMBT3904W 84.M3904.A11

LLW-1 / LGG-1

Tuesday, November 09, 2010

LLW-1 / LGG-1

N/A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

28 94

1

84.03904.R11ON

SB

5

D D

AUD_3D3V

12

C2908

SC1U10V2KX-1GP

HDA_CODE C_RST#21

HDA_CODE C_BITCLK21

1 2

D

HDA_SDIN021

AUD_DMIC_CLK49

AUD_DMIC_DA TA4 9

D2901

C C

HDA_SPKR21

KBC_BEEP27

BEEP_ENABLE27

D2901

2

1

BAT54CGP-GP

AUD_PC_BEEP _C_R

3

R2906 100R2J-2-GPR2 906 100R2J-2-GP

Q2903

G

S

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.031

AUD_3D3V

12

C2909

12

DY

SCD1U25V2ZY-1GP

C2910

SC10U10V5ZY-1GP

R2912 33R2J-2-GPR2912 33R2J-2-GP

1 2

DY

C2915

C2915 SC6D8P50V2DN -GP

SC6D8P50V2DN -GP

1 2

AUD_PC_BEEP _C

12

R2907 100R2F-L1-GP -UR2907 100R2F-L1- GP-U

12

C2905

SC10U10V5ZY-1GP

AUD_3D3V

12

SCD1U25V2ZY-1GP

C2917 SCD1U 10V2KX-5GPC2917 SCD1U 10V2KX-5GP

R2905

R2905 10KR2J-3-GP

10KR2J-3-GP

1 2

DY

12

C2934

C2934 SC33P50V2JN-3G P

SC33P50V2JN-3G P

For EMI issue.

DY

R2921 0R2J-2-GP

1 2

DY

R2922 0R2J-2-GP

B B

AU_GND

Place R2913/R2914 under CODEC, and place R2921/R2922 near CODEC

20100705_AUD

AUD_SYNC_G

12

C2931

C2931 SC33P50V2JN-3G P

SC33P50V2JN-3G P

HDA_CODE C_SYNC21 HDA_CODE C_SDOUT21

A A

5

1 2

R2913 0R0805-PAD-1 -GPR2913 0R0 805-PAD-1-GP

1 2

R2914 0R0805-PAD-1 -GPR2914 0R0 805-PAD-1-GP

1 2

Q2901

D

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.031

12

C2906

SCD1U25V2ZY-1GP

C2911

10KR2F-2-GP

12

C2914

C2914 SC6D8P50V2DN -GP

SC6D8P50V2DN -GP

1 2

AUD_3D3V

G

S

12

DY

R2903

AUD_SDATA IN

DY

AMP_MUTE#27

12

AUD_SYNC

4

12

C2907

SCD1U25V2ZY-1GP

SC10U10V5ZY-1GP

AUD_DMIC_CLK _R

DY

12

C2933

C2933 SC33P50V2JN-3G P

SC33P50V2JN-3G P

R2918

R2918 33KR2F-GP

33KR2F-GP

4

12

C2912

AUD_SYNC AUD_SDATA _OUT

DY

C2916

C2916 SC22P50V2JN-4G P

SC22P50V2JN-4G P

1 2

AUD_PC_BEEP

12

SCD1U25V2ZY-1GP

3

AUDIO CODEC

AUD_LDO_OU T_3D3V

AUD_FILT_1D65V

12

C2902

C2901

SC1U10V2KX-1GP

SCD1U25V2ZY-1GP

AU_GND

AUD_FILT_1D8V

C2913

9 5

8 6 4

10

39 38 37

40

1

71.20671.A03

U2901

CX20671-21Z-GP

SC100P50V2JN-3 GP

2

3

7

18

26

27

29

VDD_IO

FILT_1_8

AVDD_HP

FILT_1_65

VAUX_3_3

AVDD_3_3

RESET# BIT_CLK

SYNC SDATA_IN SDATA_OUT

PC_BEEP

SPDIF GPIO0/EAPD# GPIO1/SPK_MUTE#

DMIC_CLK DMIC_1/2

DVDD_3_3

LEFT+

LEFT-13RIGHT-

RIGHT+

11

14

16

AUD_SPK_R-

AUD_SPK_L-

AUD_SPK_L+

AUD_SPK_R+

Should be used at least 20 MIL width copper line for "AUD_SPK_L+","AUD_SPK_L-", "AUD_SPK_R+", "AUD_SPK_R-

AUD_SDATA _OUT_G

12

DY

C2932

Q2902

D

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.031

R2919 0R2J-2-GPR291 9 0R2J-2-GP

1 2

12

C2903

SC10U10V5ZY-1GP

C2926

SCD1U10V2KX-5GP

1 2

AUD_CLASSDREF

12

15

17

28

AVDD_5V

LPWR_5_0

RPWR_5_0

CLASS_D_REF

36

SENSE_A

35

PORTB_R

34

PORTB_L

33

B_BIAS

32

C_BIAS

31

PORTC_R

30

PORTC_L

25

NC#25

24

NC#24

23

PORTA_R

22

PORTA_L

21

AVEE

20

FLY_N

19

FLY_P

GND

41

R2911 0R2J-2-GPR291 1 0R2J-2-GP

1 2

R2910 0R2J-2-GPR291 0 0R2J-2-GP

1 2

R2909 0R2J-2-GPR290 9 0R2J-2-GP

1 2

R2908 0R2J-2-GPR290 8 0R2J-2-GP

1 2

AUD_3D3V

12

DY

R2920

R2920 33KR2F-GP

33KR2F-GP

G

AUD_SDATA _OUT

S

12

C2904

SCD1U25V2ZY-1GP

AU_GND

12

C2924

SC10U10V5ZY-1GP

12

C2927

SCD1U25V2ZY-1GP

AUD_PORTC _R AUD_PORTC _L

AUD_FLY_N AUD_FLY_P

3

AUD_SENSE_A

C2919

C2919 SC2D2U10V3KX- 1GP

SC2D2U10V3KX- 1GP

AUD_SPK_R+_ L 58 AUD_SPK_R- _L 58 AUD_SPK_L-_L 58 AUD_SPK_L+_L 58

AUD_5V

12

C2925

Layout Note: Path from +5V to LPWR_5.0 and RPWR_5.0 must be very low resistance ( <0.01 ohms).

SCD1U25V2ZY-1GP

Place bypass caps very close to device.

12

C2928

C2929

SC10U10V5ZY-1GP

SCD1U25V2ZY-1GP

C2922 SC2D 2U10V3KX-1GPC2922 SC2D 2U10V3KX-1GP

1 2

C2923 SC2D 2U10V3KX-1GPC2923 SC2D 2U10V3KX-1GP

1 2

AUD_PORTA _R 58 AUD_PORTA _L 58

1 2

SCD1U25V2ZY-1GP

AUD_SPK_R+ AUD_SPK_RAUD_SPK_LAUD_SPK_L+

AUD_5V 5V_S0

R2901 0R5J-5-GPR2901 0R5J -5-GP

1 2

3D3V_S0AUD_3D3V

R2902 0R3J-0-U- GPR2902 0R3J-0-U-G P

1 2

12

C2930

SC10U10V5ZY-1GP

AUD_AVEE

12

C2920

12

EC2904

EC2904 SC1KP50V2KX-1G P

SC1KP50V2KX-1G P

12

C2921

SC10U10V5ZY-1GP

Port Configuration

Port A: Headphone jack Port B: Port C: Microphone jack Port G: Internal stereo speakers Port J: Internal stereo digital mic

AUD_PORTC _R_C 58 AUD_PORTC _L_C 58

12

EC2903

EC2903 SC1KP50V2KX-1G P

SC1KP50V2KX-1G P

Place EMI components close to audio codec.

12

EC2902

EC2902 SC1KP50V2KX-1G P

SC1KP50V2KX-1G P

2

12

EC2901

EC2901 SC1KP50V2KX-1G P

SC1KP50V2KX-1G P

2

1

JACK DETECT RESISTORS

Close to Pin36

SENSE PIN A

AUD_3D3V

12

R2915

R2915 5K11R2F-L1-GP

5K11R2F-L1-GP

AUD_SENSE_A

AUD_SENSE_A 58

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Tuesday, Novem ber 09, 2010

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

AUDIO CODEC

LLW-1 / LGG-1

1

29 94

SB