Wistron Leopard2 Schematic

A

CLK GEN

3

Leopard2 Block Diagram

ICS954206

4 4

31

1394 Conn

27,28

PCMCIA 1 SLOT

SD/MS 6 in 1

29 28

29

Power Switch

TPS2220A

PCI 7411

CARDBUS 1394 SD/MS/MMC/SM

Card Slost

3 3

Mini-PCI

34

802.11a/b/g

RJ45 CONN

RJ11 CONN

31

10/100 RTL8100C

31

MODEM

MDC Card

30,31

PCI BUS

35

AC97-LINK

B

4,5

Mobile CPU

Dothan

Host BUS 400/533MHz

6,7,8,9,10

Alviso

DMI I/F 100MHz

21,22,23,24

ICH6-M

PEG

C

Project code: 91.4C701.001 PCB P/N : 48.4C701.011 REVISION : 05202 -1

DDRII*2

13,14,15

VGA

ATI M26P

USB 2.0

11,12

SVIDEO/COMP

BLUE THUMB

D

DDR-SDRAM

16,17

HY5DS573222F-28

LVDS

TVOUT

RGB CRT

DAUGHTER BOARD

USB x 2 USB x 2

P EIDE

HDD

LCD

CRT

E

SYSTEM DC/DC

42

45

19

18

40

TPS5130

INPUTS

DCBATOUT

OUTPUTS

1D8V_S3 5V_S3 3V_AUX

SYSTEM DC/DC

MAX8743

INPUTS

DCBATOUT

OUTPUTS

1D05V_S0 1D2V_VGA_S0

MAXIM CHARGER

MAX8725

INPUTS

OUTPUTS

BT+

DCBATOUT

35

26

CPU DC/DC

41

INPUTS

18V 4.0A

5V 100mA

MAX1907

OUTPUTS VCC_CORE

S EIDE

DVD/ CD-RW

26

DCBATOUT

0.844~1.3V 27A

2 2

MIC IN

18

AC'97 CODEC

31

AD1981B

LINE OUT

OP AMP

G1420B

33

Docking

18

KBC

NS97551

PCI EXPRESS/ USB2.0

LPC Bus

36

LPC Debug Conn

EXPRESSCARD

38

DAUGHTER BOARD

Comsumer

35 3837

IR

1 1

A

B

37

Touch Pad

C

Int. KB

Thermal & Fan

G768D

25

FlashRom

4Mb (512kB)

D

26

PCB LAYER

Signal 1

L1:

GND

L2:

Signal 2

26

Power Switch

TPS2231

Title

Size Document Number Rev

A3

Date: Sheet

Block Diagram

L3:

Signal 3

L4:

VCC

L5:

Signal 4

L6:

GNDL7: Signal 5L8:

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Leopard2

147Monday, July 11, 2005

E

-1

of

-1

A

B

C

D

E

ICH6-M Integrated Pull-up and Pull-down Resistors

ACZ_BIT_CLK, EE_DOUT, EE_CS, GNT[5]#/GPO[17], GNT[6]#/GPO[16],

4 4

LAD[3:0]#/FB[3:0]#, LDRQ[0], PME#, PWRBTN#,

LAN_RXD[2:0]

ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC, ACZ_SDOUT,ACZ_BITCLK, SPKR

USB[7:0][P,N]

DD[7],

LAN_CLK

3 3

ICH6-M IDE Integrated Series

DPRSLP#, EE_DIN,

TP[3]

SDDREQ

LDRQ[1]/GPI[41],

DPRSLPVR,

ICH6 internal 20K pull-ups

ICH6 internal 10K pull-ups

ICH6 internal 20K pull-downs

ICH6 internal 15K pull-downs

ICH6 internal 11.5K pull-downs

ICH6 internal 100K pull-downs

ICH6-M EDS 14308 0.8V1

Termination Resistors

DD[15:0], DDACK#, DCS3#,

IORDY,

IDEIRQ

DIOR#, DREQ,DIOW#,

DA[2:0],

DCS1#,

approximately 33 ohm

Power name description

5V_S0= 5 Voltage power up on system work(S0 state) 5V_S3= 5 Voltage suspend to RAM(S3 state) 5V_S5= 5 Voltage soft off(S5 state) 3D3V_S0= 3.3 Voltage power up on system work(S0 state) 3D3V_S3= 3.3 Voltage suspend to RAM(S3 state) 3D3V_S5= 3.3 Voltage soft off(S5 state) LVDDR_2D8V= 2.8 Voltage power up on system work(S0 state) 1D8V_S3= 1.8 Voltage suspend to RAM(S3 state) 2D5V_S0= 2.5 Voltage power up on system work(S0 state)

VCC_CORE_S0= CPU VID Voltage power up on system work(S0 state) 1D5V_VCCA_S0= 1.5 Voltage power up on system work(S0 state) 1D5V_S0= 1.5 Voltage power up on system work(S0 state) 1D5V_S5= 1.5 Voltage soft off(S5 state) DDR_VREF= 0.9 Voltage power up on system work(S0 state) 1D2V_VGA_S0= 1.2 Voltage power up on system work(S0 state) for VGA VRAM_VDDQ= 1.8 Voltage power up on system work(S0 state) for VRAM 1D05V_S0= 1.05 Voltage power up on system work(S0 state) CORE_GMCH_S0= 1.05 Voltage power up on system work(S0 state) for ALVISO core power VCCP_GMCH_S0= 1.05 Voltage power up on system work(S0 state)for ALVISO BUSIO power

PCI RESOURCE TABLE

2 2

1 1

A

B

C

DEVICE IDSEL

Mini-PCI

Cardbus Controller TI7411

LAN

Blue Thumb

D

AD21

AD22

AD23

AD24

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

PCI IRQ

P_INTE#

(CARBUS)P_INTG# (1394)P_INTF# (CARD READER)P_INTG#

P_INTE#

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

ITP

Leopard2

REQ# / GNT#

REQ0#/GNT0#

REQ1#/GNT1#

REQ2#/GNT2#

247Wednesday, July 06, 2005

E

-1

of

-1

A

L17

1 2

MLB-201209-11

4 4

3D3V_S0

L38

1 2

MLB-201209-11

12

3D3V_APWR_S0 3D3V_48MPWR_S0

12

C519

C519 SC10U10V6ZY-U

SC10U10V6ZY-U

C199

C199 SC4D7U10V5ZY

SC4D7U10V5ZY

12

3D3V_CLKGEN_S0

C532

C532 SCD1U16V

SCD1U16V

C524

C524 SCD1U16V

SCD1U16V

DY

12

C523

C523 SCD1U16V

SCD1U16V

B

3D3V_S03D3V_S0

1 2

4D7R3

R196

12

R196

C538

C538 SCD1U16V

SCD1U16V

12

C543

C543 SCD1U16V

SCD1U16V

C218

C218 SC4D7U10V5ZY

SC4D7U10V5ZY

12

DY

12

C219

C219 SCD1U16V

SCD1U16V

DY

C525

C525 SCD1U16V

SCD1U16V

12

DY

C

C518

C518 SCD1U16V

SCD1U16V

12

DY

C539

C539 SCD1U16V

SCD1U16V

3D3V_S0

12

R200

R200 10KR2

10KR2

R221

R221 10KR2

10KR2

DY

ITP_EN

D

DummyR200(up side),Mounting R221(down side)

--SRC7 on

Mounting R200(up side),DummyR221(down side)

--CPU2_ITP on

E

CLK_PWRGD#25,41

CPU

266M 133M

166M

400M

20 23 25 27 30 32

19 22 24 26 31 33

52 53 46 47

CLK_XOUT CLK_XIN

49

X150X2

SRCCLKC1 SRCCLKC2 SRCCLKC3 SRCCLKC4_SATA SRCCLKC5 SRCCLKC6

SRCCLKT1 SRCCLKT2 SRCCLKT3 SRCCLKT4_SATA SRCCLKT5 SRCCLKT6

REF0 REF1/FSLC/TEST_SEL SCLK SDATA

51

1 2

R589

1 2

R220

B

10

22R2

33R2

VTT_PWRGD#/PD

34

GND2GND6GND13GND29GND45GND

GNDA

38

SS_SEL

VDDSRC21VDDSRC28VDDSRC

SEL100_96MHZ#/PCICLK_F1

9

ITP_EN

7

CPUCLKC2_ITP/SRCCLKC7

CPUCLKT2_ITP/SRCCLKT7

55

1 2

C544 SC22PC544 SC22P

1 2

C545 SC22PC545 SC22P

RN20

CLK_PCIE_NEW#26

3 3

CLK_PCIE_NEW26

CLK_MCH_3GPLL#7

CLK_MCH_3GPLL7

CLK_PCIE_ICH#22

CLK_PCIE_ICH22

TP_SRCC6 CLK_SRCT6

TP31TPAD30 TP31TPAD30

TP_SRCT6 CLK_SRCC6

TP30TPAD30 TP30TPAD30

PREQ2#26

CLK_ICH1422

CLK_CODEC32 CPU_SEL04,7 SMBC_ICH11,24

SMBD_ICH11,24

CLK_PCIE_PEG#13

CLK_PCIE_PEG13

2 2

3D3V_S0

12

R606

R606 10KR2

10KR2

1 1

12

REQSEL

R605

R605 DUMMY-R2

DUMMY-R2

4

SRN33-2-U2

SRN33-2-U2 RN18

RN18

4

SRN33-2-U2

SRN33-2-U2 RN19

RN19

4

SRN33-2-U2

SB

R584

R568

1 2

R602

1 2

R601

2K2R2

RN21

4

SRN33-2-U2

A

CLK_SRCC1

1

CLK_SRCT1

23

CLK_SRCC3

1

CLK_SRCT3

23

CLK_SRCC5

1

CLK_SRCT5

23

12

DY

0R2-0

12

0R2-0

DY

22R2

22R2 22R2

22R2

12

R222

CLK_SRCC2

1

CLK_SRCT2

23

3D3V_CLKGEN_S0

R197

FS_C

0 0

0 1 1 100M 1 1

X7

X-14D31818M-17

1 2

CLK_REF14

PCLK_KBC36

PM_STPPCI#22

CLK_ICHPCI22

NEAR CLKGEN

1 2

FS_B

0 0 1 1 0 0 1 1

FS_A

10KR2

FS_A

0

01200M 1 00333M 1 0 1 Reserved

3D3V_APWR_S0 3D3V_48MPWR_S0 3D3V_CLKGEN_S0

37

42

11

48

VDDA

VDD48

VDDPCI1VDDPCI

VDDREF

VDDCPU

CPU_STOP#

CPUCLKC0 CPUCLKC1

CPUCLKT0 CPUCLKT1

FSLA/USB_48MHZ

FSLB/TEST_MODE

96MHZ_SSC/SRCCLKC0 96MHZ_SST/SRCCLKT0

DOTC_96MHZ DOTT_96MHZ

IREF

ITP_EN/PCICLK_F08PCI/SRC_STOP#

PCICLK256PCICLK33PCICLK44PCICLK5

5

39

CLK_IREF

475R2F

REQSEL

CLK_PCI3

CLK_PCI4

CLK_PCI5

CLK_CPU_BCLK

CLK_CPU_BCLK#

close to CPU

U72

33R2

33R2 33R2

33R2

54 43 40 35

44 41 36

12 16

18 17

15 14

ICS954206AG

12

R181

12

R600

12

R218

12

R219

TP33

TP33 TPAD30

TPAD30 TP32

TP32 TPAD30

TPAD30

CLK_CPUT1 CLK_CPUC1

CLK_CPUC2 CLK_CPUT2

CLK_CPUT0 CLK_CPUC0

FS_A

CLK_SRCC0 CLK_SRCT0

DOT96C DOT96T

C

RN22

1 2 3

SRN33-2-U2

SRN33-2-U2 RN24

RN24

2 3

DY

1

SRN33-2-U2

RN25

1 2 3

SRN33-2-U2

RN23

1 2 3

SRN33-2-U2

SRN33-2-U2 R199 33R2R199 33R2 R201 33R2R201 33R2

PCLK_PCM 27 PCLK_LAN 30 PCLK_MINI 34

SS3 SS2 SS1 SS0 Spread Amount%

000 0000

0 0 0 0 0 1 +-0.3 1 1 1 1 1 11 11

4

R592 10R2R592 10R2

1 2

R593 33R2R593 33R2

1 2

SC

4

12 12

CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6

PM_STPCPU# 22,41

CLK_XDP_CPU# 4 CLK_XDP_CPU 4

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4

CLK48_USB 22 CLK48_CARDBUS 27 CPU_SEL1 4,7

DREFSSCLK# 7 DREFSSCLK 7

DREFCLK# 7 DREFCLK 7

ICS954206AG Spread Spectrum Select

1

0

1

0

1

0

1 1

1

11

0

0 00 001

1

0 1

0 1 1

1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

-0.8

-1.0

-1.25

-1.5

-1.75

-2.0

-2.5

-3.0

+-0.4 +-0.5 +-0.6 +-0.8 +-1.0 +-1.25 +-1.5

D

DREFCLK DREFCLK# CLK_PCIE_NEW CLK_PCIE_NEW# CLK_XDP_CPU CLK_XDP_CPU# CLK_CPU_BCLK CLK_CPU_BCLK# CLK_MCH_BCLK CLK_MCH_BCLK#

DREFSSCLK DREFSSCLK# CLK_MCH_3GPLL CLK_MCH_3GPLL# CLK_PCIE_PEG CLK_PCIE_PEG# CLK_PCIE_ICH CLK_PCIE_ICH#

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

Clock Generator (ICS954206AG )

3D3V_S0

12

R590

R590 10KR2

10KR2

H/L: 100/96MHz

SS_SEL

12

R591

R591 10KR2

10KR2

DY

1 2

49D9R2F

R202

1 2

49D9R2F

R198

1 2

49D9R2F

R582

1 2

49D9R2F

R580

1 2

DY

49D9R2F

R603

1 2

DY

49D9R2F

R594

1 2

49D9R2F

R596

1 2

49D9R2F

R595

1 2

49D9R2F

R585

1 2

49D9R2F

R586

1 2

49D9R2F

R194

1 2

49D9R2F

R195

1 2

49D9R2F

R566

1 2

49D9R2F

R567

1 2

49D9R2F

R581

1 2

49D9R2F

R583

1 2

49D9R2F

R569

1 2

49D9R2F

R570

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Leopard2

347Monday, July 11, 2005

E

-1

A

H_A#[31..3]6

U53A

62.10055.011

PZ47903

4 4

H_ADSTB#06

H_REQ#[4..0]6

3 3

H_ADSTB#16

H_A20M#21

H_FERR#21

H_IGNNE#21

H_STPCLK#21

H_INTR21

H_NMI21

H_SMI#21

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

CPU

2 2

PZ47903

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

U3

ADSTB#0

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

AE5

ADSTB#1

C2

A20M#

D3

FERR#

A3

IGNNE#

C6

STPCLK#

D1

LINT0

D4

LINT1

B4

SMI#

ITP Conn.

ADDR GROUP 0

ADDR GROUP 1

THERMTRIP#

HCLK THERM XTP/ITP SIGNALS CONTROL

TCK(PIN 5)

TCK(PIN A13)

FBO(PIN 11)

VCCP_GMCH_S0

H_CPURST# XDP_TDO CPU_PROCHOT#

1 1

XDP_TDI XDP_TMS XDP_TRST#

XDP_TCK

R391

R391 R386

R386 R384

R384

1 2

R387

1 2

R389

1 2

R388

1 2

R390

12

54D9R2F

12

54D9R2F

12

56R2J

56R2J 150R2

150R2 39D2R2F

39D2R2F 680R2

680R2 27D4R2F

27D4R2F

All place within 2" to CPU

A

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS0# RS1# RS2#

TRDY#

HIT#

HITM#

BPM#0 BPM#1 BPM#2 BPM#3 PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

PROCHOT#

THERMDA THERMDC

ITP_CLK1 ITP_CLK0

BCLK1 BCLK0

B

N2 L1 J3

L4 H2 M2

N4 A4

B5 J2 B11

H_RS#0

H1

H_RS#1

K1

H_RS#2

L2 M3

K3 K4

C8 B8 A9 C9 A10

XDP_BPM#5

B10

XDP_TCK

A13

XDP_TDI

C12

TDI

A12 C11 B13 A7

B17 B18 A18

C17 A15

A16 B14 B15

B

XDP_TDO XDP_TMS XDP_TRST# DBR#

CPU_PROCHOT#

H_ADS# 6 H_BNR# 6 H_BPRI# 6

H_DEFER# 6 H_DRDY# 6 H_DBSY# 6

H_BREQ#0 6

H_INIT# 21 H_LOCK# 6

H_TRDY# 6 H_HIT# 6

H_HITM# 6

THERMDP1 25 THERMDN 25 PM_THRMTRIP-A# 7,21

PM_THRMTRIP-I# 7,21 CLK_XDP_CPU# 3 CLK_XDP_CPU 3 CLK_CPU_BCLK# 3 CLK_CPU_BCLK 3

VCCP_GMCH_S0

H_IERR#

H_CPURST# 6

H_RS#[2..0] 6

VCCP_GMCH_S0

12

VCC_CORE_S0

R393

R393 56R2J

56R2J

12

R396

R396 56R2J

56R2J

R27

R27 150R2

150R2

Place testpoint on H_IERR# with a GND

0.1" away

PM_THRMTRIP# should connect to ICH6 and Alviso without T-ing

( No stub)

CPU_SEL03,7 CPU_SEL13,7

C

VCCP_GMCH_S0

1 2

R34

C

R383

R383 R385

R385

1KR2F

H_DSTBN#06 H_DSTBP#06

H_DINV#06

H_DSTBN#16 H_DSTBP#16

H_DINV#16

1 2 1 2

12

R33

R33 2KR2F

2KR2F

0R0402-PAD

BSEL[1:0] Freq.(MHz) L H 100 L L 133

CPU_SEL0_CPU CPU_SEL1_CPU

Layout Note:

0.5" max length.

TP2TP2

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

GTLREF

PSI#

C20 D24 C26

C25 C23 C22 D25

H23 G25

M26 H24

G24 M23

N24 M25 H26 N25

C16 C14

AF7 AC1

AD26

A19 A25 A22 B21 A24 B26 A21 B20

B24 E24 B23

E23

L23

F25

K25 K24 L24

E26

J23 J25

L26

J26

E1

C3

D

U53B

U53B PZ47903

PZ47903

62.10055.011

D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12#

DATA GRP 0DATA GRP 1

D13# D14# D15# DSTBN0# DSTBP0# DINV0#

D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1#

PSI# BSEL0

BSEL1

MISC

RSVD2 RSVD3 RSVD4 RSVD5

GTLREF0

D

Y26

D32#

AA24

D33#

T25

D34#

U23

D35#

V23

D36#

R24

D37#

R26

D38#

R23

D39#

AA23

D40#

U26

D41#

V24

D42#

U25

D43#

V26

D44#

DATA GRP 2

Y23

D45#

AA26

D46#

Y25

D47#

W25

DSTBN2#

W24

DSTBP2#

T24

DINV2#

AB25

D48#

AC23

D49#

AB24

D50#

AC20

D51#

AC22

D52#

AC25

D53#

AD23

D54#

AE22

D55#

AF23

D56#

AD24

D57#

AF20

D58#

AE21

D59#

AD21

D60#

DATA GRP 3

AF25

D61#

AF22

D62#

AF26

D63#

AE24

DSTBN3#

AE25

DSTBP3#

AD20

DINV3#

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

G1

DPRSTP#

B7

DPSLP#

C19

DPWR#

SLP#

TEST1 TEST2

E4 A6

C5 F23

PWRGOOD

E

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0

R402 27D4R2FR402 27D4R2F

COMP1

R403 54D9R2FR403 54D9R2F

COMP2

R35 27D4R2FR35 27D4R2F

COMP3

R36 54D9R2FR36 54D9R2F

TEST1 TEST2

12

R29

R29 1KR2

1KR2

DY

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet of

H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6

Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .

H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6

1 2 1 2 1 2 1 2

H_DPRSLP# 21 H_DPSLP# 21 H_DPWR# 6

H_CPUSLP# 6,21

R392

R392 1KR2

1KR2

DY

H_D#[63..0] 6

VCCP_GMCH_S0

12

R395

R395 200R2J

200R2J

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (1 of 2)

Leopard2

447Monday, July 11, 2005

E

H_PWRGD 21

of

-1

A

VCC_CORE_S0 VCC_CORE_S0

4 4

3 3

2 2

1 1

AA11 AA13 AA15 AA17 AA19 AA21

AA5 AA7

AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB22

AB6

AB8 AC11 AC13 AC15 AC17 AC19

AC9 AD10 AD12 AD14 AD16 AD18

AD8 AE11 AE13 AE15 AE17 AE19

AE9

AF10 AF12 AF14 AF16 AF18

AF8 D18 D20 D22

D6

D8 E17 E19 E21

E5

E7

E9 F18 F20 F22

F6

F8

G21

Layout Note:

U53C

PZ47903

62.10055.011

VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58

VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71

VCCA0 VCCA1 VCCA2 VCCA3

VCCP0 VCCP1 VCCP2 VCCP3 VCCP4 VCCP5 VCCP6 VCCP7 VCCP8

VCCP9 VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16 VCCP17 VCCP18 VCCP19 VCCP20 VCCP21 VCCP22 VCCP23 VCCP24

VCCQ0 VCCQ1

VID0 VID1 VID2 VID3 VID4 VID5

VCCSENSE

VSSSENSE

VCCSENSE and VSSSENSE lines should be of equal length.

Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.

G5 H22 H6 J21 J5 K22 U5 V22 V6 W21 W5 Y22 Y6

F26 B1 N1 AC26

D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16 K6 L21 L5 M22 M6 N21 N5 P22 P6 R21 R5 T22 T6 U21

P23 W4

E2 F2 F3 G3 G4 H4

AE7 AF6

TP_VCCA1 TP_VCCA2 TP_VCCA3

CPU_D10

1D5V_VCCA_S0

1 2

R394

TP_VCCSENSE

TP_VSSSENSE

54D9R2F

C17

SCD01U16V2KX

TP1TP1 TP3TP3 TP20TP20

0R2-0

H_VID0 41 H_VID1 41 H_VID2 41 H_VID3 41 H_VID4 41 H_VID5 41

12

R40

DY

12

VCCP_GMCH_S0

12

R39

R39 54D9R2F

54D9R2F

DY

B

12

C15

C15 SC10U10V6ZY-U

SC10U10V6ZY-U

AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA25

AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB26

AC2 AC5

AC8 AC10 AC12 AC14 AC16 AC18 AC21 AC24

AD1

AD4

AD7

AD9 AD11 AD13 AD15 AD17 AD19 AD22 AD25

AE10 AE12 AE14 AE16 AE18 AE20 AE23 AE26

AF11 AF13 AF15 AF17 AF19 AF21 AF24

A11 A14 A17 A20 A23 A26 AA1 AA4 AA6 AA8

AB3 AB5 AB7 AB9

AE3 AE6 AE8

AF2 AF5 AF9

B12 B16 B19 B22 B25

C10 C13 C15 C18 C21 C24

D11

U53D

A2

VSS0

A5

VSS1

A8

VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74

B3

VSS75

B6

VSS76

B9

VSS77 VSS78 VSS79 VSS80 VSS81 VSS82

C1

VSS83

C4

VSS84

C7

VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91

D2

VSS92

D5

VSS93

D7

VSS94

D9

VSS95 VSS96

VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191

D13 D15 D17 D19 D21 D23 D26 E3 E6 E8 E10 E12 E14 E16 E18 E20 E22 E25 F1 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F24 G2 G6 G22 G23 G26 H3 H5 H21 H25 J1 J4 J6 J22 J24 K2 K5 K21 K23 K26 L3 L6 L22 L25 M1 M4 M5 M21 M24 N3 N6 N22 N23 N26 P2 P5 P21 P24 R1 R4 R6 R22 R25 T3 T5 T21 T23 T26 U2 U6 U22 U24 V1 V4 V5 V21 V25 W3 W6 W22 W23 W26 Y2 Y5 Y21 Y24

PZ47903

62.10055.011

C

VCCP_GMCH_S0

12

C21

C21 SCD1U10V2MX-1

SCD1U10V2MX-1

3D3V_S0

1 2 3

12

BC85

BC85 SC1U10V3ZY

SC1U10V3ZY

DY

0.1u *10 150u *1

12

C20

C20 SCD1U10V2MX-1

SCD1U10V2MX-1

VCC_CORE_S0

C29

C29 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C18

C19

SC10U6D3V5MX

12

SC10U6D3V5MX

I max = 120 mA

U52

SHDN# GND IN

G913C-U

DY

12

C30

C25

SCD1U10V2MX-1

12

C23

C24

SC10U6D3V5MX

SET

OUT

12

C16

C16 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C33

C35

SC10U6D3V5MX

1D5V_VCCA_S0

5 4

12

SC10U6D3V5MX

D

12

BC2

BC2 SC1U10V3ZY

SC1U10V3ZY

DY

12

C28

C31

C31 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C42

C36

SC10U6D3V5MX

BC84

BC84 SC22P

SC22P

DY

1D5V_VCCA_SET

12

C22

C22 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C39

C40

DY

SC10U6D3V5MX

12

R398

R398 49K9R2F

49K9R2F

DY

12

C32

C32 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C41

C50

DY

SC10U6D3V5MX

SC10U10V5ZY-L

12

TC1

TC1 ST100U6D3VM-U

ST100U6D3VM-U

12

C318

DY

SC10U10V5ZY-L

12

R397

R397 12K7R3F

12K7R3F

DY

12

C319

DY

SC10U10V5ZY-L

1D5V_VCCA_S0 1D5V_S0

12

C322

C321

DY

SC10U10V5ZY-L

R28

12

C323

DY

SC10U10V5ZY-L

1 2

12

C325

DY

SC10U10V5ZY-L

0R2-0

12

C324

E

12

C326

DY

SC10U10V5ZY-L

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet of

A

B

C

D

Date: Sheet of

CPU (2 of 2)

Leopard2

SC

547Sunday, July 03, 2005

E

of

SC

A

B

C

D

E

Trace 10 mil wide with 20 mil spacing

H_XRCOMP

12

R97

R97 24D9R2F

24D9R2F

4 4

VCCP_GMCH_S0

R96

R96 54D9R2F

54D9R2F

1 2

H_XSCOMP

VCCP_GMCH_S0

12

R105

R105 221R3F

221R3F

H_XSWING

12

R95

R95 100R2F

3 3

100R2F

1 2

C95

C95 SCD1U16V

SCD1U16V

VCCP_GMCH_S0

Trace 10 mil wide with 20 mil spacing

Alviso Strapping Signals and Configuration

Pin Name

CFG[2:0]

CFG[4:3] Reserved CFG5 DMI x2 Select

2 2

CFG6 Reserved 0 = DDR2

CFG7

CFG8

CFG9

CFG[11:10] CFG[13:12]

CFG[15:14] Reversed CFG16

CFG17 CFG18

1 1

CFG19

CFG20 SDVOCRTL

_DATA

All strap signals are sampled with respect to the leading

NOTE:

edge of the Alviso GMCH PWORK In signal.

Strap Description Configuration

CPU Strap

Reserved PCI Express Graphics

Lane Reversal Reserved XOR/ALL Z test

straps

FSB Dynamic ODT

Reversed GMCH core VCC

Select CPU VTT Select

Reversed SDVO Present

A

H_YRCOMP

12

R118

R118 24D9R2F

24D9R2F

R109

R109 54D9R2F

54D9R2F

1 2

H_YSCOMP

12

R116

R116 221R3F

221R3F

H_YSWING

12

R117

R117 100R2F

100R2F

001 = FSB533FSB Frequency Select

101 = FSB400

others = Reversed

0 = DMI x2

1 = DMI x4

1 = DDR1

0 = Reserved

1 = Dothan

0 = Reserve Lanes

1 = Normal

00 = Reserved 01 = XOR mode enabled 10 = All Z mode enabled

11 = Normal Operation

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled

0 = 1.05V

1 = 1.5V

0 = 1.05V

1 = 1.2V

C128

C128 SCD1U16V

SCD1U16V

1 2

REV.NO. 1.0 REF. NO. 15577

(Default)

0 = No SDVO device present

1= SDVO device present

U19A

H_D#[63..0]4 H_A#[31..3] 4

page 183

(Default)

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING

(Default)

ALVISO-GM:71.0GMCH.08U ALVISO-PM:71.0GMCH.0BU

E4 E1 F4 H7 E2 F1 E3 D3 K7 F2

J7

J8 H6 F3 K8 H5 H1 H2 K5 K6

J4

G3

H3

J1 L5 K4

J5 P7 L7

J3 P5 L3 U7 V6 R6 R5 P3 T8 R7 R8 U8 R4 T4 T5 R1 T3 V8 U6

W6

U3 V5

W8 W7

U2 U1 Y5 Y2 V4 Y7

W1 W3

Y3 Y6

W2

C1 C2 D1 T1 L1 P1

U19A

HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#

HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING

ALVISO-GM

HADSTB#0 HADSTB#1

HCPURST#

HOST

HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3

HCPUSLP#

HA3# HA4# HA5# HA6# HA7# HA8#

HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#

HADS#

HVREF HBNR#

HBPRI#

HBREQ0#

HCLKINN HCLKINP

HDBSY#

HDEFER#

HDINV#0 HDINV#1 HDINV#2 HDINV#3

HDPWR#

HDRDY#

HEDRDY#

HHIT# HHITM# HLOCK#

HPCREQ#

HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4

HRS0# HRS1# HRS2#

HTRDY#

G9 C9 E9 B7 A10 F9 D8 B10 E10 G10 D9 E11 F10 G11 G13 C10 C11 D11 C12 B13 A12 F12 G12 E12 C13 B11 D13 A13 F13

F8 B9 E13 J11 A5 D5 E7 H10

AB1 AB2

C6 E6 H8 K3 T7 U5 G6 F7 G4 K1 R3 V3 G5 K2 R2 W4 F6 D4 D6 B3 A11 A7 D7 B8 C7 A8 A4 C5 B4 G8 B5

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2

H_CPUSLP#_GMCH

H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4

H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_CPURST# 4

CLK_MCH_BCLK# 3 CLK_MCH_BCLK 3

H_DBSY# 4 H_DEFER# 4

H_DPWR# 4 H_DRDY# 4

H_HIT# 4 H_HITM# 4 H_LOCK# 4

H_TRDY# 4

VCCP_GMCH_S0

H_VREF

12

C384

C384 SCD1U10V2KX

SCD1U10V2KX

1 2

R54 0R0402-PADR54 0R0402-PAD

ALVISO-GML:71.0GMCH.0JU

B

C

12

R457

R457 100R2F

100R2F

12

R458

R458 200R2F

200R2F

H_DINV#[3..0] 4

H_DSTBN#[3..0] 4

H_DSTBP#[3..0] 4

H_REQ#[4..0] 4

H_RS#[2..0] 4

D

VID

VR_ON

Vcc_core

Vccp

Vcc_mch

MCH_PWERGD

CLK_ENABLE#

VGATE TO ICH6

H_CPUSLP# 4,21

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet of

Power On Sequencing

>3mS

Vboot Vvid

>100uS

3~10mS

647Monday, July 11, 2005

E

10~30uS

Vboot

<10uS

CORE_GMCH_S0

12

H_DPWR#

GMCH (1 of 5)

Leopard2

R519

R519 0R2-0

0R2-0

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-1

of

-1

A

U19B

AA31

DMIRXN0

AB35

DMIRXN1

AC31

DMIRXN2

AD35

DMIRXN3

Y31

DMIRXP0

AA35

DMIRXP1

AB31

DMIRXP2

AC35

DMIRXP3

AA33

DMITXN0

AB37

DMITXN1

AC33

DMITXN2

AD37

DMITXN3

Y33

DMITXP0

AA37

DMITXP1

AB33

DMITXP2

AC37

DMITXP3

AM33

SM_CK0

AL1

SM_CK1

AE11

SM_CK2

AJ34

SM_CK3

AF6

SM_CK4

AC10

SM_CK5

AN33

SM_CK0#

AK1

SM_CK1#

AE10

SM_CK2#

AJ33

SM_CK3#

AF5

SM_CK4#

AD10

SM_CK5#

AP21

SM_CKE0

AM21

SM_CKE1

AH21

SM_CKE2

AK21

SM_CKE3

AN16

SM_CS0#

AM14

SM_CS1#

AH15

SM_CS2#

AG16

SM_CS3#

AF22

SM_OCDCOMP0

AF16

SM_OCDCOMP1

AP14

SM_ODT0

AL15

SM_ODT1

AM11

SM_ODT2

AN10

SM_ODT3

AK10

SMRCOMPN

AK11

SMRCOMPP

AF37

SMVREF0

AD1

SMVREF1

AE27

SMXSLEWIN

AE28

SMXSLEWOUT

AF9

SMYSLEWIN

AF10

SMYSLEWOUT

ALVISO-GM

Ref ALVISO EDS-1 Page 115

For Dothan-B

R420

R420 1KR2

1KR2

CFG2 CFG1 CFG0

R419

CFG2=0(R419):133MHZ CFG2=1(R420):100MHZ

CPU_SEL0 3,4 CPU_SEL1 3,4

CFG(2..1) FREQ.(MHz) 10 400 00 533 11 Reserved

R535

R535 40D2R2F

40D2R2F

10KR2

FOR DDR2

R533

R533 80D6R2F

80D6R2F

M_RCOMPN M_RCOMPP

R543

R543 80D6R2F

80D6R2F

DMI_TXN[3..0]22

DMI_TXP[3..0]22

DMI_RXN[3..0]22

DMI_RXP[3..0]22

12

R534

R534 40D2R2F

40D2R2F

PM_EXTTS#0

PM_EXTTS#1

M_CLK_DDR011 M_CLK_DDR111

M_CLK_DDR311 M_CLK_DDR411

M_CLK_DDR#011 M_CLK_DDR#111

M_CLK_DDR#311 M_CLK_DDR#411

M_CKE011,12 M_CKE111,12 M_CKE211,12 M_CKE311,12

M_CS#011,12 M_CS#111,12 M_CS#211,12 M_CS#311,12

M_OCDCOMP0 M_OCDCOMP1

M_ODT011,12 M_ODT111,12 M_ODT211,12 M_ODT311,12

DDR_VREF_S3

A

12

C154

C154 SCD1U10V2MX-1

SCD1U10V2MX-1

R465

R465 10KR2

10KR2

4 4

3 3

Layout Note: Route as short as possible

12

2 2

2D5V_S0

1 2

R498

1 2

R471

1D8V_S3

12

1 1

12

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2

DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

M_RCOMPN M_RCOMPP

SMXSLEW SMYSLEW

VCCP_GMCH_S0

12

R437

R437 10KR2

10KR2

12

R438

4K7R2

DY

12

4K7R2

DY

B

CFG/RSVD

RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27

BM_BUSY#

EXT_TS0# EXT_TS1#

THRMTRIP#

PM

PWROK

DREF_CLKN DREF_CLKP

DREF_SSCLKN

CLK

DREF_SSCLKP

NC

B

CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

RSTIN#

DMI

DDR MUXING

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9

NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8

NC9 NC10 NC11

CFG1

H13 G14

CFG3 PEG_COMP

F16

CFG4

F15

CFG5

G15

CFG6

E16

CFG7

D17

CFG8

J16

CFG9

D15

CFG10

E15

CFG11

D14

CFG12

E14

CFG13

H12

CFG14

C14

CFG15

H15

CFG16

J15

CFG17

H14

CFG18

G22

CFG19

G23

CFG20

D23 G25 G24 J17 A31 A30 D26 D25

J23

PM_EXTTS#0

J21

PM_EXTTS#1

H22 F5 AD30 AE29

A24 A23 C37 D37

AP37 AN37 AP36 AP2 AP1 AN1 B1 A2 B37 A36 A37

CFG0

G16

When Low 2.2K Ohm

1 2

R441 DUMMY-R2R441 DUMMY-R2

1 2

R440 DUMMY-R2R440 DUMMY-R2

1 2

R464 DUMMY-R2R464 DUMMY-R2

1 2

R469 2K2R2R469 2K2R2

1 2

R442 DUMMY-R2R442 DUMMY-R2

1 2

R461 DUMMY-R2R461 DUMMY-R2

1 2

R439 DUMMY-R2R439 DUMMY-R2

1 2

R468 DUMMY-R2R468 DUMMY-R2

1 2

R69 DUMMY-R2R69 DUMMY-R2

1 2

R466 DUMMY-R2R466 DUMMY-R2

1 2

R459 DUMMY-R2R459 DUMMY-R2

1 2

R467 DUMMY-R2R467 DUMMY-R2

1 2

R463 DUMMY-R2R463 DUMMY-R2

1 2

R460 DUMMY-R2R460 DUMMY-R2

1 2

R462 DUMMY-R2R462 DUMMY-R2

RST1#

1 2

R52

1 2

R536

1KR2

C

CFG2

Note: CRT_RED, CRT_GREEN, CRT_BLUE, are ground referenced.

Place 150 Ohm termination resistors close to GMCH

PM_BMBUSY# 22

PM_THRMTRIP-A# 4,21 PWROK 25

100R2

DREFCLK# 3 DREFCLK 3 DREFSSCLK# 3 DREFSSCLK 3

PLT_RST1# 13,24,26

CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

Strapping

CFG16 CFG17

Intel suggest NC Due to votusly DVO

Intel design guide suggest Ref no.:14511 page 210

Note: Intel design guide suggest(page 203) If the LVDS interface is not implementd, all signals associated with the interface can be left as no connects.

CFG[17:3] have internal pullup resistors. CFG[19:18] have internal pulldown resistors

C

CLK_MCH_3GPLL#3

CLK_MCH_3GPLL3

CORE_GMCH_S0

Alviso will provide SDVO_CTRLCLK and CTRLDATA pulldowns on-die

SDVO_DAT

TP22TPAD30 TP22TPAD30

SDVO_CLK

TP23TPAD30 TP23TPAD30

R494 0R2-0R494 0R2-0

1 2

R495 0R2-0R495 0R2-0

1 2

R493 0R2-0R493 0R2-0

1 2

R492 0R2-0R492 0R2-0

1 2

H24

H25 AB29 AC29

A15

C16

A17

B15

B16

B17

E24

E23

E21

D21

C20

B20

A19

B19

H21

G21

E25

F25

C23

C22

F23

F22

F26

C33

C31

F28

F27

B30

B29

C25

C24

B34

B33

B32

A34

A33

B31

C29

D28

C27

C28

D27

C26

J18

J20

D

U19G

SDVOCTRL_DATA SDVOCTRL_CLK GCLKN GCLKP

TVDAC_A TVDAC_B TVDAC_C TV_REFSET TV_IRTNA TV_IRTNB TV_IRTNC

DDCCLK DDCDATA BLUE BLUE# GREEN GREEN# RED RED# VSYNC HSYNC REFSET

LBKLT_CRTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL

LACLKN LACLKP LBCLKN LBCLKP

LADATAN0 LADATAN1 LADATAN2

LADATAP0 LADATAP1 LADATAP2

LBDATAN0 LBDATAN1 LBDATAN2

LBDATAP0 LBDATAP1 LBDATAP2

ALVISO-GM

D

E

EXP_COMPI

EXP_ICOMPO

EXP_RXN0

MISCTVVGALVDS

EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8

EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

PCI-EXPRESS GRAPHICS

EXP_TXN7

EXP_TXN8

EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet of

D36 D34

PEG_RXN0

E30

PEG_RXN1

F34

PEG_RXN2

G30

PEG_RXN3

H34

PEG_RXN4

J30

PEG_RXN5

K34

PEG_RXN6

L30

PEG_RXN7

M34

PEG_RXN8

N30

PEG_RXN9

P34

PEG_RXN10

R30

PEG_RXN11

T34

PEG_RXN12

U30

PEG_RXN13

V34

PEG_RXN14

W30

PEG_RXN15

Y34

PEG_RXP0

D30

PEG_RXP1

E34

PEG_RXP2

F30

PEG_RXP3

G34

PEG_RXP4

H30

PEG_RXP5

J34

PEG_RXP6

K30

PEG_RXP7

L34

PEG_RXP8

M30

PEG_RXP9

N34

PEG_RXP10

P30

PEG_RXP11

R34

PEG_RXP12

T30

PEG_RXP13

U34

PEG_RXP14

V30

PEG_RXP15

W34

TXN0

E32

TXN1

F36

TXN2

G32

TXN3

H36

TXN4

J32

TXN5

K36

TXN6

L32

TXN7

M36

TXN8

N32

TXN9

P36

TXN10

R32

TXN11

T36

TXN12

U32

TXN13

V36

TXN14

W32

TXN15

Y36

TXP0

D32

TXP1

E36

TXP2

F32

TXP3

G36 H32

TXP5

J36

TXP6

K32

TXP7

L36 M32

TXP9

N36

TXP10

P32

TXP11

R36

TXP12

T32

TXP13

U36

TXP14

V32

TXP15

W36

2D5V_S0

GMCH (2 of 5)

Leopard2

R473

PEG_RXN[15..0] 13

PEG_RXP[15..0] 13

1 2

PEG_TXN0

SCD1U16V

PEG_TXN1

SCD1U16V

PEG_TXN2

SCD1U16V

PEG_TXN3

SCD1U16V

PEG_TXN4

SCD1U16V

PEG_TXN5

SCD1U16V

PEG_TXN6

SCD1U16V

PEG_TXN7

SCD1U16V

PEG_TXN8

SCD1U16V

PEG_TXN9

SCD1U16V

PEG_TXN10

SCD1U16V

PEG_TXN11

SCD1U16V

PEG_TXN12

SCD1U16V

PEG_TXN13

SCD1U16V

PEG_TXN14

SCD1U16V

PEG_TXN15

SCD1U16V

PEG_TXP0

SCD1U16V

PEG_TXP1

SCD1U16V

PEG_TXP2

SCD1U16V

PEG_TXP3

SCD1U16V

PEG_TXP4TXP4

SCD1U16V

PEG_TXP5

SCD1U16V

PEG_TXP6

SCD1U16V

PEG_TXP7

SCD1U16V

PEG_TXP8TXP8

SCD1U16V

PEG_TXP9

SCD1U16V

PEG_TXP10

SCD1U16V

PEG_TXP11

SCD1U16V

PEG_TXP12

SCD1U16V

PEG_TXP13

SCD1U16V

PEG_TXP14

SCD1U16V

PEG_TXP15

SCD1U16V

C372

C372 C107

C107 C387

C387 C108

C108 C386

C386 C116

C116 C409

C409 C118

C118 C410

C410 C117

C117 C430

C430 C131

C131 C429

C429 C130

C130 C452

C452 C142

C142 C373

C373 C97

C97 C389

C389 C106

C106 C388

C388 C105

C105 C407

C407 C119

C119 C408

C408 C115

C115 C431

C431 C129

C129 C432

C432 C132

C132 C453

C453 C143

C143

When High 1K Ohm

1 2

R470 DUMMY-R2R470 DUMMY-R2

1 2

R497 DUMMY-R2R497 DUMMY-R2

1 2

R496 DUMMY-R2R496 DUMMY-R2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

747Thursday, July 07, 2005

E

PEG_TXN[15..0]

PEG_TXP[15..0]

of

24D9R2F

13

1D5V_S0

12

CFG18 CFG19 CFG20

-1

A

4 4

U19C

M_A_DQ[63..0]11

3 3

2 2

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AG35 AH35

AL35 AL37

AH36

AJ35

AK37

AL34 AM36 AN35 AP32 AM31 AM34 AM35

AL32 AM32 AN31 AP31 AN28 AP28

AL30 AM30 AM28

AL28 AP27 AM27 AM23 AM22

AL23 AM24 AN22 AP22

AM9

AL9 AL6

AP7 AP11 AP10

AL7

AM7 AN5 AN6 AN3

AP3

AP6

AM6

AL4

AM3

AK2

AK3

AG2 AG1

AL3

AM2 AH3 AG3

AF3

AE3

AD6 AC4

AF2

AF1

AD4 AD5

U19C

SADQ0 SADQ1 SADQ2 SADQ3 SADQ4 SADQ5 SADQ6 SADQ7 SADQ8 SADQ9 SADQ10 SADQ11 SADQ12 SADQ13 SADQ14 SADQ15 SADQ16 SADQ17 SADQ18 SADQ19 SADQ20 SADQ21 SADQ22 SADQ23 SADQ24 SADQ25 SADQ26 SADQ27 SADQ28 SADQ29 SADQ30 SADQ31 SADQ32 SADQ33 SADQ34 SADQ35 SADQ36 SADQ37 SADQ38 SADQ39 SADQ40 SADQ41 SADQ42 SADQ43 SADQ44 SADQ45 SADQ46 SADQ47 SADQ48 SADQ49 SADQ50 SADQ51 SADQ52 SADQ53 SADQ54 SADQ55 SADQ56 SADQ57 SADQ58 SADQ59 SADQ60 SADQ61 SADQ62 SADQ63

ALVISO-GM

SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#

DDR SYSTEM MEMORY A

SA_RCVENIN#

SA_RCVENOUT#

SA_BS0# SA_BS1# SA_BS2#

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_CAS# SA_RAS#

SA_WE#

B

AK15 AK16 AL21

AJ37 AP35 AL29 AP24 AP9 AP4 AJ2 AD3

AK36 AP33 AN29 AP23 AM8 AM4 AJ1 AE5

AK35 AP34 AN30 AN23 AN8 AM5 AH1 AE4

AL17 AP17 AP18 AM17 AN18 AM18 AL19 AP20 AM19 AL20 AM16 AN20 AM20 AM15

AN15 AP16 AF29 AF28 AP15

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

GMCH_TP48 GMCH_TP49

M_A_BS#0 11,12 M_A_BS#1 11,12 M_A_BS#2 11,12 M_A_DM[7..0] 11

M_A_DQS[7..0] 11

M_A_DQS#[7..0] 11

M_A_A[13..0] 11,12

M_A_CAS# 11,12 M_A_RAS# 11,12

TP29 TPAD30TP29 TPAD30 TP28 TPAD30TP28 TPAD30

M_A_WE# 11,12

C

M_B_DQ[63..0]11

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AE31 AE32 AG32 AG36 AE34 AE33

AF31

AF30 AH33 AH32 AK31 AG30 AG34 AG33 AH31

AJ31 AK30

AJ30 AH29 AH28 AK29 AH30 AH27 AG28

AF24 AG23

AJ22 AK22 AH24 AH23 AG22

AJ21 AG10

AG9 AG8

AH8 AH11 AH10

AJ9

AK9

AJ7

AK6

AJ4 AH5 AK8

AJ8

AJ5 AK4 AG5 AG4 AD8 AD9 AH4 AG6 AE8 AD7 AC5 AB8 AB6 AA8 AC8 AC7 AA4 AA5

U19D

SBDQ0 SBDQ1 SBDQ2 SBDQ3 SBDQ4 SBDQ5 SBDQ6 SBDQ7 SBDQ8 SBDQ9 SBDQ10 SBDQ11 SBDQ12 SBDQ13 SBDQ14 SBDQ15 SBDQ16 SBDQ17 SBDQ18 SBDQ19 SBDQ20 SBDQ21 SBDQ22 SBDQ23 SBDQ24 SBDQ25 SBDQ26 SBDQ27 SBDQ28 SBDQ29 SBDQ30 SBDQ31 SBDQ32 SBDQ33 SBDQ34 SBDQ35 SBDQ36 SBDQ37 SBDQ38 SBDQ39 SBDQ40 SBDQ41 SBDQ42 SBDQ43 SBDQ44 SBDQ45 SBDQ46 SBDQ47 SBDQ48 SBDQ49 SBDQ50 SBDQ51 SBDQ52 SBDQ53 SBDQ54 SBDQ55 SBDQ56 SBDQ57 SBDQ58 SBDQ59 SBDQ60 SBDQ61 SBDQ62 SBDQ63

ALVISO-GM

D

SB_BS0# SB_BS1# SB_BS2#

SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

DDR SYSTEM MEMORY B

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13

SB_CAS# SB_RAS#

SB_RCVENIN#

SB_RCVENOUT#

SB_WE#

AJ15 AG17 AG21

AF32 AK34 AK27 AK24 AJ10 AK5 AE7 AB7

AF34 AK32 AJ28 AK23 AM10 AH6 AF8 AB4

AF35 AK33 AK28 AJ23 AL10 AH7 AF7 AB5

AH17 AK17 AH18 AJ18 AK18 AJ19 AK19 AH19 AJ20 AH20 AJ16 AG18 AG20 AG15

AH14 AK14 AF15 AF14 AH16

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

GMCH_TP50 GMCH_TP51

E

M_B_BS#0 11,12 M_B_BS#1 11,12 M_B_BS#2 11,12 M_B_DM[7..0] 11

M_B_DQS[7..0] 11

M_B_DQS#[7..0] 11

M_B_A[13..0] 11,12

M_B_CAS# 11,12 M_B_RAS# 11,12

TP27 TPAD30TP27 TPAD30 TP26 TPAD30TP26 TPAD30

M_B_WE# 11,12

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet of

GMCH (3 of 5)

Leopard2

E

847Thursday, July 07, 2005

of

-1

A

4 4

1D5V_DLVDS_S0

3 3

H17

B26

3D3V_S0 2D5V_S0

U59

2

VOUT

3

12

C359

C359 SCD1U10V2MX-1

SCD1U10V2MX-1

VIN

1

GND

APL5308-25AC-TR

12

C63

U19E

F17

E17

D18

C18

F18

E18

H18

VCCA_TVDACA0

VCCA_TVDACA1

VCCA_TVBG

VCCA_TVDACB0

VCCA_TVDACB1

VCCA_TVDACC0

VCCA_TVDACC1

G18

VSSA_TVBG

D19

B25

VCCD_LVDS0

VCCD_TVDAC

VCCDQ_TVDAC

B

G10

AE26

AP25

VCCSM15

12

AN25

AM25

VCCSM16

VCCSM17

1 2

C75

C75 SC10U10V5ZY-L

SC10U10V5ZY-L

AL25

AK25

AJ25

AH25

VCCSM18

VCCSM19

VCCSM20

VCCSM21

POWER

GAP-CLOSE-PWR

AG25

VCCSM22

VCCSM23

12

C76

C76 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C160

C160 SCD1U10V2MX-1

SCD1U10V2MX-1

Note: All VCCSM

C161

C161 SCD1U10V2MX-1

SCD1U10V2MX-1

V1.8_DDR_CAP5

AP29

AD28

AD27

AC27

VCCSM1

VCCSM2

VCCSM3

VCCSM4

VCCSM5

pins shorted internally

1 2

AP26

AN26

AM26

AL26

VCCSM6

VCCSM7

VCCSM8

VCCSM9

C165

C165 SCD1U10V2MX-1

SCD1U10V2MX-1

AK26

AJ26

AH26

AG26

AF26

VCCSM10

VCCSM11

VCCSM12

VCCSM13

VCCSM14

12

V1.8_DDR_CAP1

V1.8_DDR_CAP2

A25

A35

VCCD_LVDS1

VCCD_LVDS2

AM37

AH37

B22

B21

A21

VCCHV0

VCCHV1

VCCHV2

VCCA_LVDS

VCCSM0

AF25

AE25

VCCSM24

2D5V_S02D5V_TVDAC_S0

AE24

AE23

VCCSM25

VCCSM26

C

12

C449

C449 SC10U10V5ZY-L

SC10U10V5ZY-L

AE22

AE21

AE20

AE19

VCCSM27

VCCSM28

VCCSM29

VCCSM30

1D5V_S0

2D5V_S0 2D5V_ALVDS_S0

2D5V_S0 2D5V_TXLVDS_S0

G11

1 2

GAP-CLOSE-PWR

G13

1 2

GAP-CLOSE-PWR

G12

1 2

GAP-CLOSE-PWR

12

C79

C79 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C84

C84 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C81

C81 SCD1U10V2MX-1

SCD1U10V2MX-1

FOR DDR2

12

C447

C447 SC10U10V5ZY-L

SC10U10V5ZY-L

AE18

AE17

AE16

VCCSM31

VCCSM32

VCCSM33

AE15

AE14

VCCSM34

VCCSM35

12

TC9

TC9 ST100U4VBM-U

ST100U4VBM-U

DY

AP13

AN13

AM13

AL13

AK13

AJ13

AH13

AG13

AF13

AE13

AP12

VCCSM36

VCCSM37

VCCSM38

VCCSM39

VCCSM40

VCCSM41

VCCSM42

VCCSM43

VCCSM44

VCCSM45

VCCSM46

VCCSM47

1D5V_DLVDS_S0

12

C80

C80 SC10U10V5ZY-L

SC10U10V5ZY-L

12

C83

C83 SCD01U16V3KX

SCD01U16V3KX

12

C82

C82 SC4D7U10V5ZY

SC4D7U10V5ZY

1D8V_S3

Note: All VCCSM

AN12

AM12

AL12

AK12

AJ12

AH12

VCCSM48

VCCSM49

VCCSM50

VCCSM51

VCCSM52

VCCSM53

pins shorted internally

C164

1 2

SCD1U10V2MX-1

AG12

AF12

AE12

AD11

AC11

AB11

VCCSM54

VCCSM55

VCCSM56

VCCSM57

VCCSM58

VCCSM59

AB10

VCCSM60

AB9

VCCSM61

D

V1.8_DDR_CAP6

AP8

VCCSM62

V1.8_DDR_CAP4

12

C159

C159 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C158

C158 SCD1U10V2MX-1

SCD1U10V2MX-1

2D5V_TXLVDS_S02D5V_ALVDS_S0

V1.8_DDR_CAP3

AM1

AE1

B28

VCCSM63

VCCSM64

VCCTX_LVDS0

E

1D5V_S01D5V_DDRDLL_S0

G15

1 2

12

C472

C472 SCD1U10V2MX-1

SCD1U10V2MX-1

12

C385

C385 SC10U10V5ZY-L

SC10U10V5ZY-L

R37

VCC3G2

VCC3G3

N37

L37

VCC3G4

J37

VCC3G5

VCC3G6

Y29

VCCA_3GPLL0

AE37

W37

AF20

AP19

A28

A27

VCCA_SM0

VCCTX_LVDS1

VCCTX_LVDS2

U37

AF19

AF18

VCC3G0

VCC3G1

VCCA_SM1

VCCA_SM2

VCCA_SM3

GAP-CLOSE-PWR

C166

C166 ST100U6D3VM-U

ST100U6D3VM-U

C451

C451 SC10U10V5ZY-L

SC10U10V5ZY-L

Y28

12

TC22

TC22 ST100U6D3VM-U

ST100U6D3VM-U

DY

1D5V_3GPLL_S0

1 2

12

C473

C473 SC10U10V5ZY-L

SC10U10V5ZY-L

C450

C450 SCD1U10V2MX-1

SCD1U10V2MX-1

2D5V_3GBG_S0 2D5V_S0

12

Y27

G37

F37

VSSA_3GBG

VCCA_3GBG

VCCA_3GPLL2

VCCA_3GPLL1

1D5V_S01D5V_PCIE_S0

G55

1 2

GAP-CLOSE-PWR

1D5V_S0

G54

GAP-CLOSE-PWR

G14

1 2

C96

GAP-CLOSE-PWR

SCD1U10V2MX-1

VCC0

VCC1

VCC2

VCC3

VCC4

VCC5

VCC6

VCC7

VCC8

VCC9

VCC10

VCC11

VCC12

VCC13

VCC14

VCC15

VCC16

VCC17

VCC18

VCC19

VCC20

VCC21

VCC22

VCC23

VCC24

VCC25

VCC26

VCC27

VCC28

VCC29

VCC30

VCC31

VCC32

VCC33

VCC34

VCC35

VCC36

VCC37

VCC38

VCC39

VCC40

VCC41

VCC42

VCC43

VCC44

VCC45

VCC46

VCC47

VCC48

VCCH_MPLL1

VCCH_MPLL0

VCCA_DPLLA

VCCA_DPLLB

VCCA_HPLL

VCCA_MPLL

VCCA_CRTDAC0

VCCA_CRTDAC1

VSSA_CRTDAC

VCC_SYNC

VTT0

VTT1

VTT2

VTT3

VTT4

VTT5

VTT6

VTT7

VTT8

VTT9

VTT10

VTT11

VTT12

VTT13

VTT14

VTT15

VTT16

VTT17

VTT18

VTT19

VTT20

VTT21

VTT22

SC4D7U6D3V5KX

2 2

CORE_GMCH_S0

12

1 1

12

C448

C448 SC10U10V5ZY-L

SC10U10V5ZY-L

12

C403

C403 SC10U10V5ZY-L

SC10U10V5ZY-L

A

C404

SC10U10V5ZY-L

12

J29

T29

K29

R29

N29

M29

12

C406

C406 SCD1U10V2MX-1

SCD1U10V2MX-1

T28

V28

P28

U28

R28

N28

GMCH_CORE_VCC

C405

C405 SCD1U10V2MX-1

SCD1U10V2MX-1

J28

L28

K28

H28

M28

12

C428

C428 SCD1U10V2MX-1

SCD1U10V2MX-1

1D5V_S0

12

G53

GAP-CLOSE-PWR

G28

T27

V27

U27

B

L27

P27

R27

N27

M27

L2

1 2

IND-D1UH

L31

1 2

IND-D1UH

L11

1 2

IND-D1UH

L13

1 2

IND-D1UH

K27

J27

H27

J25

K26

K25

H26

12

C78

C78 SC10U6D3V5MX

SC10U6D3V5MX

DY

12

C370

C370 SC10U6D3V5MX

SC10U6D3V5MX

DY

12

C139

C139 SC10U6D3V5MX

SC10U6D3V5MX

DY

12

C153

C153 SC10U6D3V5MX

SC10U6D3V5MX

DY

K24

T20

K23

K22

K21

K20

U20

W20

12

V19

K19

V18

U19

W18

1D5V_HMPLL_S0

1D5V_DPLLA_S0

C77

C77 SCD1U10V2MX-1

SCD1U10V2MX-1

1D5V_DPLLB_S0

C371

C371 SCD1U10V2MX-1

SCD1U10V2MX-1

1D5V_HPLL_S0

C141

C141 SCD1U10V2MX-1

SCD1U10V2MX-1

1D5V_MPLL_S0

C140

C140 SCD1U10V2MX-1

SCD1U10V2MX-1

T18

K18

K17

AC2

F19

B23

AC1

E19

C35

AA1

AA2

G19

C

J13

K13

K12

H20

W11

VCCP_GMCH_S0

12

C103

SCD1U10V2MX-1

V11

U11

2D5V_S0

T11

P11

R11

N11

R55 10R2R55 10R2

12

C102

ST100U6D3VM-U

L11

K11

M11

W10

1 2

12

T10

V10

U10

R10

C114

C114 SC10U10V6ZY-U

SC10U10V6ZY-U

VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51

J10

P10

K10

N10

M10

VCCP_GMCH_CAP1

12

C74

C74 SCD47U16V3ZY

SCD47U16V3ZY

VCCP_GMCH_S0

D6

21

SSM5818SL

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

D

Date: Sheet of

12

C73

C73 SCD47U16V3ZY

SCD47U16V3ZY

12

C427

C427 SC4D7U10V5ZY

SC4D7U10V5ZY

GMCH (4 of 5)

G1

VCCP_GMCH_CAP2

VCCP_GMCH_CAP3

VCCP_GMCH_CAP4

12

C127

C104

C104 SCD22U16V3ZY

SCD22U16V3ZY

12

C426

C426 SC4D7U10V5ZY

SC4D7U10V5ZY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Leopard2

947Thursday, July 07, 2005

E

-1

A

4 4

L29

H29

G29

F29

E29

D29

A29

AC28

AB28

AA28

W28

E28

AN27

AL27

AJ27

AG27

AF27

AB27

AA27

W27

G27

E27

B27

J26

G26

E26

A26

AN24

U19F

ALVISO-GM

3 3

AL24

VSS109

VSS110

VSS111

VSS112

VSS113

VSS114

VSS115

VSS116

VSS117

VSS118

VSS119

VSS120

VSS121

VSS122

VSS123

VSS124

VSS125

VSS126

VSS127

VSS128

VSS129

VSS261

VSS262

VSS263

VSS264

VSS265

VSS266

VSS267

VSS259P2VSS258T2VSS257V2VSS256

VSS255

VSS254

VSS253

VSS252

VSS251A3VSS250C3VSS249

VSS248

VSS247

VSS246

AA3

AB3

AC3

VSS245C4VSS244H4VSS243L4VSS242P4VSS241U4VSS240Y4VSS239

AJ3

AF4

AN4

VSSALVDS

B36

VSS260L2VSS268J2VSS269G2VSS270D2VSS271

Y1

AL2

AE2

AD2

AH2

AN2

B

W31

V31

U31

T31

R31

P31

N31

M31

L31

K31

J31

H31

G31

F31

E31

D31

AP30

AE30

AC30

AB30

AA30

Y30

C30

AM29

AJ29

AG29

AD29

AA29

W29

V29

U29

P29

VSS76

VSS77

VSS78

VSS79

VSS80

VSS81

VSS82

VSS83

VSS84

VSS85

VSS86

VSS87

VSS88

VSS89

VSS90

VSS91

VSS92

VSS93

VSS94

VSS95

VSS96

VSS97

VSS98

VSS99

VSS100

VSS101

VSS102

VSS103

VSS104

VSS105

VSS106

VSS107

VSS108

VSS238

VSS237E5VSS236W5VSS235

VSS234

AL5

AP5

VSS233B6VSS232J6VSS231L6VSS230P6VSS229T6VSS228

AA6

VSS227

VSS226

VSS225

VSS224G7VSS223V7VSS222

VSS221

VSS220

VSS219

VSS218C8VSS217E8VSS216L8VSS215P8VSS214Y8VSS213

AJ6

AE6

AA7

AC6

AK7

AN7

AG7

VSS212A9VSS211H9VSS210K9VSS209T9VSS208V9VSS207

AL8

AA9

VSS206

AC9

AD31

AE9

VSS75

VSS205

AG31

VSS74

VSS

VSS204

AH9

C

AA34

C34

AL33

AF33

AD33

W33

V33

U33

T33

R33

P33

N33

M33

L33

K33

J33

H33

G33

F33

E33

D33

AN32

AJ32

AD32

AC32

AB32

AA32

Y32

C32

A32

AL31

VSS44

VSS45

VSS46

VSS47

VSS48

VSS49

VSS50

VSS51

VSS52

VSS53

VSS54

VSS55

VSS56

VSS57

VSS58

VSS59

VSS60

VSS61

VSS62

VSS63

VSS64

VSS65

VSS66

VSS67

VSS68

VSS69

VSS70

VSS71

VSS72

VSS73

VSS196

VSS195

VSS194

VSS193

VSS192

VSS191

VSS190

VSS189

VSS188

VSS187

VSS186

VSS185

VSS184

VSS183

VSS182

VSS181

VSS180

VSS179

VSS178

VSS177

VSS176

VSS175

VSS203

VSS202

VSS201

VSS200

VSS199

VSS198

VSS197

J12

L10

F11

Y11

Y10

D10

AN9

H11

AA11

AA10

B12

AJ11

AL11

AF11

AN11

AG11

D12

J14

F14

A14

B14

K14

AJ14

AG14

VSS174

K15

A16

C15

D16

AL14

H16

AN14

D

AJ36

AF36

AE36

AD36

AC36

AB36

AA36

C36

AE35

Y35

W35

V35

U35

T35

R35

P35

N35

M35

L35

K35

J35

H35

G35

F35

E35

D35

B35

AN34

AH34

AD34

AC34

AB34

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

VSS31

VSS32

VSS33

VSS34

VSS35

VSS36

VSS37

VSS38

VSS39

VSS40

VSS41

VSS42

VSS43

VSS173

VSS172

VSS171

VSS170

VSS169

VSS168

VSS167

VSS166

VSS165

VSS164

VSS163

VSS162

VSS161

VSS160

VSS159

VSS158

VSS157

VSS156

VSS155

VSS154

VSS153

VSS152

VSS151

VSS150

VSS149

VSS148

VSS147

VSS146

VSS145

VSS144

VSS143

VSS142

VSS141

J19

K16

AL16

C17

G17

A18

B18

AJ17

AF17

AN17

U18

T19

C19

H19

W19

AL18

F20

G20

F21

V20

A22

C21

AK20

E22

D22

AF21

AN21

A20

E20

D20

AN19

AG19

E

AL36

K37

H37

E37

AN36

VSS7

VSS8

VSS9

VSS10

VSS140

VSS139

VSS138

VSS137

J22

H23

AL22

AF23

AH22

M37

VSS6

VSS136

B24

P37

VSS5

VSS135

D24

T37

VSS4

VSS134

F24

V37

VSS3

VSS133

J24

Y37

VSS2

VSS132

AG24

AG37

VSS1

VSS131

AJ24

VSS0

VSS130

VCC_NCTF6

VSS_NCTF6

P26

VCC_NCTF5

VSS_NCTF5

Y25

R26

AA25

VCC_NCTF4

VSS_NCTF4

T26

VCC_NCTF3

VSS_NCTF3

AB25

CORE_GMCH_S0

W26

V26

U26

VCC_NCTF0

VCC_NCTF1

VCC_NCTF2

VSS_NCTF2

VSS_NCTF1

VSS_NCTF0

Y26

AA26

AB26

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GMCH (5 of 5)

Leopard2

10 47Thursday, July 07, 2005

E

-1

of

-1

AD14

AC14

AD13

VCCSM_NCTF24

VCCSM_NCTF25

VCCSM_NCTF26

VCCSM_NCTF27

VCCP_GMCH_S0

FOR DDR2

AC18

AD17

AC17

AD16

AC16

AD15

AC15

VCCSM_NCTF17

VCCSM_NCTF18

VCCSM_NCTF19

VCCSM_NCTF20

VCCSM_NCTF21

VCCSM_NCTF22

VCCSM_NCTF23

AD21

AC21

AD20

AC20

AD19

AC19

AD18

VCCSM_NCTF13

VCCSM_NCTF14

VCCSM_NCTF15

VCCSM_NCTF16

AD23

AC23

AD22

AC22

VCCSM_NCTF7

VCCSM_NCTF8

VCCSM_NCTF9

VCCSM_NCTF10

VCCSM_NCTF11

VCCSM_NCTF12

VTT_NCTF17

VTT_NCTF16

VTT_NCTF15

VTT_NCTF14

VTT_NCTF13

L12

T12

P12

N12

R12

M12

B

VCCSM_NCTF6

VTT_NCTF12

AC24

U12

VCCSM_NCTF5

VTT_NCTF11

AD24

V12

AC25

VCCSM_NCTF4

VTT_NCTF10

W12

VCCSM_NCTF3

VTT_NCTF9

AD26

AC26

AD25

L13

VCCSM_NCTF2

VTT_NCTF8

M13

VCCSM_NCTF1

VTT_NCTF7

N13

VCCSM_NCTF0

VTT_NCTF6

N17

M17

L17

VCC_NCTF77

VCC_NCTF78

VTT_NCTF5

VTT_NCTF4

VTT_NCTF3

T13

P13

R13

U13

VCC_NCTF76

VTT_NCTF2

L18

W17

V17

U17

T17

P17

V13

VCC_NCTF75

VTT_NCTF1

W13

VCC_NCTF74

VTT_NCTF0

M18

VCC_NTTF69

VCC_NCTF70

VCC_NCTF71

VCC_NCTF72

VCC_NCTF73

N18

Y12

N19

M19

L19

Y18

R18

P18

VCC_NCTF63

VCC_NCTF64

VCC_NCTF65

VCC_NCTF66

VCC_NCTF67

VCC_NCTF68

VSS_NCTF68

VSS_NCTF67

VSS_NCTF66

VSS_NCTF65

VSS_NCTF64

VSS_NCTF63

L14

Y13

N14

M14

AA12

AA13

N20

M20

L20

Y19

R19

P19

VCC_NCTF56

VCC_NCTF57

VCC_NCTF58

VCC_NCTF59

VCC_NCTF60

VCC_NCTF61

VCC_NCTF62

NCTF

VSS_NCTF62

VSS_NCTF61

VSS_NCTF60

VSS_NCTF59

VSS_NCTF58

VSS_NCTF57

VSS_NCTF56

T14

P14

V14

R14

U14

W14

P21

N21

M21

L21

Y20

R20

P20

VCC_NCTF53

VCC_NCTF54

VCC_NCTF55

VSS_NCTF55

VSS_NCTF54

VSS_NCTF53

L15

Y14

AA14

AB14

C

V21

U21

T21

VCC_NCTF49

VCC_NCTF50

VCC_NCTF51

VCC_NCTF52

VCC_NCTF47

VCC_NCTF48

VSS_NCTF52

VSS_NCTF51

VSS_NCTF50

VSS_NCTF49

VSS_NCTF48

VSS_NCTF47

T15

P15

N15

R15

U15

M15

R22

P22

N22

M22

L22

W21

VCC_NCTF41

VCC_NCTF42

VCC_NCTF43

VCC_NCTF44

VCC_NCTF45

VCC_NCTF46

VSS_NCTF46

VSS_NCTF45

VSS_NCTF44

VSS_NCTF43

VSS_NCTF42

VSS_NCTF41

L16

V15

Y15

W15

AA15

AB15

M23

L23

W22

V22

U22

T22

VCC_NCTF35

VCC_NCTF36

VCC_NCTF37

VCC_NCTF38

VCC_NCTF39

VCC_NCTF40

VSS_NCTF40

VSS_NCTF39

VSS_NCTF38

VSS_NCTF37

VSS_NCTF36

VSS_NCTF35

T16

P16

N16

R16

U16

M16

V23

U23

T23

R23

P23

N23

VCC_NCTF29

VCC_NCTF30

VCC_NCTF31

VCC_NCTF32

VCC_NCTF33

VCC_NCTF34

VSS_NCTF34

VSS_NCTF33

VSS_NCTF32

VSS_NCTF31

VSS_NCTF30

VSS_NCTF29

V16

Y16

R17

W16

AA16

AB16

R24

P24

N24

M24

L24

W23

VCC_NCTF23

VCC_NCTF24

VCC_NCTF25

VCC_NCTF26

VCC_NCTF27

VCC_NCTF28

VSS_NCTF28

VSS_NCTF27

VSS_NCTF26

VSS_NCTF25

VSS_NCTF24

VSS_NCTF23

Y17

AA17

AB17

AA18

AB18

AA19

M25

L25

W24

V24

U24

T24

VCC_NCTF17

VCC_NCTF18

VCC_NCTF19

VCC_NCTF20

VCC_NCTF21

VCC_NCTF22

VSS_NCTF22

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

Y21

R21

AB19

AA20

AB20

AA21

D

V25

U25

T25

R25

P25

N25

VCC_NCTF13

VCC_NCTF14

VCC_NCTF15

VCC_NCTF16

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF13

Y22

AB21

AA22

AB22

N26

M26

L26

W25

VCC_NCTF7

VCC_NCTF8

VCC_NCTF9

VCC_NCTF10

VCC_NCTF11

VCC_NCTF12

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

Y23

Y24

AA23

AB23

AA24

AB24

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

Date: Sheet

1D8V_S3

AC13

AB13

AD12

AC12

U19H

2 2

ALVISO-GM

1 1

A

AB12

VCCSM_NCTF28

VCCSM_NCTF29

VCCSM_NCTF30

VCCSM_NCTF31

A

DM2

M_B_A[13..0]8,12

4 4

M_B_BS#28,12 M_B_BS#08,12

M_B_BS#18,12

M_B_DQ[63..0]8

3 3

2 2

M_B_DQS#[7..0]8

M_B_DQS[7..0]8

1 1

M_ODT27,12 M_ODT37,12

12

SC2D2U6D3V3MX-1

C548

12

BC123

BC123 SCD1U16V

SCD1U16V

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

102 101 100

99 98 97 94 92 93 91

105

90 89

116

86 84 85

107 106

17 19

14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74

76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194

11

29

49

68 129 146 167 186

13

31

51

70 131 148 169 188

114 119

202

DM2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

BA0 BA1

5

DQ0

7

DQ1 DQ2 DQ3

4

DQ4

6

DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

/DQS0 /DQS1 /DQS2 /DQS3 /DQS4 /DQS5 /DQS6 /DQS7

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

1

VREF

2

VSS GND

DDR2-200P-4

/RAS

/WE

/CAS /CS0

/CS1

CKE0 CKE1

CK0

/CK0

CK1

/CK1 DM0

DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA SCL

VDDSPD

SA0 SA1

NC#50 NC#69 NC#83

NC#120

NC#163/TEST

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NORMAL TYPE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND

Hi 9.2 mm

A

B

108 109 113

110 115

79 80

30 32

164 166

M_B_DM0

10

M_B_DM1

26

M_B_DM2

52

M_B_DM3

67

M_B_DM4

130

M_B_DM5

147

M_B_DM6

170

M_B_DM7

185 195

197 199 198

200 50

69 83 120 163

81 82 87 88 95 96 103 104 111 112 117 118

3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196

201

1 2

R229

12

R230

R230 10KR2

10KR2

1D8V_S3

10KR2

M_B_RAS# 8,12 M_B_WE# 8,12 M_B_CAS# 8,12

M_CS#2 7,12 M_CS#3 7,12

M_CKE2 7,12 M_CKE3 7,12

M_CLK_DDR3 7 M_CLK_DDR#3 7

M_CLK_DDR4 7 M_CLK_DDR#4 7 M_B_DM[7..0] 8

SMBD_ICH 3,24 SMBC_ICH 3,24

3D3V_S0

12

BC122

SCD1U16V

12

Place near DM1

M_CLK_DDR4

12

C231

C231 SC10P50V2JN-1

SC10P50V2JN-1

DY

M_CLK_DDR#4 M_CLK_DDR3

12

C244

C244 SC10P50V2JN-1

SC10P50V2JN-1

DY

M_CLK_DDR#3

High 9.2mm

B

C

M_A_DQ[63..0]8

3D3V_S0

C547

C547 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

DY

M_A_DQS#[7..0]8

M_A_DQS[7..0]8

DDR_VREF_S3DDR_VREF_S3

SBSB

C

M_A_A[13..0]8,12

M_A_BS#28,12 M_A_BS#08,12

M_A_BS#18,12

M_ODT07,12 M_ODT17,12

12

SC2D2U6D3V3MX-1

C205

12

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

BC43

BC43 SCD1U16V

SCD1U16V

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

102 101 100

99 98 97 94 92 93 91

105

90 89

116

86 84 85

107 106

5

7 17 19

4

6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76

123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194

11 29 49 68

129 146 167 186

13 31 51 70

131 148 169 188

114 119

1

2

202

DM1

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

BA0 BA1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

/DQS0 /DQS1 /DQS2 /DQS3 /DQS4 /DQS5 /DQS6 /DQS7

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF VSS

GND

DDR2-200P-5

Low5.2 mm

D

108

/RAS

109

/WE

113

/CAS

110

/CS0

115

/CS1

79

CKE0

80

CKE1

30

CK0

32

/CK0

164

CK1

166

/CK1 DM0

DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

VDDSPD

NC#50 NC#69 NC#83

NC#120

NC#163/TEST

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

NORMAL TYPE

GND

D

SCL

SA0 SA1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

M_A_DM0

10

M_A_DM1

26

M_A_DM2

52

M_A_DM3

67

M_A_DM4

130

M_A_DM5

147

M_A_DM6

170

M_A_DM7

185

SMBD_ICH

195

SMBC_ICH

197 199 198

200

12

50 69 83 120 163

81 82 87 88 95 96 103 104 111 112 117 118

3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196

201

R175

R175 10KR2

10KR2

Title

Size Document Number Rev

Custom

Date: Sheet

12

1D8V_S3

M_A_RAS# 8,12 M_A_WE# 8,12 M_A_CAS# 8,12

M_CS#0 7,12 M_CS#1 7,12

M_CKE0 7,12 M_CKE1 7,12

M_CLK_DDR0 7 M_CLK_DDR#0 7

M_CLK_DDR1 7 M_CLK_DDR#1 7

M_A_DM[7..0] 8

BC44

SCD1U16V

R176

R176 10KR2

10KR2

Place near DM2

DY

DDR2 Socket

E

3D3V_S0

12

C220

C220 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

DY

M_CLK_DDR0

12

C511

C511 SC10P50V2JN-1

SC10P50V2JN-1

M_CLK_DDR#0 M_CLK_DDR1

12

C510

C510 SC10P50V2JN-1

SC10P50V2JN-1

M_CLK_DDR#1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Leopard2 -1

11 47Thursday, July 07, 2005

of

E

of

A

B

C

D

PARALLEL TERMINATION Decoupling Capacitor

E

Put decap near power(0.9V) and pull-up resistor

DDR_VREF

4 4

3 3

2 2

1 1

DDR_VREF

R561 56R2JR561 56R2J R608 56R2JR608 56R2J R562 56R2JR562 56R2J R609 56R2JR609 56R2J

RN30

A

RN28

8 7 6

SRN56-1

1 2 1 2 1 2 1 2

8 7 6

RN26

8 7 6

SRN56-1

SRN56-1 RN27

RN27

8 7 6

SRN56-1

SRN56-1 RN31

RN31

8 7 6

SRN56-1

SRN56-1 RN29

RN29

8 7 6

SRN56-1

SRN56-1 RN15

RN15

8 7 6

SRN56-1

SRN56-1 RN13

RN13

8 7 6

SRN56-1

SRN56-1 RN14

RN14

8 7 6

SRN56-1

SRN56-1 RN16

RN16

8 7 6

SRN56-1

SRN56-1 RN17

RN17

8 7 6

SRN56-1

SRN56-1 RN12

RN12

8 7 6

SRN56-1

1 2 3 45

SRN56-1

1 2 3 45

M_B_A10 M_B_A11

M_B_A1

M_A_A12 M_B_A3

M_B_A0 M_B_A2 M_B_A7

M_B_A13

M_B_A4 M_B_A6

M_B_A5 M_B_A8 M_B_A9 M_B_A12

M_A_A8 M_A_A1 M_A_A4 M_A_A2

M_A_A13 M_A_A10

M_A_A0 M_A_A3

M_A_A5 M_A_A11 M_A_A7 M_A_A6

M_A_A9

M_B_BS#1 8,11

M_CS#1 7,11 M_CS#3 7,11

M_B_BS#2 8,11

M_ODT2 7,11 M_ODT3 7,11

M_CS#2 7,11

M_B_RAS# 8,11 M_B_CAS# 8,11 M_B_WE# 8,11 M_B_BS#0 8,11

M_CKE2 7,11

M_CKE3 7,11

M_CS#0 7,11 M_ODT0 7,11

M_A_BS#1 8,11 M_A_RAS# 8,11

M_CKE0 7,11 M_A_BS#2 8,11 M_CKE1 7,11

M_A_WE# 8,11 M_A_BS#0 8,11 M_A_CAS# 8,11 M_ODT1 7,11

B

M_A_A[13..0] 8,11 M_B_A[13..0] 8,11

1D8V_S3

12

DY

Put decap near power(0.9V) and pull-up resistor

12

C554

C499

C499 SCD1U16V

SCD1U16V

DY

12

C553

C553 SCD1U16V

SCD1U16V

DY

12

C236

C236 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

12

C233

C233 SCD1U16V

SCD1U16V

C554 SCD1U16V

SCD1U16V

C550

C550 SCD1U16V

SCD1U16V

12

DY

C

12

C193

C193 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

12

C201

C201 SCD1U16V

SCD1U16V

DY

12

C235

C235 SCD1U16V

SCD1U16V

DY

C500

C500 SCD1U16V

SCD1U16V

C556

C556 SCD1U16V

SCD1U16V

Place these Caps near DM1

Place these Caps near DM2

12

C501

C501 SCD1U16V

SCD1U16V

12

C492

C492 SCD1U16V

SCD1U16V

12

C204

C204 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

12

C192

C191

SCD1U16V

DY

C240

C240 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

12

C241

C241 SCD1U16V

SCD1U16V

DY

12

DY

12

C242

SCD1U16V

12

C502

C502 SCD1U16V

SCD1U16V

12

C557

C557 SCD1U16V

SCD1U16V

12

C203

C203 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

12

C202

C202 SCD1U16V

SCD1U16V

C243

C243 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

C551

C551 SCD1U16V

SCD1U16V

DY

C558

C558 SCD1U16V

SCD1U16V

12

C503

C503 SCD1U16V

SCD1U16V

12

C552

C552 SCD1U16V

SCD1U16V

DY

12

C232

C232 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

D

C555

C555 SCD1U16V

SCD1U16V

DY

C495

C495 SCD1U16V

SCD1U16V

12

C234

C234 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

12

C200

C200 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

12

C493

C493 SCD1U16V

SCD1U16V

DY

12

C496

C496 SCD1U16V

SCD1U16V

12

C190

C190 SC2D2U6D3V3MX-1

SC2D2U6D3V3MX-1

Title

Size Document Number Rev

A3

Date: Sheet of

Date: Sheet

12

C497

C497 SCD1U16V

SCD1U16V

DY

12

C504

C504 SCD1U16V

SCD1U16V

DDR2 Termination Resistor

C498

C498 SCD1U16V

SCD1U16V

DY

C559

C559 SCD1U16V

SCD1U16V

12

C494

C494 SCD1U16V

SCD1U16V

C560

C560 SCD1U16V

SCD1U16V

Leopard2 -1

C562

C562 SCD1U16V

SCD1U16V

12

C561

C561 SCD1U16V

SCD1U16V

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

12 47Thursday, July 07, 2005

of

A

12

R443

R443 1MR2

C65

1MR2

BC90

BC90 SC6P50V3DN

SC6P50V3DN

12

BC95

SC22P

4 4

SCD1U16V3KX

P2779A_XIN

X5

XTAL-27MHZ-3-U1

1 2

P2779A_XOUT

1 2

620R3F

R56

P2779A_LF

12

U57

1

XIN/CLKIN

2

XOUT

3

PD#

4

LF

P2779A-08ST

C64

C64 SC270P50V

SC270P50V

VDD REF

MODOUT

VSS

XTALIN_M24

adjust SWING at 1.2v

PEG_TXP[15..0]7 PEG_TXN[15..0]7

3 3

2 2

1 1

PEG_RXP[15..0]7 PEG_RXN[15..0]7

3D3V_S0

12

R504

R504 10KR2

10KR2

STERE0SYNC PWRGD_MASK

12

R503

R503 DUMMY-R2

DUMMY-R2

3D3V_S0

12

1 2

R481

R481 DUMMY-R2

DUMMY-R2

R480

R480 0R2-0

0R2-0

ATI suggest 0 ohm

DY

R525

M24_RST#22

PLT_RST1#7,24,26

1 2

0R2-0

0R2-0 R524

R524

1 2

0R2-0

U62

1

A

2

B GND3Y

NC7S08-U

VCC

LUMA_VGA18

CRMA_VGA18

COMP_VGA18

DDC_CLK & DATA level shift

3D3V_S03D3V_S0 3D3V_S0

12

R445

R445 4K7R2

4K7R2

VGA_DDCDATA DDC_DATA

VGA_DDCCLK DDC_CLK

12

A

R446

R446 4K7R2

4K7R2

2 3

G

S

12

R57

R57 0R2-0

0R2-0

1

Q37

Q37 2N7002

2N7002

D

Q38 2N7002

2 3

S

0703 -1

G

1

D

5

4

3D3V_S0

PERSTBPERSTB

R71

R71 150R2

150R2

3D3V_S0

12

R505

R505 4K7R2

4K7R2

1D2V_VDDR_S0

12

R73

R73 150R2

150R2

DDC_DATA 20

DDC_CLK 20

R506

R506 4K7R2

4K7R2

R74

R74 150R2

150R2

B

3D3V_SS_S0

8

P2779A_REF

7

VGA_GPIO16

6 5

EDID_CLK 19,25 EDID_DAT 19,25

DDC3_CLK 19,25 DDC3_DATA 19,25

R70 10KR2R70 10KR2

B

3D3V_S0

12

C360

C360 SCD1U16V

SCD1U16V

12

R444

R444 182R3F

182R3F

12

R474

R474 105R3F

105R3F

CLK_PCIE_PEG3

CLK_PCIE_PEG#3

R447 150R2FR447 150R2F

1 2

R520 100R2FR520 100R2F

1 2

R448 10KR2F-UR448 10KR2F-U

1 2 1 2

R98 10KR2R98 10KR2

1 2

715R3

R502

1 2 1 2

10KR2

R501

R99 1KR2R99 1KR2

1 2

R537 1KR2R537 1KR2

1 2

R138 1KR2R138 1KR2

1 2

R472

R472 0R5J-1

0R5J-1

PEG_RXP0 PEG_RXN0 PEG_RXP1 PEG_RXN1 PEG_RXP2 PEG_RXN2 PEG_RXP3 PEG_RXN3 PEG_RXP4 PEG_RXN4 PEG_RXP5 PEG_RXN5 PEG_RXP6 PEG_RXN6 PEG_RXP7 PEG_RXN7 PEG_RXP8 PEG_RXN8 PEG_RXP9 PEG_RXN9 PEG_RXP10 PEG_RXN10 PEG_RXP11 PEG_RXN11 PEG_RXP12 PEG_RXN12 PEG_RXP13 PEG_RXN13 PEG_RXP14 PEG_RXN14 PEG_RXP15 PEG_RXN15

SCD1U16V

SCD1U16V C110

C110

1 2

C109C109

C391C391

1 2

C392C392

C111C111

1 2

C112C112

C393C393

1 2

C390C390

C120C120

1 2

C121C121

C412C412

1 2

C414C414

C123C123

1 2

C122C122

C413C413

1 2

C411C411

C137C137

1 2

C134C134

C435C435

1 2

C436C436

C135C135

1 2

C133C133

C433C433

1 2

C434C434

C136C136

1 2

C146C146

C455C455

1 2

C456C456

C145C145

1 2

C147C147

C454C454

1 2

C457C457

PEG_TXP0

PEG_TXN0

PEG_TXP1

PEG_TXN1

PEG_TXP2

PEG_TXN2

PEG_TXP3

PEG_TXN3

PEG_TXP4

PEG_TXN4

PEG_TXP5

PEG_TXN5

PEG_TXP6

PEG_TXN6

PEG_TXP7

PEG_TXN7

PEG_TXP8

PEG_TXN8

PEG_TXP9

PEG_TXN9

PEG_TXP10

PEG_TXN10

PEG_TXP11

PEG_TXN11

PEG_TXP12

PEG_TXN12

PEG_TXP13

PEG_TXN13

PEG_TXP14

PEG_TXN14

PEG_TXP15

PEG_TXN15

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

PEG_CALRP PEG_CALRN PEG_CALI

PEG_TESTIN

PERSTB PWRGD_MASK

ATI_R2SET

DDC3_CLK DDC3_DATA

ATI_SSIN ATI_SSOUT

XTALIN_M24

TESTEN TEST_YCLK TEST_MCLK

STERE0SYNC

RXP0 RXN0 RXP1 RXN1 RXP2 RXN2 RXP3 RXN3 RXP4 RXN4 RXP5 RXN5 RXP6 RXN6 RXP7 RXN7 RXP8 RXN8 RXP9 RXN9 RXP10 RXN10 RXP11 RXN11 RXP12 RXN12 RXP13 RXN13 RXP14 RXN14 RXP15 RXN15

AH30 AG30 AG29

AF29 AE29 AE30 AD30 AD29 AC29 AB29 AB30 AA30 AA29

Y29 W29 W30

V30

V29

U29

T29

T30

R30

R29

P29

N29

N30 M30 M29

L29 K29 K30

J30

AF26 AE26 AC25 AB25 AC27 AB27 AC26 AB26

Y25

W25

Y27

W27

Y26

W26

U25 T25 U27 T27 U26 T26 P25 N25 P27 N27 P26 N26

L25

K25

L27

K27

L26

K26

AF27 AE27

AC23 AB24 AB23

AE25 AD25

AD24 AH21 AK21

AJ22 AK22

AJ24 AK24

AG22 AG23

AJ23 AH24

AH28

AJ29

AH27

AF25 AH25

M26-P-1

U20A

PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N PCIE_RX4P PCIE_RX4N PCIE_RX5P PCIE_RX5N PCIE_RX6P PCIE_RX6N PCIE_RX7P PCIE_RX7N PCIE_RX8P PCIE_RX8N PCIE_RX9P PCIE_RX9N PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N PCIE_RX12P PCIE_RX12N PCIE_RX13P PCIE_RX13N PCIE_RX14P PCIE_RX14N PCIE_RX15P PCIE_RX15N

PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N PCIE_TX4P PCIE_TX4N PCIE_TX5P PCIE_TX5N PCIE_TX6P PCIE_TX6N PCIE_TX7P PCIE_TX7N PCIE_TX8P PCIE_TX8N PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N PCIE_TX11P PCIE_TX11N PCIE_TX12P PCIE_TX12N PCIE_TX13P PCIE_TX13N PCIE_TX14P PCIE_TX14N PCIE_TX15P PCIE_TX15N

PCIE_REFCLKP PCIE_REFCLKN

PCIE_CALRP PCIE_CALRN PCIE_CALI

PCIE_TEST PERSTB

PERSTB_MASK R2SET Y_G

C_R_PR COMP_B_PB

H2SYNC V2SYNC

DDC3CLK DDC3DATA

SSIN SSOUT

XTALIN XTALOUT

TESTEN

E8

TEST_YCLK

B6

TEST_MCLK PLLTEST

STEREOSYNC

C

1 OF 6

AJ5

GPIO_0

AH5

GPIO_1

AJ4

GPIO_2

AK4

GPIO_3

AH4

GPIO_4

AF4

GPIO_5

AJ3

GPIO_6

AK3

GPIO_7

AH3

GPIO_8

AJ2

GPIO_9

AH2

GPIO_10

AH1

GPIO_11

AG3

GPIO_12

AG1

GPIO_13

AG2

GPIO_14

C6

GPIO_17

VREFG

TXCLK_LN TXCLK_LP

DIGON

BLON TX0M

TX0P

TX1M

TX1P

TX2M

TX2P TXCM TXCP

DDC2CLK

HPD1

HSYNC

VSYNC

RSET

DDC1CLK

DPLUS

DMINUS

AF3 AF2

AE10 AH6

AJ6 AK6 AH7 AK7 AJ7 AH8 AJ8 AH9 AJ9 AK9 AH10 AE6 AG6 AF6 AE7 AF7 AE8 AG8 AF8 AE9 AF9 AG10 AF10

AJ10 AK10 AJ11 AH11

AG4 AH15

AH16 AJ16 AJ17 AJ18 AK18 AJ20 AJ21 AK19 AJ19 AG16 AG17 AF16 AF17 AE18 AE19 AF19 AF20 AG19 AG20

AE12 AG12

AK13 AJ13 AJ14 AJ15 AK15 AK16 AJ12 AK12

AE13 AE14

AF12 AK27

R

AJ27

G

AJ26

B

AJ25 AK25

AH26 AG25

AF24 AG24 AF11

AE11

GPIO_PWRCNTL

GPIO_MEMSSIN

DVOVMODE DVPDATA_0

DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9

DVO / EXT TMDS / GPIO

DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22

PCI EXPRESS

DVPDATA_23

DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCNTL_3

TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXOUT_L3N TXOUT_L3P

TXOUT_U0N

TXOUT_U0P

LVDS

TXOUT_U1N

TXOUT_U1P

TXOUT_U2N

TXOUT_U2P

TXOUT_U3N

TXOUT_U3P

TXCLK_UN TXCLK_UP

DAC2

DDC2DATA

TMDS

SS

DAC1

DDC1DATA

CLK

GPIO_AUXWIN

THERM

VGA_GPIO0 VGA_GPIO1 VGA_GPIO2 VGA_GPIO3 VGA_GPIO4

VGA_GPIO5 VGA_GPIO6 VGA_GPIO7 VGA_GPIO8 VGA_GPIO9

VGA_GPIO10

VGA_GPIO11

VGA_GPIO12

VGA_GPIO13 VGA_GPIO14

VGA_GPIO16

DVOMODE

DY

R435 0R2-0

1 2

R434 0R2-0

1 2

DY

DVPCNTL_0

1 2

DVPCNTL_1

1 2

DVPCNTL_2

1 2

DVPCNTL_3

1 2

ATI_VREFG

R477

R478

150R2

1 2

ATI_RSET

VGA_DDCDATA VGA_DDCCLK

GPIO_AUXWIN

1 2

R515

SB

R479

R479 150R2

150R2

R499

R500

D

VGA_GPIO14

ATI_MODE_0 15 VGA_PWRCNTL 45

1 2

0R2-0

DVPDATA_0 15 DVPDATA_1 15 DVPDATA_2 15

EDID_DAT EDID_CLK

R78 0R2-0R78 0R2-0 R77 0R2-0R77 0R2-0 R75 0R2-0R75 0R2-0 R76 0R2-0R76 0R2-0

12

R513

R513 10KR2

10KR2

HPD

1 2

R514

1 2

499R3F

1 2

4K7R2

THERMDP_M24 25 THERMDN_M24 25

D

E

DY

1 2

R654 0R2-0

ATI_MODE_0

1 2

SB

VGA_ALERT# 25

R653

DVOMODE=VSS 3.3V MODE

0R2-0

DVOMODE=VDDC to 1.8V 1.8V MODE DVOMODE=GND NO USE DVPDATA

STRAPS

PLL_CAL_FORCE_EN PCIE_MODE(1:0) CAL_OFF BYPASS_PLL ICOMP DEBUG_ACCESS ROMIDCFG(3:0)

MULTIFUNC(1:0) VIP_DEVICE DWNGR0

ATI Ref. Datasheets(page 3-32) DOC.NO.:CHS-216M24-03

GPIO[0..13] are internal

12

R508

R508 100R2F

100R2F

R507

R507 100R2F

100R2F

pull-down.

VGA_GPIO0

R82

VGA_GPIO2 VGA_GPIO4 VGA_GPIO1 VGA_GPIO11 VGA_GPIO13 VGA_GPIO12 VGA_GPIO10 VGA_GPIO6 VGA_GPIO9 VGA_GPIO5 VGA_GPIO7 VGA_GPIO8 VGA_GPIO3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

ATI(1 of 3)

Leopard2

E

3D3V_S0

TXAOUT0- 19 TXAOUT0+ 19 TXAOUT1- 19 TXAOUT1+ 19 TXAOUT2- 19 TXAOUT2+ 19

TXACLK- 19 TXACLK+ 19 TXBOUT0- 19 TXBOUT0+ 19 TXBOUT1- 19 TXBOUT1+ 19 TXBOUT2- 19 TXBOUT2+ 19

TXBCLK- 19 TXBCLK+ 19

LCDVDD_ON 19 BL_ON 36

VGA_RED 20 VGA_GREEN 20 VGA_BLUE 20

VGA_HSYNC 20 VGA_VSYNC 20

12

C381

C381 SCD1U16V

SCD1U16V

100KR2

Title

Size Document Number Rev

A3

Date: Sheet of

Date: Sheet

GPIO0CAL_BG_BACKUP GPIO1

GPIO(3:2)

GPIO4 GPIO5 GPIO6 GPIO8

GPIO(9,13:11)

LCDDATA(17:16) LCDDATA(20) LCDDATA(21)

(internal pull-down)

1 2

10KR2

DUMMY-R2

1 2

DY

R85

1 2

DY

R516

1 2

DY

R83

1 2

DY

R100

1 2

DY

R107

1 2

DY

R510

1 2

DY

R106

1 2

DY

R87

1 2

DY

R101

1 2

DY

R517

1 2

DY

R86

1 2

DY

R511

1 2

DY

R84

of

13 47Monday, July 11, 2005

3D3V_S0

R509

10KR2

10KR2 10KR2

10KR2

DEFAULTPIN

0000

00

3D3V_S0

12

0 0 00 0 0 0 0

0 0

-1

A

VRAM_VDDQ

12

C458

C424

SCD01U16V3KX

DY

4 4

VRAM_VDDQ VRAM_VDDQ

12

C422

C467

DY

SC1U10V3ZY

C344

SC1U10V3ZY

3 3

2D5V_S0

2 2

1 2

MLB-201209-11

1 1

VRAM_VDDQ

L37

1 2

MLB-201209-11

C400

SCD01U16V3KX

12

C461

DY

SC1U10V3ZY

3D3V_S0

12

1D8V_VGA_S0

L32

SC10U10V6ZY-U

12

C481

SC10U10V6ZY-U

12

SCD01U16V3KX

U55

1

SHDN#

2

GND

3

IN

G913C-U

1 2

MLB-201209-11

12

C364

1D8V_VGA_S0

VDDRH

12

C476

C476 SC1U10V3ZY

SC1U10V3ZY

A

12

C479

12

C486

LVDDR_2D8V

L33

12

C363

C363 SC1U10V3ZY

SC1U10V3ZY

MLB-201209-11

C468

SCD01U16V3KX

12

C470

C470 SC10U10V6ZY-U

SC10U10V6ZY-U

DY

SC10U10V6ZY-U

SET OUT

1 2

MLB-201209-11

C365

1D8V_VGA_S0

R449

A2VDD_2D5V

L25

1 2

MLB-201209-11

12

C347

SC10U10V6ZY-U

L3

1 2

12

C475

SCD01U16V3KX

C343

C343 SC22P

SC22P

LVDDR_2D8V

5 4

L4

SC10U10V6ZY-U

12

C376

SC10U10V6ZY-U

1 2

0R5J-1

C355

1D8V_VGA_S0

12

C396

SC1U10V3ZY

1 2

MLB-201209-11

12

C348

SC10U10V6ZY-U

12

C85

SC10U10V6ZY-U

12

SCD01U16V3KX

LVDDR_2D8V

12

2D8V_SET

12

C90

12

C377

SC1U10V3ZY

12

SC10U10V6ZY-U

A2VDDQ_1D8V

1D8V_VGA_S0

L26

12

C353

C353 SC1U10V3ZY

SC1U10V3ZY

PVDD_1D8V

12

C86

SC1U10V3ZY

12

C469

SCD01U16V3KX

12

R417

R417 124KR2F

124KR2F

12

R418

R418 100KR2F

100KR2F

LVDDR_2D8V_S0

12

C397

SCD1U16V2KX-1

LPVDD_1D8V

12

C378

SC1U10V3ZY

LVDDR_1D8V

12

C354

C398

SC1U10V3ZY

1D8V_VGA_S0

L36

1 2

MLB-201209-11

12

C464

12

C349

SC1U10V3ZY

SC100P

12

SC100P

AVDD_1D8V

L34

1 2

MLB-201209-11

SC10U10V6ZY-U

1.8V

SCD01U16V3KX

1.8V

VDDRH

C374

1.8V

MPVDD_1D8V

12

C477

B

2.8V

1.8V

2.5V

1.8V

VDD1DI_1D8V

12

C395

SC1U10V3ZY

12

C478

C478 SC1U10V3ZY

SC1U10V3ZY

B

A15 A21 A28

A3

A9 AA1 AA4 AA7 AA8

AD4

B1 B30 D11 D14 D17 D20 D23 D26

D5

D8 E27

F4 G10 G13 G15 G19 G22 G27

G7 H10 H13 H15 H17 H19 H22

J1 J4 J7

J8 K23 K24 L23

L8

M4

N4 N7 N8 R1 R4 T7 T8 V4 V7 V8

AE16 AE17 AE15

AF15

AH19 AH13

AF13 AF14

F18

N6

AF21

AE20

AF23

AH23

AE23 AE22

AK28

A7

1.8V

U20D

VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

LVDDR_25 LVDDR_25 LVDDR_18 LVDDR_18

LPVDD TPVDD

TXVDDR TXVDDR

VDDRH0 VDDRH1

A2VDD A2VDD

A2VDDQ AVDD

VDD1DI VDD2DI

PVDD MPVDD

M26-P-1

4 OF 6

I/O

POWER

I/O

POWER

VDDC VDDC VDDC VDDC VDDC

VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15

VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3

VDDR4 VDDR4 VDDR4 VDDR4 VDDR4

PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12

PCIE_PVDD_12 PCIE_PVDD_12 PCIE_PVDD_12

PCIE_PVDD_18 PCIE_PVDD_18 PCIE_PVDD_18 PCIE_PVDD_18

NC#D9 NC#D13 NC#D19 NC#D25

NC#E4 NC#T4

NC#AB4

AVSSQ

LVSSR

LPVSS

TPVSS TXVSSR

TXVSSR TXVSSR

VSSRH0 VSSRH1

A2VSSN A2VSSN

A2VSSQ

AVSSN

VSS1DI VSS2DI

PVSS

MPVSS

1.2V

AC13 AC15 AC17 AD13 AD15

AC11 AC20 H11 H20 M23 P8 Y23 Y8

AC19 AC21 AC22 AC8 AD19 AD21 AD7

AC10 AC9 AD10 AD9 AG7

AG26 AG27 AG28 AJ30 AK29

N23 N24 P23

T23 U23 V23 W23

D9 D13 D19 D25 E4 T4 AB4

AD22 AF18

AG15 AG18 AH17

AH18 AH12

AG13 AG14 AH14

F19 M6

AH20 AG21

AF22 AH22

AE24 AE21

AJ28 A6

C

1.5V

3.3V

1.2V

1.8V

C

C421

SC10U10V6ZY-U

1D5V_1_S0

D9

1 2

2 1

1 2

12

C418

SC1U10V3ZY

12

C66

SC10U10V6ZY-U

PCIE_PVDD

3D3V_S0

12

C445

SCD01U16V3KX

DY

R669 0R2-0

R668 0R2-0R668 0R2-0

R60

1 2

GAP-CLOSE-PWR

12

C423

C423 SC1U10V3ZY

SC1U10V3ZY

C144

U14

APL1087

C69

C69 SC1U10V3ZY

SC1U10V3ZY

DY

12

C444

3D3V_S0

SSM5818SL

3D3V_VDDR3

12

C399

3D3V_VDDR4

PCIE_PVDD_1D8V

SC1U10V3ZY

Imax=1A

Vo=1.25/110*(110+48.7)=1.803V

D

1D2V_VGA_S0

12

C375

12

1 2 3

SCD01U16V3KX

12

SC1U10V3ZY

12

C465

DY

SCD1U16V3KX

12

C362

C394

SC1U10V3ZY

R126

1 2

GAP-CLOSE-PWR

12

C416

APL1085_ADJ

D

12

C446

SCD01U16V3KX

12

C68

C443

SCD1U16V3KX

1D2V_VGA_S0

12

C419

SC22U10V6ZY-L1

1D5V_1_S0

12

C466

1D2V_VDDR_S0

R475

1 2

GAP-CLOSE-PWR

1D2V_VDDR_S0

SCD01U16V3KX

12

C439

SCD01U16V3KX

1D8V_VGA_S0

12

R48

R48 110R3

110R3

12

R45

R45 48D7R3F

48D7R3F

C459

SCD01U16V3KX

SC1U10V3ZY

L28

1 2

MLB-201209-11

12

C350

12

C441

C442

SCD01U16V3KX

DY

SC

C67

1D5V_VGA_S0

1D5V_S0

1 2

GAP-CLOSE-PWR

PCIE_VDDR

12

EC119

DY

12

SC22U10V6ZY-L1

ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED

WITH AS MANY AS POSSIBLE PLACED UNDER THE ASIC

C67

3D3V_S0

R58

12

C361

SCD1U10V2MX-1

SC22U10V6ZY-L1

12

C437

C440

SC1U10V3ZY

12

C438

C415

SC1U10V3ZY

PLACED CLOSE TO THE POWER/GND PINS

ADJ/GND

VOUT

VIN

12

C462

SCD01U16V3KX

DY

12

C382

C463

12

SCD01U16V3KX

C98

C98 SC47U6D3V0ZY

SC47U6D3V0ZY

SC

12

C460

C417

C460

SC1U10V3ZY

PCIE_PVDD_18 PCIE_VDDR_12

/PCIE_PVDD_12

12

TC19

TC19 ST100U6D3VM-U

ST100U6D3VM-U

C420

SC1U10V3ZY

1D8V_VGA_S0

SC10U10V5ZY-L

Title

Size Document Number Rev

A3

Date: Sheet

E

3D3V_S0

D7

D7 SSM5818SL

SSM5818SL

1D2V_VGA_S0

2 1

12

3D3V_S0

12

TC21

SE220U2VDM-6

SC1U10V3ZY

DIODE SUPPLIES POWER TO VDDC RAIL WHILE VDDC REGULATOR STABALIZES DURING POWER ON

SC

U83

2

VOUT

3

VIN

1

GND

DY

APL5308-15AC-TR

M26 Power UP Squence

3D3_VDDR3 3D3_VDDR4 2D5_VDDR1 1D2_VDDC VDD_15

T5 time delay between full PCIE_PVDD_18 and 90% of PCIE_VDDR_12

T6 time delay between full PCIE_VDDR_12 and 90% of 1D2_VDDC

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

ATI(2 of 3)

Leopard2

T1 < 1mS

T2 < 1mS

T3 < 1mS

T5 --

T6 --

14 47Thursday, July 07, 2005

E

1D5V_VGA_S0

T4 < 1mS

of

DY

12

C619

SC2D2U10V3ZY

-1

A

U20B

2 OF 6

G26 G30

G29 G28

G25

H28 H29

H25 H26

D29 D28 E28 E29

F28 F26

E26 F25 E24 F23 E23 D22 B29 C29 C25 C27 B28 B25 C26 B26 F17 E17 D16 F16 E15 F14 E14 F13 C17 B18 B17 B15 C13 B14 C14 C16 A13 A12 C12 B12 C10

B10 E13 E12 E10 F12 F11

2 OF 6

MAA0

DQA_0 DQA_1

J28

DQA_2

J29

DQA_3

J26

DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52

C9

DQA_53

B9

DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60

E9

DQA_61

F9

DQA_62

F8

DQA_63

M26-P-1

MEMORY INTERFACE

A

MEMORY INTERFACE

A

NC_DIMA_0 NC_DIMA_1

MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8

MAA_9 MAA_10 MAA_11 MAA_12 MAA_13 MAA_14

DQMA_0# DQMA_1# DQMA_2# DQMA_3# DQMA_4# DQMA_5# DQMA_6# DQMA_7#

QSA_0

QSA_1

QSA_2

QSA_3

QSA_4

QSA_5

QSA_6

QSA_7

RASA#

CASA#

WEA# CSA_0# CSA_1#

CKEA

CLKA0

CLKA0#

CLKA1

CLKA1#

MVREFD

MVREFS

E22 B22 B23 B24 C23 C22 F22 F21 C21 A24 C24 A25 E21 B20 C19

J25 F29 E25 A27 F15 C15 C11 E11

J27 F30 F24 B27 E16 B16 B11 F10

A19 E18 E19 E20 F20 B19 B21

C20 C18

A18

B7 B8

D30 B13

MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13

DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7

QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7

CLKA0_R CLKA#0_R

CLKA1_R CLKA#1_R

ATI_MVREFD ATI_MVREFS

DIMA_0 DIMA_1

MDA[63..0]16 MDB[63..0]17

4 4

3 3

2 2

MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

B

RASA# 16 CASA# 16 WEA# 16 CSA#0 16 CSA#1 16 CKEA 16

1 2

R128 10R2R128 10R2

1 2

R129 10R2R129 10R2

1 2

R131 10R2R131 10R2

1 2

R132 10R2R132 10R2

TP5TP5 TP6TP6

MAA[13..0] 16

DQMA#[7..0] 16

QSA[7..0] 16

CLKA0 16 CLKA#0 16

CLKA1 16 CLKA#1 16

12

R134

R134 100R2

100R2

R136

R136 100R2

100R2

CKEA

CKEB

VRAM_VDDQ

12

C162

C162 SCD1U16V

SCD1U16V

C

3 OF 6

U20C

MDB0

D7

AD6 AD5

AC2 AC3 AD3

AA2 AA6 AA5 AB6 AB5

AE5 AE4 AB2 AB3

AE1 AE2 AE3

DQB_0

F7

DQB_1

E7

DQB_2

G6

DQB_3

G5

DQB_4

F5

DQB_5

E5

DQB_6

C4

DQB_7

B5

DQB_8

C5

DQB_9

A4

DQB_10

B4

DQB_11

C2

DQB_12

D3

DQB_13

D1

DQB_14

D2

DQB_15

G4

DQB_16

H6

DQB_17

H5

DQB_18

J6

DQB_19

K5

DQB_20

K4

DQB_21

L6

DQB_22

L5

DQB_23

G2

DQB_24

F3

DQB_25

H2

DQB_26

E2

DQB_27

F2

DQB_28

J3

DQB_29

F1

DQB_30

H3

DQB_31

U6

DQB_32

U5

DQB_33

U3

DQB_34

V6

DQB_35

W5

DQB_36

W4

DQB_37

Y6

DQB_38

Y5

DQB_39

U2

DQB_40

V2

DQB_41

V1

DQB_42

V3

DQB_43

W3

DQB_44

Y2

DQB_45

Y3

DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58 DQB_59 DQB_60 DQB_61 DQB_62 DQB_63

M26-P-1

MEMORY INTERFACE

B

MEMORY INTERFACE

B

NC_DIMB_0 NC_DIMB_1

NC_MEMVMODE_1

MEMORY CHANNEL BMEMORY CHANNEL A

MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31

1 2

10KR2

R130

1 2

10KR2

R526

R137

R137 100R2

100R2

VRAM_VDDQ 1D8V_VGA_S0

C163

C163 SCD1U16V

SCD1U16V

12

R133

R133 100R2

100R2

As close to CHIP as possible

MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63

MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8

MAB_9 MAB_10 MAB_11 MAB_12 MAB_13 MAB_14

DQMB_0# DQMB_1# DQMB_2# DQMB_3# DQMB_4# DQMB_5# DQMB_6# DQMB_7#

QSB_0 QSB_1 QSB_2 QSB_3 QSB_4 QSB_5 QSB_6

QSB_7 RASB# CASB#

WEB# CSB_0# CSB_1#

CKEB

CLKB0

CLKB0#

CLKB1

CLKB1#

ROMCS#

MEMTEST

N5 M1 M3 L3 L2 M2 M5 P6 N3 K2 K3 J2 P5 P3 P2

E6 B2 J5 G3 W6 W2 AC6 AD2

F6 B3 K6 G1 V5 W1 AC5 AD1

R2 T5 T6 R5 R6 R3 N1

N2 T2

T3

E3 AA3

AF5

C7 C8

R135

R135 240R2J

240R2J

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13

DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7

QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7

CLKB0_R CLKB#0_R

CLKB1_R CLKB#1_R

DIMB_0 DIMB_1

ROMCS# ATI_MODE_0

MEMTEST

12

D

RASB# 17 CASB# 17 WEB# 17 CSB#0 17 CSB#1 17 CKEB 17

1 2

R120 10R2R120 10R2

1 2

R121 10R2R121 10R2

1 2

R122 10R2R122 10R2

1 2

R119 10R2R119 10R2

TP4TP4 TP25TP25

TP24TP24

ATI_MODE_1

12

R538

R538 DUMMY-R2

DUMMY-R2

MAB[13..0] 17

1D2V_VGA_S0

DQMB#[7..0] 17

QSB[7..0] 17

CLKB0 17 CLKB#0 17

CLKB1 17 CLKB#1 17

ATI_MODE_0 13

1 2

R544 DUMMY-R2R544 DUMMY-R2

1 2

R539 DUMMY-R2R539 DUMMY-R2

12

R545

R545 10KR2

10KR2

E

6 OF 6

U20F

P17 P18 P19 U12 U13 U14 U17 U18 U19 V19 V18 V17 V14 V13 V12 N18 N17

N14 W17 W18 W12 W13 W14

N13

N19 M19 M18 M12

N12 M13 M14

P12

P13

P14 M17 W19

M26-P-1

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

1 2

L35

MLB-201209-11

ARRAYCENTER

SC10U10V6ZY-U

M16

VSS

N16

VSS

N15

VSS

P15

VSS

P16

VSS

R18

VSS

R17

VSS

R16

VSS

R15

VSS

R14

VSS

R13

VSS

R12

VSS

T13

VSS

T14

VSS

T15

VSS

W15

VSS

V16

VSS

V15

VSS

U15

VSS

U16

VSS

T19

VSS

T18

VSS

T17

VSS

T16

VSS

W16

VDDCI

M15

VDDCI

R19

VDDCI

T12

VDDCI

12

C379

C379 SC1U10V3ZY

SC1U10V3ZY

VDDCI

12

C380

ATI suggest

VDDR1 MEMVMODE_0 MEMVMODE_1

1.8V

+VDDC_CTGND

VRAM Selection

K28

L28

M27

M26

M24

M25

M28

P28

N28

R25

R23

R24

R26

R27

R28

T28

T24

U28

V24

V26

V27

V25

V28

Y28

W24

W28

AA26

AA27

AA23

AA24

AA25

AA28

AB28

AC28

AD28

AD26

AD27

AE28

AF28

PCIE_VSS

AH29

PCIE_VSS

T1

AB8

AB7

AB1

AC4

AC12

AC14

AD16

AC16

AC18

AD18

AK2

VSS

D21

VSS

D18

D15

VSS

D12

AJ1

VSS

PCIE_VSS

VSS

VSSD6VSSD4VSS

D10

PCIE_VSS

CORE GND

VSSG9VSS

VSS

VSSH9VSSH8VSSH4VSS

VSS

VSSR7VSSP4VSSM7VSSM8VSSL4VSSK1VSSK7VSSK8VSSR8VSS

J23

F27

G12

G16

G18

G21

G24

H27

H23

H21

H18

H16

H14

H12

J24

AG5

AG9

AD12

AG11

U20E

VSSU4VSSU8VSSW7VSSW8VSSY4VSS

5 OF 6

1 1

VSSA2VSS

VSS

VSSC1VSSC3VSS

VSS

A10

A16

A22

A29

C28

C30

D27

D24

Vendor/Size

HYNIX/128M 000 SAMSUNG/128M RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

SETTING DVPDATA_[2:0]

001 010 011 100 101 110 111

VRAM_VDDQ

Hynix : 72.55732.B0U Samsng : 72.45532.M0U

1 2

R79 DUMMY-R2R79 DUMMY-R2

1 2

R81 DUMMY-R2R81 DUMMY-R2

1 2

R80 DUMMY-R2R80 DUMMY-R2

R482

R482 10KR2

10KR2

DVPDATA_0 13

DVPDATA_1 13

DVPDATA_2 13

12

R484

R484 10KR2

10KR2

R483

R483 10KR2

10KR2

Hynix : HY5DS573222F(P)-28 (8Mx32) Samsung : K4D553235F-VC2A (8Mx32)

A

B

C

D

Title

Size Document Number Rev

A3

Date: Sheet

2.5V

2.8V

+VDDC_CT +VDDC_CT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

ATI(3 of 3)

Leopard2

15 47Thursday, July 07, 2005

E

GND+VDDC_CT

-1

of

-1