Page 1
5
DCCBBAA
4
3
2
1
UMA & Optimus Schematics Document
D
IVY Bridge(rPGA989)
Intel PCH(Panther Point)
DY :NotInstalled
UMA:UMA platform installed
OPS:Optimus
HR:Huron River
CR:Chief River
V: V-Series installed
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
Cover Page
Cover Page
Cover Page
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
LA480
LA480
LA480
Date: Sheet of
Date: Sheet of
Date: Sheet of
1 103Friday, January 06, 2012
1 103Friday, January 06, 2012
1 103Friday, January 06, 2012
SD
SD
SD
Page 2
5
##OnMainBoard
VRAM
D D
2GB/1GB/512MB
88,89,90,91
DDR3
800MHz
4
NVIDIA
N13P-GL (V)
N13M-GE1 (B)
83.84,85,86,87
C C
HDMI
LCD
CRT
Finger Print BD
SD/MMC+/MS/
B B
MS Pro/xD
(V only)
(B only)
74
Internal DMIC
Analog DMIC
Combo
Jack
A A
2CH SPEAKER
51
49
50
Bluetooth
CAMERA
Finger Print
CardReader
ALCOR
AU6435B52
63
49
64
Azalia
CODEC
REALTEK
ALC269Q-VC2
(Discrete only)
29
4
3
Block Diagram
(UMA/Optimus co-lay)
LA480 LA580
PCIe x 16
HDMI
LVDS
RGB CRT
USB2.0 x 3
USB 2.0 x 1
AZALIA
Intel CPU
IVY Bridge
DDRIII: 1066/1333/1600 MHz
FDI x 4 x 2
(UMA only)
PCH
Panther Point
USB 3.0/2.0 ports (14)
ETHERNET (10/100/1000Mb)
High Definition Audio
17,18,19,20,21,22,23,24,25
SPI
Flash ROM
8MB
G-Sensor
(V only)
79
4,5,6,7,8,9,10
DMI x 4
Intel
SATA ports (6)
PCIE ports (8)
LPC I/F
ACPI 1.1
60
KBC
NUVOTON
NPCE885G
Touch
PAD
69
PCIE x 1/USB2.0 x 1
SATA x 1/USB2.0 x 1
USB 3.0 x 2
USB 2.0 x 2
LPC Bus
27
KB
69 25
Project Code
PCB P/N
Revision
DDRIII 1066/1333/1600 Channel A
DDRIII 1066/1333/1600 Channel B
71.08111.N03, IC PCIE CTRL RTL8111F-CGT QFN 48P
PCIE x 1
SATA x 2
LPC debug port
SMBus
EMC2103-2-AP
71
ThermalInt.
28
91.4TD01.001
11264
SC
GLAN
REALTEK
RTL8111F
Mini-Card
WLAN
Mini-Card
USB x 2
USB x 2
Fan
28
DDRIII
1066/1333/1600
1066/1333/1600
31
65
66
HDD
ODD
RJ45
CONN
56
56
2
91.4TE01.001
11273
SC
Slot 0
14
Slot 1DDRIII
15
59
1
CPU DC/DC
TPS51640
INPUTS
DCBATOUT
SYSTEM DC/DC
TPS51219
INPUTS
DCBATOUT
SYSTEM DC/DC
TPS51225
INPUTS
DCBATOUT 5V_S5
SYSTEM DC/DC
RT8207M
INPUTS
DCBATOUT
SYSTEM DC/DC
TPS51640
INPUTS
DCBATOUT
VGA
TPS51728
INPUTS
DCBATOUT
TI CHARGER
BQ24737
INPUTS
+DC_IN_S5
26
SYSTEM DC/DC
RT8068A
INPUTS OUTPUTS
3D3V_S5 1D8V_S0
LDO
RT8207
INPUTS OUTPUTS
26
5V_S5
42~43
OUTPUTS
VCC_CORE
OUTPUTS
1D05V_VTT
OUTPUTS
3D3V_AUX_S5
3D3V_S5
OUTPUTS
0D75V_S0
1D5V_S3
DDR_VREF_S3
OUTPUTS
VCC_GFXCORE
OUTPUTS
VGA_CORE
OUTPUTS
DCBATOUT+PBATT
0D75V_S0
45
41
46
44
92
40
47
46
PCB LAYER
L1:Top
L2:GND
L3:Signal
L4:Signal
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA480
LA480
LA480
Date: Sheet of
Date: Sheet of
Date: Sheet of
L5:VCC
L6:Signal
L7:GND
L8:Signal
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
2 103Friday, January 06, 2012
2 103Friday, January 06, 2012
2 103Friday, January 06, 2012
SD
SD
SD
Page 3
5
PCH Strapping
Chief River Schematic Checklist Rev0.72
Name Schematics Notes
SPKR
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
GNT3#/GPIO55
D D
GNT2#/GPIO53
GNT1#/GPIO51
SPI_MOSI
NV_ALE
Reboot option at power-up
Internal weak Pull-down.
Default Mode:
Connect to Vcc3_3 with 8.2-kΩ
No Reboot Mode with TCO Disabled:
- 10-kΩ weak pull-up resistor.
GNT[3:0]# functionality is not available on Mobile.
Mobile: Used as GPIO only
Pull-up resistors are not required on these signals.
If pull-ups are used, they should be tied to the Vcc3_3power rail.
Enable Danbury:
Disable Danbury:
Enable Danbury:
Disable Danbury:
Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.
Left floating, no pull-down required.
Connect to +NVRAM_VCCQ with 8.2-kohm
weak pull-up resistor [CRB has it pulled up
with 1-kohm no-stuff resistor]
Leave floating (internal pull-down)
4
3
Processor Strapping
Pin Name Strap Description Configuration (Default value for each bit is
CFG[2]
PCI-Express Static
Lane Reversal
CFG[4]
CFG[6:5]
CFG[7]
PCI-Express
Port Bifurcation
Straps
PEG DEFER TRAINING
1 unless specified otherwise)
1:
Normal Operation.
Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
0:
Disabled - No Physical Display Port attached to
1:
Embedded DisplayPort.
Enabled - An external Display Port device is
0:
connectd to the EMBEDDED display Port
11 : x16 - Device 1 functions 1 and 2 disabled
10 : x8, x8 - Device 1 function 1 enabled ;
function 2 disabled
01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
enabled
1:
PEG Train immediately following xxRESETB de assertion
PEG Wait for BIOS for training
0:
2
Chief River Schematic Checklist Rev0.72
Default
Value
1
0
11
1
1
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features.
HAD_DOCK_EN#
/GPIO[33]
C C
High (1) - Security measure defined in the Flash Descriptor will be enabled.
Platform design should provide appropriate pull-up or pull-down depending on
the desired settings. If a jumper option is used to tie this signal to GND as
required by the functional strap, the signal should be pulled low through a weak
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently.
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for
strapping functions.
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
HDA_SYNC
GPIO15
GPIO8
B B
GPIO27
PCIe Routing
LANE1
LANE2
LANE3 Card Reader
LANE4
A A
LANE5
LANE6
LANE7
LANE8 Express Card
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low(0) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no
confidentiality. High(1) - Intel ME Crypto Transport Layer Security (TLS) cipher
suite with confidentiality.
Note : This is an un-muxed signal.
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low.
Sampled at rising edge of RSMRST#.
CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
X
Mini Card2(WWAN)
Mini Card1(WLAN)
X
Intel GBE LAN / LAN
X
5
USB Table
Pair
USB3.0 ext port 1
0
USB3.0 ext port 2
1
USB3.0 ext port 3
2
USB3.0 ext port 4
3
BLUETOOTH (USB1.1)
4
Fingerprint (USB1.1)
5
X
6
X
7
Mini Card2 (WWAN)
8
USB ext. port 4 / E-SATA /USB CHARGER
9
CARD READER
10
Mini Card1 (WLAN)
11
CCD
12
New Card
13
port9 is debug port
Device
4
POWER PLANE
5V_S0
3D3V_S0
1D8V_S0
1D5V_S0
1D05V_VTT
1D0V_S0
VCCSA
0D75V_S0
VCC_CORE
VCC_GFXCORE
1D8V_VGA_S0
3D3V_VGA_S0
1V_VGA_S0
5V_USBX_S3
1D5V_S3
DDR_VREF_S3
BT+
DCBATOUT
5V_S5
5V_AUX_S5
3D3V_S5
3D3V_AUX_S5
3D3V_M
1D05V_M 1.05V S0/M0, SX/M3, WOL_EN
3D3V_AUX_KBC 3.3V
3D3V_AUX_S5
VOLTAGE DESCRIPTION
5V
3.3V
1.8V
1.5V
1.05V
1.0V
0.9 - 0.675V
0.75V
0.35V to 1.5V
0.4 to 1.25V
1.8V
3.3V
1V
5V
1.5V
0.75V
6V-14.1V
6V-14.1V
5V
5V
3.3V
3.3V
3.3V
3.3V
SMBus ADDRESSES
2
I C / SMBus Addresses
Device
EC SMBus 1
Battery
CHARGER
EC SMBus 2
PCH
eDP
PCH SMBus
SO-DIMMA (SPD)
SO-DIMMB (SPD)
Digital Pot
G-Sensor
MINI
3
Voltage Rails
ACTIVE IN
S0
S3
All S states
DSW, Sx ON for supporting Deep Sleep states
G3, Sx
Ref Des
Address Hex Bus
CPU Core Rail
Graphics Core Rail
AC Brick Mode only
ON whenever iAMT is active1D05V_LAN 1.05V S0/M0, SX/M3
ON for iAMTLegacy WOL
Powered by Li Coin Cell in G3
and 3D3V_S5 in Sx
Chief River CRV
BAT_SCL/BAT_SDA
BAT_SCL/BAT_SDA
BAT_SCL/BAT_SDA
SML1_CLK/SML1_DATA
SML1_CLK/SML1_DATA
SML1_CLK/SML1_DATA
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
2
SATA Table
SATA
Pair
0
1
2
3
4
5
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Table of Content
Table of Content
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Table of Content
Taipei Hsien 221, Taiwan, R.O.C.
LA480
LA480
LA480
HDD1
mSATA
N/A
N/A
ODD
ESATA
1
Device
3 103Friday, January 06, 2012
3 103Friday, January 06, 2012
3 103Friday, January 06, 2012
SD
SD
SD
Page 4
5
4
3
2
1
SSID = CPU
Note:
Intel DMI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
D D
Note:
Intel FDI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
C C
enabled via a soft strap.
Note:
Lane reversal does not apply to
FDI sideband signals.
1D05V_VTT
B B
NOTE:
Select a Fast FET similar to 2N7002E whose rise/
fall time is less than 6 ns. If HPD on eDP interface is
disabled, connect it to CPU VCCIO via a 10-kΩ pull-Up
resistor on the motherboard.
DMI_TXN[3:0]19
DMI_TXP[3:0]19
DMI_RXN[3:0]19
DMI_RXP[3:0]19
FDI_TXN[7:0]19
FDI_TXP[7:0]19
FDI_FSYNC019
FDI_FSYNC119
FDI_INT19
FDI_LSYNC019
FDI_LSYNC119
R402 24D9R2F-L-GPR402 24D9R2F-L-GP
1 2
R403 10KR2J-3-GP
R403 10KR2J-3-GP
1 2
DY
DY
01.00IVY.000 IVY BRIDGE ORCAD SYMBOL.
CPU1A
CPU1A
SANDY
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
DP_COMP
eDP_HPD
B27
B25
A25
B24
B28
B26
A24
B23
G21
E22
F21
D21
G22
D22
F20
C21
A21
H19
E19
F18
B21
C20
D18
E17
A22
G19
E20
G18
B20
C19
D19
F17
J18
J17
H20
J19
H17
A18
A17
B16
C15
D15
C17
F16
C16
G15
C18
E16
D16
F15
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
DMI_RX#0
DMI_RX#1
DMI_RX#2
DMI_RX#3
DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3
DMI_TX#0
DMI_TX#1
DMI_TX#2
DMI_TX#3
DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3
FDI0_TX#0
FDI0_TX#1
FDI0_TX#2
FDI0_TX#3
FDI1_TX#0
FDI1_TX#1
FDI1_TX#2
FDI1_TX#3
FDI0_TX0
FDI0_TX1
FDI0_TX2
FDI0_TX3
FDI1_TX0
FDI1_TX1
FDI1_TX2
FDI1_TX3
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
EDP_COMPIO
EDP_ICOMPO
EDP_HPD
EDP_AUX
EDP_AUX#
EDP_TX0
EDP_TX1
EDP_TX2
EDP_TX3
EDP_TX#0
EDP_TX#1
EDP_TX#2
EDP_TX#3
SANDY
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
SKT-BGA989C470395-1H180
SKT-BGA989C470395-1H180
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1 OF 9
1 OF 9
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PEG_TX#11
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_IRCOMP_R
PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0
PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0
PEG_C_TXN15
PEG_C_TXN14
PEG_C_TXN13
PEG_C_TXN12
PEG_C_TXN11
PEG_C_TXN10
PEG_C_TXN9
PEG_C_TXN8
PEG_C_TXN7
PEG_C_TXN6
PEG_C_TXN5
PEG_C_TXN4
PEG_C_TXN3
PEG_C_TXN2
PEG_C_TXN1
PEG_C_TXN0
PEG_C_TXP15
PEG_C_TXP14
PEG_C_TXP13
PEG_C_TXP12
PEG_C_TXP11
PEG_C_TXP10
PEG_C_TXP9
PEG_C_TXP8
PEG_C_TXP7
PEG_C_TXP6
PEG_C_TXP5
PEG_C_TXP4
PEG_C_TXP3
PEG_C_TXP2
PEG_C_TXP1
PEG_C_TXP0
R401
R401
1 2
24D9R2F-L-GP
24D9R2F-L-GP
C401 SCD22U10V2KX-1GP
C401 SCD22U10V2KX-1GP
1 2
C402 SCD22U10V2KX-1GP
C402 SCD22U10V2KX-1GP
1 2
C403 SCD22U10V2KX-1GP
C403 SCD22U10V2KX-1GP
1 2
C404 SCD22U10V2KX-1GP
C404 SCD22U10V2KX-1GP
1 2
C405 SCD22U10V2KX-1GP
C405 SCD22U10V2KX-1GP
1 2
C406 SCD22U10V2KX-1GP
C406 SCD22U10V2KX-1GP
1 2
C407 SCD22U10V2KX-1GP
C407 SCD22U10V2KX-1GP
1 2
C408 SCD22U10V2KX-1GP
C408 SCD22U10V2KX-1GP
1 2
C409 SCD22U10V2KX-1GP
C409 SCD22U10V2KX-1GP
1 2
C410 SCD22U10V2KX-1GP
C410 SCD22U10V2KX-1GP
1 2
C411 SCD22U10V2KX-1GP
C411 SCD22U10V2KX-1GP
1 2
C412 SCD22U10V2KX-1GP
C412 SCD22U10V2KX-1GP
1 2
C413 SCD22U10V2KX-1GP
C413 SCD22U10V2KX-1GP
1 2
C414 SCD22U10V2KX-1GP
C414 SCD22U10V2KX-1GP
1 2
C415 SCD22U10V2KX-1GP
C415 SCD22U10V2KX-1GP
1 2
C416 SCD22U10V2KX-1GP
C416 SCD22U10V2KX-1GP
1 2
C417 SCD22U10V2KX-1GP
C417 SCD22U10V2KX-1GP
1 2
C418 SCD22U10V2KX-1GP
C418 SCD22U10V2KX-1GP
1 2
C419 SCD22U10V2KX-1GP
C419 SCD22U10V2KX-1GP
1 2
C420 SCD22U10V2KX-1GP
C420 SCD22U10V2KX-1GP
1 2
C421 SCD22U10V2KX-1GP
C421 SCD22U10V2KX-1GP
1 2
C422 SCD22U10V2KX-1GP
C422 SCD22U10V2KX-1GP
1 2
C423 SCD22U10V2KX-1GP
C423 SCD22U10V2KX-1GP
1 2
C424 SCD22U10V2KX-1GP
C424 SCD22U10V2KX-1GP
1 2
C425 SCD22U10V2KX-1GP
C425 SCD22U10V2KX-1GP
1 2
C426 SCD22U10V2KX-1GP
C426 SCD22U10V2KX-1GP
1 2
C427 SCD22U10V2KX-1GP
C427 SCD22U10V2KX-1GP
1 2
C428 SCD22U10V2KX-1GP
C428 SCD22U10V2KX-1GP
1 2
C429 SCD22U10V2KX-1GP
C429 SCD22U10V2KX-1GP
1 2
C430 SCD22U10V2KX-1GP
C430 SCD22U10V2KX-1GP
1 2
C431 SCD22U10V2KX-1GP
C431 SCD22U10V2KX-1GP
1 2
C432 SCD22U10V2KX-1GP
C432 SCD22U10V2KX-1GP
1 2
1D05V_VTT
PEG_RXN[0..15] 83
PEG_RXP[0..15] 83
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
NOTE.
If PEG is not implemented, the RX&TX pairs can be left as No Connect
PEG Static Lane Reversal
PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0
PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0
PEG_TXN[0..15] 83
PEG_TXP[0..15] 83
Signal Routing Guideline:
EDP_ICOMPO keep W/S=12/15 mils and routing
A A
length less than 500 mils.
EDP_COMPIO keep W/S=4/15 mils and routing
length less than 500 mils.
NOTE.
Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
CPU (PCIE/DMI/FDI)
CPU (PCIE/DMI/FDI)
CPU (PCIE/DMI/FDI)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA480
LA480
LA480
Date: Sheet of
Date: Sheet of
Date: Sheet of
4 103Friday, January 06, 2012
4 103Friday, January 06, 2012
4 103Friday, January 06, 2012
SD
SD
SD
Page 5
SSID = CPU
5
R509
R509
750R2F-GP
750R2F-GP
H_SNB_IVB#22
TP501TP501
TP502TP502
1 2
R513 56R2J-4-GPR513 56R2J-4-GP
H_THERMTRIP#22,36
H_PM_SYNC19
1 2
R504 0R0402-PADR504 0R0402-PAD
1 2
R503 10KR2J-3-GPR503 10KR2J-3-GP
12
1
1
12
1D05V_VTT
1 2
R501
R501
62R2J-GP
62R2J-GP
D D
Intel
recommends
43pf
H_PROCHOT#
12
C502
C502
SC47P50V2JN-3GP
SC47P50V2JN-3GP
H_PECI22,27
H_PROCHOT#27,42
Connect EC to PROCHOT# through inverting OD buffer.
If PROCHOT# is not used, then it must
be terminated with a 68ohm ±5%
pull-up resistor to VTT.
H_CPUPW RGD22,97
C C
VDDPWRGOOD37
PLT_RST#18,27,31,36,65,66,71,80,82,83,97
0511-CHECK
1 2
R510
R510
1K5R2F-2-GP
1K5R2F-2-GP
DEL U501
4
SKTOCC#_R
H_CATERR#
H_PROCHOT#_R
H_CPUPW RGD_R
BUF_CPU_RST#
C501
C501
SC220P50V2KX-3GP
SC220P50V2KX-3GP
DY
DY
CPU1B
CPU1B
C26
SNB_IVB#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWROK
AR33
RESET#
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
SANDY
SANDY
3
2 OF 9
2 OF 9
A28
BCLK
A27
BCLK#
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
DBR#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
A16
A15
R8
AK1
A5
A4
AP29
AP27
AR26
AR27
AP30
AR28
TDI
AP26
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
SKT-BGA989C470395-1H180
SKT-BGA989C470395-1H180
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR3
DDR3
MISC
MISC
JTAG & BPM
JTAG & BPM
2
Need Add Test PointC26: PROC_SELECT#
CLK_EXP_P 20
CLK_EXP_N 20
CLK_DP_P_R
CLK_DP_N_R
SM_DRAMRST# 37
SM_DRAMRST#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
Signal Routing Guideline:
SM_RCOMP keep routing length less than 500 mils.
XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
XDP_DBRESET#
R502 4K99R2F-L-GPR502 4K99R2F-L-GP
R506 140R2F-GPR506 140R2F-GP
R507 25D5R2F-GPR507 25D5R2F-GP
R508 200R2F-L-GPR508 200R2F-L-GP
1 2
1 2
1 2
TP511TP511
1
TP512TP512
1
TP513TP513
1
TP516TP516
1
12
0511-CHECK
Disabling Guidelines:
If motherboard only supports external graphics:
Connect DPLL_REF_SSCLK on Processor to GND through
1K +/- 5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP
through 1K +/- 5% resistorpower (~15 mW) may be
wasted.
1D05V_VTT
RN502
RN502
SRN1KJ-7-GP
CLK_DP_N_R
CLK_DP_P_R
In order to minimize resistance, use thick traces to
route all COMP signals, use 10-mils wide trace for
routing less than 500 mils, or 20-mils wide trace
for routing between 500 mils and 1000 mils. Keep
20-mils spacing to any other signals in order to
minimize crosstalk.
XDP_TDO
XDP_TMS
XDP_TDI
XDP_TCLK
XDP_TRST#
XDP_DBRESET#19
XDP_DBRESET#
SRN1KJ-7-GP
1
4
2 3
R523 51R2J-2-GPR523 51R2J-2-GP
1 2
RN501
RN501
1
8
2
7
3
6
4 5
SRN51J-1-GP
SRN51J-1-GP
1 2
R516 1KR2J-1-GPR516 1KR2J-1-GP
1
1D05V_VTT
3D3V_S0
DEL R519
B B
DEL C503
DEL R517
DEL R515
ASM R510
ASM R509
<Core Design>
<Core Design>
A A
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
CPU (THERMAL/CLOCK/PM )
CPU (THERMAL/CLOCK/PM )
CPU (THERMAL/CLOCK/PM )
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA480
LA480
LA480
Date: Sheet of
Date: Sheet of
Date: Sheet of
5 103Friday, January 06, 2012
5 103Friday, January 06, 2012
5 103Friday, January 06, 2012
SD
SD
SD
Page 6
5
4
3
2
1
SSID = CPU
3 OF 9
CPU1C
CPU1C
SANDY
SANDY
M_A_DQ[63:0]14 M_B_DQ[63:0]15
D D
C C
B B
M_A_BS014
M_A_BS114
M_A_BS214
M_A_CAS#14
M_A_RAS#14
M_A_WE#14
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AE8
AD9
AF9
C5
SA_DQ0
D5
SA_DQ1
D3
SA_DQ2
D2
SA_DQ3
D6
SA_DQ4
C6
SA_DQ5
C2
SA_DQ6
C3
SA_DQ7
F10
SA_DQ8
F8
SA_DQ9
SA_DQ10
G9
SA_DQ11
F9
SA_DQ12
F7
SA_DQ13
G8
SA_DQ14
G7
SA_DQ15
K4
SA_DQ16
K5
SA_DQ17
K1
SA_DQ18
J1
SA_DQ19
J5
SA_DQ20
J4
SA_DQ21
J2
SA_DQ22
K2
SA_DQ23
M8
SA_DQ24
SA_DQ25
N8
SA_DQ26
N7
SA_DQ27
SA_DQ28
M9
SA_DQ29
N9
SA_DQ30
M7
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
AJ5
SA_DQ38
AJ6
SA_DQ39
AJ8
SA_DQ40
SA_DQ41
AJ9
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
V6
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_BS0
SA_BS1
SA_BS2
SA_CAS#
SA_RAS#
SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
3 OF 9
SA_CLK0
SA_CLK#0
SA_CKE0
SA_CLK1
SA_CLK#1
SA_CKE1
SA_CLK2
SA_CLK#2
SA_CKE2
SA_CLK3
SA_CLK#3
SA_CKE3
SA_CS#0
SA_CS#1
SA_CS#2
SA_CS#3
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DIM0_CLK_DDR0 14
M_A_DIM0_CLK_DDR#0 14
M_A_DIM0_CKE0 14
M_A_DIM0_CLK_DDR1 14
M_A_DIM0_CLK_DDR#1 14
M_A_DIM0_CKE1 14
M_A_DIM0_CS#0 14
M_A_DIM0_CS#1 14
M_A_DIM0_ODT0 14
M_A_DIM0_ODT1 14
M_A_DQS#[7:0] 14
M_A_DQS[7:0] 14
M_A_A[15:0] 14
CPU1D
CPU1D
SANDY
SANDY
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_BS015
M_B_BS115
M_B_BS215
M_B_CAS#15
M_B_RAS#15
M_B_WE#15
D10
K10
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
AA10
AB8
AB9
C9
SB_DQ0
A7
SB_DQ1
SB_DQ2
C8
SB_DQ3
A9
SB_DQ4
A8
SB_DQ5
D9
SB_DQ6
D8
SB_DQ7
G4
SB_DQ8
F4
SB_DQ9
F1
SB_DQ10
G1
SB_DQ11
G5
SB_DQ12
F5
SB_DQ13
F2
SB_DQ14
G2
SB_DQ15
J7
SB_DQ16
J8
SB_DQ17
SB_DQ18
K9
SB_DQ19
J9
SB_DQ20
J10
SB_DQ21
K8
SB_DQ22
K7
SB_DQ23
M5
SB_DQ24
N4
SB_DQ25
N2
SB_DQ26
N1
SB_DQ27
M4
SB_DQ28
N5
SB_DQ29
M2
SB_DQ30
M1
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
R6
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BS0
SB_BS1
SB_BS2
SB_CAS#
SB_RAS#
SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
4 OF 9
4 OF 9
SB_CLK0
SB_CLK#0
SB_CKE0
SB_CLK1
SB_CLK#1
SB_CKE1
SB_CLK2
SB_CLK#2
SB_CKE2
SB_CLK3
SB_CLK#3
SB_CKE3
SB_CS#0
SB_CS#1
SB_CS#2
SB_CS#3
SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
AE2
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DIM0_CLK_DDR0 15
M_B_DIM0_CLK_DDR#0 15
M_B_DIM0_CKE0 15
M_B_DIM0_CLK_DDR1 15
M_B_DIM0_CLK_DDR#1 15
M_B_DIM0_CKE1 15
M_B_DIM0_CS#0 15
M_B_DIM0_CS#1 15
M_B_DIM0_ODT0 15
M_B_DIM0_ODT1 15
M_B_DQS#[7:0] 15
M_B_DQS[7:0] 15
M_B_A[15:0] 15
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
A A
5
4
3
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU (DDR)
CPU (DDR)
CPU (DDR)
LA480
LA480
LA480
1
6 103Friday, January 06, 2012
6 103Friday, January 06, 2012
6 103Friday, January 06, 2012
SD
SD
SD
Page 7
5
4
3
2
1
SSID = CPU
CFG2
D D
12
R702
R702
1KR2J-1-GP
1KR2J-1-GP
OPS
OPS
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
1: Normal Operation; Lane #
definition matches socket pin map definition
TP717TP717
TP702TP702
TP703TP703
0:Lane Reversed
CFG4
C C
B B
12
R703
R703
1KR2J-1-GP
1KR2J-1-GP
DY
DY
Display Port Presence Strap
CFG4
1: Disabled; No Physical Display Port
attached to Embedded Display Port
0: Enabled; An external Display Port device is
connected to the Embedded Display Port
TP704TP704
DDR_WR_VREF0112
DDR_WR_VREF0212
TP705TP705
CFG0
1
CFG1
1
CFG2
CFG3
1
CFG4
CFG5
CFG6
CFG7
CFG16
1
H_VCCP_SEL
1
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
AJ31
AH31
AJ33
AH33
AJ26
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
B18
A19
B4
D1
J20
J15
CPU1E
CPU1E
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
RSVD#AJ31
RSVD#AH31
RSVD#AJ33
RSVD#AH33
RSVD#AJ26
RSVD#B4
RSVD#D1
RSVD#F25
RSVD#F24
RSVD#F23
RSVD#D24
RSVD#G25
RSVD#G24
RSVD#E23
RSVD#D23
RSVD#C30
RSVD#A31
RSVD#B30
RSVD#B29
RSVD#D30
RSVD#B31
RSVD#A30
RSVD#C29
RSVD#J20
RSVD#B18
RSVD#A19
RSVD#J15
SANDY
SANDY
RESERVED
RESERVED
5 OF 9
5 OF 9
RSVD#L7
RSVD#AG7
RSVD#AE7
RSVD#AK2
RSVD#W8
RSVD#AT26
RSVD#AM33
RSVD#AJ27
RSVD#T8
RSVD#J16
RSVD#H16
RSVD#G16
RSVD#AR35
RSVD#AT34
RSVD#AT33
RSVD#AP35
RSVD#AR34
RSVD#B34
RSVD#A33
RSVD#A34
RSVD#B35
RSVD#C35
RSVD#AJ32
RSVD#AK32
RSVD#AH27
RSVD#AN35
RSVD#AM35
RSVD#AT2
RSVD#AT1
RSVD#AR1
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AH27
AN35
AM35
AT2
AT1
AR1
TP713
CLK_XDP_ITP_P
CLK_XDP_ITP_N
TP720TP720
1
TP718TP718
1
TP719TP719
1
SANDY
SANDY
62.10055.421
CFG5
CFG6
CFG7
A A
DY
DY
12
12
R701
R701
1KR
1KR
DY
DY
2J-1-GP
2J-1-GP
12
R705
R705
1KR2J-1-GP
1KR2J-1-GP
DY
DY
PCIE Port Bifurcation Straps
R704
R704
1KR
1KR
CFG[6:5]
2J-1-GP
2J-1-GP
11: x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PEG DEFER TRAINING
CFG7
5
1: PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
4
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
3
SKT-BGA989C470395-1H180
SKT-BGA989C470395-1H180
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU (RESERVED)
CPU (RESERVED)
CPU (RESERVED)
LA480
LA480
LA480
7 103Friday, January 06, 2012
7 103Friday, January 06, 2012
7 103Friday, January 06, 2012
1
SD
SD
SD
Page 8
5
0511-CHECK CAP.
VCC_CORE
C802
C802
C801
D D
C C
B B
A A
C801
12
C815
C815
12
C816
C816
12
C837
C837
12
SC
DY
SC
DY
SC
SC
12
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
C817
C817
SC
SC
SC
SC
12
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
C821
C821
SC
SC
SC
SC
12
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
C836
C836
SC
SC
SC
SC
12
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
5
VCC CORE:53A
C803
C803
C804
C804
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
SC10U6D3V5KX-1GP
DY
12
12
C819
C819
C818
C818
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C823
C823
C822
C822
DY
DY
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C834
C834
C835
C835
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C811
C811
12
C820
C820
12
C824
C824
12
C833
C833
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C825
C825
C826
C826
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C832
C832
DY
DY
12
SC10U6D3V5KX-1GP
12
C831
C831
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C827
C827
12
C828
C828
12
4
POWER
CPU1F
CPU1F
VCC_CORE
AG35
VCC
AG34
VCC
AG33
VCC
AG32
VCC
AG31
VCC
AG30
VCC
AG29
VCC
AG28
VCC
AG27
VCC
AG26
VCC
AF35
VCC
AF34
VCC
AF33
VCC
AF32
VCC
AF31
VCC
AF30
VCC
AF29
VCC
AF28
VCC
AF27
VCC
AF26
VCC
AD35
VCC
AD34
VCC
AD33
VCC
AD32
VCC
AD31
VCC
AD30
VCC
AD29
VCC
AD28
VCC
AD27
VCC
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
4
AD26
VCC
AC35
VCC
AC34
VCC
AC33
VCC
AC32
VCC
AC31
VCC
AC30
VCC
AC29
VCC
AC28
VCC
AC27
VCC
AC26
VCC
AA35
VCC
AA34
VCC
AA33
VCC
AA32
VCC
AA31
VCC
AA30
VCC
AA29
VCC
AA28
VCC
AA27
VCC
AA26
VCC
Y35
VCC
Y34
VCC
Y33
VCC
Y32
VCC
Y31
VCC
Y30
VCC
Y29
VCC
Y28
VCC
Y27
VCC
Y26
VCC
V35
VCC
V34
VCC
V33
VCC
V32
VCC
V31
VCC
V30
VCC
V29
VCC
V28
VCC
V27
VCC
V26
VCC
U35
VCC
U34
VCC
U33
VCC
U32
VCC
U31
VCC
U30
VCC
U29
VCC
U28
VCC
U27
VCC
U26
VCC
R35
VCC
R34
VCC
R33
VCC
R32
VCC
R31
VCC
R30
VCC
R29
VCC
R28
VCC
R27
VCC
R26
VCC
P35
VCC
P34
VCC
P33
VCC
P32
VCC
P31
VCC
P30
VCC
P29
VCC
P28
VCC
P27
VCC
P26
VCC
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
POWER
SANDY
SANDY
CORE SUPPLY
CORE SUPPLY
3
6 OF 9
6 OF 9
AH13
VCCIO
AH10
VCCIO
AG10
VCCIO
AC10
VCCIO
Y10
VCCIO
U10
VCCIO
P10
VCCIO
L10
VCCIO
J14
VCCIO
J13
VCCIO
J12
VCCIO
J11
VCCIO
H14
VCCIO
H12
VCCIO
H11
VCCIO
G14
VCCIO
G13
VCCIO
G12
VCCIO
F14
VCCIO
F13
VCCIO
F12
VCCIO
F11
VCCIO
E14
VCCIO
E12
VCCIO
E11
VCCIO
D14
VCCIO
D13
VCCIO
D12
VCCIO
D11
VCCIO
C14
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VIDALERT#
VIDSCLK
VIDSOUT
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
PEG AND DDR
PEG AND DDR
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSSIO_SENSE
SENSE LINES SVID
SENSE LINES SVID
3
2
0511-CHECK CAP.
C805
C805
12
C812
C812
12
For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7
For CRB VIDALERT# need to pull high 75 ohm close to CPU
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
0511-CHECK
VCCIO:8.5A
C806
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C808
C808
C807
C807
C806
Reserve C846 & C847
C829
C813
C813
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
1 2
R803 43R2J-GPR803 43R2J-GP
1 2
R804 130R2F-1-GPR804 130R2F-1-GP
VCCIO_SENSE 45
VSSIO_SENSE 45
C829
C814
C814
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
R807 75R2F-2-GPR807 75R2F-2-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
VCC_CORE
12
12
2
C810
C810
C809
C809
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C842
C842
C830
C830
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
VR_SVID_ALERT# 42
H_CPU_SVIDCLK 42
H_CPU_SVIDDAT 42
1D05V_VTT
R801
R801
100R2F-L1-GP-U
100R2F-L1-GP-U
VCCSENSE 42
VSSSENSE 42
R802
R802
100R2F-L1-GP-U
100R2F-L1-GP-U
C838
C838
C839
C839
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1D05V_VTT
SC10U6D3V5KX-1GP
12
12
1D05V_VTT
C844
C844
C843
C843
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
DY
12
12
check
Place neer PCU pin.
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
0511-CHECK
1D05V_VTT
C841
C841
C840
C840
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
SC10U6D3V5KX-1GP
DY
12
12
C845
C845
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
1D05V_VTT
12
R808
R808
10R2F-L-GP
10R2F-L-GP
VCCIO_SENSE
VSSIO_SENSE
12
R809
R809
10R2F-L-GP
10R2F-L-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU (VCC_CORE)
CPU (VCC_CORE)
CPU (VCC_CORE)
LA480
LA480
LA480
1
SD
SD
8 103Friday, January 06, 2012
8 103Friday, January 06, 2012
8 103Friday, January 06, 2012
1
SD
Page 9
5
4
3
2
1
C914
C914
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCC_GFXCORE
12
R906
R906
100R2F-L1-GP-U
100R2F-L1-GP-U
12
R907
R907
100R2F-L1-GP-U
100R2F-L1-GP-U
1D5V_S0
0511-CHECK CAP
POWER
CPU1G
D D
C C
B B
VCC_GFXCORE
C901
C901
12
C907
C907
12
PROCESSOR VAXG: 24A
C902
C902
C903
C903
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC
SC
12
C908
C908
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1D8V_S0
12
C918
C918
12
C926
C926
12
10U6D3V5KX-1GP
10U6D3V5KX-1GP
SC
SC
10U6D3V5KX-1GP
10U6D3V5KX-1GP
C904
C904
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C919
C919
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
VCCPLL:1.2A
C923
C923
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C905
C905
12
C920
C920
12
C922
C922
12
0511-CHECK
RC901
C906
C906
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C921
C921
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C924
C924
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
RC901
SC33P50V2JN-3GP
DY
DY
DY
DY
12
RC902
RC902
12
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
CPU1G
AT24
VAXG
AT23
VAXG
AT21
VAXG
AT20
VAXG
AT18
VAXG
AT17
VAXG
AR24
VAXG
AR23
VAXG
AR21
VAXG
AR20
VAXG
AR18
VAXG
AR17
VAXG
AP24
VAXG
AP23
VAXG
AP21
VAXG
AP20
VAXG
AP18
VAXG
AP17
VAXG
AN24
VAXG
AN23
VAXG
AN21
VAXG
AN20
VAXG
AN18
VAXG
AN17
VAXG
AM24
VAXG
AM23
VAXG
AM21
VAXG
AM20
VAXG
AM18
VAXG
AM17
VAXG
AL24
VAXG
AL23
VAXG
AL21
VAXG
AL20
VAXG
AL18
VAXG
AL17
VAXG
AK24
VAXG
AK23
VAXG
AK21
VAXG
AK20
VAXG
AK18
VAXG
AK17
VAXG
AJ24
VAXG
AJ23
VAXG
AJ21
VAXG
AJ20
VAXG
AJ18
VAXG
AJ17
VAXG
AH24
VAXG
AH23
VAXG
AH21
VAXG
AH20
VAXG
AH18
VAXG
AH17
VAXG
B6
VCCPLL
A6
VCCPLL
A2
VCCPLL
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
POWER
SANDY
SANDY
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
SENSE
SENSE
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
7 OF 9
7 OF 9
VAXG_SENSE
VSSAXG_SENSE
LINES
LINES
SM_VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA_SENSE
FC_C22
VCCSA_VID1
AK35
AK34
Refer to the latest Huron River Mainstream PDG
(Doc# 436735) for more details on S3 power
reduction implementation.
VCC_AXG_SENSE 42
VSS_AXG_SENSE 42
+V_SM_VREF_CNT should have 10 mil trace width
AL1
Routing Guideline:
Power from DDR_VREF_S3 and +V_SM_VREF_CNT
should have 10 mils trace width.
+V_SM_VREF_CNT 37
VDDQ:5A
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
VCCA:6A
C916
C916
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C909
C909
DY
DY
12
4
1
2 3
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C915
C915
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
RN901
RN901
SRN1KJ-7-GP
SRN1KJ-7-GP
C910
C910
C911
C911
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C917
C917
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
VCCSA_SENSE 48
VCCSA_SELECT0 48
VCCSA_SELECT1 48
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCCSA
+V0.85S - VCCSA - System Agent rail voltage can be
[0.9, 0.725, 0.8, 0.675] V for IVB
[0.9, 0.8] V for SNB
C912
C912
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCC_AXG_SENSE
VSS_AXG_SENSE
C913
C913
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (VCC_GFXCORE)
CPU (VCC_GFXCORE)
CPU (VCC_GFXCORE)
Taipei Hsien 221, Taiwan, R.O.C.
LA480
LA480
LA480
9 103Friday, January 06, 2012
9 103Friday, January 06, 2012
9 103Friday, January 06, 2012
1
SD
SD
SD
Page 10
5
4
3
2
1
SSID = CPU
9 OF 9
8 OF 9
CPU1H
CPU1H
AT35
VSS
AT32
VSS
AT29
VSS
AT27
VSS
AT25
VSS
AT22
VSS
D D
C C
B B
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SANDY
SANDY
VSS
VSS
8 OF 9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
H33
H30
H27
H24
H21
H18
H15
H13
H10
G35
G32
G29
G26
G23
G20
G17
G11
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
L33
L30
L27
K35
K32
K29
K26
J34
J31
F34
F31
F29
CPU1I
CPU1I
SANDY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P9
VSS
P8
VSS
P6
VSS
P5
VSS
P3
VSS
P2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L9
VSS
L8
VSS
L6
VSS
L5
VSS
L4
VSS
L3
VSS
L2
VSS
L1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H9
VSS
H8
VSS
H7
VSS
H6
VSS
H5
VSS
H4
VSS
H3
VSS
H2
VSS
H1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SANDY
VSS
VSS
9 OF 9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
SANDY
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
A A
5
4
3
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU (VSS)
CPU (VSS)
CPU (VSS)
LA480
LA480
LA480
SD
SD
10 103Friday, January 06, 2012
10 103Friday, January 06, 2012
10 103Friday, January 06, 2012
1
SD
Page 11
5
DCCBBAA
4
3
2
1
D
BLANK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LA480 SD
A4
LA480 SD
A4
LA480 SD
A4
Date: Sheet of
Date: Sheet of
Date: Sheet of
11 103Friday, January 06, 2012
11 103Friday, January 06, 2012
11 103Friday, January 06, 2012
Page 12
5
4
3
2
VREF circuit -M1 (Voltage Driver Network) & M3 (Driven by Processor) Implementation
CAD Note: All VREF traces should have 20:20 mil trace geometry. Note that while 20 mil trace width is optimal, short violations is acceptable if
required due to tight routing constraints.
1
1 2
DY
D D
C C
B B
Driven by process (PIN#B4) Driven by process (PIN#D1)
DDR_WR_VREF017
1KR2F-3-GP
1KR2F-3-GP
DRAMRST_CNTRL_PCH20,37
DDR_VREF_S3 DDR_VREF_S3
R1228
R1228
1 2
R1207
R1207
0R0402-PAD
0R0402-PAD
12
DY
DY
1 2
R1203
R1203
0R0402-PAD
0R0402-PAD
SA_DIMM_VREFDQ SB_DIMM_VREFDQ
DY
R1226 0R2J-2-GP
R1226 0R2J-2-GP
U1201
U1201
S
D
G
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
DDR_WR_VREF01_B4
12
R1204
R1204
0R0402-PAD
0R0402-PAD
12
R1209
R1209
0R2J-2-GP
0R2J-2-GP
DY
DY
+V_VREF_PATH1
12
R1225
R1225
0R2J-2-GP
0R2J-2-GP
DY
DY
12
R1210
R1210
0R0402-PAD
0R0402-PAD
CLOSE PIN1
M_VREF_DQ_DIMM0
12
C1201
C1201
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
M_VREF_DQ_DIMM1
12
C1202
C1202
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SODDIM1
DDR_WR_VREF027
SODDIM0
M_VREF_CA_DIMM0
1KR2F-3-GP
1KR2F-3-GP
DRAMRST_CNTRL_PCH20,37
M_VREF_CA_DIMM1
12
R1227
R1227
DY
DY
12
C1203
C1203
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
CLOSE PIN
12
C1204
C1204
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2
DY
DY
R1208 0R2J-2-GP
R1208 0R2J-2-GP
U1202
U1202
S
D
G
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
DDR_VREF_S3DDR_VREF_S3
1 2
R1216
R1216
0R2J-2-GP
0R2J-2-GP
DDR_WR_VREF01_D1DDR_WR_VREF01_B4
0R0402-PAD
0R0402-PAD
DY
DY
R1232
R1232
1 2
12
R1218
R1218
0R0402-PAD
0R0402-PAD
+V_VREF_PATH3
12
R1217
R1217
0R0402-PAD
0R0402-PAD
1 2
R1222
R1222
0R0402-PAD
0R0402-PAD
1 2
DY
DY
R1219
R1219
0R2J-2-GP
0R2J-2-GP
+V_SM_VREF 37
DDR_WR_VREF01_D1
12
R1221
R1221
0R0402-PAD
0R0402-PAD
CLOSE PIN
CLOSE PIN
+V_VREF_PATH2
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
M3
M3
M3
LA480
LA480
LA480
12 103Friday, January 06, 2012
12 103Friday, January 06, 2012
12 103Friday, January 06, 2012
1
SD
SD
SD
Page 13
5
DCCBBAA
4
3
2
1
D
BLANK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LA480 SD
A4
LA480 SD
A4
LA480 SD
A4
Date: Sheet of
Date: Sheet of
Date: Sheet of
13 103Friday, January 06, 2012
13 103Friday, January 06, 2012
13 103Friday, January 06, 2012
Page 14
5
DIMM1
SSID = MEMORY
D D
C C
Place these caps
C1419
C1419
12
SC1
SC1
U6D3V2KX-GP
U6D3V2KX-GP
close to VTT1 and
VTT2.
C1420
C1420
SC1
SC1
12
U6D3V2KX-GP
U6D3V2KX-GP
DY
DY
C1421
C1421
12
C1422
C1422
SC1
SC1
SC1
SC1
12
U6D3V2KX-GP
U6D3V2KX-GP
U6D3V2KX-GP
U6D3V2KX-GP
DY
DY
0D75V_S0
B B
M_A_DQ[63:0]6
C1418
C1418
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
DY
DY
M_A_DQS#[7:0] 6
M_A_DQS[7:0] 6
M_A_DIM0_ODT06
M_A_DIM0_ODT16
M_VREF_CA_D IMM0
M_VREF_DQ_D IMM0
DDR3_DR AMRST#15,37
M_A_A[15:0] 6
M_A_BS26
M_A_BS06
M_A_BS16
0D75V_S0
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
DIMM1
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12
119
A13
80
A14
78
A15
79
A16/BA2
109
BA0
108
BA1
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
10
DQS0#
27
DQS1#
45
DQS2#
62
DQS3#
135
DQS4#
152
DQS5#
169
DQS6#
186
DQS7#
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
116
ODT0
120
ODT1
126
VREF_CA
1
VREF_DQ
30
RESET#
203
VTT1
204
VTT2
DDR3-204P- 96-GP-U1
DDR3-204P- 96-GP-U1
62.10017.V61
62.10017.V61
2ND = *62.10017.X51
2ND = *62.10017.X51
3RD = *62.10017.V61
3RD = *62.10017.V61
(H=8mm)
4
RAS#
CAS#
CS0#
CS1#
CKE0
CKE1
CK0#
CK1#
EVENT#
VDDSPD
NC#77
NC#122
NC#125/TEST
3
NP1
NP1
NP2
NP2
110
113
WE#
115
114
121
73
74
101
CK0
103
102
CK1
104
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
200
SDA
202
SCL
198
199
SA0_DIM0
197
SA0
SA1_DIM0
201
SA1
77
122
125
75
VDD
76
VDD
81
VDD
82
VDD
87
VDD
88
VDD
93
VDD
94
VDD
99
VDD
100
VDD
105
VDD
106
VDD
111
VDD
112
VDD
117
VDD
118
VDD
123
VDD
124
VDD
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
44
VSS
48
VSS
49
VSS
54
VSS
55
VSS
60
VSS
61
VSS
65
VSS
66
VSS
71
VSS
72
VSS
127
VSS
128
VSS
133
VSS
134
VSS
138
VSS
139
VSS
144
VSS
145
VSS
150
VSS
151
VSS
155
VSS
156
VSS
161
VSS
162
VSS
167
VSS
168
VSS
172
VSS
173
VSS
178
VSS
179
VSS
184
VSS
185
VSS
189
VSS
190
VSS
195
VSS
196
VSS
205
VSS
206
VSS
1D5V_S3
M_A_RAS# 6
M_A_WE# 6
M_A_CAS# 6
M_A_DIM0_CS#0 6
M_A_DIM0_CS#1 6
M_A_DIM0_CKE0 6
M_A_DIM0_CKE1 6
M_A_DIM0_CLK_DDR 0 6
M_A_DIM0_CLK_DDR #0 6
M_A_DIM0_CLK_DDR 1 6
M_A_DIM0_CLK_DDR #1 6
PCH_SMBDAT A 15,20,65,66
PCH_SMBCLK 15,20,65,66
TS#_DIMM0_1 15
C1401
C1401
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
Layout Note:
Place these Caps near
SO-DIMMB.
12
3D3V_S0
12
C1402
C1402
SC2D2U10V3KX- 1GP
SC2D2U10V3KX- 1GP
DY
DY
1D5V_S3
0511-CHECK
TC1401
TC1401
12
DY
DY
C1414
C1414
12
C1403
C1403
ST330U2VDM-4-GP
ST330U2VDM-4-GP
12
C1415
C1415
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
SODIMM A DECOUPLING
C1404
C1404
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
DY
DY
C1416
C1416
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
SA0_DIM0
SA1_DIM0
12
R1401
R1401
10KR2J-3-GP
10KR2J-3-GP
Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
If SA0 DIM0 = 1, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32
Thermal EVENT
TS#_DIMM0_1
1 2
R1403
R1403
10KR2J-3-GP
10KR2J-3-GP
C1405
C1405
12
C1417
C1417
12
C1406
C1406
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1407
C1407
12
C1408
C1408
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
DY
DY
R1402
R1402
10KR2J-3-GP
10KR2J-3-GP
3D3V_S0
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
DY
DY
C1409
C1409
12
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
DY
12
C1410
C1410
2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
DDR3-SODIMM1
DDR3-SODIMM1
DDR3-SODIMM1
LA480
LA480
LA480
1
14 103
14 103
14 103
SD
SD
SD
Page 15
5
SSID = MEMORY
D D
C C
Place these caps
close to VTT1 and
0D75V_S0
VTT2.
C1520
C1519
C1519
12
C1520
C1521
C1521
SC1
SC1
SC1
SC1
U6D3V2KX-GP
U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
U6D3V2KX-GP
U6D3V2KX-GP
DY
DY
C1518
C1518
SC1
SC1
12
U6D3V2KX-GP
U6D3V2KX-GP
DY
DY
B B
M_B_A[15:0] 6
M_B_BS26
M_B_BS06
M_B_BS16
M_B_DQ[63:0]6
M_B_DQS#[7:0] 6
M_B_DQS[7:0] 6
M_B_DIM0_ODT06
M_B_DIM0_ODT16
M_VREF_CA_D IMM1
M_VREF_DQ_D IMM1
DDR3_DR AMRST#14,37
0D75V_S0
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
(H=4mm)
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
109
108
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
10
27
45
62
135
152
169
186
12
29
47
64
137
154
171
188
116
120
126
1
30
203
204
DDR3-204P- 144-GP-U1
DDR3-204P- 144-GP-U1
62.10024.G21
62.10024.G21
2nd = *62.10017.X41
2nd = *62.10017.X41
3rd = *62.10017.V51
3rd = *62.10017.V51
DIMM2
DIMM2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2
4
RAS#
CAS#
CS0#
CS1#
CKE0
CKE1
CK0#
CK1#
EVENT#
VDDSPD
NC#1
NC#2
NC#/TEST
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
3
NP1
NP1
NP2
NP2
110
113
WE#
115
114
121
73
74
101
CK0
103
102
CK1
104
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
200
SDA
202
SCL
198
199
SA0_DIM1
197
SA0
SA1_DIM1
201
SA1
77
122
125
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
44
VSS
48
VSS
49
VSS
54
VSS
55
VSS
60
VSS
61
VSS
65
VSS
66
VSS
71
VSS
72
VSS
127
VSS
128
VSS
133
VSS
134
VSS
138
VSS
139
VSS
144
VSS
145
VSS
150
VSS
151
VSS
155
VSS
156
VSS
161
VSS
162
VSS
167
VSS
168
VSS
172
VSS
173
VSS
178
VSS
179
VSS
184
VSS
185
VSS
189
VSS
190
VSS
195
VSS
196
VSS
205
VSS
206
VSS
1D5V_S3
M_B_RAS# 6
M_B_WE# 6
M_B_CAS# 6
M_B_DIM0_CS#0 6
M_B_DIM0_CS#1 6
M_B_DIM0_CKE0 6
M_B_DIM0_CKE1 6
M_B_DIM0_CLK_DDR 0 6
M_B_DIM0_CLK_DDR #0 6
M_B_DIM0_CLK_DDR 1 6
M_B_DIM0_CLK_DDR #1 6
PCH_SMBDAT A 14,20,65,66
PCH_SMBCLK 14,20,65,66
TS#_DIMM0_1 14
C1501
C1501
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
12
1D5V_S3
DY
DY
12
C1502
C1502
SC2D2U10V3KX- 1GP
SC2D2U10V3KX- 1GP
DY
DY
3D3V_S0
0511-CHECK
SODIMM B DECOUPLING
C1504
C1504
C1505
C1503
C1503
12
C1511
C1511
12
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1505
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
DY
DY
C1512
C1512
C1513
C1513
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
3D3V_S0
12
R1501
R1501
10KR2J-3-GP
10KR2J-3-GP
SA1_DIM1
SA0_DIM1
12
R1502
R1502
10KR2J-3-GP
10KR2J-3-GP
Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
SO-DIMMB is placed farther from
the Processor than SO-DIMMA
C1508
C1507
C1507
12
C1508
C1509
C1509
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
DY
DY
C1506
C1506
12
C1514
C1514
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1510
C1510
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
DY
DY
2
1
62.10017.X41
3RD:62.10017.V51
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
DDR3-SODIMM2
DDR3-SODIMM2
DDR3-SODIMM2
LA480
LA480
LA480
1
15 103
15 103
15 103
SD
SD
SD
Page 16
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
DDR3-SODIMM2
DDR3-SODIMM2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
DDR3-SODIMM2
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
16 103
16 103
16 103
1
SD
Page 17
A
B
C
D
E
3D3V_S0
4 4
3 3
2 2
RN1701
RN1701
1
2 3
SRN2K2J-1-GP
SRN2K2J-1-GP
RN1702
RN1702
2 3
1
SRN100KJ-6-GP
SRN100KJ-6-GP
0511-CHECK 0511-CHECK
EC1701
EC1701
12
DY
DY
L_CTRL_DATA
4
L_CTRL_CLK
L_BKLT_EN49
L_DDC_DATA(K47):
This signal is on the LVDS interface.
This signal needs to be left NC if eDP is
used for the local flat panel display
L_BKLT_EN
LVDS_VDD_EN LVDS_VREFH
4
Close to PCH
Close to PCH and keep 20mil
away from other signal.
CRT_RED
CRT_BLUE
CRT_GREEN
678
RN1705
RN1705
SRN150F-1-GP
SRN150F-1-GP
123
4 5
Close to PCH
CRT_BLUE
CRT_GREEN
CRT_RED
EC1702
EC1702
EC1703
EC1703
SC
SC
SC
SC
12
D1U50V3KX-GP
D1U50V3KX-GP
DY
DY
SCD1U50V3KX-GP
SCD1U50V3KX-GP
12
D1U50V3KX-GP
D1U50V3KX-GP
DY
DY
12
R1701
R1701
2K37R2F-GP
2K37R2F-GP
CRT_BLUE50
CRT_GREEN50
CRT_RED50
LVDS_VDD_EN49
L_BKLT_CTRL49
LVDS_DDC_CLK_R49
LVDS_DDC_DATA_R49
RN1704
RN1704
2 3
1
SRN0J-6-GP
SRN0J-6-GP
LVDSA_CLK#49
LVDSA_CLK49
LVDSA_DATA0#49
LVDSA_DATA1#49
LVDSA_DATA2#49
LVDSA_DATA049
LVDSA_DATA149
LVDSA_DATA249
CRT_DDC_CLK50
CRT_DDC_DATA50
CRT_HSYNC50
CRT_VSYNC50
R1702
R1702
1KR2D-1-GP
1KR2D-1-GP
4 OF 10
PCH1D
PCH1D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_CTRL_CLK
L_CTRL_DATA
LVDS_IBG
LVDS_VREFL
4
12
DAC_IREF_R
T45
P39
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
N48
P49
T49
T39
M40
M47
M49
T43
T42
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
PANTHER-GP-NF
PANTHER-GP-NF
LVDS
LVDS
Digital Display Interface
Digital Display Interface
CRT
CRT
4 OF 10
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
RN1706
RN1706
SRN2K2J-1-GP
SRN2K2J-1-GP
3D3V_S0
DDI Port B Detect:(SDVO_CTRL_ DATA)
1: Port B detected
4
0: Port B not detected
1
2 3
PCH_HDMI_CLK 51
PCH_HDMI_DATA 51
HDMI_PCH_DET 51
HDMI_DATA2_R# 51
HDMI_DATA2_R 51
HDMI_DATA1_R# 51
HDMI_DATA1_R 51
HDMI_DATA0_R# 51
HDMI_DATA0_R 51
HDMI_CLK_R# 51
HDMI_CLK_R 51
PORT
PORT-B
DDI PCH Pin
Names
DDPB_[0]P
DDPB_[0]N
DDPB_[1]P
DDPB_[1]N
DDPB_[2]P
DDPB_[2]N
DDPB_[3]P
DDPB_[3]N
DDPB_AUXP
DDPB_AUXN
DDPB_HPD
SDVO_CTRLCLK
SDVO_CTRLDATA
HDMI/DVI
Mapping
TMDSB_DATA2
TMDSB_DATA2#
TMDSB_DATA1
TMDSB_DATA1#
TMDSB_DATA0
TMDSB_DATA0#
TMDSB_CLK
TMDSB_CLK#
NA
NA
HDMIB_HPD
HDMIB_CTRLCLK
HDMIB_CTRLDATA
HDMI
Notes:
1K 0.5% 0402
1 1
A
B
The recommended value for this external resistor is 1.0 k ±0.5%. The CRT DAC outputs may be
measured when the display is completely white. If CRT DAC signal voltage value is between 665
mV to 770 mV, then the video level is within VESA specification and the reference resistor
value is optimal for the motherboard design.
C
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
PCH : LVDS/CRT/DDI
PCH : LVDS/CRT/DDI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
PCH : LVDS/CRT/DDI
Taipei Hsien 221, Taiwan, R.O.C.
LA480
LA480
LA480
SD
SD
17 103Friday, January 06, 2012
17 103Friday, January 06, 2012
17 103Friday, January 06, 2012
E
SD
Page 18
A
B
C
D
E
4 4
3 3
2 2
SSID = PCH
INT_PIRQH#
INT_PIRQB#
INT_PIRQF#
3D3V_S0
PCI_GNT#3 Low = A16 swap
3D3V_S0
R1817
R1817
8K2R2J-3-GP
8K2R2J-3-GP
DY
DY
1 2
DGPU_PW M_SELECT#
RN1801
RN1801
1
2
3
4
5 6
A16 swap override Strap/Top-Block
Swap Override jumper
DGPU_HOLD _RST#
DGPU_PW R_EN#
10
INT_PIRQD#
9
LCD_DET#
8
INT_PIRQC#INT_PIRQA#
7
PCI_GNT3#
12
R1801
R1801
4K7R2J-2-GP
4K7R2J-2-GP
1 2
3D3V_S0
1 2
1 2
R1814
R1814
10KR2F-2-GP
10KR2F-2-GP
DY
DY
R1815
R1815
10KR2F-2-GP
10KR2F-2-GP
INT_PIRQG#
SRN8K2J-2-G P-U
SRN8K2J-2-G P-U
DY
DY
override/Top-Block
Swap Override enabled
High = Default
R1819 10KR2J-3-GPR1819 10KR 2J-3-GP
3D3V_S0
For PPT USB3.0 feature
USB3_RX1_N62
USB3_RX3_N62
USB3_RX1_P62
USB3_RX3_P62
USB3_TX1_N62
USB3_TX3_N62
USB3_TX1_P62
USB3_TX3_P62
3D3V_S0
R1818
R1818
INT_PIRQA#
8K2R2J-3-GP
8K2R2J-3-GP
INT_PIRQB#
INT_PIRQC#
DY
DY
INT_PIRQD#
1 2
1 2
1 2
1 2
1
TP1813TP1813
DGPU_HOLD _RST#
DGPU_SELEC T#
DGPU_PW R_EN#
BBS_BIT1
DGPU_PW M_SELECT#
PCI_GNT3#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
PCI_PME#
1
PCI_PLTRST#
CLK_PCI_LPC_R
CLK_PCI_FB_R
CLK_PCI_KBC_R
DGPU_HOLD _RST#8 3
TP1805TP1805
DGPU_PW R_EN#93
LCD_DET#49
SATA_ODD_D A#27,56
CLK_PCI_LPC65,71
CLK_PCI_FB20
CLK_PCI_KBC27
1 2
R1813
R1813
0R2J-2-GP
0R2J-2-GP
R1804 22R2J-2-GPR1804 22R2J-2-GP
R1805 22R2J-2-GPR1805 22R2J-2-GP
R1806 22R2J-2-GPR1806 22R2J-2-GP
BG26
BH25
BG16
AH38
AH37
AK43
AK45
AH12
AB46
AB45
AY16
BG46
BE28
BC30
BE32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
BJ26
BJ16
C18
N30
H3
AM4
AM5
Y13
K24
L24
B21
M20
BJ32
K40
K38
H38
G38
C46
C44
E40
D47
E42
F46
G42
G40
C42
D44
K10
C6
H49
H43
J48
K42
H40
PCH1E
PCH1E
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24
USB3RN1
USB3RN2
USB3RN3
USB3RN4
USB3RP1
USB3RP2
USB3RP3
USB3RP4
USB3TN1
USB3TN2
USB3TN3
USB3TN4
USB3TP1
USB3TP2
USB3TP3
USB3TP4
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PME#
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
PANTHER- GP-NF
PANTHER- GP-NF
RSVD
RSVD
PCI
PCI
USB
USB
5 OF 10
5 OF 10
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
NV_ALE
AV5
NV_RCOMP
AV10
AT8
AY5
BA2
AT12
BF3
Utilize Port 9 for USB debug
USB_PN0
C24
USB_PP0
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USB_RBIAS
C33
B33
USB_OC#0_1
A14
USB_OC#2_3
K20
USB_OC#4_5
B17
USB_OC#6_7
C16
USB_OC#8_9
L16
USB_OC#10_11
A16
USB_OC#12_13
D14
PCH_GPIO14
C14
OC[3:0]# for Device 29 (Ports 0-7)
OC[7:4]# for Device 26 (Ports 8-13)
1
1
1
1
1 2
R1811
R1811
22D6R2F-L1-G P
22D6R2F-L1-G P
USB_OC#0_1 62
USB_OC#2_3 61
USB_OC#4_5 62
USB_OC#8_9 82
TP1814TP1814
TP1812TP1812
TP1819TP1819
TP1820TP1820
USB_PN1 62
USB_PP1 62
USB_PN2 82
USB_PP2 82
USB_PN3 62
USB_PP3 62
USB_PN4 63
USB_PP4 63
USB_PN5 82
USB_PP5 82
USB_PN8 66
USB_PP8 66
USB_PN9 82
USB_PP9 82
USB_PN10 64
USB_PP10 64
USB_PN11 65
USB_PP11 65
USB_PN12 49
USB_PP12 49
GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19
Mini Card2 (WWAN)
USB3.0 ext port 1
USB2.0 ext port 4
USB3.0 ext port 2
BLUETOOTH
CARD READER
USB2.0 ext port 3
Fingerprint
Mini Card1 (WLAN)
CAMERA
USB 2.0 Overcurrent Pin Default Usage
Pin
OC0#
OC1#
OC2#
OC3#
DY
1KR2J-1-GP
1KR2J-1-GP
BBS_BIT0 21
BBS_BIT1
R1802
R1802
1 2
DY
DY
1KR2J-1-GP
1KR2J-1-GP
R1803
R1803
1 2
DY
BOOT BIOS Strap
0 0 LPC
0 1 Reserved
11
Default Port
Mapping
Port 0, Port 1
Port 2, Port 3
Port 4, Port 5
Port 6, Port 7
Pin
OC4#
OC5#
OC6#
OC7#
Reserved 01
SPI(Default)
Default Port
Mapping
Port 8, Port 9
Port 10, Port 11
Port 12, Port 13
Not Used
Gx8 USB Table
Pair
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Device
X
USB3.0, ext port1
USB2.0, ext port4
USB3.0, ext port2
Bluetooth
CARD READER
X
X
3G
USB2.0, ext. port 3
Finger Print
Mini Card1 (WLAN)
CAMERA
X
Reserve Buffer or not?
PLT_RST#5,27,31,36,65,66,71,80,82,83,97
R1816
R1816
100KR2J-1-GP
100KR2J-1-GP
1 1
A
1 2
R1807
R1807
0R2J-2-GP
0R2J-2-GP
12
C1801
C1801
12
SC220P50V2KX-3GP
SC220P50V2KX-3GP
DY
DY
DY
DY
B
3D3V_S5
USB_OC#2_3
PCH_GPIO14
RN1802
RN1802
1
2
3
4
5 6
SRN8K2J-2-G P-U
SRN8K2J-2-G P-U
C
10
9
8
7
USB_OC#12_13
USB_OC#8_9USB_OC#6_7
USB_OC#10_11USB_OC#0_1PCI_PLTRST#
USB_OC#4_5
3D3V_S5
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
PCH : PCI/USB/NVRAM/RSVD
PCH : PCI/USB/NVRAM/RSVD
PCH : PCI/USB/NVRAM/RSVD
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
LA480
LA480
LA480
E
SD
SD
18 103Friday, January 06, 2012
18 103Friday, January 06, 2012
18 103Friday, January 06, 2012
SD
Page 19
A
B
C
D
E
SSID = PCH
For platforms not supporting Deep S4/S5
1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)
4 4
3 OF 10
PCH1C
Signal Routing Guideline:
DMI_ZCOMP keep W=4 mils and
routing length less than 500
mils.
DMI_IRCOMP keep W=4 mils and
routing length less than 500
mils.
SYS_PWROK
1 2
DY
DY
R1926 10KR 2J-3-GP
R1926 10KR 2J-3-GP
PWROK
1 2
R1904 100KR 2J-1-GPR 1904 100KR2J- 1-GP
R1905
R1905
Platforms supporting Deep S4/S5, but not wishing
to participate in the handshake during wake and Deep S4/S5
entry may tie SUSACK# to SUSWARN#.
3 3
2 2
SUSPWRDNACK : No longer requires a 10-K pull-up to VccSUS
(3.3 V).
3D3V_S0
10KR2J-3-GP
10KR2J-3-GP
SYS_PWROK: the system is ready to start the exit from
reset (de-asserts PLT_RST# to the processor)
PWROK: it indicates to PCH that
its CORE well power is stable.
Active Sleep Well
(ASW) Power OK
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
SYS_RESET#
1 2
DY
DY
MPWROK45
3D3V_S5
RN1901
RN1901
8
7
6
SRN10KJ-6-G P
SRN10KJ-6-G P
R1909 10KR2J-3-GPR1909 10KR2J- 3-GP
DY
DY
R1922 10KR2J-3-GP
R1922 10KR2J-3-GP
R1908
R1908
10KR2J-3-GP
10KR2J-3-GP
1
2
3
45
12
12
12
XDP_DBRESE T#5
S0_PWR_G OOD27
BATLOW#
PM_RI#
SUS_PWR _ACK
PCIE_WAKE#
1D05V_VTT
SUS_ACK#: For non-DWS platforms, this signal can be left unconnected.
Due to the internal pull-up on this signal it will be pulled high
in order for the boot sequence to proceed.
SYS_PWROK36
1 2
R1931 0R 2J-2-GP
R1931 0R 2J-2-GP
SBA
SBA
AC_PRESENT
PM_PWRBT N#
PM_RSMRST#
DMI_RXN[3:0]4
DMI_RXP[3:0]4
DMI_TXN[3:0]4
DMI_TXP[3:0]4
R1901
R1901
49D9R2F-GP
49D9R2F-GP
1 2
R1902
R1902
1 2
750R2F-GP
750R2F-GP
1 2
DY
DY
R1915 0R 2J-2-GP
R1915 0R 2J-2-GP
R1916 0R0402-PADR1916 0R0402-PAD
1 2
1 2
R1914 0R 0402-PADR1914 0R0402- PAD
1 2
R1930 0R 2J-2-GP
R1930 0R 2J-2-GP
Non-SBA
Non-SBA
PM_DRAM_PW RGD37
PM_PWRBT N#27,97
AC_PRESENT27
PCH_WAKE#
CRB : 1K
CHKLIST: 10K
DMI_COMP_R
RBIAS_CPY
1 2
DY
DY
R1923
R1923
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
SUSACK#SUS_PWR _ACK
SYS_RESET#
0R2J-2-GP
0R2J-2-GP
PWROK
MEPWROK
PM_RSMRST#
SUS_PWR _ACK
PM_PWRBT N#
BATLOW#
PM_RI#
PCH1C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT/GPIO31
E10
BATLOW#/GPIO72
A10
RI#
PANTHER- GP-NF
PANTHER- GP-NF
DMI
DMI
System Power Management
System Power Management
3D3V_AUX_S5
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI
FDI
FDI_RXP7
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
CLKRUN#/GPIO32
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
SLP_SUS#
PMSYNCH
SLP_LAN#/GPIO29
R1925 100K R2J-1-GPR 1925 100KR 2J-1-GP
R1924
R1924
10KR2J-3-GP
10KR2J-3-GP
1 2
3V_5V_POK_#
3 OF 10
FDI_INT
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
12
2N7002KDW -GP
2N7002KDW -GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
6
Q1901
Q1901
2.DPWROK and RSMRST# will rise at the same time (connected on board)
3.SLP_SUS# and SUSACK# are left as ‘no connect’
4.SUSWARN# used as SUSPWRDNACK/GPIO30
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
DSWOD VREN
PCH_DPW ROK
PM_SUS_STAT#
SUS_CLK
PM_SLP_S5#
PM_SLP_SUS#
PM_SLP_LAN#
2345
1
FDI_TXN[7:0] 4
FDI_TXP[7:0] 4
FDI_INT 4
FDI_FSYNC0 4
FDI_FSYNC1 4
FDI_LSYNC0 4
FDI_LSYNC1 4
1 2
R1992 0R0402- PADR1992 0R0402-PAD
1 2
R1911
R1911
10KR2J-3-GP
10KR2J-3-GP
TP1901TP1901
1
R1913
R1913
1 2
0R0402-PAD
0R0402-PAD
TP1902TP1902
1
TP1904TP1904
1
TP1905TP1905
1
PM_RSMRST#
1 2
R1921
R1921
1KR2J-1-GP
1KR2J-1-GP
DY
DY
PM_RSMRST#
RTC_AUX_S5
PCIE_WAKE# 31,65,66
PM_CLKRUN # 27
PCH_SUSC LK_KBC 27
PM_SLP_S4# 27,46,97
PM_SLP_S3# 27,36,37,47
PM_SLP_A# 27,45
H_PM_SYNC 5
RSMRST#_KBC 27
3V_5V_POK 41
DSWODVREN - On Die DSW VR Enable
HIGH Enabled (DEFAULT)
LOW Disabled
DSWOD VREN
PM_CLKRUN #
This signal is used to control power planes to the IntelR ME
sub-system. This signal will be asserted in M-off state. If M3
is not supported then SLP_A# will have the same timings as
SLP_S3#.
For platforms supporting DEEP S4/S5 state, a low on this
signal indicates that PCH is in Deep Sleep state and that
EC/platform logic does not need to keep the Suspend Rails
ON.
If high means EC must keep SUS rails ON.
If DEEP S4/S5 is not supported, then this pin can be left
unconnected.
R1917 330KR2J-L1-G PR1917 330KR2J-L1-GP
1 2
R1918 330KR2J-L1-G P
R1918 330KR2J-L1-G P
1 2
DY
DY
R1919 8K2R2J-3-GPR1919 8K2R2J- 3-GP
1 2
RTC_AUX_S5
3D3V_S0
1 1
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
PCH : DMI/FDI/PM
PCH : DMI/FDI/PM
PCH : DMI/FDI/PM
LA480
LA480
LA480
E
SD
SD
19 103Friday, January 06, 2012
19 103Friday, January 06, 2012
19 103Friday, January 06, 2012
SD
Page 20
A
B
C
D
E
3D3V_S5
RN2003
RN2003
1
SRN2K2J-1-G P
SRN2K2J-1-G P
23
RN2004
RN2004
1
SRN2K2J-1-G P
SRN2K2J-1-G P
23
RN2005
RN2005
SRN2K2J-1-G P
SRN2K2J-1-G P
4
RN2006
RN2006
4
SRN10KJ-5-G P
SRN10KJ-5-G P
R2009
R2009
1KR2J-1-GP
1KR2J-1-GP
PCH_SMBDAT A 14,15,65,66
PCH_SMBCLK 14,15,65,66
12
C2008
C2008
SC15P50V2JN-2- GP
SC15P50V2JN-2- GP
C2007
C2007
SC15P50V2JN-2- GP
SC15P50V2JN-2- GP
12
SBA_Support# 22
CLK_PCIE_NEW _REQ#
PCIE_CLK_LAN_R EQ#
PCIE_CLK_RQ5#
PCIE_CLK_RQ4#
EC_SWI#
PCIE_CLK_RQ0#
PEG_B_CLKRQ#
10KR2J-3-GP
10KR2J-3-GP
PEG_CLKREQ#_ R
10KR2J-3-GP
10KR2J-3-GP
4
4
4
3D3V_S5
12
R2004
R2004
12
R2005
R2005
DY
DY
SMB_DATA
SMB_CLK
XTAL25_IN
XTAL25_OUT
3D3V_S0 3D3V_S0
12
R2012
R2012
10KR2J-3-GP
10KR2J-3-GP
Non-SBA
Non-SBA
12
R2010
R2010
10KR2J-3-GP
10KR2J-3-GP
SBA
SBA
CLK_PCH_48M 82
SMB_CLK
SMB_DATA
SML0_DATA
SML0_CLK
SML1_CLK
SML1_DATA
PCIE_CLK_RQ6#
PCH_GPIO74
DRAMRST_C NTRL_PCH
3D3V_S0
RN2007
RN2007
2 3
1
SRN2K2J-1-G P
SRN2K2J-1-G P
Q2001
Q2001
6
2N7002KDW -GP
2N7002KDW -GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
R2006
R2006
1M1R2J-GP
1M1R2J-GP
1 2
12
12
4
1
2345
X2001
X2001
2 3
XTAL-25MHZ- 155-GP
XTAL-25MHZ- 155-GP
82.30020.D41
82.30020.D41
2nd = 82.30020.G71
2nd = 82.30020.G71
3rd = 82.30020.G61
3rd = 82.30020.G61
R2013
R2013
10KR2J-3-GP
10KR2J-3-GP
UMA
UMA
DGPU_PRSN T#
R2011
R2011
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
3D3V_S5
RN2001
RN2001
1
2
3
4 5
SRN10KJ-6-G P
SRN10KJ-6-G P
RN2002
RN2002
1
2
3
4 5
SRN10KJ-6-G P
SRN10KJ-6-G P
4
4
2 3
1
1
2 3
1 2
41
UMA_DISCRETE#
UMA: 1 1
DIS :0 1
SG(PX) : 0 0
Optimus(Muxless) : 1 0
8
7
6
8
7
6
4 4
3 3
2 2
12
EC2001
EC2001
DY
DY
U16V2KX-3GP
U16V2KX-3GP
SCD1
SCD1
WLAN CLK
LAN CLK
SSID = PCH
If PCIE port 1 is disabled, it will
cause all PCIE port disabled
PCIE_RXN265
PCIE_RXP265
PCIE_TXN265
PCIE_TXP265
PCIE_RXN431
PCIE_RXP431
PCIE_TXN431
PCIE_TXP431
CLK_PCIE_WLA N#65
CLK_PCIE_WLA N65
PCIE_CLK_WL AN_REQ#65
CLK_PCIE_LAN#31
CLK_PCIE_LAN31
PCIE_CLK_LAN_R EQ#31
PCIE_CLK_WL AN_REQ#PCIE_CLK_LAN_R EQ#
12
EC2002
EC2002
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
3D3V_S0
RN2018
RN2018
PCIE_CLK_CR_R EQ#
1
4
PCIE_CLK_WL AN_REQ#
2 3
SRN10KJ-5-G P
SRN10KJ-5-G P
PCIECLKRQ1# and PCIECLKRQ2#
Support S0 power only
C2016 SCD 1U10V2KX-5GPC2016 SCD1U 10V2KX-5GP
1 2
C2015 SCD 1U10V2KX-5GPC2015 SCD1U 10V2KX-5GP
1 2
C2005 SCD 1U10V2KX-5GPC2005 SCD1U 10V2KX-5GP
1 2
C2006 SCD 1U10V2KX-5GPC2006 SCD1U 10V2KX-5GP
1 2
RN2012 SRN0J-6-GPRN2012 SRN0J-6-GP
1
4
2 3
RN2016 SRN 0J-6-GPRN2016 SRN0J -6-GP
1
4
2 3
TP2010TP2010
1
TP2011TP2011
1
PCIE_TXN2_C
PCIE_TXP2_C
PCIE_TXN4_C
PCIE_TXP4_C
PCIE_CLK_RQ0#
CLK_PCH_SR C1_N
CLK_PCH_SR C1_P
PCIE_CLK_WL AN_REQ#
PCIE_CLK_CR_R EQ#
CLK_PCH_SR C3_N
CLK_PCH_SR C3_P
PCIE_CLK_LAN_R EQ#
PCIE_CLK_RQ4#
PCIE_CLK_RQ5#
PEG_B_CLKRQ#
PCIE_CLK_RQ6#
CLK_PCIE_NEW _REQ#
PCIE_CLK_XDP_N
PCIE_CLK_XDP_P
2 OF 10
PCH1B
PCH1B
BG34
PERN1
BJ34
PERP1
AV32
WWAN
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
WLAN
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
Card Reader
PETN3
AU34
PETP3
BF36
PERN4
BE36
LAN
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0#/GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1#/GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2#/GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3#/GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4#/GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5#/GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ#/GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6#/GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7#/GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
PANTHER- GP-NF
PANTHER- GP-NF
– Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3
– Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2
if more than 2 PCI clocks + PCI loopback are routed.
PCI-E*
PCI-E*
CLOCKS
CLOCKS
SMBUSController
SMBUSController
SML1ALERT#/PCHHOT#/GPIO74
Link
Link
FLEX CLOCKS
FLEX CLOCKS
2 OF 10
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
PEG_A_CLKRQ#/GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
EC_SWI#
E12
SMB_CLK
H14
SMB_DATA
C9
DRAMRST_C NTRL_PCH
A12
SML0_CLK
C8
SML0_DATA
G12
PCH_GPIO74
C13
SML1_CLK
E14
SML1_DATA
M16
CL_CLK
M7
CL_DATA
T11
CL_RST#
P10
PEG_CLKREQ#_ R
M10
AB37
AB38
AV22
AU22
CLK_DP_N
AM12
CLK_DP_P
AM13
CLK_BUF_EXP_N
BF18
CLK_BUF_EXP_P
BE18
CLK_BUF_CP YCLK_N
BJ30
CLK_BUF_CP YCLK_P
BG30
CLK_BUF_DO T96_N
G24
CLK_BUF_DO T96_P
E24
CLK_BUF_CK SSCD_N
AK7
CLK_BUF_CK SSCD_P
AK5
CLK_BUF_RE F14
K45
CLK_PCI_FB
H45
XTAL25_IN
V47
XTAL25_OUT
V49
XCLK_RCOMP
Y47
JTAG_TCK
K43
CLK_PCH_48M_L
F47
CLK_27M_VGA_R
H47
DGPU_PRSN T#
K49
1 2
R2003 0R 0402-PADR2003 0R0402- PAD
CLK_PCI_FB 18
+VCCDIFFC LKN
1 2
R2007
R2007
90D9R2F-1-G P
90D9R2F-1-G P
SMB_CLK 80
SMB_DATA 80
DRAMRST_C NTRL_PCH 12,37
SML1_CLK 27
SML1_DATA 27
TP2001TP2001
1
TP2002TP2002
1
TP2003TP2003
1
CLK_PCIE_VGA# 83
CLK_PCIE_VGA 83
serial 0ohm RN?
CLK_EXP_N 5
CLK_EXP_P 5
TP2006TP2006
1
TP2007TP2007
1
RN2008
RN2008
2 3
1
4
SRN10KJ-5-G P
SRN10KJ-5-G P
PL 10K FOR Integrated CLOCK GEN mode.
CLK_BUF_DO T96_N
CLK_BUF_DO T96_P
CLK_BUF_CK SSCD_N
CLK_BUF_CK SSCD_P
CLK_BUF_EXP_N
CLK_BUF_EXP_P
CLK_BUF_RE F14
TP2004TP2004
1
1 2
R2016 22R2J-2-GP
R2016 22R2J-2-GP
TP2005TP2005
1
0511-CHECK
PEG_CLKREQ# 83
DY
DY
0511-CHECK
RN2020 SRN10KJ- 5-GPRN2020 SRN 10KJ-5-GP
1
2 3
RN2021 SRN10KJ- 5-GPRN2021 SRN 10KJ-5-GP
1
2 3
RN2019 SRN10KJ- 5-GPRN2019 SRN 10KJ-5-GP
1
2 3
1 2
R2008
R2008
10KR2J-3-GP
10KR2J-3-GP
12
EC2003
EC2003
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 1
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
PCH : PCIE/SMBUS/CLK
PCH : PCIE/SMBUS/CLK
PCH : PCIE/SMBUS/CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
LA480
LA480
LA480
E
SD
SD
20 103Friday, January 06, 2012
20 103Friday, January 06, 2012
20 103Friday, January 06, 2012
SD
Page 21
A
SSID = PCH
RTC_X1
1 2
R2101 10MR2J-L-GPR2101 10MR2J- L-GP
X2101
X2101
C2101
C2101
4 4
+3VS_+1.5VS_HDA _IO
3D3V_S0
3 3
1 2
SC1
SC1
12
XTAL-32D768KH Z-15-GP
XTAL-32D768KH Z-15-GP
5P50V2JN-2-GP
5P50V2JN-2-GP
82.30001.C21
82.30001.C21
HDA_CODE C_SYNC29
HDA_CODE C_SDOUT29
HDA_CODE C_RST#29
HDA_CODE C_BITCLK29
1 2
DY
DY
R2102 1KR2J-1-GP
R2102 1KR2J-1-GP
NO REBOOT STRAP
1 2
DY
DY
R2106 1KR2J-1-GP
R2106 1KR2J-1-GP
+3VS_+1.5VS_HDA _IO
R2103 1KR2J-1-GPR2103 1KR2J-1- GP
1 2
This signal has a weak internal pull down.
On Die PLL VR is supplied by 1.5V when
sampled high, 1.8 V when sampled low.
Needs to be pulled High for Huron River platform.
co-operate with R2310
PLL ODVR VOLTAGE
HDA_SYNC
This signal has a weak internal pull-down.
On Die PLL VR is supplied by 1.5 V from VccVRM when
sampled high, 1.8 V from VccVRM when sampled low.
2 2
RTC_X2
C2102
C2102
SC1
SC1
12
5P50V2JN-2-GP
5P50V2JN-2-GP
RTCRST_O N27
1 2
DY
DY
R2131 0R2J-2-G P
R2131 0R2J-2-G P
0511-CHECK ADD BLOCK FET IN CODEC PAGE.
R212233R2J-2-GP
R212233R2J-2-GP
12
DY
DY
R212333R2J-2-GP R212333R2J-2- GP
12
R212633R2J-2-GP R212633R2J-2- GP
12
R212933R2J-2-GP R212933R2J-2- GP
12
Flash Descriptor Security Overide
HDA_SDOU T
HDA_SDOUT
HDA_SPKR
Low = 1.8V (Default)
High = 1.5V
No Reboot Strap
HDA_SPKR
HDA_SYNC
HDA_SYNC
HDA_SDOU T
HDA_RST#
HDA_BITCLK
Low = Default
High = Enable
Low = Default
High = No Reboot
CHECK
RTC_AUX_S5
SRN20KJ-GP -U
SRN20KJ-GP -U
1
2 3
RN2104
RN2104
Q2102
Q2102
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
R2130
R2130
0R2J-2-GP
0R2J-2-GP
1 2
DY
DY
4
12
C2103
C2103
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
D
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
1
3
HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to
sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this
signal on the board. Signal may have leakage paths via powered off devices (Audio
Codec) and hence contend with the external pull-up. A blocking FET is
recommended in such a case to isolate HDA_SYNC from the Audio Codec device
until after the Strap sampling is complete.
21
G2101
G2101
12
C2104
C2104
GAP-OPEN
GAP-OPEN
RTC_AUX_S5
2
D2130
D2130
BAS16-6-GP
BAS16-6-GP
83.00016.K11
83.00016.K11
2nd = 83.00016.M11
2nd = 83.00016.M11
3rd = 83.00016.N11
3rd = 83.00016.N11
KBC_RTCR ST# 27
Notes:
ME_UNLOCK (HDA_SDO) connect to EC.
Make sure EC drive this pin "low" all the time.
ME_UNLOCK27
B
INTVRMEN- Integrated SUS
1.05V VRM Enable
High - Enable internal VRs
Low - Enable external VRs
R2104 1M1R2J -GPR2104 1M1R2J -GP
1 2
R2105 330KR 2F-L-GPR2105 330KR2F -L-GP
HDA_SPKR29
HDA_SDIN029
R2107 1KR2J-1-GPR 2107 1KR2J-1-GP
1 2
TP2105TP2105
TP2102TP2102
TP2103TP2103
TP2104TP2104
CHECK
1 2
R2108 33R2J -2-GPR 2108 33R2J-2 -GP
1 2
R2109 0R2J -2-GPR2109 0R2J -2-GP
1 2
R2117 0R2J -2-GP
R2117 0R2J -2-GP
1 2
R2110 33R2J -2-GPR 2110 33R2J-2 -GP
CHECK 4.7K PD
R2134 51R2J-2-GPR2134 51R2J-2-GP
SPI_CLK_R27,60
SPI_CS0#_R27,60
SPI_CS1#_R60
SPI_SI_R2 7,60
SPI_SO_R27,60
PCH_JTAG_T CK_BUF
12
1
1
1
1
SBA
SBA
1 2
RTC_X1
RTC_X2
RTC_RST#
SRTC_RST #
SM_INTRUDER #
PCH_INTVRME N
HDA_BITCLK
HDA_SYNC
HDA_RST#
HDA_SDOU T
PCH_GPIO33
PCH_JTAG_T CK_BUF
PCH_JTAG_T MS
PCH_JTAG_T DI
PCH_JTAG_T DO
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_SI
PCH1A
PCH1A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN#/GPIO33
N32
HDA_DOCK_RST#/GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
PANTHER- GP-NF
PANTHER- GP-NF
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
PCH_SPI_CLK
12
EC2104
EC2104
DY
DY
JTAG
JTAG
RTCIHDA
RTCIHDA
SPI
SPI
DY
DY
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
LPC
LPC
FWH4/LFRAME#
LDRQ1#/GPIO23
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA 6G
SATA 6G
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP/GPIO21
SATA1GP/GPIO19
EC2102
EC2102
1 2
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
1 OF 10
1 OF 10
LDRQ0#
SERIRQ
C
LPC_AD0_TPM
C38
LPC_AD1_TPM
A38
LPC_AD2_TPM
B37
LPC_AD3_TPM
C37
LPC_FRAME#_L
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
SATA_LED#
P3
SATA_DET#0
V14
P1
HDA_CODE C_SDOUT
EC2103
EC2103
DY
DY
1 2
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
0511-CHECK
R2111 22R2F-1-GPR 2111 22R2F-1-GP
R2118 22R2F-1-GPR 2118 22R2F-1-GP
R2119 22R2F-1-GPR 2119 22R2F-1-GP
R2120 22R2F-1-GPR 2120 22R2F-1-GP
R2121 22R2F-1-GPR 2121 22R2F-1-GP
SATA_COMP
SATA3_COMP
RBIAS_SATA3
OD
SPI_CS0#_RHDA_CODE C_BITCLK
EC2101
EC2101
DY
DY
1 2
1 2
1 2
1 2
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
SATA_LED# 68
BBS_BIT0 18
1 2
1 2
1 2
1 2
1 2
APS_LED 68
R2112 37D4R2F-G PR2112 37D4R2F- GP
R2113 49D9R2F-G PR2113 49D9R2F- GP
R2114 750R2F-GPR2114 750R2F-GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
INT_SERIRQ 27
SATA_RXN0 66
SATA_RXP0 66
SATA_TXN0 66
SATA_TXP0 66
SATA_RXN1 56
SATA_RXP1 56
SATA_TXN1 56
SATA_TXP1 56
SATA_RXN4 56
SATA_RXP4 56
SATA_TXN4 56
SATA_TXP4 56
1D05V_VTT
1D05V_VTT
SATA_LED#
SATA_DET#0
S_GPIO22
INT_SERIRQ
LPC_AD[0..3] 27,65,71
LPC_FRAME# 27,6 5,71
RN2103
RN2103
1
2
3
4 5
SRN10KJ-6-G P
SRN10KJ-6-G P
R2125
R2125
8K2R2J-3-GP
8K2R2J-3-GP
1 2
APS_LED
m-SATA
HDD1
mSATA, CRV USE PORT2
ODD
E-SATA
3D3V_S0
8
7
6
D
Check with SW
3D3V_S0
R2128
R2128
10KR2J-3-GP
10KR2J-3-GP
DY
DY
1 2
10K?
E
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
Q2101
R2127
R2127
Q2101
S
12
G
2N7002K-2-GP
2N7002K-2-GP
HDA_SYNC
D
Vth?
5V_S0
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
PCH : HDA/JTAG/SATA
PCH : HDA/JTAG/SATA
PCH : HDA/JTAG/SATA
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
B
C
D
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
LA480
LA480
LA480
E
SD
SD
21 103Friday, January 06, 2012
21 103Friday, January 06, 2012
21 103Friday, January 06, 2012
SD
HDA_CODE C_SYNC HDA_CO DEC_SYNC_L
1 1
R2124
R2124
33R2J-2-GP
33R2J-2-GP
12
1MR2F-GP
1MR2F-GP
A
Page 22
A
R2202
HR:200K (64.20035.6DL)
3D3V_S0
4 4
G-Sensor ST KIXNOK
R2226 DY 10K
CRV:10K (63.10334.1DL)
1 2
R2202 10KR2J-3- GPR2202 10KR2J- 3-GP
3D3V_S0
2 3
1
GPIO27 has a weak[20K] internal pull up.
To enable on-die PLL Voltage regurator,
should not place external pull down.
RN2203
RN2203
SRN10KJ-5-G P
SRN10KJ-5-G P
4
SATA_ODD_PR SNT#
H_A20GATE
H_RCIN#
DGPU_PW ROK92,93
SATA_ODD_PR SNT#56
R2221 10K DY
3D3V_S0
3D3V_S5
PCH_GPIO48
FP_DET#
3 3
2 2
PCH_TEMP_ALE RT#
EC_SMI#
EC_SCI#
DGPU_HPD _INTR#
PCH_GPIO22
PSW_CLR #
MFG_MODE
PCH_GPIO27
RTC_DET#
USB3_PWR _ON
PCH_GPIO15
PLL_ODVR_EN
INTERNAL GFX EXTERNAL GFX
R2205 DY 10K
1 2
R2220 10KR2 J-3-GPR 2220 10KR2J- 3-GP
1 2
DY
DY
R2224 10KR2 J-3-GP
R2224 10KR2 J-3-GP
1 2
R2222 10KR2 J-3-GPR 2222 10KR2J- 3-GP
RN2201
RN2201
1
8
2
7
3
6
4 5
SRN10KJ-6-G P
SRN10KJ-6-G P
R2225
R2225
10KR2J-3-GP
10KR2J-3-GP
1 2
1 2
R2228 10KR 2J-3-GPR 2228 10KR 2J-3-GP
1 2
R2229 10KR 2J-3-GPR 2229 10KR 2J-3-GP
RN2204 SRN10KJ-5-G PR N2204 SRN10KJ-5-GP
1
4
23
1 2
R2201 1KR2J -1-GPR2201 1 KR2J-1-GP
1 2
R2234 10KR2 J-3-GP
R2234 10KR2 J-3-GP
DY
DY
3D3V_S5
R2206 100K DY
3D3V_S0
12
R2205
R2205
10KR2J-3-GP
10KR2J-3-GP
DY
DY
GFX_CRB_D ET
12
R2206
R2206
100KR2J-1-GP
100KR2J-1-GP
R2221
R2221
10KR2J-3-GP
10KR2J-3-GP
1 2
Gsensor_ID
R2226
R2226
10KR2J-3-GP
10KR2J-3-GP
1 2
3D3V_S0
DY
DY
12
B
Note:
For PCH debug with XDP, need to NO STUFF R2218
1 2
R2218 100R2J-2-GPR221 8 100R2J-2-GP
EC_SCI#27
RTC_DET#60
1 2
R2215 0R2J-2-GPR2215 0R2J-2-GP
DGPU_PW ROK_C
TP2206TP2206
TP2212TP2212
TP2207TP2207
TP2208TP2208
TP2209TP2209
EC_SMI#
DGPU_HPD _INTR#
EC_SCI#
ICC_EN#
PCH_GPIO15
PCH_GPIO16
PCH_GPIO22
Gsensor_ID
PCH_GPIO27
PLL_ODVR_EN
PSW_CLR #
FP_DET#
DMI_OVRVLTG
FDI_OVRVLTG
MFG_MODE
GFX_CRB_D ET
PCH_GPIO48
PCH_TEMP_ALE RT#
USB3_PWR _ON
PCH_NCT F_1
1
PCH_NCT F_7
1
PCH_NCT F_2
1
PCH_NCT F_3
1
PCH_NCT F_4
1
1 2
R2216 0R2J-2-GPR2216 0R2J-2-GP
DY
DY
A K
D2201
D2201
CH751H-40-1 -GP
CH751H-40-1 -GP
FP_DET#
12
R2230
R2230
10KR2J-3-GP
10KR2J-3-GP
DY
DY
S_GPIO21
SATA_ODD_PR SNT#
G2201
G2201
GAP-OPEN
GAP-OPEN
21
R2223
R2223
10KR2J-3-GP
10KR2J-3-GP
12
R2232
R2232
10KR2J-3-GP
10KR2J-3-GP
DY
DY
VRAM_SIZE1
VRAM_SIZE2
GPIO0
BD49
BE49
BF49
A42
H36
E38
C10
G2
D40
E16
M5
M3
V13
A44
A45
A46
B47
BD1
BE1
BF1
PCH1F
PCH1F
T7
BMBUSY#/GPIO0
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
C4
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
U2
SATA4GP/GPIO16
TACH0/GPIO17
T5
SCLOCK/GPIO22
E8
GPIO24
GPIO27
P8
GPIO28
K1
STP_PCI#/GPIO34
K4
GPIO35
V8
SATA2GP/GPIO36
SATA3GP/GPIO37
N2
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
V3
SATA5GP/GPIO49/TEMP_ALERT#
D6
GPIO57
A4
VSS_NCTF_1#A4
VSS_NCTF_2#A44
VSS_NCTF_3#A45
VSS_NCTF_4#A46
A5
VSS_NCTF_5#A5
A6
VSS_NCTF_6#A6
B3
VSS_NCTF_7#B3
VSS_NCTF_8#B47
VSS_NCTF_9#BD1
VSS_NCTF_10#BD49
VSS_NCTF_11#BE1
VSS_NCTF_12#BE49
VSS_NCTF_13#BF1
VSS_NCTF_14#BF49
PANTHER- GP-NF
PANTHER- GP-NF
C
6 OF 10
6 OF 10
C40
TACH4/GPIO68
B41
TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71
PROCPWRGD
THRMTRIP#
GPIO
GPIO
CPU/MISC
CPU/MISC
VSS_NCTF_15#BG2
VSS_NCTF_16#BG48
VSS_NCTF_17#BH3
VSS_NCTF_18#BH47
VSS_NCTF_19#BJ4
VSS_NCTF_20#BJ44
VSS_NCTF_21#BJ45
NCTF
NCTF
VSS_NCTF_22#BJ46
VSS_NCTF_23#BJ5
VSS_NCTF_24#BJ6
VSS_NCTF_25#C2
VSS_NCTF_26#C48
VSS_NCTF_27#D1
VSS_NCTF_28#D49
VSS_NCTF_29#E1
VSS_NCTF_30#E49
NCTF TEST PIN:
A4,A44,A45,A46,A5,A6,B3,B47,
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
D49,E1,E49,F1,F49
NCTF TEST PIN:
A4,A44,A45,A46,A5,A6,B3,B47,
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
D49,E1,E49,F1,F49
VSS_NCTF_31#F1
VSS_NCTF_32#F49
A20GATE
RCIN#
INIT3_3V#
DF_TVS
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
VRAM_SIZE1
C41
VRAM_SIZE2
A40
P4
H_PECI_R
AU16
PECI
P5
AY11
PCH_THER MTRIP_R
AY10
INIT3_3V#
NV_CLE
TS_VSS
PCH_NCT F_9
PCH_NCT F_10
PCH_NCT F_5
PCH_NCT F_8
PCH_NCT F_6
1
1 2
R2219
R2219
0R0402-PAD
0R0402-PAD
1
1
1
1
1
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
PLL ON DIE VR ENABLE
NOTE:This signal has a weak internal pull-up 20K
ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT
DISABLED -- LOW (R2212 STUFFED)
PLL_ODVR_EN
1 2
DY
DY
R2212
R2212
1KR2J-1-GP
1KR2J-1-GP
SATA_ODD_PW RGT 56
SBA_Support# 20
H_A20GATE 27
1 2
DY
DY
R2203 0R2J-2-GP
R2203 0R2J-2-GP
H_RCIN# 27
H_CPUPW RGD 5,97
1 2
R2204
R2204
390R2J-1-GP
390R2J-1-GP
TP2201TP2201
TS Signal Disable Guideline:
TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4
should not float on the motherboard. They
should be tied to GND directly.
TP2214TP2214
TP2215TP2215
TP2210TP2210
TP2213TP2213
TP2211TP2211
R2211 BOM CTRL
HR:1K
CRV:DY
D
1D8V_S0
12
R1808
R1808
2K2R2J-2-GP
2K2R2J-2-GP
NV_CLE
1 2
R1809 1KR2J-1-GPR1809 1KR2J-1 -GP
DMI & FDI Termination Voltage
Set to Vss when LOW
NV_CLE
Set to Vcc when HIGH
H_PECI 5,27
H_THERMT RIP# 5,36
3D3V_S0
3D3V_S0
ICC_EN#
12
DY
DY
12
12
DY
DY
12
R2207
R2207
10KR2J-3-GP
10KR2J-3-GP
FDI_OVRVLTG
R2208
R2208
10KR2J-3-GP
10KR2J-3-GP
R2209
R2209
10KR2J-3-GP
10KR2J-3-GP
DMI_OVRVLTG
R2210
R2210
10KR2J-3-GP
10KR2J-3-GP
DY
DY
1 2
R2211
R2211
1KR2J-1-GP
1KR2J-1-GP
FDI TERMINATION VOLTAGE OVERRIDE
GPIO37
(FDI_OVRVLTG)
DMI TERMINATION VOLTAGE OVERRIDE
GPIO36
(DMI_OVRVLTG)
Integrated Clock Enable functionality is achieved
via soft-strap. The default is integrated clock
enable.
Integrated Clock Chip Enable
ICC_EN#
GPIO8 has a weak[20K] internal pull up.
Integrated Clock Enable functionality is achieved
via soft-strap. The default is integrated clock
enable.
H_SNB_IVB# 5
PROCPWRGD (PCH) --> UNCOREPOWRGOOD (CPU)
Indicates that VccSA, VDDQ, VccA (1.8V) and VccIO power
supplies are stable. This signal will be asserted only after
PWROK assertion.
LOW - Tx, Rx terminated to same voltage
(DC Coupling Model DEFAULT)
LOW - Tx, Rx terminated to same voltage
(DC Coupling Model DEFAULT)
HIGH (R2211 DY)- DISABLED [DEFAULT]
LOW (R2211)- ENABLED
E
1 1
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
PCH : GPIO/NTCF/MISC
PCH : GPIO/NTCF/MISC
PCH : GPIO/NTCF/MISC
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
LA480
LA480
LA480
E
SD
SD
22 103Friday, January 06, 2012
22 103Friday, January 06, 2012
22 103Friday, January 06, 2012
SD
Page 23
5
SSID = PCH
4
3
2
1
6A
R2301 0R2J-2-GP
R2301 0R2J-2-GP
7 OF 10
POWER
PCH1G
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
AN19
BJ22
AN16
AN17
AN21
AN26
AN27
AP21
AP23
AP24
AP26
AT24
AN33
AN34
BH29
AP16
BG6
AP17
AU20
PCH1G
VCCCORE1
VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE5
VCCCORE6
VCCCORE7
VCCCORE8
VCCCORE9
VCCCORE10
VCCCORE11
VCCCORE12
VCCCORE13
VCCCORE14
VCCCORE15
VCCCORE16
VCCCORE17
VCCIO28
VCCAPLLEXP
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCC3_3_3
VCCVRM2
VCCAFDIPLL
VCCIO27
VCCDMI2
PANTHER-GP-NF
PANTHER-GP-NF
D D
C C
C2327
C2327
12
C2328
C2328
SC
SC
12
1U6D3V2KX-GP
1U6D3V2KX-GP
C2311
C2311
SC
SC
12
1U6D3V2KX-GP
1U6D3V2KX-GP
1D05V_VTT
SC
SC
1U6D3V2KX-GP
1U6D3V2KX-GP
C2312
C2312
12
SC
SC
1U6D3V2KX-GP
1U6D3V2KX-GP
1D05V_VTT
1.3A(Total current of VCCCORE)
C2302
C2302
C2304
C2304
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
12
1D05V_VTT
1
(10uF x1)
C2308
C2308
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
TP2301TP2301
2.925A(Total current of VCCIO)
C2307
C2307
C2306
C2306
SC
SC
12
12
1U6D3V2KX-GP
1U6D3V2KX-GP
C2303
C2303
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
VCCAPLLEXP
C2309
C2309
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
0.266A (Totally VCC3_3 current)
3D3V_S0
B B
0.159A(Totally current of VCCVRM)
(0.1uF x1)
+VCCAFDI_VRM
TP2302TP2302
1D05V_VTT
0.042A (Totally current of VCCDMI)
VCCVRM(Internal PLL and VRMs):
A.1.5V for Mobile
B.1.8 V for Desktop
12
C2310
C2310
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VCCFDIPLL
1
+1.05VS_VCC_DMI
POWER
VCC CORE
VCC CORE
VCCIO
VCCIO
FDI
FDI
CRTLVDS
CRTLVDS
DMI
DMI
DFT / SPI HVCMOS
DFT / SPI HVCMOS
7 OF 10
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCCTX_LVDS1
VCCTX_LVDS2
VCCTX_LVDS3
VCCTX_LVDS4
VCC3_3_6
VCC3_3_7
VCCVRM3
VCCDMI1
VCCCLKDMI
VCCDFTERM1
VCCDFTERM2
VCCDFTERM3
VCCDFTERM4
VCCSPI
0.001A
+VCCA_DAC_1_2
U48
U47
0.001A
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
0.16A
AT16
0.042A
AT20
AB36
AG16
AG17
AJ16
AJ17
0.02A
V1
+1.05VS_VCC_DMI
C2313
C2313
C2314
C2314
12
12
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
+3VS_VCCA_LVDS
0.06A
+1.8VS_VCCTX_LVDS
C2316
C2316
12
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
0.266A
C2319
C2319
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2320
C2320
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
0.02A
+1.05VS_VCC_DMI_CCI
12
C2321
C2321
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
0.19A
12
C2322
C2322
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VCCSPI_3D3V
12
C2323
C2323
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
(1uFx1)
L2301
L2301
1 2
BLM18PG181SN1D-GP
C2315
C2315
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2317
C2317
12
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
(0.1uFx1)
R2306 0R0402-PADR2306 0R0402-PAD
1 2
BLM18PG181SN1D-GP
C2333
C2333
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
(0.01uF x2)
(22uF x1)
1 2
3D3V_S0
Reserve 0ohm for power measurement?
R2308
R2308
0R0402-PAD
0R0402-PAD
(1uF x1)
R2307
R2307
1 2
0R0402-PAD
0R0402-PAD
R2309
R2309
1 2
0R0402-PAD
0R0402-PAD
1D05V_VTT
(1uFx1)
(10uFx1)
1D8V_S0
Reserve 0ohm for power measurement?
(0.1uFx1)
3D3V_S5
+VCCA_DAC_3V
R2302 0R2J-2-GPR2302 0R2J-2-GP
12
C2326
C2326
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1 2
R2304
R2304
0R0603-PAD
0R0603-PAD
1 2
R2305
R2305
0R0603-PAD
0R0603-PAD
1D5V_S0+VCCAFDI_VRM
1D05V_VTT
DY
DY
1 2
1 2
3D3V_DAC_S0
3D3V_S0
3D3V_S0
1D8V_S0
C2330
C2330
C2329
C2329
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
3.3V CRT LDO
5V_S0 3D3V_DAC_S0
12
DY
DY
C2325
C2325
SC1U10V2KX-1GP
SC1U10V2KX-1GP
74.09091.J3F GMT OBS REASON:G9091
series is going to EOL and no room for further cost reduction.
Pls help to use AME AME8818 , TI TLV702 and GMT G9090 for replacement.
74.09198.G7F OBS
U2302
U2302
DY
DY
1
IN
OUT
2
GND
EN3NC#4
AME8818BEEV330Z-GP
AME8818BEEV330Z-GP
74.08818.B3F
74.08818.B3F
5
4
12
DY
DY
C2324
C2324
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
A A
5
4
Refer to NPCE795 shared SPI flash architecture
3
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
PCH : POWER1
PCH : POWER1
PCH : POWER1
LA480
LA480
LA480
1
SD
SD
23 103Friday, January 06, 2012
23 103Friday, January 06, 2012
23 103Friday, January 06, 2012
SD
Page 24
A
B
C
D
E
(0.1uFx1)
0.001A
1
(1uFx1)
1D05V_VTT
(1uFx1)
3D3V_S5
3D3V_S5
(0.1uFx1)
0.001A
TP2403TP2403
3D3V_S5
(1uFx1)
(0.1uFx2)
12
C2431
C2431
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
(0.1uFx1)
(1uFx1)
TP2407TP2407
1D05V_VTT
3D3V_S5
D2401
D2401
21
CH751H-40PT-GP
CH751H-40PT-GP
83.R0304.A8F
83.R0304.A8F
2nd = 83.R2004.B8F
2nd = 83.R2004.B8F
R2408
R2408
1 2
10R2J-2-GP
10R2J-2-GP
12
C2426
C2426
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3D3V_S0
D2402
D2402
21
CH751H-40PT-GP
CH751H-40PT-GP
83.R0304.A8F
83.R0304.A8F
2nd = 83.R2004.B8F
2nd = 83.R2004.B8F
R2407
R2407
1 2
10R2J-2-GP
10R2J-2-GP
12
C2427
C2427
SC1U10V2KX-1GP
SC1U10V2KX-1GP
3D3V_S0
3D3V_S0
1D05V_VTT
+3VS_+1.5VS_HDA_IO
1 2
R2409
R2409
0R0603-PAD
0R0603-PAD
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH : POWER2
PCH : POWER2
PCH : POWER2
Taipei Hsien 221, Taiwan, R.O.C.
LA480
LA480
LA480
(0.1uFx1)
(1uFx1)
3D3V_S5
E
5V_S5
5V_S0
24 103Friday, January 06, 2012
24 103Friday, January 06, 2012
24 103Friday, January 06, 2012
SD
SD
SD
10 OF 10
POWER
PCH1J
SSID = PCH
3D3V_S5
0.002A
(0.1uFx1)
(10uFx1)
+V3.3S_VCC_CLKF33
12
C2401
C2401
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
+VCCDIFFCLK
12
12
+V1.05S_SSCVCC
12
12
A
(1uFx1)
+1.05VS_VCCA_A_DPL
12
C2443
C2443
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
DY
DY
(1uFx1)
(220uFx1)
+1.05VS_VCCA_B_DPL
12
C2444
C2444
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
DY
DY
(1uFx1)
(220uFx1)
(0.1uFx2)
(4.7uFx1_0603)
12
C2402
C2402
SC1U10V2KX-1GP
SC1U10V2KX-1GP
1D05V_VTT
(1uFx1)
(0.1uFx2)
(1uFx1)
1D05V_M
C2403
C2403
12
12
C2409
C2409
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C2410
C2410
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1D05V_VTT
0R0402-PAD
0R0402-PAD
C2436
C2436
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C2411
C2411
(0.1uFx1)
1 2
R2406
R2406
0R0603-PAD
0R0603-PAD
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
(0.1uFx1)
R2413
R2413
RTC_AUX_S5
(10uFx1)
0.08A
0.08A
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
3D3V_S0
4 4
3 3
1D05V_VTT
2 2
1D05V_VTT
1D05V_VTT
1 1
L2401
L2401
1 2
IND-10UH-218-GP
IND-10UH-218-GP
68.10050.10Y
68.10050.10Y
2nd = 68.1001E.10N
2nd = 68.1001E.10N
L2402
L2402
1 2
IND-10UH-218-GP
IND-10UH-218-GP
68.10050.10Y
68.10050.10Y
2nd = 68.1001E.10N
2nd = 68.1001E.10N
L2403
L2403
1 2
IND-10UH-218-GP
IND-10UH-218-GP
68.10050.10Y
68.10050.10Y
2nd = 68.1001E.10N
2nd = 68.1001E.10N
R2404
R2404
0R0402-PAD
0R0402-PAD
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
R2405
R2405
0R0402-PAD
0R0402-PAD
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C2412
C2412
C2413
C2413
TP2401TP2401
1 2
R2403
R2403
0R0603-PAD
0R0603-PAD
TP2405TP2405
TP2404TP2404
1D05V_VTT
TP2402TP2402
1.01A (Total current of VCCASW)
C2406
C2406
C2437
C2437
12
C2414
C2414
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
+VCCRTCEXT
0.16A (Totally current of VCCVRM
12
+VCCDIFFCLKN
0.055A
12
C2415
C2415
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
(1uFx1)
C2417
C2417
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
C2418
C2418
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2416
C2416
B
1
1
1
1
C2407
C2407
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
+VCCAFDI_VRM
(1uFx1)
12
TP2406TP2406
V_PROC_IO_R
12
C2421
C2421
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VCCACLK
+VCCPDSW
DCPSUSBYP
+V3.3S_VCC_CLKF33
+VCCAPLL_CPY_PCH
+VCCSUS1
C2408
C2408
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
+1.05VS_VCCA_A_DPL
+1.05VS_VCCA_B_DPL
+VCCDIFFCLK
+V1.05S_SSCVCC
(1uFx1)
+VCCSST
DCPSUS
1
0.001A
12
C2419
C2419
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
6uA
AD49
T16
V12
T38
BH23
AL29
AL24
AA19
AA21
AA24
AA26
AA27
AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31
W21
W23
W24
W26
W29
W31
W33
N16
Y49
BD47
BF47
AF17
AF33
AF34
AG34
0.095A
AG33
V16
T17
V19
BJ8
A22
12
C2422
C2422
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PCH1J
VCCACLK
VCCDSW3_3
DCPSUSBYP
VCC3_3_5
VCCAPLLDMI2
VCCIO14
DCPSUS3
VCCASW1
VCCASW2
VCCASW3
VCCASW4
VCCASW5
VCCASW6
VCCASW7
VCCASW8
VCCASW9
VCCASW10
VCCASW11
VCCASW12
VCCASW13
VCCASW14
VCCASW15
VCCASW16
VCCASW17
VCCASW18
VCCASW19
VCCASW20
DCPRTC
VCCVRM4
VCCADPLLA
VCCADPLLB
VCCIO7
VCCDIFFCLKN1
VCCDIFFCLKN2
VCCDIFFCLKN3
VCCSSC
DCPSST
DCPSUS1
DCPSUS2
V_PROC_IO
VCCRTC
PANTHER-GP-NF
PANTHER-GP-NF
POWER
Clock and Miscellaneous
Clock and Miscellaneous
CPURTC
CPURTC
C
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
SATA USB
SATA USB
HDA
HDA
10 OF 10
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCSUS3_3_7
VCCSUS3_3_8
VCCSUS3_3_9
VCCSUS3_3_10
VCCSUS3_3_6
VCCIO34
V5REF_SUS
DCPSUS4
VCCSUS3_3_1
V5REF
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCC3_3_1
VCC3_3_8
VCC3_3_4
VCC3_3_2
VCCIO5
VCCIO12
VCCIO13
VCCIO6
VCCAPLLSATA
VCCVRM1
VCCIO2
VCCIO3
VCCIO4
VCCASW22
VCCASW23
VCCASW21
VCCSUSHDA
N26
P26
P28
T27
T29
0.097A (Totally current of VCCSUS3_3)
T23
T24
V23
V24
P24
T26
M26
AN23
AN24
P34
N20
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
AF14
AK1
AF11
AC16
AC17
AD17
T21
V21
T19
P32
1D05V_VTT
+5VA_PCH_VCC5REFSUS
+VCCA_USBSUS
+5VS_PCH_VCC5REF
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
+V1.05S_VCCAPLL_SATA3
+VCCAFDI_VRM
1D05V_M
+3VS_+1.5VS_HDA_IO
0.01A
C2433
C2433
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3D3V_S5
12
C2428
C2428
C2430
C2430
C2429
C2429
C2432
C2432
(0.1uFx1)
12
C2423
C2423
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2424
C2424
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2425
C2425
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
12
12
12
12
12
C2435
C2435
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
D
Page 25
A
B
C
D
E
SSID = PCH
4 4
3 3
2 2
1 1
A
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
H5
PCH1H
PCH1H
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
PANTHER-GP-NF
PANTHER-GP-NF
B
8 OF 10
8 OF 10
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
C
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
B7
D3
D8
F3
PCH1I
PCH1I
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
PANTHER-GP-NF
PANTHER-GP-NF
9 OF 10
9 OF 10
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS328
VSS329
VSS330
VSS331
VSS333
VSS334
VSS335
VSS337
VSS338
VSS340
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
PCH : VSS
PCH : VSS
PCH : VSS
LA480
LA480
LA480
25 103Friday, January 06, 2012
25 103Friday, January 06, 2012
25 103Friday, January 06, 2012
E
SD
SD
SD
Page 26
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
26 103
26 103
26 103
1
SD
Page 27
5
SSID = KBC
1 2
R2702
R2702
0R0603-PAD
D D
3D3V_AUX_KBC
12
R2707
100KR2F-L1-GP
100KR2F-L1-GP
3D3V_AUX_S5
12
10KR2F-2-GP
10KR2F-2-GP
ADT_TYPE
R2701
R2701
R2776
R2776
100KR2J-1-GP
100KR2J-1-GP
R2707
DY
DY
-MSATA_DET
C2713
C2713
12
12
65W: 1.7V
90W: 3.3V
RC2702
RC2702
SC33P50V2JN-3GP
SC33P50V2JN-3GP
12
DY
DY
SC
SC
D1U10V2KX-5GP
D1U10V2KX-5GP
C C
0R0603-PAD
C2704
C2704
C2706
USB_CHG_EN82
AC_PRESENT19
-MSATA_DET66
RSMRST#_KBC19
PM_SLP_S4#19,46,97
12
GSENSE_X79
GSENSE_Y79
CAMERA_EN49
CAP_LED68
AOAC_EN65
S5_ENABLE36,97
ADP_LED82
LID_CLOSE#49,70
WIFI_RF_EN65
SPI_CS1#_R21,60
SPI_CS0#_R21,60
SPI_CLK_R21,60
SPI_SI_R21,60
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AD_IA40
AD_OFF38
BAT_IN#39
SPI_SO_R21,60
C2706
C2705
C2705
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
DY
DY
33R2J-2-GP R2744
33R2J-2-GP R2744
33R2J-2-GP R2736
33R2J-2-GP R2736
33R2J-2-GP R271933R2J-2-GP R2719
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2701
C2701
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
12
VGA_CURRENT42 NUM_LED68
CPU_CURRENT42
PCIE_WLAN_WAKE#65
BLUETOOTH_EN63,65
S0_PWR_GOOD19
KBC_RTCRST#21
PM_PWRBTN#19,97
USB_PWR_EN_R61,62,82
TP2704TP2704
C2707
C2707
12
Non-SBA
Non-SBA
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2708
C2708
12
C2714
C2714
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
TP2703TP2703
SBA
SBA
C2709
C2709
C2710
C2710
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
1 2
DY
DY
PCB_VER_AD LPC_AD3
ADT_TYPE
MODEL_ID_AD
3G_EN
1
NC_KBC_GPIO51
1
12
EC_SPI_CS#_C
12
EC_SPI_CLK_C
12
EC_SPI_DI_C
R27370R2J-2-GP R27370R2J-2-GP
12
EC_SPI_DO_C
R272233R2J-2-GP R272233R2J-2-GP
12
VBAT
U2701A
U2701A
104
VREF
97
GPIO90 /AD0
98
GPIO91 /AD1
99
GPIO92 /AD2
100
GPIO93 /AD3
108
GPIO5/A D4
96
GPIO4/A D5
95
GPIO3/A D6
94
GPIO7/A D7
101
GPIO94 /DA0
105
GPIO95 /DA1
106
GPIO96 /DA2
107
GPIO97 /DA3
79
GPIO2
6
GPIO24
109
GPIO30 /F_WP#
14
GPIO34 /CIRRXL
15
GPIO36
80
GPIO41 /F_WP#
17
GPIO42 /TCK
20
GPIO43 /TMS
21
GPIO44 /TDI
26
GPIO51 /N2TCK
123
GPIO67 N2TMS
82
GPIO75
83
GPIO76
84
GPIO77
90
F_CS0#
92
F_SCK
86
F_SDI_ F_SDIO 1
87
F_SDI_ F_SDIO 0
91
GPIO81 /F_WP#
117
GPIO20 /TA2/IOX _DIN_DI O
112
GP/I/O84 /IOX_SC LK/XORT R#
110
GPO82/I OX_LDS H/TEST#
NPCE885GA0DX-GP
NPCE885GA0DX-GP
VCC119VCC246VCC376VCC488VCC5
4
3D3V_S0_KBC3D3V_AUX_KBC
C2703
C2703
12
12
12
C2702
C2702
SC2D2U10V3KX-1GP
1 2
R2743 0R0402-PADR2743 0R0402-PAD
1 2
R2739 0R0402-PADR2739 0R0402-PAD
114
VBKUP
LRESET #/GPIOF 7
LCLK/GP IOF5
LFRAME# /GPIOF6
LAD3/GP IOF4
LAD2/GP IOF3
LAD1/GP IOF2
LAD0/GP IOF1
SERIRQ /GPIOF0
GPIO11 /CLKRUN#
GPIO65 /SMI#
ECSCI# /GPIO54
GPIO10 /LPCPD#
GPIO85 /GA20
KBRST# /GPIO86
GPIO52 /PSDAT3 /RDY#
GPIO50 /PSCLK3 /TDO
GPIO27 /PSDAT2
GPIO26 /PSCLK2
GPIO35 /PSDAT1
GPIO37 /PSCLK1
GPIO17 /SCL1/N2T CK
GPIO22 /SDA1/N2T MS
GPIO73 /SCL2
GPIO74 /SDA2
GPIO23 /SCL3
GPIO31 /SDA3
GPIO47 /SCL4
GPIO53 /SDA4
PSL_OUT _GPIO7 1#
PSL_IN2 _GPI6#
PSL_IN1 _GPI70 #
VCORF
103
EC_AGND
1 OF 2
1 OF 2
SC2D2U10V3KX-1GP
DY
DY
7
2
3
1
128
127
126
125
8
9
29
124
121
122
27
25
11
10
71
72
70
69
67
68
119
120
24
28
74
93
73
44
DY
DY
PLT_RST#_EC
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
ECSCI#_KBC
SATA_ODD_DA#_R
PROCHOT_EC
NC_EC_ENABLE
KBC_PWRBTN_EC#
AC_IN_KBC
KBC_VCORF
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
115
102
4
75
VDD
VSBY
AVCC
GND118GND245GND378GND489GND5
GND65AGND
116
R2711
R2711
1 2
0R0402-PAD
0R0402-PAD
RC2701
RC2701
SC33P50V2JN-3GP
SC33P50V2JN-3GP
3D3V_AUX_KBC
RTC_AUX_S5
1 2
R2709
R2709
0R0805-PAD
0R0805-PAD
1
C2711
C2711
SC220P50V2KX-3GP
SC220P50V2KX-3GP
BLON_OUT 49
PM_SLP_A# 19,45
GSENSE_ON# 79
CHG_USB_OC# 82
TPDATA 69
TPCLK 69
BAT_SCL 39,40
BAT_SDA 39,40
SML1_CLK 20
SML1_DATA 20
LAN_PWR_ON 31
CHG_ON# 40
12
3D3V_S0
DY
DY
1 2
1 2
R2735 0R0402-PADR2735 0R0402-PAD
R2730 33R2J-2-GPR2730 33R2J-2-GP
1 2
0R0402-PAD
0R0402-PAD
R2740
R2740
1 2
0R0402-PAD
0R0402-PAD
R2741
R2741
1 2
0R0402-PAD
0R0402-PAD
R2742
R2742
1 2
1 2
R2729 33R2J-2-GPR2729 33R2J-2-GP
1 2
R2738 0R2J-2-GPR2738 0R2J-2-GP
<------ TP
<------ BATTERY / CHARGER
<------PCH / eDP
RTCRST_ON 21
TP2705TP2705
C2712
C2712
SC1U10V2KX-1GP
SC1U10V2KX-1GP
LPC_AD2
LPC_AD1
LPC_AD0LPC_AD0_R
LPC_AD[0..3] 21,65,71
INT_SERIRQ 21
PM_CLKRUN# 19
PANEL_BLEN 49
SATA_ODD_DA# 18,56
H_A20GATE 22
H_RCIN# 22
3
PLT_RST# 5,18,31,36,65,66,71,80,82,83,97
CLK_PCI_KBC 18
LPC_FRAME# 21,65,71
3D3V_AUX_S5
12
KBC_NOVO_BTN#68
PCH_SUSCLK_KBC19
R2775
R2775
100KR2J-1-GP
100KR2J-1-GP
HDD_DET#56
USB_AO_SEL082ADT_TYPE38
PM_SLP_S3#19,36,37,47
DC_BATFULL68
KBC_BEEP29
STOP_CHG#40
AD_DETECT38
CHARGE_LED68
ME_UNLOCK21
AMP_MUTE#29
1D05V_VTT
HDD_DET#
PWRLED68
E51_RxD65
E51_TxD65
ECRST#41
H_PECI5,22
R2721 43R2J-GPR2721 43R2J-GP
1 2
R2720 0R2J-2-GPR2720 0R2J-2-GP
1 2
R2720 and C2716
Need very close to EC
1 2
R2725
R2725
0R0805-PAD
0R0805-PAD
12
3D3V_AUX_S53D3V_AUX_KBC
118
113
111
ECRST#
EC_VTT
C2716
C2716
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2
U2701B
U2701B
31
GPIO56 /TA1
63
GPIO14 /TB1
64
GPIO1/TB 2
32
GPIO15 /A_PWM
GPIO21 /B_PWM
62
GPIO13 /C_PWM
65
GPIO32 /D_PWM
22
GPIO45 /E_PWM
81
GPIO66 /G_PWM
66
GPIO33 /H_PWM
16
GPIO40 /F_PWM
23
GPIO46 /CIRRXM/T RIST#
GPIO87 /CIRRXM/S IN_CR
GP/I/O83/S OUT_CR/T RIST#
77
GPIO0/EX TCLK
30
GPIO55 /CLKOUT/I OX_DIN_ DIO
85
VCC_PO R#
13
PECI
12
VTT
NPCE885GA0DX-GP
NPCE885GA0DX-GP
KBSOUT0/G POB0/JE NK#
KBSOUT1/G PIOB1/T CK
KBSOUT2/G PIOB2/T MS
KBSOUT3/G PIOB3/T DI
KBSOUT4/G POB4/JE N0#
KBSOUT5/G PIOB5/T DO
KBSOUT6/G PIOB6/R DY#
KBSOUT7/G PIOB7
KBSOUT8/G PIOC0
KBSOUT9/G POC1/SD P_VIS #
KBSOUT10 _P80_ CLK/GPI OC2
KBSOUT11 _P80_ DAT/GPI OC3
KBSOUT12 /GPIO64
KBSOUT13 /GPIO63
KBSOUT14 /GPIO62
KBSOUT15 /GPIO61 /XOR_O UT
GPIO60 /KBSOUT16
GPIO57 /KBSOUT17
KBSIN0/GP IOA0/N2T CK
KBSIN1/GP IOA1/N2T MS
KBSIN2/GP IOA2
KBSIN3/GP IOA3
KBSIN4/GP IOA4
KBSIN5/GP IOA5
KBSIN6/GP IOA6
KBSIN7/GP IOA7
1
Code change to Low Active on 8/19
2 OF 2
2 OF 2
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
54
55
56
57
58
59
60
61
KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6PECI
KROW7
KCOL[0..15] 69
TP2707TP2707
1
TP2708TP2708
1
KROW[0..7] 69
3D3V_AUX_KBC
3D3V_AUX_KBC
12
R2717
R2717
10KR2J-3-GP
10KR2J-3-GP
12
R2714
R2714
10KR2J-3-GP
10KR2J-3-GP
12
R2773
R2773
100KR2J-1-GP
100KR2J-1-GP
AC_IN_KBC
12
R2706
R2706
100KR2J-1-GP
100KR2J-1-GP
DY
DY
DY
DY
PM_SLP_A#
KBC_NOVO_BTN#
EC_SPI_DI_C
R2712
R2712
1 2
0R0402-PAD
0R0402-PAD
AC_IN# 40
EC_GPIO47 High Active
12
ECRST#_B
MMBT3906-4-GP
MMBT3906-4-GP
84.03906.F11
84.03906.F11
KBC_PWRBTN#68
ECRST#
E
DY
DY
B
Q2701
Q2701
C
G2701
G2701
GAP-OPEN
GAP-OPEN
Q2702
R2732
R2732
12
Q2702
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.031
84.2N702.031
2ND = 84.2N702.J31
2ND = 84.2N702.J31
H_PROCHOT#_EC
D
1 2
R2733
R2733
0R0402-PAD
0R0402-PAD
H_PROCHOT# 5,42
PURE_HW_SHUTDOWN#28,36,86
R2723
R2723
10KR2J-3-GP
10KR2J-3-GP
2nd = 84.C3906.A11
2nd = 84.C3906.A11
AD_OFF
12
R2770
R2770
1KR2J-1-GP
1KR2J-1-GP
1 2
DY
DY
R2716 0R2J-2-GP
R2716 0R2J-2-GP
D2704
D2704
B B
EC_SCI#22
1
3
2
BAS16-6-GP
BAS16-6-GP
83.00016.K11
83.00016.K11
2ND = 83.00016.F11
2ND = 83.00016.F11
ECSCI#_KBC
PROCHOT_EC
100KR2J-1-GP
100KR2J-1-GP
Reset IC: Prevent BIOS data loss solution
3D3V_AUX_S5
12
C2715
C2715
PURE_HW_SHUTDOWN#
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
3D3V_AUX_S5
12
R2704
R2704
10KR2J-3-GP
10KR2J-3-GP
WHY
KBC_PWRBTN_EC#
12
R2703
R2703
470R2J-2-GP
470R2J-2-GP
12
R2774
R2774
DY
DY
100KR2J-1-GP
100KR2J-1-GP
2 1
12
R2705
R2705
10KR2J-3-GP
10KR2J-3-GP
C2717
C2717
12
SC220P50V2KX-3GP
SC220P50V2KX-3GP
U2702
U2702
1
GND
2
RESET#
G690L293T73UF-GP
G690L293T73UF-GP
74.00690.I7B
74.00690.I7B
3D3V_AUX_S5
DY
DY
3
VCC
EC GPIO standard PH/PL
3D3V_AUX_KBC
RN2701
3D3V_AUX_KBC
SML1_CLK
Q2703
Q2703
SML1_DATA
3D3V_S0
2345
1
6
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
A A
SMBC_THERM
SMBD_THERM
RN48
RN48
SRN10KJ-5-GP
SRN10KJ-5-GP
SMBC_THERM 28,86
SMBD_THERM 28,86
1234
3D3V_S0
MODEL_ID_AD
(Pin100)
UMA
OPTIMUS
12
R2727
R2727
47KR2F-GP
47KR2F-GP
BOM CTRL
BOM CTRL
MODEL_ID_AD
12
R2728
R2728
100KR2F-L1-GP
100KR2F-L1-GP
Pull Down Pull High Voltage
100.0K
33.0K 2.481V
100.0K 47.0K 2.245V
BAT_SCL
BAT_SDA
BAT_IN#
LID_CLOSE#
S5_ENABLE
ECRST#
PCIE_WLAN_WAKE#
E51_RxD
BLUETOOTH_EN
RN2701
SRN4K7J-8-GP
SRN4K7J-8-GP
RN2703
RN2703
SRN100KJ-6-GP
SRN100KJ-6-GP
RN2705
RN2705
SRN10KJ-5-GP
SRN10KJ-5-GP
DY
1 2
R2708
R2708
10KR2J-3-GP
10KR2J-3-GP
R2710
R2710
10KR2J-3-GP
10KR2J-3-GP
1234
1234
1234
12
R271510KR2J-3-GPDYR271510KR2J-3-GP
3D3V_S0
DY
DY
12
DY
DY
3D3V_AUX_KBC
PCB_VER_AD
71.00885.A0G
IC EMB CTRL NPCE885PA0DX LQFP 128P
12
R2724
R2724
64K9R2F-1-GP
64K9R2F-1-GP
BOM CTRL
BOM CTRL
12
R2726
R2726
100KR2F-L1-GP
100KR2F-L1-GP
PCB Version A/D
(Pin98)
SA
SB
SC
-1
Reserved
Reserved
Reserved
Pull-Low Resistor Pull-High Resistor
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
(3D3V_AUX_S5)
10.0K
20.0K
33.0K
47.0K
64.9K
76.8K
100.0K
Voltage
3.0V
2.75V
2.48V
2.24V
2.0V
1.87V
1.65V
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LA480 SD
A1
LA480 SD
A1
LA480 SD
A1
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
27 103Friday, January 06, 2012
27 103Friday, January 06, 2012
27 103Friday, January 06, 2012
Page 28
5
4
3
2
1
SSID = Thermal
Close to SO-DIMM on top side.
SA 0905 change to 390p
3
D D
20110718_Carrey:
C C
B B
For Vendor suggestion, add 10k pull high to 3D3V_S0
3D3V_S0
12
R2812
R2812
10KR2J-3-GP
10KR2J-3-GP
DY
DY
THERM_SCI#
E
C
Q2802
Q2802
MMBT3904WT1G-GP
MMBT3904WT1G-GP
2
E
C
Q2804
Q2804
MMBT3904WT1G-GP
MMBT3904WT1G-GP
between CPU, VGA and DIMM on bottom side
pin6, ALERT# OD
pin7, SYS_SHDN# OD
B
B
H_THERMDA
H_THERMDC
REMOTE2+
REMOTE2-
SMBC_THERM27,86
SMBD_THERM27,86
12
C2803
C2803
SC390P50V2KX-GP
SC390P50V2KX-GP
12
C2804
C2804
SC390P50V2KX-GP
SC390P50V2KX-GP
DY
DY
Thermal sensor
2200p close to smsc2103 chip
3D3V_S0
12
R2805
R2805
68R2-GP
68R2-GP
U2801
2103_VDD
1 2
C2806 SCD1U10V2KX-4GPC2806 SCD1U10V2KX-4GP
THERM_SYS_SHDN# SHDN_SEL
THERM_SCI#
U2801
3
VDD
2
DP1
1
DN1
16
DP2/DN3
15
ND2/DP3
7
SYS_SHDN#
6
ALERT#
9
SMCLK
8
SMDATA
EMC2103-2-AP-GP
EMC2103-2-AP-GP
REMOTE2-
12
C2805
C2805
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
REMOTE2+
GPIO1
GPIO2
TACH
PWM
TRIP_SET
SHDN_SEL
GND
GND
20110718_Carrey:
For Vendor suggestion, add 390pF Cap. as closed to pin B/C and E of Q2803
T8
1
C
B
Q2803
Q2803
E
MMBT3904WT1G-GP
MMBT3904WT1G-GP
CPU backside or inside the socket
CPU TEMP:
H_THERMDA and H_THERMDC routing 10mil trace width
and spacing. Locate Capacity near Thermal diode.
3D3V_S0
12
R2801
R2801
6K8R2J-GP
6K8R2J-GP
SHDN_SEL
SHDN --> 2N3904 ON External diode
2103_4
4
2103_5
5
10
11
TRIP_SET
14
13
TRIP_SET: 649 ohm => 87 dgree C
12
17
TP2802TP2802
1
TP2803TP2803
1
FAN_TACH_1
R2806 649R2F-GPR2806 649R2F-GP
1 2
T8 = 98
RN2801
RN2801
2 3
1
SRN10KJ-5-GP
SRN10KJ-5-GP
D2801
D2801
CH551H-30PT-GP
CH551H-30PT-GP
83.R5003.C8F
83.R5003.C8F
1st = 83.R5003.J8F
1st = 83.R5003.J8F
2ND = 83.R5003.I8F
2ND = 83.R5003.I8F
12
C2808
C2808
SC390P50V2KX-GP
SC390P50V2KX-GP
4
FAN_TACH
21
FAN_PW M
2200p close to smsc2103 chip
4 WIRE PWM Fan Control circuit
FAN_TACH
R2804
R2804
0R0402-PAD
0R0402-PAD
3D3V_S0
C2801
C2801
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
1 2
20100707_EMI
H_THERMDA
12
C2802
C2802
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
H_THERMDC
5V_S0
R2803
R2803
12
10KR2J-3-GP
10KR2J-3-GP
EC2802
EC2802
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
DY
DY
12
R2802
R2802
0R0805-PAD
0R0805-PAD
EC2801
EC2801
12
DY
DY
AFTP2801AFTP2801
AFTP2805AFTP2805
AFTP2806AFTP2806
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
AFTP2807AFTP2807
1
5V_S0_FAN
FAN_PW M_CFAN_PWM
FAN_PW M_C
1
FAN_TACH
1
5V_S0_FAN
1
FAN1
FAN1
6
4
3
2
1
5
ACES-CON4-GP-U1
ACES-CON4-GP-U1
20.F0714.004
20.F0714.004
CHECK PIN DEFINE
3D3V_AUX_S5
3
D2802
D2802
BAT54PT-GP
BAT54PT-GP
83.00054.T81
83.00054.T81
2ND = 83.BAT54.D81
2ND = 83.BAT54.D81
3rd = 83.BAT54.S81
A A
5
PURE_HW _SHUTDOWN#27,36,86
3rd = 83.BAT54.S81
12
R2810
R2810
10KR2J-3-GP
10KR2J-3-GP
DY
DY
1
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
4
DY
DY
C2807
C2807
DY
DY
2
D
84.2N702.031
84.2N702.031
2ND = 84.2N702.J31
2ND = 84.2N702.J31
Q2801
Q2801
2N7002K-2-GP
2N7002K-2-GP
THERM_SYS_SHDN#
S
IMVP_PWRGD_T
G
R2808
R2808
100KR2J-1-GP
100KR2J-1-GP
3D3V_S0 3D3V_S0
12
1 2
3
R2809
R2809
10KR2J-3-GP
10KR2J-3-GP
1 2
R2811
R2811
0R0402-PAD
0R0402-PAD
IMVP_PWRGD 36,42
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
THERMAL SENSOR SMSC EMC2103
THERMAL SENSOR SMSC EMC2103
THERMAL SENSOR SMSC EMC2103
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
LA480
LA480
LA480
Taipei Hsien 221, Taiwan, R.O.C.
28 103
28 103
28 103
1
SD
SD
SD
Page 29
5
4
3
2
1
R2905 75R2J -1-GPR 2905 75R2J-1 -GP
R2906 75R2J -1-GPR 2906 75R2J-1 -GP
AUD_LDO_C AP
28
29
30
31
LDO-CAP
MIC2-VREFO
MIC1-VREFO-L
MIC1-VREFO-R
AUD_DVDD
AUD_SDATA IN
HDA_CODE C_BITCLK_R
12
C2924
C2924
DY
DY
AUD_5V
12
C2905
C2905
SC10U6D3V3MX- GP
SC10U6D3V3MX- GP
AU_GND
1 2
1 2
AUD_MIC1_VREF O_L
25
26
27
VREF
AVSS1
AVDD1
MONO-OUT
SENSE_B
SENSE_A
12
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
HDA_CODE C_RST#
R2917 22R2J-2-GPR2917 22R2J-2- GP
R2919 0R0402-PADR2919 0R0402-PAD
HDA_CODE C_RST#
SC6D8P50V2DN -GP
SC6D8P50V2DN -GP
1 2
R2904 0R0805-PADR2904 0R0805-PAD
AUD_HPOU T_R 82
AUD_HPOU T_L 82
AUD_MIC2_VREF O 58
1 2
C2907
C2907
SC10U6D3V3MX- GP
SC10U6D3V3MX- GP
12
C2909
C2909
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
AU_GND
12
AU_GND
24
LINE1-R
23
LINE1-L
AUD_PORT B_R
22
MIC1-R
AUD_PORT B_L
21
MIC1-L
20
AUD_JDRE F
19
JDREF
18
AUD_PORT F_R
17
MIC2-R
AUD_PORT F_L
16
MIC2-L
15
LINE2-R
14
LINE2-L
13
AUD_SENSE_A
DIGITAL
AUD_PC_BEEP
C2918
C2918
4K7R2J-2-GP
4K7R2J-2-GP
12
12
12
C2925
C2925
DY
DY
5V_S0
AU_GND
close to pin27
12
C2910
C2910
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
AUD_5V
C2913
C2913
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
AU_GND
C2914 SC4D 7U6D3V3KX-G PC2914 SC4D7U6D 3V3KX-GP
C2915 SC4D 7U6D3V3KX-G PC2915 SC4D7U6D 3V3KX-GP
R2909
R2909
20KR2F-L-GP
20KR2F-L-GP
C2916 SC4D 7U6D3V3KX-G P
C2916 SC4D 7U6D3V3KX-G P
B Series-MIC
B Series-MIC
C2917 SC4D 7U6D3V3KX-G P
C2917 SC4D 7U6D3V3KX-G P
B Series-MIC
B Series-MIC
ANALOG
KBC_BEEP_R
12
12
12
R2915
R2915
HDA_CODE C_RST# 21
HDA_CODE C_SYNC 21
HDA_SDIN0 21
HDA_CODE C_BITCLK 21
HDA_CODE C_BITCLK_R
SC6D8P50V2DN -GP
SC6D8P50V2DN -GP
20100705_AUD
AU_GND
EXT MIC
close to pin27
12
C2901
C2901
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
1 2
1 2
1 2
1 2
1 2
1 2
R2912
R2912
39K2R2F-L-GP
39K2R2F-L-GP
C2921
C2921
SC100P50V2JN-3 GP
SC100P50V2JN-3 GP
12
C2926
C2926
DY
DY
R2902 0R5J-5-GPR2902 0R5J -5-GP
1 2
Tied at one point only under the
ALC269 or near the ALC269
AUD_MIC1_VREF O_L
AUD_MIC1_COMB O
AUD_COMBO JACK
Capacitor Working Voltage
ALC269 having AVDD=5V ±5%, so the capacitors must have a 10V working voltage. A working
voltage of 16V is recommended to provide margin for variations in the application
AU_GND
R2914
R2914
12
10KR2J-3-GP
10KR2J-3-GP
R2916
R2916
12
10KR2J-3-GP
10KR2J-3-GP
AUD_MIC1_COMB O
AUD_MIC2 58
HPOUT_JD 82
HDA_SPKR 21
KBC_BEEP 27
EXT MIC
ANALOG MIC
1 2
R2922 2K2R2J-2-GPR2922 2K2R2J-2-G P
1 2
R2923 1KR2J-1-GPR2923 1KR2J-1- GP
AUD_MIC1_COMB O_R
R2925
R2925
22KR2J-GP
22KR2J-GP
1 2
1 2
12
C2928
C2928
SC10U6D3V3MX- GP
SC10U6D3V3MX- GP
R2924
R2924
22KR2J-GP
22KR2J-GP
AUD_MIC1_COMB O_R 82
5V_S0
1 2
R2903 0R0805-PADR2903 0R0805-PAD
D D
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
R2920
R2920
3D3V_S0
12
R2921
R2921
10KR2J-3-GP
10KR2J-3-GP
12
DY
DY
AUD_SPK_L+58
AUD_SPK_L-58
AUD_SPK_R-58
AUD_SPK_R+58
C C
B B
AMP_MUTE#
4K7R2J-2-GP
4K7R2J-2-GP
12
Close to Codec
C2911
C2911
3D3V_S0
AUD_DMIC_DA TA58
AUD_DMIC_CLK58
HDA_CODE C_SDOUT21
C2902
C2902
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
R2913 0R0805-PADR2913 0R0805-PAD
AMP_MUTE#27
C2904
C2904
C2903
C2903
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
AUD_5V
C2912
C2912
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
AU_GND AU_GND AU_G ND
AUD_PVDD
AUD_PVDD
AUD_COMBO JACK
1 2
R2901 0R0402-PADR2901 0R0402 -PAD
R2918 0R0402-PADR2918 0R0402 -PAD
AUD_DMIC_CLK
C2922
C2922
SC33P50V2JN-3G P
SC33P50V2JN-3G P
For EMI issue.
1A
AUD_PVDD
C2927
C2927
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
<<Attention>>
Surges of PVDD >7V duration 0.1ms when
DY
DY
class D amplifier is working may damage
the amplifier, 10uF tantalum capacitors
are required at PVDD1 and PVDD2 to
suppress the surge.
C2906
C2906
SC2D2U10V3KX- 1GP
SC2D2U10V3KX- 1GP
SC2D2U10V3KX- 1GP
SC2D2U10V3KX- 1GP
Close to Codec
AU_GND
C2920
C2920
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
AUD_DMIC_DA TA
12
SC33P50V2JN-3G P
SC33P50V2JN-3G P
12
C2908
C2908
U2901
U2901
37
AVSS2
38
AVDD2
39
PVDD1
40
SPK-L+
41
SPK-L-
42
PVSS1
43
PVSS2
44
SPK-R-
45
SPK-R+
46
PVDD2
47
EAPD/COMBO_JACK
48
SPDIFO
49
GND
AUD_DVDD
AUD_DMIC_CLK _R
C2923
C2923
AU_GND
12
C2919
C2919
12
1 2
1 2
DY
DY
Close to Codec
AUD_PORT A_R
AUD_PORT A_L
AUD_CPVEE
12
AUD_CBP
AUD_CBN
34
32
33
35
36
CBP
CBN
CPVEE
HP-OUT-L
HP-OUT-R
ALC269Q-VC-GR-GP
ALC269Q-VC-GR-GP
DVDD11GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3PD#4SDATA-OUT5BIT-CLK6DVSS27SDATA-IN8DVDD-IO9SYNC10RESET#11PCBEEP
AUD_SDATA_OUT
AUD_SDATA _OUT
12
SC22P50V2JN-4G P
SC22P50V2JN-4G P
DY
DY
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
AUDIO CODEC
AUDIO CODEC
AUDIO CODEC
LA480
LA480
LA480
1
29 103
29 103
29 103
SD
SD
SD
Page 30
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
SD
30 103Friday, January 06, 2012
30 103Friday, January 06, 2012
30 103Friday, January 06, 2012
1
Page 31
5
25MHz XTAL
X3101
X3101
4 1
XTAL-25MHZ- 155-GP
XTAL-25MHZ- 155-GP
82.30020.D41
82.30020.D41
D D
2nd = 82.30020.G71
2nd = 82.30020.G71
3rd = 82.30020.G61
3rd = 82.30020.G61
1 2
R3130 1M1R2J-GPR3130 1M1R2J-GP
12
C3103
C3103
SC12P50V2JN-3G P
SC12P50V2JN-3G P
BOM CTRL
BOM CTRL
C C
LAN_XTAL0
LAN_XTAL1
23
12
C3148
C3148
SC12P50V2JN-3G P
SC12P50V2JN-3G P
71.08111.N03, IC PCIE CTRL RTL8111F-CGT QFN 48P
71.08111.J03, IC PCI-E RTL8111E-VL-CGT QFN 48P
8111F can use G PIO to inform system to do LA N PHY power do wn.
C3103 C3148
VB480
78.15034.1FL
VB580
78.12034.1FL
15pF
12pF
1D05V_LAN_S5
1D05V_LAN_S5
1D05V_LAN_S5
3D3V_LAN_S5
MDI0+59
MDI0-59
MDI1+59
MDI1-59
MDI2+59
MDI2-59
MDI3+59
MDI3-59
12pF
12pF
1 2
R3123 2K49R2F-GPR3123 2K49R2F-GP
1D05V_LAN_S5
PCIE_CLK_LAN_R EQ#20
PCIE_TXP420
PCIE_TXN420
CLK_PCIE_LAN20
CLK_PCIE_LAN#20
PCIE_RXP420
PCIE_RXN420
1D05V_LAN_REG OUT
B B
1 2
L3102
L3102
IND-4D7UH- 192-GP
IND-4D7UH- 192-GP
C3146
C3146
12
1D05V_LAN_S5
C3130
C3130
C3131
C3129
C3129
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C3131
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
12
C3132
C3132
C3133
C3133
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
4
1D05V_LAN_S5 1D 05V_LAN_S5
3D3V_LAN_S5 3D3V_LAN_S5
LAN_RSET
LAN_XTAL0
LAN_XTAL1
40
U3101
U3101
49
GND
1
MDIP0
2
MDIN0
3
AVDD10
4
MDIP1
5
MDIN1
6
AVDD10
7
MDIP2
8
MDIN2
9
AVDD10
10
MDIP3
11
MDIN3
12
AVDD33
RTL8111F-CG T-GP
RTL8111F-CG T-GP
SMB_LAN_DATA
LAN_CLKREQ#
12
R31210R0402-PAD R 31210R0402-PAD
1D05V_LAN_EVD D10
C3145
C3145
SCD1U10V2KX- 4GP
SCD1U10V2KX- 4GP
C3147
C3147
SCD1U10V2KX- 4GP
SCD1U10V2KX- 4GP
C3138
C3138
C3134
C3134
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
1 2
1 2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
47
46
AVDD3348AVDD33
DVDD10
SMBCLK14SMBDATA15CLKREQ#
13
PCIE_RXP4_C
PCIE_RXN4_C
C3139
C3139
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
45
RSET
AVDD10
CKXTAL244CKXTAL1
HSIP17HSIN18REFCLK_P19REFCLK_N20EVDD1021HSOP22HSON
16
1 2
43
42
41
AVDD33
DVDD10
R3131
R3131
0R0603-PAD
0R0603-PAD
37
38
39
LED0
DVDD3
LED1/EESK
REGOUT
VDDREG
GPO/SMBALERT
VDDREG
ENSWREG
EEDI/SDA
LED3/EEDO
EECS/SCL
LANWAKE#
ISOLATE#
GND
24
23
C3128
C3128
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
DVDD10
DVDD33
PERST#
GPO
C3149
C3149
12
3
LAN_ACT_LED # 59
SPEED_100# 59
3D3V_LAN_VDD SREG
1D05V_LAN_REG OUT
36
35
34
LAN_ENSW REG
33
LAN_EEDI
32
LAN_EEDO
31
LAN_EECS
30
29
28
27
RTL_ISOLATE#
26
25
Make sure PCIE_Wake# & PCIE_CLK_LAN_RQ1#connected to 10K
resistor pull high close to PCH side
1D05V_LAN_EVD D10
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
TP3102TP3102
1
1D05V_LAN_S5
PCIE_WAKE# 19,65,66
3D3V_LAN_S5
PLT_RST# 5,18,27,36,65,66,71,80,82,83,97
R3125 For Enab le Switch Regul ator.
R3124 For Disab le Switch Regu lator.
1 2
R3125 0R0402-PADR3125 0R0402-PAD
12
R3124
R3124
0R2J-2-GP
0R2J-2-GP
DY
DY
3D3V_LAN_S5
2
main pwr if have no ASF
RTL_ISOLATE#
High:Link up
Low:Link down
3D3V_S0
12
R3136
R3136
1KR2J-1-GP
1KR2J-1-GP
12
R3119
R3119
15KR2F-GP
15KR2F-GP
GPO
R3120 1KR 2J-1-GPR3120 1KR 2J-1-GP
1 2
LAN_EECS
R3122 10KR 2J-3-GPR 3122 10KR 2J-3-GP
R3126 10KR 2J-3-GPR 3126 10KR 2J-3-GP
R3128 10KR 2J-3-GPR 3128 10KR 2J-3-GP
C3152
C3152
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
Q3104
Q3104
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
1 2
1 2
1 2
12
D
G
1 2
R3135 0R5J-5-G P
R3135 0R5J-5-G P
R3133
R3133
100KR2J-1-GP
100KR2J-1-GP
LAN_PWR _ON_T
S
LAN_EEDI
SMB_LAN_DATA
The SM DATA with 10K ohm pull GND.
3D3V_S5
C3151
C3151
12
2ND = 84.2N702.031
2ND = 84.2N702.031
LAN_PWR _ON27
DY
DY
S
3D3V_LAN_S5
D
Q3103
Q3103
AO3419L-GP
AO3419L-GP
G
84.03419.031
84.03419.031
2nd = 84.00048.031
2nd = 84.00048.031
3rd = 84.03334.031
3rd = 84.03334.031
1
3D3V_LAN_S5
12
C3150
C3150
SC1U10V2KX-1GP
SC1U10V2KX-1GP
L3102 adopt spec.
C3104 change to 4.7uF X5R
type capacitor
C3135
C3135
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
Layout Note: C3135, C3140~C3144 Close to U3101 pin
A A
For VDD33 pins - 12, 27, 39, 42, 47, 48.
5
Layout Note: Close to U3101 pin C3130 ~ C3134,C3138,C3139
For VDD10 pins - 3, 6, 9, 13, 29, 41, 45.
3D3V_LAN_S5
C3142
C3142
C3143
C3140
C3140
C3141
C3141
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
C3143
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
C3144
C3144
12
1 2
R3134
R3134
0R0603-PAD
0R0603-PAD
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
3D3V_LAN_VDD SREG
C3137
C3137
C3136
C3136
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
4
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
Layout Note: C3128&C3149
Close to U3101 pin21
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
<Core Desig n>
<Core Desig n>
Title
Title
Title
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
<Core Desig n>
LAN RTL8111F
LAN RTL8111F
LAN RTL8111F
LA480
LA480
LA480
1
31 103
31 103
31 103
SD
SD
SD
Page 32
5
D D
C C
4
3
2
1
B B
A A
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A1
A1
A1
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
R5U220 (CARD READER)
R5U220 (CARD READER)
R5U220 (CARD READER)
LA480
LA480
LA480
32 103
32 103
32 103
SD
SD
SD
Page 33
A
4 4
3 3
B
C
D
E
BLANK
2 2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
1 1
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
A
B
C
Date: Sheet of
D
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
33 103
33 103
33 103
E
SD
Page 34
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
34 103
34 103
34 103
1
SD
Page 35
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
USB 3.0 Controller
USB 3.0 Controller
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
USB 3.0 Controller
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
35 103
35 103
35 103
1
SD
Page 36
5
4
3
2
1
U3601
U3601
S
S
1
S
S
2
S
S
3
G D
G D
4 5
AO4468-GP
AO4468-GP
84.04468.037
84.04468.037
U3602
U3602
S
S
1
S
S
2
S
S
3
G D
G D
4 5
AO4468-GP
AO4468-GP
84.04468.037
84.04468.037
U3606
U3606
S
S
1
S
S
2
S
S
3
G D
G D
4 5
AO4468-GP
AO4468-GP
84.04468.037
84.04468.037
PS_S3CNTRL 37,97
Q3606
Q3606
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
S
5V_S5
D
D
8
D
D
7
D
D
6
3D3V_S5
D
D
8
D
D
7
D
D
6
1D5V_S3
D
D
8
D
D
7
D
D
6
DY
DY
C3611
C3611
1 2
R3608 100KR2J-1-GPR3608 100KR2J-1-GP
PM_SLP_S3#19,27,37,47
5V_S0
2nd = 84.08882.037
2nd = 84.08882.037
3D3V_S0
RUN_ENABLE_ALL_G
2nd = 84.08882.037
2nd = 84.08882.037
1D5V_S0
12
2nd = 84.08882.037
2nd = 84.08882.037
1D5V_S0
MAX Current 3000 mA
Design Current 2100 mA
Total= 11.39A
D
G
Power Sequence
R3614
CRB : 1K
R3614
1
2
D3603
D3603
BAS16-6-GP
BAS16-6-GP
83.00016.K11
83.00016.K11
2ND = 83.00016.M11
2ND = 83.00016.M11
3rd = 83.00016.N11
3rd = 83.00016.N11
1 2
DY
DY
R3622
R3622
56R2J-4-GP
56R2J-4-GP
2
3
D3601
D3601
BAS16-6-GP
BAS16-6-GP
1
83.00016.K11
83.00016.K11
2ND = 83.00016.M11
2ND = 83.00016.M11
3rd = 83.00016.N11
3rd = 83.00016.N11
1 2
TP3601TP3601
1 2
1KR2F-3-GP
1KR2F-3-GP
B
12
C3602
C3602
1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
R3614
E
Q3601
Q3601
MMBT2222A-3-GP
MMBT2222A-3-GP
C
SYS_PWROK 19
12
C3612
C3612
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
DY
DY
H_THERMTRIP# 5,22
PURE_HW_SHUTDOWN# 27,28,86
S5_ENABLE 27,97
D D
C C
PLT_RST#5,18,27,31,65,66,71,80,82,83,97
3V_5V_EN41
200KR2F-L-GP
200KR2F-L-GP
IMVP_PWRGD28,42
3
PM_SLP_S3#19,27,37,47
1D05V_VTT
1 2
R3616
R3616
12
4K7R2J-2-GP
4K7R2J-2-GP
R3632
R3632
2K2R2J-2-GP
2K2R2J-2-GP
12
R3602
R3602
DY
DY
R3603 2KR2F-3-GPR3603 2KR2F-3-GP
Run Power
DCBATOUT
1 2
R3619 10KR2J-3-GPR3619 10KR2J-3-GP
1 2
R3618 330KR2J-L1-GPR3618 330KR2J-L1-GP
3D3V_AUX_S5
1 2
R3612 10KR2J-3-GPR3612 10KR2J-3-GP
G
PM_SLP_S3#19,27,37,47
S
2nd = 84.2N702.031
2nd = 84.2N702.031
Q3603
Q3603
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
D
2ND = 84.00610.C31
2ND = 84.00610.C31
84.S0610.B31
84.S0610.B31
Q3604
Q3604
Z_12V
S D
NDS0610-NL-GP
NDS0610-NL-GP
12
G
R3620
R3620
10KR2J-3-GP
12
R3617
R3617
100KR2J-1-GP
100KR2J-1-GP
10KR2J-3-GP
Z_12V_D4
Q3605
Q3605
2345
1
6
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
Z_12V_G3
PM_SLP_S3 PM_SLP_S3#
RUN_ENABLE
1 2
C3607 SCD1U50V3KX-GP
C3607 SCD1U50V3KX-GP
1 2
R3626 0R0402-PADR3626 0R0402-PAD
12
12
R3621
R3621
C3606
C3606
SCD22U25V3KX-GP
SCD22U25V3KX-GP
D3602
D3602
330KR2J-L1-GP
330KR2J-L1-GP
MMPZ5239BPT-GP
MMPZ5239BPT-GP
83.9R103.D3F
83.9R103.D3F
A K
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
3D3V_S5
B B
A A
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A1
A1
A1
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Power Plane Enable
Power Plane Enable
Power Plane Enable
LA480
LA480
LA480
SD
SD
SD
36 103Friday, January 06, 2012
36 103Friday, January 06, 2012
36 103Friday, January 06, 2012
Page 37
5
4
3
2
1
Close to CPU
S3 Power Reduction Circuit Processor VREF_DQ Implementation
DEL R3714
R3705 ->100K
1 2
DY
R3707 0R2J-2-GP
R3707 0R2J-2-GP
D D
+V_SM_VREF12
FROM M1/M3
SM_DRAMPWROK must have a maximum of 15ns rise or fall time
over VDDQ * 0.55± 200mV and the edge must be monotonic
C C
PM_DRAM_PWRGD19
B B
1 2
R3715 0R0402-PADR3715 0R0402-PAD
2ND = 84.2N702.031
2ND = 84.2N702.031
PM_DRAM_PWRGD_R
0D75V_EN
C3704
C3704
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
Q3708
Q3708
D
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
3D3V_S5
12
DY
DY
PS_S3CNTRL36,97
S
R3705
R3705
100KR2J-1-GP
100KR2J-1-GP
G
12
R3713
R3713
200R2F-L-GP
200R2F-L-GP
U3701
U3701
1
IN B
VCC
2
IN A
GND3OUT Y
74VHC1G09DFT2G-GP
74VHC1G09DFT2G-GP
OD AND gate required
73.01G09.AAH
73.01G09.AAH
2nd = 73.01G09.0AB
2nd = 73.01G09.0AB
3rd = 73.01G09.BAH
3rd = 73.01G09.BAH
Q3707
Q3707
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
DY C3701
+V_SM_VREF_CNT 9
12
12
C3701
C3701
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
PM_SLP_S3# 19,27,36,47
Close to CPU
S3 Power Reduction Circuit SM_DRAMPWROK
add 0.1uF
5
4
1D5V_S0
12
VDDPWRGOOD_R
12
DY
DY
DY
DY
D
R3708
R3708
200R2F-L-GP
200R2F-L-GP
1 2
R3719
R3719
130R2F-1-GP
130R2F-1-GP
R3722
R3722
39R2J-L-GP
39R2J-L-GP
VDDPWRGOOD_D
DY
DY
12
R3720
R3720
0R2J-2-GP
0R2J-2-GP
VDDPWRGOOD 5
SM_DRAMRST#5
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
PS_S3CNTRL36,97
Close to DIMM
S3 Power Reduction Circuit SM_DRAMPWROK
12
R3703
R3703
22R2J-2-GP
22R2J-2-GP
Q3701_D
D
Q3701
Q3701
2N7002K-2-GP
2N7002K-2-GP
2ND = 84.2N702.031
2ND = 84.2N702.031
S
G
Close to CPU
S3 Power Reduction Circuit SM_DRAMPWROK
DY
DY
1 2
R3709 0R2J-2-GP
R3709 0R2J-2-GP
Q3703
1 2
R3711
R3711
0R0402-PAD
0R0402-PAD
4K99R2F-L-GP
4K99R2F-L-GP
SM_DRAMRST#_R
12
R3701
R3701
DY
DY
Q3703
S
G
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
220R2J-L2-GP
220R2J-L2-GP
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
PS_S3CNTRL
D
12
1D5V_S00D75V_S0
12
R3704
R3704
DY
DY
Q3702_D
D
Q3702
Q3702
DY
DY
S
G
1D5V_S3
12
R3706
R3706
1KR2F-3-GP
1KR2F-3-GP
SM_DRAMRST#_D
12
C3702
C3702
DY
DY
SC100P50V2JN-3GP
SC100P50V2JN-3GP
C3703
C3703
SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
S3 Power Reduction Circuit
SM_DRAMRST#
1 2
R3712
R3712
1KR2F-3-GP
1KR2F-3-GP
DRAMRST_CNTRL_PCH 12,20
DDR3_DRAMRST# 14,15
S3 Power Reduction
5
Q3704
Q3704
5
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
PM_SLP_S3#19,27,36,47
D
0D75V_EN
R3716 22R2J-2-GP
R3716 22R2J-2-GP
1 2
DY
DY
12
R3710
R3710
0R0402-PAD
0R0402-PAD
12
C3705
C3705
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
1.05VTT_PWRGD 45,48
0D75V_EN 46
4
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
ADAPTER
ADAPTER
ADAPTER
LA480
LA480
LA480
SD
SD
37 103Friday, January 06, 2012
37 103Friday, January 06, 2012
37 103Friday, January 06, 2012
1
SD
PS_S3CNTRL36,97
A A
Page 38
5
4
3
2
1
Adaptor in to generate DCBATOUT
D D
ADT_TYPE_R1
12
R3801
R3801
274R2F-GP
274R2F-GP
C C
B B
ADT_TYPE_R
DCIN14
DCIN14
1
2
3
4
5
MLX-CONN10-4-GP
MLX-CONN10-4-GP
21.D0241.205
21.D0241.205
1 2
BAV99-8-GP
BAV99-8-GP
6
7
8
9
10
12
C3801
C3801
SC100P50V2JN-3GP
SC100P50V2JN-3GP
AD_JK_F
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
C3802
C3802
1 2
PR3806
PR3806
0R0402-PAD
0R0402-PAD
PD3802
PD3802
3
12
PC3807
PC3807
SCD1U50V3KX-GP
SCD1U50V3KX-GP
F3801
F3801
1 2
FUSE-7A24V-5-GP
FUSE-7A24V-5-GP
AFTP3805AFTP3805
AFTP3804AFTP3804
AFTP3801AFTP3801
AFTP3802AFTP3802
AFTP3803AFTP3803
AFTP3806AFTP3806
3D3V_AUX_KBC
12
PC3806
PC3806
SCD1U50V3KX-GP
SCD1U50V3KX-GP
DY
DY
PC3803
PC3803
SCD1U50V3KX-GP
SCD1U50V3KX-GP
1
1
AD_JK_F
1
ADT_TYPE_R
1
GND
1
1
ADT_TYPE 27
12
DY
DY
12
12
DY
DY
DY
DY
PR3803
PR3803
200KR2F-L-GP
200KR2F-L-GP
AD_DETECT 27
PR3804
PR3804
34K8R2F-1-GP
34K8R2F-1-GP
AD_JK
PU3801
PU3801
S
D
S
S
S
S
S
G D
G D
AO4407AL-GP
AO4407AL-GP
84.04407.G37
84.04407.G37
D
D
D
D
D
1
PD3801
12
PC3801
PC3801
SCD1U50V3KX-GP
SCD1U50V3KX-GP
DY
DY
PQ3801
PQ3801
C
R1
R1
AD_OFF27
B
R2
R2
PDTC124EU-1-GP
PDTC124EU-1-GP
84.00124.H1K
84.00124.H1K
2ND = 84.00124.X1K
2ND = 84.00124.X1K
E
PD3801
P6SBMJ27APT-GP
P6SBMJ27APT-GP
83.P6SBM.DAG
83.P6SBM.DAG
2ND = 83.P6SMB.JAG
2ND = 83.P6SMB.JAG
3TH = 83.P6SMB.CAG
3TH = 83.P6SMB.CAG
A K
AD_OFF#_1
12
PR3805
PR3805
DY
DY
100KR2J-1-GP
100KR2J-1-GP
PQ3802
PQ3802
R2
R2
B
PDTA124EU-1-GP
PDTA124EU-1-GP
84.00124.K1K
84.00124.K1K
2ND = 84.00024.01K
2ND = 84.00024.01K
E
R1
R1
C
PR3801
PR3801
200KR2F-L-GP
200KR2F-L-GP
12
PC3802
PC3802
SC1U50V5ZY-1-GP
SC1U50V5ZY-1-GP
12
12
AD+_2
PR3802
PR3802
100KR2J-1-GP
100KR2J-1-GP
2
3
4 5
Id= -10A
Qg= -22nC
Rdson=14~22mohm
AD+
8
7
6
DCIN14 for 14" VB480 & VB485
DCIN15 for 15" VB580 & VB585
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
DCIN_JACK
DCIN_JACK
DCIN_JACK
LA480
LA480
LA480
1
38 103Friday, January 06, 2012
38 103Friday, January 06, 2012
38 103Friday, January 06, 2012
SD
SD
SD
Page 39
5
D D
4
3
2
1
BATTERY CONNECTOR
BT+
12
PC3901
PC3901
SCD1U50V3KX-GP
SCD1U50V3KX-GP
C C
B B
BAT_SCL27,40
BAT_SDA27,40
BAT_IN#27
83.5R603.D3F
83.5R603.D3F
2ND = 83.5R603.Q3F
2ND = 83.5R603.Q3F
AFTP3902AFTP3902
AFTP3903AFTP3903
AFTP3904AFTP3904
AFTP3905AFTP3905
AFTP3906AFTP3906
AFTP3907AFTP3907
KA
BATA_SDA_1
1
BATA_SCL_1
1
BT+
1
1
1
BAT_IN#_1
1
12
PC3902
PC3902
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
Swap for V480
RN3901
RN3901
PD3901
PD3901
MMPZ5232BPT-GP-U
MMPZ5232BPT-GP-U
1
2
3
4 5
8
7
6
SRN33J-7-GP
SRN33J-7-GP
PC3905
PC3905
SC470P50V2KX-3GP
SC470P50V2KX-3GP
AFTP3908AFTP3908
12
DY
DY
1
DY
DY
1 2
BAV99-8-GP
BAV99-8-GP
BAT_IN#
3
PL3901
PL3901
12
D3902
D3902
PL3902
PL3902
MLVS0402M04-GP
MLVS0402M04-GP
12
DY
DY
Varistor
MLVS0402M04-GP
MLVS0402M04-GP
DY
DY
PL3903
PL3903
12
PC3904
PC3904
MLVS0402M04-GP
MLVS0402M04-GP
12
BAT_SDA
D3903
D3903
DY
DY
3
1 2
BAV99-8-GP
BAV99-8-GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
AFTP3909AFTP3909
AFTP3910AFTP3910
PC3903
PC3903
12
SC10P50V2JN-4GP
SC10P50V2JN-4GP
BT+
BATA_SCL_1
BATA_SDA_1
BAT_IN#_1
1
1
DY
DY
1 2
BAV99-8-GP
BAV99-8-GP
BAT1
BAT1
1
BAT_VCC
2
BAT_VCC
3
I2C_CLK
4
I2C_DAT
5
TEMP
6
GND
7
GND
8
GND
9
GND
ALP-CON7-33-GP
ALP-CON7-33-GP
20.81720.007
20.81720.007
ME change P/N at SIT
Old 20.81529.007
Nwq 20.81720.007
BAT_SCL
D3901
D3901
3
3D3V_AUX_KBC
DY on LAB stage
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
BATT_CONN
BATT_CONN
BATT_CONN
LA480
LA480
LA480
1
39 103Friday, January 06, 2012
39 103Friday, January 06, 2012
39 103Friday, January 06, 2012
SD
SD
SD
Page 40
5
SSID = Charger
A8( ANNIE/ASTRO)
PR4007,PR4008
D D
AD+ total power
65w
80w
120w
3D3V_AUX_S5
STOP_CHG#27
PR4009
PR4009
10KR2F-2-GP
10KR2F-2-GP
1 2
12.4K
64.12425.6DL
41.2k
60.4k
64.60425.6DL
118k
STOP_CHG#
connects to KBC
PQ4005
PQ4005
2N7002A-7-GP
2N7002A-7-GP
G
S D
C C
CHG_AGND
12
DY
DY
3D3V_AUX_S5
1 2
DY
DY
PR4033 3K3R2J-3-GP
PR4033 3K3R2J-3-GP
1 2
DY
DY
PR4034 3K3R2J-3-GP
PR4034 3K3R2J-3-GP
B B
CHG_AGND
BAT_SCL
BAT_SDA
AC_IN
R2R1
100K
100K
100K90w
100K
BQ24737_CMPOUT
PR4026
PR4026
33KR2F-GP
33KR2F-GP
3D3V_AUX_S5
AD+
PR4010
PR4010
49K9R2F-L-GP
49K9R2F-L-GP
3D3V_AUX_S5
12
PR4030
PR4030
100KR2J-1-GP
100KR2J-1-GP
AD_JK
12
PR4020
PR4020
100KR2J-1-GP
100KR2J-1-GP
PQ4007
PQ4007
2N7002A-7-GP
2N7002A-7-GP
S D
10KR2F-2-GP
10KR2F-2-GP
12
PR4006
PR4006
316KR3F-2-GP
316KR3F-2-GP
12
12
PC4007
PC4007
SCD01U50V2KX- 1GP
SCD01U50V2KX- 1GP
CHG_AGND
3D3V_AUX_S5
G
PR4001
PR4001
AC_IN
12
D
D
8
D
D
7
D
D
6
AO4407AL-GP
AO4407AL-GP
12
84.04407.G37
84.04407.G37
Id= -10A
Qg= -22nC
DC_IN_D
Rdson=14~22mohm
PWR_CH G_IOUT
R1
R2
CHG_AGND
BQ24737_REGN
PR4032
PR4032
100KR2J-1-GP
100KR2J-1-GP
CHG_ON# 27
AC_IN#27
PU4001
PU4001
S
S
S
S
S
S
GD
GD
PQ4001
PQ4001
3 4
2
1
2N7002KDW -GP
2N7002KDW -GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
12
PR4007
PR4007
12K4R2F-GP
12K4R2F-GP
BOM CTRL
BOM CTRL
12
PR4008
PR4008
100KR2F-L1-GP
100KR2F-L1-GP
CHG_AGND
BAT_SCL27,39
BAT_SDA27,39
1
2
3
45
5
6
AC_IN#
AD+_G_2
PR4003
PR4003
49K9R2F-L-GP
49K9R2F-L-GP
1 2
PR4015
PR4015
20R5F-1GP
20R5F-1GP
BQ24737_REGN
12
PR4011
PR4011
100KR2J-1-GP
100KR2J-1-GP
12
PR4014
PR4014
120KR2F-L-GP
120KR2F-L-GP
3D3V_AUX_S5
12
4
12
12
AD+_G_1
3D3MR2J-GP
3D3MR2J-GP
PR4029
PR4029
100KR2J-1-GP
100KR2J-1-GP
PR4002
PR4002
100KR2J-1-GP
100KR2J-1-GP
PR4016
PR4016
12
PR4022
PR4022
10KR2F-2-GP
10KR2F-2-GP
DY
DY
SC1U25V5KX-1GP
SC1U25V5KX-1GP
BQ24737_VCC
PC4001
PC4001
12
CHG_AGND
BQ24737_CMPOUT
12
BQ24737_CMPIN
BQ24737_ILIM
BQ24737_REGN_R
PG4001
PG4001
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
PC4002
PC4002
SCD1U50V3KX- GP
SCD1U50V3KX- GP
CHG_AGND
20
10
11
6
3
4
9
8
5
12
PU4003
PU4003
VCC
ACDET
CMPOUT
CMPIN
SCL
SDA
ILIM
BM#
ACOK#
PR4004
PR4004
1 2
D01R3721F-GP -U
D01R3721F-GP -U
12
PC4003PC4003
PWR_CHG_ACP
2
ACP
BQ24737RGRR -GP
BQ24737RGRR -GP
GND
21
12
12
PWR_CHG_ACN
1
ACN
LODRV
GND
14
DCBATOUTAD+_TO_SYS
PG4002
PG4002
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
12
PC4004
PC4004
SCD1U50V3KX- GP
SCD1U50V3KX- GP
CHG_AGND
BQ24737_BTSTBQ24737_ACDET
17
BTST
16
REGN
BQ24737_HIDRV
18
HIDRV
BQ24737_PHASE
19
PHASE
BQ24737_LODRV
15
BQ24737_SRP
13
SRP
BQ24737_SRN
12
SRN
PWR_CH G_IOUT
7
IOUT
1 2
PR4018
PR4018
0R0402-PAD
0R0402-PAD
CHG_AGND
PR4019
PR4019
1 2
0R2J-2-GP
0R2J-2-GP
3
1st = 83.R2003.P8F
1st = 83.R2003.P8F
2nd = 83.1R003.N8F
2nd = 83.1R003.N8F
3rd = 83.R2003.B8M
3rd = 83.R2003.B8M
CH520S-30PT- GP
CH520S-30PT- GP
12
1 2
PR4013
PR4013
0R0402-PAD
0R0402-PAD
PC4011
PC4011
12
SC220P50V2KX-3GP
SC220P50V2KX-3GP
CHG_AGND
BQ24737_REGN
K A
PD4003
PD4003
PC4017
PC4017
SCD1U50V3KX- GP
SCD1U50V3KX- GP
PR4025
PR4025
10R2F-L-GP
10R2F-L-GP
1 2
1 2
PR4024
PR4024
7D5R2F-GP
7D5R2F-GP
PC4009
PC4009
SC1U10V2KX-1G P
SC1U10V2KX-1G P
1 2
SC470P50V2KX-3GP
SC470P50V2KX-3GP
AD_IA 27
SCD1U25V2KX-GP
SCD1U25V2KX-GP
PC4023
PC4023
12
CHG_AGND
PC4025
PC4025
12
12
PC4016
PC4016
SCD1U50V3KX- GP
SCD1U50V3KX- GP
678
DDD
DDD
SSS
GD
SSS
GD
123
4 5
678
DDD
DDD
SSS
GD
SSS
GD
123
4 5
BQ24737_CSOP_1
BQ24737_CSON_1
DCBATOUT _L
PU4004
PU4004
SIS412DN-T1-GE 3-GP
SIS412DN-T1-GE 3-GP
PL4001
PL4001
1 2
IND-5D6UH- 48-GP-U1
IND-5D6UH- 48-GP-U1
PU4005
PU4005
SIS412DN-T1-GE3-GP
SIS412DN-T1-GE3-GP
12
BT+_R
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4003
PG4003
2
PU4002
PU4002
S
S
1
S
S
2
S
S
3
G D
AD+
PR4005
PR4005
470KR2J-2-GP
470KR2J-2-GP
68.00143.041
68.00143.041
1 2
BLM18PG330SN1D- GP
BLM18PG330SN1D- GP
1 2
BLM18PG330SN1D- GP
BLM18PG330SN1D- GP
68.00143.041
68.00143.041
PC4006
PC4006
SCD1U25V2KX- GP
SCD1U25V2KX- GP
PR4017
PR4017
D01R3721F-GP -U
D01R3721F-GP -U
1 2
1 2
G D
4 5
AO4407AL-GP
AO4407AL-GP
84.04407.G37
84.04407.G37
12
Id= -10A
Qg= -22nC
Rdson=14~22mohm
L4001
L4001
L4002
L4002
Charger Current=1.4~3.6A
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4004
PG4004
PC4019
PC4019
SC10U25V5KX-GP
SC10U25V5KX-GP
1 2
D
D
D
D
D
D
12
PC4020
PC4020
1
BT+
8
7
6
DCBATOUT
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
PC4024
PC4024
PC4005
PC4005
12
12
BT+
SCD1U50V3KX-GP
SCD1U50V3KX-GP
PC4022
12
PC4021
PC4021
SC10U25V5KX-GP
SC10U25V5KX-GP
PC4022
12
12
SC10U25V5KX-GP
SC10U25V5KX-GP
84.2N702.E31
AC_IN#
84.2N702.E31
2ND = 84.2N702.D31
2ND = 84.2N702.D31
PQ4008
PQ4008
G
2N7002A-7-GP
2N7002A-7-GP
S D
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
1
Taipei Hsien 221, Taiwan, R.O.C
40 103Friday, January 06, 2012
40 103Friday, January 06, 2012
40 103Friday, January 06, 2012
Title
Title
Title
<Title>
<Title>
<Title>
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
LA480 SD
A2
LA480 SD
A2
LA480 SD
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Page 41
5
SSID = PWR.Plane.Regulator_5v3p3v
4
3
2
1
D D
Design Current=5.25A
OCP>7.8A
C C
3D3V_S5
B B
PG4108
PG4108
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4109
PG4109
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4110
PG4110
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4111
PG4111
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4112
PG4112
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4113
PG4113
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
12
PC4128
PC4128
SC2200P50V2KX-2G P
SC2200P50V2KX-2G P
DCBATOUT
3D3V_PWR
DCBATOUT _PWR_3D 3V
PG4102
PG4102
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4103
PG4103
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4104
PG4104
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
Cyntec. 2.2uH 7.3*6.6*3
DCR=18~20mohm
Idc=8A, Isat=14A
3D3V_PWR
SCD1
SCD1
PC4119
PC4119
12
U10V2KX-4GP
U10V2KX-4GP
Close to VFB Pin (pin5)
PT4102
PT4102
SE220U6D3VM-30-GP
SE220U6D3VM-30-GP
12
PR4112
PR4112
6K65R2F-GP
6K65R2F-GP
PR4117
PR4117
10KR2F-2-GP
10KR2F-2-GP
PC4109
PC4109
1 2
IND-2D2UH- 46-GP-U
IND-2D2UH- 46-GP-U
68.2R210.20B
68.2R210.20B
PG4116
PG4116
12
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
12
12
PR4113
PR4113
0R2J-2-GP
0R2J-2-GP
DY
DY
12
PC4124
PC4124
SC18P50V2JN-1- GP
SC18P50V2JN-1- GP
DY
DY
12
PC4110
PC4110
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
12
PL4102
PL4102
PR4110
PR4110
2D2R5F-2-G P
2D2R5F-2-G P
PC4121
PC4121
SC330P50V3KX-GP
SC330P50V3KX-GP
PWR_5V_EN 1
PWR_3D3 V_EN2
DCBATOUT _PWR_3D 3V
PC4111
PC4111
SC10U25V5KX-GP
SC10U25V5KX-GP
12
12
D
S G
12
D
DY
DY
PU4105
PU4105
SIS412DN-T1-GE3-GP
SIS412DN-T1-GE3-GP
S
PWR_3D3V_SNUB
12
DY
DY
Id=12A, Qg=3.8nC,
Rdson=24~30 mohm
SSS
SSS
123
SSS
SSS
123
678
DDD
DDD
678
DDD
DDD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
PU4104
PU4104
SIS412DN-T1-GE 3-GP
SIS412DN-T1-GE 3-GP
G D
G D
4 5
G D
G D
4 5
G
3V_5V_POK19
12
PR4121
PR4121
12
PR4127
PR4127
Id=12A, Qg=3.8nC,
Rdson=24~30 mohm
PC4117
PC4117
PWR_3D3 V_VBST2_1
12
1 2
SCD1U50V3KX- GP
SCD1U50V3KX- GP
12
3D3V_S5
12
DY
DY
PR4119
PR4119
100KR2J-1-GP
100KR2J-1-GP
3V_5V_EN 36
PR4108
PR4108
1D5R2F-GP
1D5R2F-GP
PWR_3D3 V_DRVL2
PR4101
PR4101
121KR2F-L-GP
121KR2F-L-GP
PWR_3D3 V_VBST2
PWR_3D3 V_DRVH2
PWR_3D3 V_LL2
PWR_3D3 V_FB2
PWR_3D3 V_EN2
PWR_3D3 V_CS2
TPS51225CRUK R-GP
TPS51225CRUK R-GP
3D3V_PWR _2
PG4101
PG4101
1 2
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
SC1U10V2KX-1G P
SC1U10V2KX-1G P
10
11
9
8
4
6
5
7
PC4127
PC4127
DCBATOUT
PU4103
PU4103
VBST2
DRVH2
SW2
DRVL2
VFB2
EN2
CS2
PGOOD
PWR_5V3D3V_VREG3
VREG3
3
1 2
DY
DY
12
VIN
VBST1
DRVH1
DRVL1
VFB1
VCLK
VREG5
13
1 2
PC4112
PC4112
PC4113
PC4113
SC10U25V5KX-GP
SC10U25V5KX-GP
12
12
17
16
18
SW1
15
14
VO1
2
20
EN1
1
CS1
19
21
GND
5V_PWR_2
PC4126
PC4126
SC1U10V2KX-1G P
SC1U10V2KX-1G P
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
PWR_5V_VB ST1
PWR_5V_D RVH1
PWR_5V_LL1
PWR_5V_D RVL1
PWR_5V_VO 1
PWR_5V_F B1
PWR_5V_EN 1
PWR_5V_C S1
DCBATOUT
3D3V_PWR _2
PR4109
PR4109
1 2
1D5R2F-GP
1D5R2F-GP
12
PR4116
PR4116
0R0603-PAD
0R0603-PAD
DCBATOUT _PWR_5V
PG4133
PG4133
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4131
PG4131
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4130
PG4130
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4132
PG4132
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4128
PG4128
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4129
PG4129
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
Id=12A, Qg=3.8nC,
Rdson=24~30 mohm
SIS412DN-T1-GE 3-GP
SIS412DN-T1-GE 3-GP
SCD1U50V3KX- GP
SCD1U50V3KX- GP
PC4118
PC4118
PWR_5V_VB ST1_1
Id=16A, Qg=7.3nC,
Rdson=13.5~16.5 mohm
PR4102
PR4102
121KR2F-L-GP
121KR2F-L-GP
3D3V_AUX_S5
12
1 2
SIS412DN-T1-GE 3-GP
SIS412DN-T1-GE 3-GP
PU4101
PU4101
PU4102
PU4102
DCBATOUT _PWR_5V
PC4116
SC10U25V5KX-GP
SC10U25V5KX-GP
12
DY
DY
PWR_5V_SNUB
12
DY
DY
PR4111
PR4111
2D2R5F-2-G P
2D2R5F-2-G P
PC4115
PC4115
SC10U25V5KX-GP
SC10U25V5KX-GP
12
12
PL4101
PL4101
1 2
IND-3D3UH- 57GP
IND-3D3UH- 57GP
68.3R310.20A
68.3R310.20A
PC4123
PC4123
SC560P50V-GP
SC560P50V-GP
PR4114
PR4114
0R2J-2-GP
0R2J-2-GP
PC4125
PC4125
PC4116
12
DY
DY
12
DY
DY
SCD1U50V3KX-GP
SCD1U50V3KX-GP
PWR_5V_F B1_RPWR_3D3 V_FB2_R
Design Current=5.25A
OCP>7.8A
Cyntec. 3.3uH 6.5*6.9*3
DCR=28~30mohm
Idc=6A, Isat=13.5A
PG4117
PG4117
PC4120
PC4120
12
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
12
PR4115
PR4115
15KR2F-GP
15KR2F-GP
12
PR4120
PR4120
10KR2F-2-GP
10KR2F-2-GP
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
5V_PWR
PT4101
PT4101
12
PG4119
PG4119
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4120
PG4120
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4121
PG4121
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4122
PG4122
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4114
PG4114
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4115
PG4115
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
5V_S5
12
PC4129
PC4129
SC2200P50V2KX-2G P
SC2200P50V2KX-2G P
5V_PWR
SE330U6D3VM-15-GP
SE330U6D3VM-15-GP
PC4114
PC4114
12
678
DDD
DDD
D
SSS
GD
SSS
GD
123
4 5
G
S
D
678
DDD
DDD
SSS
GD
SSS
GD
123
4 5
SG
SC18P50V2JN-1- GP
SC18P50V2JN-1- GP
Close to VFB Pin (pin2)
PR4122
PR4122
10KR2F-2-GP
10KR2F-2-GP
Vz=5.1V
ECRST# 27
DCBATOUT _UVP_2
DCBATOUTDCBATOUT 3D3V_PWR _2
PD4105
PD4105
MMPZ5231BPT-GP
MMPZ5231BPT-GP
DY
DY
1 2
12
PR4126
PR4126
1KR2F-3-GP
1KR2F-3-GP
DY
DY
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
TPS51123_5V_3D3V
TPS51123_5V_3D3V
TPS51123_5V_3D3V
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
1
SD
SD
SD
103Friday, January 06, 2012
103Friday, January 06, 2012
103Friday, January 06, 2012
41
41
41
12
PU4106
PU4106
DY
DY
DY
2N7002DW- 7F-GP
2N7002DW- 7F-GP
DY
34
2
1
12
PR4125
PR4125
40K2R2F-GP
40K2R2F-GP
DY
DY
12
PR4129
PR4129
750KR2F-GP
750KR2F-GP
DY
A A
DY
DCBATOUT _UVP_1
5
6
5
Page 42
5
4
3
2
1
PC4202
Open
D D
1D05V_VTT
C C
3D3V_S0
12
PR4211
PR4211
10KR2J-3-GP
10KR2J-3-GP
B B
A A
VCORE_AGND
D85V_PW RGD48
IMVP_PWRGD28,36
H_CPU_SVIDCLK8
VR_SVID_ALERT#8
H_CPU_SVIDDAT8
H_PROCHOT#5,27
5
PC4205
PC4205
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
3D3V_S5
PC4202
1 2
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
PR4202
PR4202
1 2
130R2F-1-GP
130R2F-1-GP
PR4203
PR4203
1 2
54D9R2F-L1-GP
54D9R2F-L1-GP
PR4208
PR4208
1 2
24KR2F-GP
24KR2F-GP
12
SCD33U6D3V2KX-1-GP
SCD33U6D3V2KX-1-GP
PC4206
PC4206
PR4234 0R0402-PADPR4234 0R0402-PAD
PR4232 0R0402-PADPR4232 0R0402-PAD
PR4213 0R0402-PADPR4213 0R0402-PAD
PR4233 0R0402-PADPR4233 0R0402-PAD
PR4231 0R0402-PADPR4231 0R0402-PAD
PWR_CPU_CORE_VREF
12
PR4220
PR4220
200KR2F-L-GP
200KR2F-L-GP
12
PR4224
PR4224
30KR2F-GP
30KR2F-GP
VCORE_AGND VCORE_AGND
Close to PWR IC
DY
DY
H_CPU_SVIDDAT
H_CPU_SVIDCLK
1 2
PWR_GFX_CORE_GSCN44
PWR_GFX_CORE_GSCP44
VCCSENSE8
VSSSENSE8
PR4209
PR4209
1 2
90K9R2F-GP
90K9R2F-GP
12
12
12
12
12
VSS_AXG_SENSE9
VCC_AXG_SENSE9
12
PR4221
PR4221
169KR2F-1-GP
169KR2F-1-GP
PWR_CPU_CORE_SLEW APWR_CPU_CORE_GF-IMAX
12
4
PWR_CPU_CORE_VREF
PWR_CPU_CORE_CF-IMAX
PWR_CPU_CORE_VREF
PWR_CPU_CORE_VRON
PWR_CPU_CORE_VCLK
PWR_CPU_CORE_ALERT#
PWR_CPU_CORE_VDIO
PWR_CPU_CORE_VR_HOT#
PWR_CPU_CORE_SLEW A
PWR_GFX_PW RGD
PWR_CPU_CORE_GF-IMAX
PR4225
PR4225
150KR2F-L-GP
150KR2F-L-GP
VCORE_AGND
PC4203
PC4203
1 2
SC33P50V2JN-3GP
SC33P50V2JN-3GP
PR4205
PR4205
1 2
10K7R2F-GP
10K7R2F-GP
1 2
PR4218 5K76R2F-2-GPPR4218 5K76R2F-2-GP
1 2
PC4209 SC33P50V2JN-3GPPC4209 SC33P50V2JN-3GP
1 2
PR4230
PR4230
0R0402-PAD
0R0402-PAD
13
14
15
16
17
18
19
20
21
22
23
24
CF_IMAX
VREF
V3R3
VR_ON
CPGOOD
VCLK
ALERT#
VDIO
VR_HOT#
SLEWA
GPGOOD
GF_IMAX
VCORE_AGND
3D3V_S5
PWR_CPU_CORE_CCOMP
8
9
10
11
12
CVFB
CGFB
CCSN3
CCOMP
PU4201
PU4201
TPS51640ARSLR-GP
TPS51640ARSLR-GP
25
PWR_CPU_CORE_GCOMP
PWR_CPU_CORE_GIMON
PWR_CPU_CORE_CTHERM
PWR_CPU_CORE_CIMON
PWR_CPU_CORE_COCP-I
1
2
4
6
CIMON3CCSP1
CCSP27CCSP3
CCSN15CCSN2
COCP_I
CTHERM
CDH1
CBST1
CSW1
CDL1
V5DRV
PGND
CDL2
CSW2
CBST2
CDH2
VBAT
CPWM336CSKIP#35GPWM34GSKIP#33GTHERM32GOCP_I31GIMON30GCSP29GCSN28GCOMP27GVFB26GGFB
PWR_CPU_CORE_CSKIP#
1 2
DY
DY
PR4222 100KR2F-L1-GP
PR4222 100KR2F-L1-GP
PWR_CPU_CORE_GTHERM
PWR_CPU_CORE_GOCP-I
3
PR4223 20KR2F-L-GP
PR4223 20KR2F-L-GP
1 2
PR4226 15K8R2F-GPPR4226 15K8R2F-GP
1 2
PR4227 NTC-100K-1-GPPR4227 NTC-100K-1-GP
PC4211 SCD1U10V2KX-4GP
PC4211 SCD1U10V2KX-4GP
PR4228
PR4228
1 2
309KR2F-GP
309KR2F-GP
PC4210
PC4210
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
1 2
PR4239
PR4239
0R0402-PAD
0R0402-PAD
PR4204
PR4204
1 2
121KR2F-L-GP
121KR2F-L-GP
PC4204
PC4204
PR4206
PR4206
1 2
NTC-100K-1-GP
NTC-100K-1-GP
PR4207
PR4207
1 2
15K8R2F-GP
15K8R2F-GP
VCORE_AGND
49
GND
48
V5
47
46
45
44
43
42
41
40
39
38
N221068268
37
1 2
DY
DY
PR4217100KR2F-L1-GP
PR4217100KR2F-L1-GP
PWR_CPU_CORE_VREF
1 2
DY
DY
PWR_CPU_CORE_VREF
1 2
DY
DY
1 2
PR4229 75KR2F-GPPR4229 75KR2F-GP
1 2
PWR_CPU_CORE_CCSP2 43
PWR_CPU_CORE_CCSN2 43
PWR_CPU_CORE_CCSN1 43
PWR_CPU_CORE_CCSP1 43
CPU_CURRENT 27
PC4201
PC4201
1 2
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
1 2
PR4201 75KR2F-GPPR4201 75KR2F-GP
1 2
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
PWR_CPU_CORE_VREF
PWR_CPU_CORE_CDH1 43
PWR_CPU_CORE_CBST1 43
PWR_CPU_CORE_CSW 1 43
PWR_CPU_CORE_CDL1 43
PWR_CPU_CORE_CDL2 43
PWR_CPU_CORE_CSW 2 43
PWR_CPU_CORE_CBST2 43
PWR_CPU_CORE_CDH2 43
1 2
PR4216 10KR2F-2-GPPR4216 10KR2F-2-GP
PWR_CPU_CORE_VREF
1 2
PR4219 56KR2F-GPPR4219 56KR2F-GP
VGA_CURRENT 27
VCORE_AGND
DCBATOUT_VCC_CORE
VCORE_AGND
PWR_GFX_GPWM 44
VCORE_AGND
PWR_GFX_GSKIP# 44
VCORE_AGND
2
5V_S5
5V_S5
12
PR4210
PR4210
10R2F-L-GP
10R2F-L-GP
12
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
PC4207
PC4208
PC4208
PC4207
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
TPS51640_CPU_CORE(1/3)
TPS51640_CPU_CORE(1/3)
TPS51640_CPU_CORE(1/3)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
<Doc>
<Doc>
<Doc>
1
42
42
42
SD
SD
SD
103Friday, January 06, 2012
103Friday, January 06, 2012
103Friday, January 06, 2012
SC4D7U10V3KX-GP
SC4D7U10V3KX-GP
12
Page 43
5
4
3
DCBATOUT_VCC_CORE
2
1
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
PC4312
PC4312
12
12
D D
PWR_CPU_CORE_CDH142
PWR_CPU_CORE_CSW 142
PWR_CPU_CORE_CBST1_1
PC4301
PWR_CPU_CORE_CBST142
PWR_CPU_CORE_CDL142
C C
PU4301
PU4302
PU4303
PU4304
B B
A A
Main source 2nd source
84.03606.037
FDMS3606S-GP-U
84.03606.037
FDMS3606S-GP-U
84.03606.037
FDMS3606S-GP-U
84.03606.037
FDMS3606S-GP-U
PWR_CPU_CORE_CDH242
PWR_CPU_CORE_CSW 242
PWR_CPU_CORE_CBST242
PWR_CPU_CORE_CDL242
5
1 2
PR4301
PR4301
0R3J-0-U-GP
0R3J-0-U-GP
PWR_CPU_CORE_CBST2_1
1 2
PR4302
PR4302
0R3J-0-U-GP
0R3J-0-U-GP
PC4301
1 2
SCD1U50V3KX-GP
SCD1U50V3KX-GP
PC4308
PC4308
1 2
SCD1U50V3KX-GP
SCD1U50V3KX-GP
BOM control
PU4304
PU4304
1
9
8
FDMS3600-02-RJK0215-COLAY-GP
FDMS3600-02-RJK0215-COLAY-GP
84.03606.037
84.03606.037
PU4303
PU4303
1
9
8
FDMS3600-02-RJK0215-COLAY-GP
FDMS3600-02-RJK0215-COLAY-GP
DY
DY
4
PU4301
PU4301
2
1
9
8
1
9
8
2
3
4
10
7
6
5
2
3
4
10
7
6
5
3
4
10
7
6
5
FDMS3600-02-RJK0215-COLAY-GP
FDMS3600-02-RJK0215-COLAY-GP
DY
DY
PU4302
PU4302
2
3
4
10
7
6
5
FDMS3600-02-RJK0215-COLAY-GP
FDMS3600-02-RJK0215-COLAY-GP
84.03606.037
84.03606.037
12
DCBATOUT_VCC_CORE
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
PC4310
PC4310
12
12
28KR2F-GP
28KR2F-GP
SC10U25V5KX-GP
PC4306
PC4306
12
PL4302
PL4302
1 2
L-D36UH-1-GP
L-D36UH-1-GP
PR4308
PR4308
18KR2F-GP
18KR2F-GP
PR4309
PR4309
1 2
121KR2F-L-GP
121KR2F-L-GP
PR4310
PR4310
1 2
1 2
NTC-100K-1-GP
NTC-100K-1-GP
PR4303
PR4303
1st = 69.60011.071
1st = 69.60011.071
1 2
PC4314 SCD027U25V2KX-GPPC4314 SCD027U25V2KX-GP
3
1 2
PR4236
PR4236
18KR2F-GP
18KR2F-GP
1 2
PR4237
PR4237
1 2
28KR2F-GP
28KR2F-GP
PC4216 SCD027U25V2KX-GPPC4216 SCD027U25V2KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
PC4307
PC4307
12
PC4302
PC4302
PC4303
PC4303
12
PL4301
PL4301
L-D36UH-1-GP
L-D36UH-1-GP
PR4238
PR4238
121KR2F-L-GP
121KR2F-L-GP
PR4235
PR4235
1 2
NTC-100K-1-GP
NTC-100K-1-GP
1st = 69.60011.071
1st = 69.60011.071
1 2
SC10U25V5KX-GP
SC10U25V5KX-GP
PC4305
PC4305
12
DY
DY
PG4302
PG4302
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 2
SC10U25V5KX-GP
SC10U25V5KX-GP
12
DY
DY
12
PC4316
PC4316
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
PC4304
PC4304
12
PC4315
PC4315
SCD1U50V3KX-GP
SCD1U50V3KX-GP
Design current: 42.4A
PG4301
PG4301
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 2
12
PWR_CPU_CORE_CCSN2 42
PWR_CPU_CORE_CCSP2 42
PT4304
PT4304
12
PT4302
PT4302
PWR_CPU_CORE_CCSN1 42
PWR_CPU_CORE_CCSP1 42
VCC_CORE
12
PT4301
PT4301
ST330U2VDM-4-GP
ST330U2VDM-4-GP
ST330U2VDM-4-GP
ST330U2VDM-4-GP
2
VCC_CORE
12
ST330U2VDM-4-GP
ST330U2VDM-4-GP
12
PT4305
PT4305
PT4303
PT4303
ST330U2VDM-4-GP
ST330U2VDM-4-GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
DCBATOUT DCBATOUT_VCC_CORE
PG4304
PG4304
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4305
PG4305
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4306
PG4306
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4307
PG4307
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4308
PG4308
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4309
PG4309
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
12
PT4306
PT4306
SE100U25VM-10GP
SE100U25VM-10GP
ST330U2VDM-4-GP
ST330U2VDM-4-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
TPS51640_CPU_CORE(2/3)
TPS51640_CPU_CORE(2/3)
TPS51640_CPU_CORE(2/3)
<Doc>
<Doc>
<Doc>
1
SD
SD
SD
103Friday, January 06, 2012
103Friday, January 06, 2012
43
43
43
103Friday, January 06, 2012
Page 44
5
4
3
2
1
Main source
PU4402
D D
DCBATOUT DCBATOUT_VCC_GFXCORE
PG4401
PG4401
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4402
PG4402
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4403
PG4403
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4404
PG4404
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PWR_GFX_CORE_DRVH
C C
PWR_GFX_CORE_SW
PWR_GFX_CORE_BST
PWR_GFX_CORE_DRVL
1 2
PR4401 0R3J-0-U-GPPR4401 0R3J-0-U-GP
PU4403
PWR_GFX_CBST1_1
84.07608.037
FDMS7608S-GP
84.07608.037
FDMS7608S-GP
1 2
PC4401 SC1U25V3KX-1-GPPC4401 SC1U25V3KX-1-GP
2nd source
BOM control
PU4402
PU4402
1
9
8
FDMS3600-02-RJK0215-COLAY-GP
FDMS3600-02-RJK0215-COLAY-GP
84.07608.037
84.07608.037
PU4403
PU4403
1
9
8
FDMS3600-02-RJK0215-COLAY-GP
FDMS3600-02-RJK0215-COLAY-GP
84.07608.037
84.07608.037
DCBATOUT_VCC_GFXCORE
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
PC4409
PC4409
12
2
3
4
10
7
6
5
2
3
4
10
7
6
5
12
28KR2F-GP
28KR2F-GP
PC4402
PC4402
12
PL4401
PL4401
1 2
L-D36UH-1-GP
L-D36UH-1-GP
PR4410
PR4410
18KR2F-GP
18KR2F-GP
PR4407
PR4407
1 2
121KR2F-L-GP
121KR2F-L-GP
PR4405
PR4405
1 2
1st = 69.60011.071
1st = 69.60011.071
SC10U25V5KX-GP
PC4403
PC4403
12
1 2
NTC-100K-1-GP
NTC-100K-1-GP
PR4409
PR4409
SC10U25V5KX-GP
SC10U25V5KX-GP
PC4404
PC4404
12
1 2
SC10U25V5KX-GP
SC10U25V5KX-GP
12
PC4410
PC4410
SCD1U50V3KX-GP
SCD1U50V3KX-GP
PG4303
PG4303
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
Design current: 22A
VCC_GFXCORE
12
12
PT4401
PT4401
ST330U2VDM-4-GP
ST330U2VDM-4-GP
PT4402
PT4402
12
PT4403
PT4403
ST330U2VDM-4-GP
ST330U2VDM-4-GP
ST330U2VDM-4-GP
ST330U2VDM-4-GP
B B
PU4401
PU4401
PWR_GFX_CORE_BST
PWR_GFX_GSKIP#42
PWR_GFX_GPWM42
A A
5
1
BST
2
SKIP#
3
PWM
4
GND
TPS51601DRBR-GP
TPS51601DRBR-GP
GND
DRVH
VDD
DRVL
9
8
7
SW
6
5
PWR_GFX_CORE_DRVH
PWR_GFX_CORE_SW
PWR_GFX_CORE_DRVL
4
5V_S5
12
PC4407
PC4407
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
3
1 2
PC4408 SCD022U25V2KX-GPPC4408 SCD022U25V2KX-GP
PWR_GFX_CORE_GSCN 42
PWR_GFX_CORE_GSCP 42
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
TPS51640_CPU_CORE(3/3)
TPS51640_CPU_CORE(3/3)
TPS51640_CPU_CORE(3/3)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
<Doc>
<Doc>
<Doc>
1
44
44
44
SD
SD
SD
103Friday, January 06, 2012
103Friday, January 06, 2012
103Friday, January 06, 2012
Page 45
5
TPS51219 for 1D05V
4
3
2
1
12
DY
DY
PC4512
PC4512
SCD01U50V2KX- 1GP
SCD01U50V2KX- 1GP
1 2
12
PWR_VC CP_VSNS
TPS51219_GSNS_M
1 2
PR4524
PR4524
2D2R2J-GP
2D2R2J-GP
SBA
SBA
PC4524
PC4524
SC22P50V2GN-G P
SC22P50V2GN-G P
PWR_VC CP_EN
PR4505
PR4505
1 2
1KR2F-3-GP
1KR2F-3-GP
PWR_VCCP_MODE
13
16
14
15
17
PU4501
PU4501
EN
BST
GND
MODE
PGOOD
1
VREF
2
REFIN
3
GSNS
4
VSNS
TPS51219RTER -GP
TPS51219RTER -GP
PWR_VC CP_COMP
PC4519
PC4519
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
DY
DY
PR4519 0R0402- PADPR4519 0R0402-PAD
PR4522 0R0402- PADPR4522 0R0402-PAD
Differential Sense feedback
Resistor need close to controller
12
SBA
SBA
PC4523
PC4523
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
MPWROK19
COMP5TRIP6GND7PGND
8
PWR_VCCP_TRIP
12
PR4520
PR4520
64K9R2F-1-GP
64K9R2F-1-GP
1 2
1 2
PWR_1D0 5V_PVDD
PWR_1D0 5V_SVIN
3D3V_S5
12
12
SW
11
DH
10
DL
9
V5
PWR_1D0 5V_EN
PR4525
PR4525
100KR2F-L1-GP
100KR2F-L1-GP
SBA
SBA
1 2
PR4508 2D2R3J -2-GPPR4508 2D2R3J-2- GP
PWR_VC CP_SW
PWR_VC CP_DRVH
PWR_VC CP_DRVL
PWR_VCCP_V5FILT
SC2D2U6D3V 2MX-GP
SC2D2U6D3V 2MX-GP
Parallel
10
9
8
5
4
PWR_VC CP_LL_1PWR_VC CP_VBST
5V_S5
PC4518
PC4518
PU4504
PU4504
PVIN
LX#1
PVIN
LX#2
SVIN
LX#3
NC#7
EN
FB
PGOOD
GND
RT8068AZQW ID-GP-U
RT8068AZQW ID-GP-U
SBA
SBA
84.00172.037
84.00172.037
Id=20A, Qg=9.8~15nC,
Rdson=10.3~12.4 mohm
PC4513
PC4513
1 2
SCD1U50V3KX- GP
SCD1U50V3KX- GP
12
PR4514
PR4514
3D3R2F-GP
3D3R2F-GP
12
VCCIO_SENSE 8
VSSIO_SENSE 8
1
PWR_1D0 5V_PHASE
2
3
7
6
11
PWR_DC BATOUT_VC CP
678
DDD
DDD
PU4502
PU4502
SIR172DP-T1-GE3-GP
SIR172DP-T1-GE3-GP
GD
GD
4 5
G S
678
DDD
DDD
G
G
4 5
PL4502
PL4502
1 2
IND-2D2UH- 161-GP-U
IND-2D2UH- 161-GP-U
SBA
SBA
12
PC4516
PC4516
D
SSS
SSS
123
D
D
D
PU4503
PU4503
SSS
SSS
123
SG
PWR_1D0 5V_FB
12
PC4517
PC4517
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
84.00460.037
84.00460.037
Id=40A, Qg=16.8~25.5nC,
Rdson=4.9~6.1 mohm
1 2
1D05V_FB_GAP
12
R1
PR4526
PR4526
15KR2F-GP
15KR2F-GP
SBA
SBA
12
PR4527
PR4527
R2
20KR2F-L-GP
20KR2F-L-GP
SBA
SBA
12
PC4520
PC4520
1 2
0.68uH 7.3*6.6*3
DCR=5~5.5mohm
Idc=15.5A, Isat=25A
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4547
PG4547
12
Vo=0.6*(1+(R1/R2))
Vout
12
PC4510
PC4510
SC2
SC2
200P50V2KX-2GP
200P50V2KX-2GP
PR4510
PR4510
0R0402-PAD
0R0402-PAD
1 2
PC4514
PC4514
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
PWR_VC CP_VREF
3D3V_S5
12
PR4511
PR4511
100KR2F-L1-GP
100KR2F-L1-GP
H_SNB_IVB#_PW RCTRL
PR4513
PR4513
0R2J-2-GP
0R2J-2-GP
DY
DY
1 2
PR4515
PR4515
0R0402-PAD
0R0402-PAD
RUNPW ROK46,47
D D
3D3V_S0
1.05VTT_PW RGD37,48
PC4515
PC4515
SCD1U10V2KX- 4GP
SCD1U10V2KX- 4GP
C C
PR4509 10KR2J-3-GPPR4509 10KR2J-3-G P
PR4502 0R0402-PADPR4502 0R0402-PAD
12
12
PR4518
PR4518
8K25R2F-1-GP
8K25R2F-1-GP
DY
DY
12
DY
DY
1 2
1 2
EC_SC_1003
PR4521
PR4521
KR2F-2-GP
KR2F-2-GP
10
10
REFIN
1.05VH
L
3D3V_S5
B B
PM_SLP_A#19,27
1V
PG4540
PG4540
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4541
PG4541
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
12
PC4521
SBA
SBA
PR4523 0 R0402-PADPR4523 0R0402-PAD
PC4521
1 2
12
PC4522
PC4522
SC1
SC1
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
0U6D3V3MX-GP
0U6D3V3MX-GP
DY
DY
12
DY
DY
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
SCD1U50V3KX-GP
SCD1U50V3KX-GP
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PL4501
PL4501
COIL-D68UH- 5-GP
COIL-D68UH- 5-GP
1D05V_PWR _M
SBA
SBA
PC4525
PC4525
SC100P50V2JN-L-GP
SC100P50V2JN-L-GP
PG4519
PG4519
PG4516
PG4516
PG4517
PG4517
PG4518
PG4518
PWR_DC BATOUT_VC CPDC BATOUT
Design Current = 11.69A
OCP> 17.9A
1D05V_PWR
PT4501
PT4501
PT4502
PT4502
SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
12
12
77.C3371.051
330uF, 2.5V,
ESR=9mΩ, Iripple=3.726A
PG4543
PG4543
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4544
PG4544
SBA
SBA
12
12
PC4527
PC4527
PC4526
PC4526
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SBA
SBA
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
1D05V_PWR 1D05V_VT T
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
1D05V_M
1 2
R4501 0R 5J-5-GP
R4501 0R 5J-5-GP
Non-SBA
Non-SBA
PG4520
PG4520
1 2
PG4521
PG4521
1 2
PG4522
PG4522
1 2
PG4523
PG4523
1 2
PG4524
PG4524
1 2
PG4525
PG4525
1 2
PG4526
PG4526
1 2
PG4527
PG4527
1 2
PG4528
PG4528
1 2
PG4529
PG4529
1 2
PG4530
PG4530
1 2
PG4531
PG4531
1 2
PG4532
PG4532
1 2
PG4533
PG4533
1 2
PG4534
PG4534
1 2
1D05V_VTT
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
TPS51211_1D05V
TPS51211_1D05V
TPS51211_1D05V
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
1
SD
SD
SD
103Friday, January 06, 2012
103Friday, January 06, 2012
103Friday, January 06, 2012
45
45
45
Page 46
A
B
C
D
E
SSID = PWR.Plane.Regulator_1p5v0p75v
DCBATOUT_1D5VDCBATOUT 1D5V_S31D5V_PWR
PG4601
PG4601
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4602
PG4602
1 2
GAP-CLOSE-PWR-3-GP
1D5V_PWR
PT4602
PT4602
SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
GAP-CLOSE-PWR-3-GP
PG4603
PG4603
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4604
PG4604
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
12
DY
DY
EC4601
EC4601
SCD1U50V3KX-GP
SCD1U50V3KX-GP
PR4601
4 4
DCBATOUT_1D5V
RUNPWROK45,47
PR4606
PR4606
3 3
0D75V_EN37
2 2
PG4624
PG4624
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4625
PG4625
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 2
1D5V_PWR
12
PC4623
PC4623
+0D75V_DDR_P0D75V_S0
PWR_1D5V_TON
620KR3J-GP
620KR3J-GP
PWR_1D5V_EN
PC4610
PC4610
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
+0D75V_DDR_P
12
PC4618
PC4618
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
3D3V_S0
12
12
12
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
PR4604
PR4604
10KR2F-2-GP
10KR2F-2-GP
DY
DY
DY
DY
PC4617
PC4617
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
PWR_1D5V_VCC5
12
PC4601
PC4601
PWR_1D5V_CS
10
PGOOD
9
TON
8
S5
7
S3
19
VLDOIN
1
VTTGND
20
VTT
2
VTTSNS
PR4602
PR4602
9K76R2F-1-GP
9K76R2F-1-GP
PWR_1D5V_PVCC5
1 2
13
12
11
PU4601
PU4601
CS
VDD
VDDP
BOOT
UGATE
PHASE
LGATE
PGND
VDDQ
FB
VTTREF
GND
GND
21
3
RT8207MZQW-GP-U
RT8207MZQW-GP-U
4
1 2
PR4610
PR4610
0R0402-PAD
0R0402-PAD
PWR_1D5V_VTTREF
12
PC4619
PC4619
SCD033U16V2KX-GP
SCD033U16V2KX-GP
PR4601
12
PR4603
PR4603
0R0603-PAD
0R0603-PAD
DDR_VREF_S3
5V_S5
5V_S5
1 2
PR4605 2D2R3J-2-GPPR4605 2D2R3J-2-GP
12
PR4608
PR4608
30K9R2F-GP
30K9R2F-GP
R1
12
PR4609
PR4609
R2
30KR2F-GP
30KR2F-GP
5D1R2F-GP
5D1R2F-GP
12
PC4602
PC4602
SC1U10V2KX-1GP
SC1U10V2KX-1GP
1 2
12
PC4607
PC4607
SC1U10V2KX-1GP
SC1U10V2KX-1GP
PWR_1D5V_VBST PWR_1D5V_VBST_1
18
PWR_1D5V_UGATE
17
PWR_1D5V_PHASE
16
PWR_1D5V_LGATE
15
14
PWR_1D5V_VDDQ
5
PWR_1D5V_FB
6
Vout=0.75*(1+R1/R2)
84.00172.037
84.00172.037
Id=20A, Qg=9.8~15nC,
Rdson=10.3~12.4 mohm
PC4608
PC4608
1 2
SCD1U50V3KX-GP
SCD1U50V3KX-GP
84.00460.037
84.00460.037
Id=40A, Qg=16.8~25.5nC,
Rdson=4.9~6.1 mohm
12
DY
DY
PC4616
PC4616
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
4 5
G
G
4 5
678
GD
GD
678
DDD
DDD
DDD
DDD
DCBATOUT_1D5V
D
PU4602
PU4602
SIR172DP-T1-GE3-GP
SIR172DP-T1-GE3-GP
SSS
SSS
123
1 2
SG
PL4601
PL4601
1 2
12
COIL-1UH-34-GP-U
D
DY
DY
PU4603
PU4603
D
D
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
SSS
SSS
DY
DY
123
PR4607
PR4607
2D2R5F-2-GP
2D2R5F-2-GP
PWR_1D5V_SW_1
12
PC4615
PC4615
SC330P50V2KX-3GP
SC330P50V2KX-3GP
COIL-1UH-34-GP-U
PC4612
PC4612
PC4611
PC4611
1 2
SC10U25V5KX-GP
SC10U25V5KX-GP
Cyntec. 1.0uH 7.3*6.6*3
DCR=9~10mohm
Idc=11A, Isat=22A
PC4613
PC4613
1 2
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
PG4626
PG4626
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 2
12
PC4620
PC4620
Design Current = 11.69A
OCP>19.92A
PC4621
PC4621
12
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SG
PM_SLP_S4#19,27,97
1 2
PR4611
PR4611
0R0402-PAD
0R0402-PAD
PWR_1D5V_EN
12
PC4622
PC4622
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
PG4605
PG4605
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4606
PG4606
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4608
PG4608
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4609
PG4609
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4610
PG4610
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4611
PG4611
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4612
PG4612
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4613
PG4613
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4614
PG4614
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4615
PG4615
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4616
PG4616
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4617
PG4617
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4618
PG4618
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4619
PG4619
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4620
PG4620
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 1
A
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
RT8207M_1D5V_0D75V
RT8207M_1D5V_0D75V
RT8207M_1D5V_0D75V
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
<Doc>
<Doc>
<Doc>
E
46
46
46
SD
SD
SD
103Friday, January 06, 2012
103Friday, January 06, 2012
103Friday, January 06, 2012
Page 47
5
4
3
2
1
SSID = PWR.Plane.Regulator_1p8v
D D
3D3V_S5
PG4712
PG4712
1 2
GAP-CLOSE-PW R
GAP-CLOSE-PW R
PG4701
PG4701
1 2
GAP-CLOSE-PW R
GAP-CLOSE-PW R
PG4703
PG4703
1 2
GAP-CLOSE-PW R
GAP-CLOSE-PW R
C C
PM_SLP_S3#19,27,36,37
1 2
PR4702 0R0402-PADPR4702 0R0402-PAD
PC4702
PC4702
PC4707
PC4707
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
12
DY
DY
DY
DY
PR4703
PR4703
2D2R2J-GP
2D2R2J-GP
PC4709
PC4709
12
12
PC4704
PC4704
SC22P50V2GN-GP
SC22P50V2GN-GP
1 2
SCD1U50V3KX-GP
SCD1U50V3KX-GP
12
RUNPWROK45,46
PC4703
PC4703
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
RT8068A for 1D8V_S0
PU4701
PWR_1D8V_PVDD
PWR_1D8V_SVIN
PWR_1D8V_EN
3D3V_S0
12
PR4705
PR4705
100KR2J-1-GP
100KR2J-1-GP
PU4701
10
PVIN
9
PVIN
8
SVIN
5
EN
4
PGOOD
RT8068AZQWID-GP-U
RT8068AZQWID-GP-U
LX#1
LX#2
LX#3
NC#7
GND
FB
1
PWR_1D8V_PHASE
2
3
7
6
11
PL4702
PL4702
1 2
IND-2D2UH-46-GP-U
IND-2D2UH-46-GP-U
PWR_1D8V_FB
PR4704
PR4704
20KR2F-L-GP
20KR2F-L-GP
PR4706
PR4706
10KR2F-2-GP
10KR2F-2-GP
1D8V_PWR
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4714
PG4714
1 2
1D8V_FB_GAP
12
R1
12
12
PC4705
PC4705
SC100P50V2JN-3GP
SC100P50V2JN-3GP
12
R2
Vo=0.6*(1+(R1/R2))
PC4706
PC4706
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
PC4708
PC4708
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
Design Current=1.1A
PG4713
PG4713
1 2
GAP-CLOSE-PW R
GAP-CLOSE-PW R
PG4704
PG4704
1 2
GAP-CLOSE-PW R
GAP-CLOSE-PW R
PG4705
PG4705
1 2
GAP-CLOSE-PW R
GAP-CLOSE-PW R
PG4711
PG4711
1 2
GAP-CLOSE-PW R
GAP-CLOSE-PW R
1D8V_S0
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PWM_1D8V_RT8015B
PWM_1D8V_RT8015B
PWM_1D8V_RT8015B
Taipei Hsien 221, Taiwan, R.O.C.
47 103Friday, January 06, 2012
47 103Friday, January 06, 2012
47 103Friday, January 06, 2012
1
SD
SD
SD
Page 48
5
TPS51461 for VCCSA
4
3
2
1
D D
5V_S5 PW R_VCCSA_VIN
PG4807
PG4807
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4808
PG4808
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4809
PG4809
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
C C
B B
PWR_VCCSA_VIN
12
PC4803
PC4803
SC
SC
D1U50V3KX-GP
D1U50V3KX-GP
12
PC4815
PC4815
VID1
L
L 0.8V
H
H
PR4806
PR4806
1R2F-GP
1R2F-GP
PWR_VCCSA_VIN
12
PC4813
PC4813
SC
SC
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
4D7U25V5KX-GP
4D7U25V5KX-GP
L
H
L 0.725V
H
5V_S5
12
PC4816
PC4816
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
12
VCCSAVID0
0.9V
0.675V
12
PC4814
PC4814
SC1U10V2KX-1GP
SC1U10V2KX-1GP
PWR_VCCSA_V5DRV
3D3V_S0
12
PR4809
PR4809
4K7R2J-2-GP
4K7R2J-2-GP
1 2
PR4808
PR4808
0R0402-PAD
0R0402-PAD
PWR_VCCSA_VID1
PWR_VCCSA_PGOOD
PWR_VCCSA_VID0
PWR_VCCSA_EN
PU4801
PU4801
13
15
16
18
17
TPS51461RGER-GP
TPS51461RGER-GP
EN
VID014VID1
V5FILT
V5DRV
PGND
PGND
PGND
VIN
VIN
VIN
GND
PGOOD
GND1VREF2COMP3SLEW4VOUT5MODE
PWR_VCCSA_COMP
PWR_VCCSA_VREF
PWR_VCCSA_SLEW
12
PR4802
PR4802
4K99R2F-L-GP
4K99R2F-L-GP
PWR_VCCSA_COMP_1
12
PC4817
PC4817
SC3300P50V2KX-1GP
SC3300P50V2KX-1GP
12
BST
11
SW#11
10
SW#10
9
SW#9
8
SW#8
7
SW#7
6
PWR_VCCSA_VOUT
74.51461.043
74.51461.043
19
20
21
22
23
24
25
D85V_PW RGD 42
1 2
PR4812 1KR2F-3-GP
PR4812 1KR2F-3-GP
1 2
PR4804 0R0402-PADPR4804 0R0402-PAD
1 2
PR4805 0R0402-PADPR4805 0R0402-PAD
1 2
PR4801
PR4801
0R0402-PAD
0R0402-PAD
20101130 X02:
12
Follow the standard schematics.
DY
DY
PC4804
PC4804
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
20101130 X02:
Follow the standard schematics.
PWR_VCCSA_BST
PWR_VCCSA_SW
PC4806
PC4806
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
1 2
PR4807
PR4807
1 2
0R2J-2-GP
0R2J-2-GP
PR4811
PR4811
1 2
100R2F-L1-GP-U
100R2F-L1-GP-U
1 2
PR4810
PR4810
0R0402-PAD
0R0402-PAD
DY
DY
VCCSA_SELECT1 9
VCCSA_SELECT0 9
1.05VTT_PWRGD 37,45
PC4805
PC4805
SCD1U50V3KX-GP
SCD1U50V3KX-GP
PWR_VCCSA_BST_R
20101130 X02:
Follow the standard schematics.
1 2
0D85V_S0
VCCSA_SENSE 9
TDK. 0.35uH 5*5*3
DCR=3.9mohm
Idc=11A, Isat=14.9A
1 2
IND-D35UH-GP
68.R3510.101
68.R3510.101
PR4803
PR4803
2D2R5F-2-GP
2D2R5F-2-GP
PC4818
PC4818
SC560P50V-GP
SC560P50V-GP
IND-D35UH-GP
DY
DY
DY
DY
12
PWR_VCCSA_SNUB
12
PL4801
PL4801
Design Current = 4.2A
OCP> 8.4A
0D85V_S0
PC4810
PC4809
PC4809
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
DY
DY
PC4810
PC4807
PC4807
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
PC4801
PC4801
PC4812
PC4811
PC4811
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
PC4812
SCD1U50V3KX-GP
SCD1U50V3KX-GP
12
12
DY
DY
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4801
PG4801
PG4802
PG4802
PG4803
PG4803
PG4804
PG4804
PG4805
PG4805
PG4806
PG4806
VCCSA
PC4802
PC4802
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
1 2
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
VCCSA_TPS51461
VCCSA_TPS51461
VCCSA_TPS51461
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
<Doc>
<Doc>
<Doc>
1
48
48
48
SD
SD
SD
103Friday, January 06, 2012
103Friday, January 06, 2012
103Friday, January 06, 2012
Page 49
SSID = VIDEO
LVDS connector
LCD / Inverter Connector
CAMERA POWER
3D3V_S0_CAMER A
Layout 40 mil
12
C4912
C4912
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
74.06288.07F SY6288CAAC
74.02171.07F AP2171WG-7 High Active
DIODES
UPI
74.07534.A7F OBS
GMT
74.05240.A7F OBS
LCDVDD 3D 3V_S0
Layout 40 mil
C4908
C4908
SC4
SC4
12
D7U6D3V3KX-GP
D7U6D3V3KX-GP
74.05285.07F OBS
check 2nd source=74.05285.07F
U4901
U4901
1
OUT
2
GND
OC#3EN/EN#
SY6288CAAC-GP
SY6288CAAC-GP
U4902
U4902
1
2
SY6288CAAC-GP
SY6288CAAC-GP
74.06288.07F
74.06288.07F
IN
OUT
GND
OC#3EN/EN#
5
4
5
IN
4
3D3V_S0_CAMER A_IN
12
C4911
C4911
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
High ActiveSILERGY
High Active
High Active
C4907
C4907
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
C4909
C4909
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
CAMERA_EN 27
LVDS_VDD_EN
12
DY
DY
1 2
R4922 0R0805-PADR4922 0R0805-PAD
3D3V_S0
LCD POWER
DCBATOUT _LCD DCBATOUT
C4904
C4904
C4905
C4905
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
12
12
LCDVDD Discharge
3D3V_AUX_S5
12
R4929
R4929
100KR2J-1-GP
100KR2J-1-GP
LVDS_VDD_EN #
Q4901
Q4901
6
2N7002KDW -GP
2N7002KDW -GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
12
F4901
F4901
POLYSW-1D1 A24V-GP-U
POLYSW-1D1 A24V-GP-U
2nd = 69.50007.A41
2nd = 69.50007.A41
Main:69.50007.A41
Second:69.50007.A31
LCDVDD_D ISCHARGE
LVDS_VDD_EN
2345
1
LCDVDD
12
R4930
R4930
100R2J-2-GP
100R2J-2-GP
3D3V_S0
1
23
4
3D3V_S0_CAMER A
C4922
C4922
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
RN4902
RN4902
SRN2K2J-1-G P
SRN2K2J-1-G P
LVDS_DDC_D ATA_R
LVDS_DDC_C LK_R
LCDVDD
12
1 2
1 2
R4928 33R2J-2-GPR4928 33R2J-2-GP
LVDS_DDC_D ATA_R17
LCD_DET#18
USB_PN1218
USB_PP1218
3D3V_AUX_S5
3D3V_S0
F4903 FUSE-D 5A32V-14-GPF 4903 FUSE-D5A 32V-14-GP
F4902 FUSE-3A 32V-12-GPF4902 FU SE-3A32V-12-G P
12
C4921
C4921
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
LVDSA_CLK17
LVDSA_CLK#17
LVDSA_DATA217
LVDSA_DATA2#17
LVDSA_DATA117
LVDSA_DATA1#17
LVDSA_DATA017
LVDSA_DATA0#17
LVDS_DDC_C LK_R17
BLON_OUT27
1 2
LID_CLOSE#27,70
BLON_OUT_C
LCD_BRIGHTN ESSL_BKLT_CTRL
3D3V_DDC_S 0
LCDVDD_R
R4903
R4903
1 2
1KR2J-1-GP
1KR2J-1-GP
LCD_PRESEN CE#
USB_CAMERA #
USB_CAMERA
LID_CLOSE#
BLON_OUT_C
12
R49260R0402-P AD R 49260R0402-PA D
12
R49250R0402-P AD R 49250R0402-PA D
12
R49240R0402-P AD R 49240R0402-PA D
Pin11 is CAMERA GND
Pin15 is CAMERA shielding GND
Pin20 is Hall Sensor GND
DCBATOUT _LCD
R4911
R4911
12
100KR2J-1-GP
100KR2J-1-GP
C4910
C4910
12
1.2A
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SC100P50V2JN-3GP
SC100P50V2JN-3GP
1 2
1
2
3
4
5
6
7
8
9
SCD1U50V3KX-GP
SCD1U50V3KX-GP
C4902
C4902
LVDS1
LVDS1
41
42
JAE-CON40- 4-GP
JAE-CON40- 4-GP
20.K0568.040
20.K0568.040
C4916
C4916
C4906
C4906
SCD01U50V2KX- L-GP
SCD01U50V2KX- L-GP
1 2
1 2
AFTP4901AF TP4901
1
LID_CLOSE#
For EMI request
Close to LVDS connector
LCD_BRIGHTN ESS
LVDSA_CLK#
LVDSA_CLK
EC4905
EC4905
EC4904
EC4904
12
12
SC5
SC5
SC5
SC5
DY
DY
DY
DY
D6P50V2CN-1GP
D6P50V2CN-1GP
D6P50V2CN-1GP
D6P50V2CN-1GP
DY
DY
EC4902
EC4902
12
Panel BL brightness/Power En/BL En
L_BKLT_EN17
L_BKLT_CTRL17
SC33P50V2JN-3GP
SC33P50V2JN-3GP
LVDS_VDD_EN17
1 2
R4905 0R0402-PADR4905 0R0402 -PAD
L_BKLT_CTRL
LVDS_VDD_EN
12
C4901
C4901
SC100P50V2JN-3 GP
SC100P50V2JN-3 GP
PANEL_BLEN 27
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
LCD Connector
LCD Connector
LCD Connector
LA480
LA480
LA480
49 103
49 103
49 103
SD
SD
SD
Page 50
5
4
3
2
1
CRT connector
CRT1
5V_CRT_S0
C5013
C5013
12
SCD01U50V2KX- 1GP
SCD01U50V2KX- 1GP
D D
CRT_DDC DATA_CON
CRT_DDC CLK_CON
CRT_R
CRT_G
CRT_B
CRT_VSYNC_C ON
CRT_HSYNC _CON 3D3V_S0_DDC
AFTP5001AFT P5001
AFTP5002AFT P5002
AFTP5003AFT P5003
AFTP5004AFT P5004
AFTP5005AFT P5005
AFTP5006AFT P5006
AFTP5007AFT P5007
AFTP5008AFT P5008
1
1
1
1
1
1
1
1
CRT1
9
VCC_CRT
12
DDCDATA_ID1
15
DDCCLK_ID3
1
CRT_RED
2
CRT_GREEN
3
CRT_BLUE
14
VSYNC
13
HSYNC
D-SUB-15-13 6-GP
D-SUB-15-13 6-GP
20.20961.015
20.20961.015
5V_CRT_S0
CRT_DDC DATA_CON
CRT_DDC CLK_CON
CRT_R
CRT_G
CRT_B
CRT_VSYNC_C ON
CRT_HSYNC _CON
NC#4
NC#11
4
11
AFTP5009AFT P5009
5
1
GND
6
GND
7
GND
8
GND
10
GND
16
GND
17
GND
CRT_DDC _DATA17
CRT_DDC _CLK17
CRT DDCDATA & DDCCLK level shift
Pull High 5V Design on CRT Board
3D3V_S0
1 2
R5003 10KR2J-3-GPR5003 10KR 2J-3-GP
3D3V_S0
1
23
4
RN5002
RN5002
SRN2K2J-1-G P
SRN2K2J-1-G P
5V_CRT_S0
F5001
F5001
FUSE-1D1A6V -4GP-U
FUSE-1D1A6V -4GP-U
69.50007.691
69.50007.691
2nd = 69.50007.771
2nd = 69.50007.771
3D3V_S0_DDC
Q5001
Q5001
2345
1
6
2N7002KDW -GP
2N7002KDW -GP
84.DM601.03F
84.DM601.03F
2nd = 84.2N702.A3F
2nd = 84.2N702.A3F
12
5V_CRT_DD C
RN5003
RN5003
SRN10KJ-5-G P
SRN10KJ-5-G P
CRT_DDC DATA_CON
CRT_DDC CLK_CON
5V_S0
500mA
D5001
D5001
CH551H-30PT -GP
CH551H-30PT -GP
83.R5003.C8F
83.R5003.C8F
2ND = 83.5R003.08F
2ND = 83.5R003.08F
2 1
3rd = 83.R5003.G8F
3rd = 83.R5003.G8F
4
1
2 3
CRT Hsync & Vsync level shift
5V_S0
12
C5007
C5007
SCD1U10V2KX- 5GP
C C
U5001
U5001
2
G1#1A1
7
4
CRT RGB
DY
DY
C5003
C5003
12
SC8P250V2CC-GP
SC8P250V2CC-GP
1 2
FCM1608CF-22 0T05-GP
FCM1608CF-22 0T05-GP
68.00245.011
68.00245.011
2nd = 68.00230.021
2nd = 68.00230.021
1 2
FCM1608CF-22 0T05-GP
FCM1608CF-22 0T05-GP
68.00245.011
68.00245.011
2nd = 68.00230.021
2nd = 68.00230.021
1 2
FCM1608CF-22 0T05-GP
FCM1608CF-22 0T05-GP
68.00245.011
68.00245.011
2nd = 68.00230.021
2nd = 68.00230.021
CRT_RED17
CRT_GREE N17
B B
CRT_BLUE17
SRN150F-1-G P
SRN150F-1-G P
RN5001
RN5001
123
678
4 5
C5002
C5002
C5001
C5001
SC8P250V2CC-GP
SC8P250V2CC-GP
SC8P250V2CC-GP
SC8P250V2CC-GP
12
12
DY
DY
DY
DY
5
A2
G2#
6
Y1
3
Y2
GND
8
VCC
TC7WT12 5FU-GP
TC7WT12 5FU-GP
73.7W125.007
73.7W125.007
2nd = 73.2G125.A0B
2nd = 73.2G125.A0B
L5001
L5001
L5002
L5002
L5003
L5003
C5004
C5004
12
SCD1U10V2KX- 5GP
CRT_VSYNC 17
CRT_HSYNC 17
CRT_VSYNC1_ 2 CRT_VSYNC_ CON
R5001 10R2J-2-GPR5001 10R2J-2-GP
CRT_HSYNC 1_2 CRT_HSYNC_C ON
C5005
C5005
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
12
1 2
R5002 10R2J-2-GPR5002 10R2J-2-GP
1 2
CRT_R
CRT_G
CRT_B
C5006
C5006
SC10P50V2JN-4GP
SC10P50V2JN-4GP
12
5V_CRT_S0
D5002
D5002
2
DY
DY
1
CH221GP-GP- U
CH221GP-GP- U
D5003
D5003
2
DY
DY
1
CH221GP-GP- U
CH221GP-GP- U
D5004
D5004
2
DY
DY
1
CH221GP-GP- U
CH221GP-GP- U
D5005
D5005
2
DY
DY
1
CH221GP-GP- U
CH221GP-GP- U
CRT_HSYNC _CON
3
CRT_VSYNC_ CON
3
CRT_DDC DATA_CON
3
CRT_DDC CLK_CON
3
5V_CRT_S0
D5006
D5006
2
DY
DY
1
CH221GP-GP- U
CH221GP-GP- U
D5007
D5007
2
DY
DY
1
CH221GP-GP- U
CH221GP-GP- U
D5008
D5008
2
DY
DY
1
CH221GP-GP- U
CH221GP-GP- U
CRT_RED
3
CRT_GREE N
3
CRT_BLUE
3
CRT_DDC DATA_CON
CRT_HSYNC _CON
CRT_VSYNC_ CON
CRT_DDC CLK_CON
C5011
C5011
C5010
C5010
C5009
C5009
C5008
C5008
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
12
12
DY
DY
DY
DY
A A
5
4
3
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
12
12
DY
DY
DY
DY
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
CRT Connector
CRT Connector
CRT Connector
LA480
LA480
LA480
1
50 103
50 103
50 103
SD
SD
SD
Page 51
SSID = VIDEO
5
4
3
2
1
HDMI Passive Level Shifter
D D
C C
HDMI_CLK_R#17
HDMI_CLK_R17
HDMI_DATA0_R #17
HDMI_DATA0_R17
HDMI_DATA1_R #17
HDMI_DATA1_R17
HDMI_DATA2_R #17
HDMI_DATA2_R17
C5103 SCD1U10V2KX- 5GPC5103 SC D1U10V2KX-5G P
C5104 SCD1U10V2KX- 5GPC5104 SC D1U10V2KX-5G P
C5105 SCD1U10V2KX- 5GPC5105 SC D1U10V2KX-5G P
C5106 SCD1U10V2KX- 5GPC5106 SC D1U10V2KX-5G P
C5110 SCD1U10V2KX- 5GPC5110 SC D1U10V2KX-5G P
C5107 SCD1U10V2KX- 5GPC5107 SC D1U10V2KX-5G P
C5108 SCD1U10V2KX- 5GPC5108 SC D1U10V2KX-5G P
C5109 SCD1U10V2KX- 5GPC5109 SC D1U10V2KX-5G P
Close to HDMI Connector
Close to HDMI Connector
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R5104
R5104
100KR2J-1-GP
100KR2J-1-GP
3D3V_S0
DY
DY
12
HDMI_CLK_R_C 1#
HDMI_CLK_R_C 1
HDMI_DATA0_R _C1#
HDMI_DATA0_R _C1
HDMI_DATA1_R _C1#
HDMI_DATA1_R _C1
HDMI_DATA2_R _C1#
HDMI_DATA2_R _C1
D
G
RN5101
RN5101
SRN680-U-G P
SRN680-U-G P
HDMI_PLL_GND
Q5103
Q5103
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.J31
2ND = 84.2N702.J31
S
123
678
678
RN5102
RN5102
SRN680-U-G P
SRN680-U-G P
4 5
123
4 5
HDMI CONNECTOR
HDMI1
HDMI1
20
CHASSIS
CHASSIS
CHASSIS
CHASSIS
SKT-HDMI21-1- GP-U
SKT-HDMI21-1- GP-U
22.10296.571
22.10296.571
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
HDMI_DATA2_R _C
HDMI_DATA2_R _C#
HDMI_DATA1_R _C
HDMI_DATA1_R _C#
HDMI_DATA0_R _C
HDMI_DATA0_R _C#
HDMI_CLK_R_C
HDMI_CLK_R_C #
HDMI_PIN13
DDC_CLK_H DMI
DDC_DAT A_HDMI
5V_HDMI
HPD_HDMI_CO N
AFTP5121AF TP5121
1
C5102
C5102
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
F5101
F5101
12
FUSE-1D1A6V -4GP-U
FUSE-1D1A6V -4GP-U
69.50007.691
69.50007.691
2nd = 69.50007.771
2nd = 69.50007.771
5V_HDMI_S0
83.R5003.C8F
83.R5003.C8F
3rd = 83.R5003.G8F
3rd = 83.R5003.G8F
2ND = 83.5R003.08F
2ND = 83.5R003.08F
CH551H-30PT -GP
CH551H-30PT -GP
2 1
D5101
D5101
1 2
DY
DY
R5113 0R2J-2-GP
R5113 0R2J-2-GP
5V_S0
ESD Request
EMI's request
HDMI_CLK_R_C 1#
HDMI_CLK_R_C 1 HDMI_CLK_R_C
R5114
R5114
0R2J-2-GP
0R2J-2-GP
1 2
R5115
R5115
0R2J-2-GP
0R2J-2-GP
1 2
HDMI_CLK_R_C #
R5118
R5118
0R2J-2-GP
HDMI_DATA1_R _C1#
HDMI_DATA1_R _C1 HDM I_DATA1_R_C
0R2J-2-GP
1 2
R5119
R5119
0R2J-2-GP
0R2J-2-GP
1 2
HDMI_DATA1_R _C#
HDMI_DATA2_R _C
HDMI_DATA1_R _C
HDMI_DATA0_R _C
HDMI_CLK_R_C
HDMI_DATA2_R _C#
1 2
R5107 180R2F -1-GP
R5107 180R2F -1-GP
DY
DY
HDMI_DATA1_R _C#
1 2
R5108 180R2F -1-GP
R5108 180R2F -1-GP
DY
DY
HDMI_DATA0_R _C#
1 2
R5109 180R2F -1-GP
R5109 180R2F -1-GP
DY
DY
HDMI_CLK_R_C #
1 2
R5110 180R2F -1-GP
R5110 180R2F -1-GP
DY
DY
HDMI_PIN13
HPD_HDMI_CO N
DDC_DAT A_HDMI
DDC_CLK_H DMI
12
12
D5105
D5105
D5106
D5106
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
12
12
D5107
D5107
D5108
D5108
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
R5120
R5116
R5116
0R2J-2-GP
B B
HDMI_DATA0_R _C1#
0R2J-2-GP
1 2
HDMI_DATA0_R _C#
HDMI_DATA2_R _C1#
R5120
0R2J-2-GP
0R2J-2-GP
1 2
HDMI_DATA2_R _C#
HDMI DDC Passive Level Shifter
D5102
D5102
BAW56-5-G P
BAW56-5-G P
83.00056.Q11
5V_HDMI_S0_1
5V_HDMI_S0_2
4
1
2 3
DG: 2.2K PU
RN5103
RN5103
SRN2K2J-1-G P
SRN2K2J-1-G P
DDC_DAT A_HDMI
DDC_CLK_H DMI
2
83.00056.Q11
2nd = 83.00056.K11
2nd = 83.00056.K11
1
3
2
5V_S0
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
LA480
LA480
LA480
1
Taipei Hsie n 221, Taiwan, R.O .C.
51 103
51 103
51 103
Title
Title
Title
HDMI Level Shifter/Connector
HDMI Level Shifter/Connector
HDMI Level Shifter/Connector
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
Date: Sheet of
SD
SD
SD
R5121
12
R5101
R5101
1MR2F-GP
1MR2F-GP
R5121
0R2J-2-GP
0R2J-2-GP
1 2
3D3V_S0
4
Q5102
Q5102
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
D
HPD_HDMI_CO N
12
R5106
R5106
100KR2J-1-GP
100KR2J-1-GP
DG: 20K PD
3D3V_S0
Q5104
Q5104
1
PCH_HDMI_DA TA17
PCH_HDMI_CLK17
3
6
2
5
3 4
2N7002KDW -GP
2N7002KDW -GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
R5117
R5117
0R2J-2-GP
HDMI_DATA0_R _C1 HDM I_DATA0_R_C
A A
0R2J-2-GP
1 2
5
HDMI_DATA2_R _C1 HDM I_DATA2_R_C
HDMI_PCH_DE T17
Page 52
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
eDP
eDP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
eDP
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
52 103
52 103
52 103
1
SD
Page 53
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
S-VIDEO
S-VIDEO
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
S-VIDEO
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
53 103
53 103
53 103
1
SD
Page 54
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
54 103
54 103
54 103
1
SD
Page 55
5
4
SSID = User.Interface
3
2
1
D D
ITP Connector
H_CPURST# use pull-up Resistor close
ITP connector 500 mil ( max ),
others place near CPU side.
C C
CPU
TCK(PIN AC5)
ITP Connector
TCK(PIN 5)
FBO(PIN 11)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
ITP
ITP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
ITP
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
55 103
55 103
55 103
1
SD
Page 56
5
4
3
2
1
SATA HDD Connector
HDD1
HDD1
24
NP2
SATA_TXP1_C
C5614SCD01U50V2KX-1GP C5614SCD01U50V2KX-1GP
C5606
C5606
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
1 2
12
SATA_TXN1_C
C5613SCD01U50V2KX-1GP C5613SCD01U50V2KX-1GP
12
SATA_RXN1_C
C5616SCD01U50V2KX-1GP C5616SCD01U50V2KX-1GP
SATA_RXP1_C
C5615SCD01U50V2KX-1GP C5615SCD01U50V2KX-1GP
3D3V_S0_HDD
5V_S0_HDD
FFS_INT2
D D
3D3V_S0
1 2
R5603
R5603
0R0805-PAD
0R0805-PAD
DY
DY
SATA_TXN121
SATA_RXN121
SATA_RXP121
C5604
C5604
12
SATA_TXP121
C5601
C5601
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
DY
12
5V_S0
1 2
R5606
R5606
0R0805-PAD
0R0805-PAD
C5605
C5605
12
HDD_DET#27
SC10U10V5KX-2GP
SC10U10V5KX-2GP
C C
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NP1
23
SKT-SATA22P-27-GP-U1
SKT-SATA22P-27-GP-U1
62.10065.471
62.10065.471
TP5607TP5607
1
FFS_INT2
ODD Connector
SATA_RX- and SATA_RX+ Trace
Length match within 20 mil
Mars:
Exchange ODD and ESATA differential pair each other.
C5611SCD01U50V2KX-1GP C5611SCD01U50V2KX-1GP
SATA_TXN421
SATA_TXP421
SATA_RXN421
SATA_RXP421
12
C5612SCD01U50V2KX-1GP C5612SCD01U50V2KX-1GP
12
C5607SCD01U50V2KX-1GP C5607SCD01U50V2KX-1GP
12
C5608SCD01U50V2KX-1GP C5608SCD01U50V2KX-1GP
12
SATA_TXN4_C
SATA_TXP4_C
SATA_RXN4_C
SATA_RXP4_C
DY
DY
12
R5604
R5604
10KR2J-3-GP
10KR2J-3-GP
SATA_ODD_DA#_C
SATA_ODD_PRSNT# 22
DY
DY
12
SATA_ODD_DA# 18,27
R5602
R5602
0R2J-2-GP
0R2J-2-GP
SATA Zero Power ODD
ODD_PW R_5V
B B
SATA_TXN4_C
SATA_TXP4_C
SATA_RXN4_C
SATA_RXP4_C
A A
SATA_ODD_PWRGT
SATA_ODD_DA#
ODD1
ODD1
GND
GND
GND
GND
GND
GND
MD
DP
SATA_ODD_DA#_C
P4
SATA_ODD_PRSNT#
P1
S1
S4
S7
P5
P6
14
15
3D3V_S0
P2
+5V
P3
+5V
A-S3GND
S2
A+
S5
B-
S6
B+
NP1
NP1
NP2
NP2
SKT-SATA7P-6P-59-GP-U
SKT-SATA7P-6P-59-GP-U
22.10300.B91
22.10300.B91
1 2
R5608 10KR2J-3-GPR5608 10KR2J-3-GP
1 2
R5609 10KR2J-3-GP
R5609 10KR2J-3-GP
DY
DY
When the drive is powered on, the FET to the MD/DA pin drive is OFF.
When the drive is powered off, the FET to the MD/DA pin is ON
SUPPORT ZERO SATA ODD
SATA_ODD_PWRGT SATA_ODD_DA#
74.02069.079 TI TPS2069DGNR MSOP 8P
74.07534.D79 UPI UP7534PRA8-15 MSOP 8P
74.00547.C79 GMT G547F1P81U MSOP 8P (OBS)
74.07534.A79 UPI UP7534ARA8-15 MSOP8P
5V_S0
12
R5605
R5605
100KR2J-1-GP
100KR2J-1-GP
ODD_PWRGT#
5
6
123 4
SATA_ODD_DA#_C
Q5601
Q5601
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
DIODES
UPI 74.07534.A7F OBS
SATA_ODD_PWRGT22
5V_S0
ODD_PW R_5V_IN
C5609
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C5609
R5607
R5607
12
0R0805-PAD
0R0805-PAD
1 2
74.02069.079 TPS2069DGNR
AP2171WG-7 High Active
High ActiveTI
High Active
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Current limit
Active High
typ =>2A
U5601
U5601
TPS2064DGNR-GP-U
TPS2064DGNR-GP-U
4
EN2#
3
EN1#
2
IN
1
GND
HDD/ODD
HDD/ODD
HDD/ODD
LA480
LA480
LA480
ODD_PW R_5V
5
OC2#
OUT2
OUT1
OC1#
GND
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
ODD_PW R_5V
6
7
8
9
100 mil
C5610
C5610
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
56 103Friday, January 06, 2012
56 103Friday, January 06, 2012
56 103Friday, January 06, 2012
12
SD
SD
SD
Page 57
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
E-SATA+USB
E-SATA+USB
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
E-SATA+USB
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
57 103
57 103
57 103
1
SD
Page 58
5
4
3
2
1
AUD_DMIC_CLK _L
AUD_DMIC_DA TA_L
V Series-MIC
V Series-MIC
C5804
C5804
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
3D3V_S0
12
MIC1
MIC1
6
4
3
2
1
5
ACES-CON 4-17-GP-U1
ACES-CON 4-17-GP-U1
20.F1621.004
20.F1621.004
ME change P/N at SIT
Old 20.F1639.004
New 20.F1621.004
Int. Digital MIC for V series
V Series-MIC
V Series-MIC
L5801
L5801
SBY100505T-601Y-N-G P
SBY100505T-601Y-N-G P
AUD_DMIC_CLK29
D D
AUD_DMIC_DA TA29
1 2
1 2
SBY100505T-601Y-N-G P
SBY100505T-601Y-N-G P
V Series-MIC
V Series-MIC
L5802
L5802
AUD_DMIC_CLK _L
AUD_DMIC_DA TA_L
12
12
C5805
C5805
C5806
C5806
DY
DY
DY
DY
MLVG0402220NV09BP-GP
MLVG0402220NV09BP-GP
MLVG0402220NV09BP-GP
MLVG0402220NV09BP-GP
CHECK PIN DEFINE
AFTP5809AFT P5809
AFTP5810AFT P5810
AFTP5805AFT P5805
AFTP5806AFT P5806
AUD_DMIC_CLK _L
1
AUD_DMIC_DA TA_L
1
3D3V_S0
1
GND
1
INTERNAL STEREO SPEAKERS
Int. Mono Analog MIC for B series
AUD_MIC2_VREF O29
AUD_MIC229
1 2
R5813 0R2J-2-GP
R5813 0R2J-2-GP
DY
C C
DY
AU_GND
1 2
R5811 2K2R 2J-2-GP
R5811 2K2R 2J-2-GP
B Series-MIC
B Series-MIC
1 2
R5808 1KR 2J-1-GP
R5808 1KR 2J-1-GP
B Series-MIC
B Series-MIC
C5807
C5807
SC100P50V2JN-3 GP
SC100P50V2JN-3 GP
B Series-MIC
B Series-MIC
12
D5801
D5801
12
DY
DY
AU_GND AU_GND
MLVG0402220NV05BP-GP-U
MLVG0402220NV05BP-GP-U
1 2
R5812 0R2J-2-GP
R5812 0R2J-2-GP
B Series-MIC
B Series-MIC
AUD_DMIC_CLK _L
AUD_DMIC_DA TA_L
AUD_SPK_L+29
AUD_SPK_L-29
Only needed if speaker
connector is physically far from
audio codec. When in doubt, it's
always a good idea to have
population option.
AUD_SPK_R+29
AUD_SPK_R-29
AFTP5801AF TP5801
AFTP5802AF TP5802
AFTP5803AF TP5803
AFTP5804AF TP5804
AUD_SPK_L+
1
AUD_SPK_L-
1
AUD_SPK_R+
1
AUD_SPK_R-
1
SC47P50V2JN-3G P
SC47P50V2JN-3G P
Place these EMI components
close to speaker connector.
EC5803
EC5803
SC47P50V2JN-3G P
SC47P50V2JN-3G P
EC5801
EC5801
12
SC47P50V2JN-3G P
SC47P50V2JN-3G P
12
SC47P50V2JN-3G P
SC47P50V2JN-3G P
EC5802
EC5802
EC5804
EC5804
12
12
Table 58.1 - Bi-direction ESD multi-source
Supplier
ROHM
ON SEMI
Description Lenovo P/N Wistron P/N
RSB5.6SMT2R
ESD5B5.0ST1G
AFTP5807AF TP5807
AFTP5808AF TP5808
N/A
N/A
3
1
2
1
4
3
1
2
1
4
83.RSB56.BAF
83.ESD5B.0AF
83.0005V.0AFNXP N/APESD5V0S1BB
SPK1
SPK1
ACES-CON 2-17-GP
ACES-CON 2-17-GP
20.F1621.002
20.F1621.002
SPK2
SPK2
ACES-CON 2-17-GP
ACES-CON 2-17-GP
20.F1621.002
20.F1621.002
CHECK PIN DEFINE, RIGHT? LEFT?
B B
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
Audio Jack
Audio Jack
Audio Jack
LA480
LA480
LA480
1
58 103
58 103
58 103
SD
SD
SD
Page 59
5
4
3
2
1
FOR CO-LAY
GIGA Lan Transformer
83.00005.BAE
DIODE ARR SRV05-4.TCT SOT-23-6
XF5901
XF5901
1CT:1CT
TVS
1CT:1CT
D D
12
C5903
C5903
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
C5901 value modify to 0.01uF ~
0.4uF capacitor
C C
MDI3+31
MDI3-31
MDI2+31
MDI2-31
MDI1+31
MDI1-31
MDI0+31
MDI0-31
2
1
3
1CT:1CT
1CT:1CT
5
4
6
1CT:1CT
1CT:1CT
8
7
9
1CT:1CT
1CT:1CT
11
10
12 13
XFORM-24P-19-GP
XFORM-24P-19-GP
68.IH601.301
68.IH601.301
2ND = 68.89240.30D
2ND = 68.89240.30D
1st
68.IH601.301(Taimag) for 1000
68.HH035.301(Taimag) for 10/100
2nd
68.2413S.30A(Lankom) for 1000
68.H6441.301(Lankom) for 10/100
LAN Connector
3D3V_LAN_S5
RJ45
RJ45
CHASSIS CHASSIS
B B
LAN_ACT_LED#31
SPEED_100#31
1 2
R5903 330R2J-3-GPR5903 330R2J-3-GP
1 2
330R2J-3-GPR5904 330R2J-3-GPR5904
close to RJ45
LAN_ACT_LED#_1
RJ45_8
RJ45_7
RJ45_6
RJ45_5
RJ45_4
RJ45_3
RJ45_2
RJ45_1
SPEED_100#_1
EC5901
EC5901
SCD1U50V3KX-GP
SCD1U50V3KX-GP
12
10
9
8
7
6
5
4
3
2
1
11
12
YELLOW
YELLOW
GREEN
GREEN
CHASSIS
CHASSIS
RJ45-8P-91-GP
RJ45-8P-91-GP
22.10277.U11
22.10277.U11
CHASSIS CHASSIS
CHASSIS
CHASSIS
1516
1314
RJ45_7
23
MCT2XRF_TDC
24
RJ45_8
22
RJ45_4
20
MCT1
21
RJ45_5
19
RJ45_3
17
MCT4
18
RJ45_6
16
RJ45_1
14
MCT3
15
RJ45_2
Swap for V480
DY
DY
D5901
RJ45_6
RJ45_3
RJ45_4
RJ45_5
D5901
SRV05-4-2-GP
SRV05-4-2-GP
5
6
DY
DY
D5902
D5902
SRV05-4-2-GP
SRV05-4-2-GP
5
6
83.09904.AAE
DIODE ESD AZC099-04S SOT23-6L
RJ45_2
34
2
RJ45_1
1
RJ45_7
34
2
RJ45_8
1
MCT2
MCT1
MCT4
MCT3
SC1KP2KV6KX-GP
SC1KP2KV6KX-GP
C5904
C5904
123
678
4 5
MCT_R
1 2
RN5902
RN5902
SRN75J-1-GP
SRN75J-1-GP
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
RJ45 / Transformer
RJ45 / Transformer
RJ45 / Transformer
LA480
LA480
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
LA480
Taipei Hsien 221, Taiwan, R.O.C.
59 103
59 103
59 103
1
SD
SD
SD
Page 60
5
4
3
2
1
SSID = Flash.ROM
SPI FLASH ROM (8M byte) for PCH
D D
R6004
R6004
4K7R2J-2-GP
4K7R2J-2-GP
3D3V_SPI 3D3V_SPI
23
12
1
RN6001
RN6001
SRN4K7J-8-GP
SRN4K7J-8-GP
4
3D3V_SPI 3D3V_S5
1 2
R6010
R6010
C6002
C6002
0R0402-PAD
0R0402-PAD
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
the same page 23 VCCSPI power
DY
DY
C6001
C6001
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
U6001
U6001
SPI_CS0#_R21,27
SPI_SO_R21,27
C C
SPI_CS1#_R21
SPI_SO_R21,27
B B
1 2
R6001
R6001
33R2J-2-GP
33R2J-2-GP
EC6002
EC6002
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
R6005
R6005
4K7R2J-2-GP
4K7R2J-2-GP
1 2
R6003
R6003
33R2J-2-GP
33R2J-2-GP
SBA
SBA
EC6004
EC6004
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
12
3D3V_SPI
12
12
DY
DY
DY
DY
SBA
SBA
SPI_WP#
SPI_SO1
SPI_WP# SPI_HOLD_0#
SPI_SO
1
S#
2
DQ1
3
W#/VPP
4
VSS
LILY-BIOS-COLAY-GP-U
LILY-BIOS-COLAY-GP-U
U6002
U6002
1
S#
2
DQ1
3
W#/VPP
4
VSS
LILY-BIOS-COLAY-GP-U
LILY-BIOS-COLAY-GP-U
SBA
SBA
HOLD#
GND
VCC
DQ0
GND
VCC
HOLD#
DQ0
C
9
8
7
6
C
5
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
9
8
7
6
5
3D3V_SPI
SPI_HOLD_0#
SPI_CLK_R_1
SPI_SI_R_1
12
EC6003
EC6003
DY
DY
3D3V_SPI
SPI_CLK_R_2
SPI_SI_R_2
EC6005
EC6005
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
12
EC6001
EC6001
DY
DY
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
12
DY
DY
1 2
R6006 33R2J-2-GPR6006 33R2J-2-GP
1 2
R6007 33R2J-2-GPR6007 33R2J-2-GP
SBA
SBA
1 2
R6008 33R2J-2-GP
R6008 33R2J-2-GP
1 2
R6009 33R2J-2-GP
R6009 33R2J-2-GP
SBA
SBA
12
EC6006
EC6006
DY
DY
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SPI_CLK_R 21,27
SPI_SI_R 21,27
SPI_CLK_R 21,27
SPI_SI_R 21,27
4MB
SO8
8MB
SO8
16MB
WSON
Marcronix
Winbond
MX25L3206EM2I-12G
W25Q032BVSSIG
Numonyx N25Q032A13ESE40
Marcronix
Winbond
MX25L6406EM2I-12G
W25Q064CVSSIG
Numonyx N25Q064A13ESE40
Marcronix
MX25L12836EZNI-10G
MX25L12835EZNI-10G
Winbond
W25Q128BVEIG
Numonyx N25Q128A13EF840
72.25320.C01
72.25Q32.A01
72.25032.H01
72.25640.D01
72.25Q64.B01
72.25Q64.D01
72.25128.X01
72.25128.Y01
72.25128.I01
72.25128.B03
SSID = RBATT
R6012
R6012
0R2J-2-GP
0R2J-2-GP
1 2
DY
RTC_AUX_S5 3D3V_AUX_S5 +RTC_VCC
C6003
C6003
SC1U6D3V2KX-GP
A A
SC1U6D3V2KX-GP
5
1 2
2nd = 83.00040.E81
2nd = 83.00040.E81
Q6001
Q6001
3
CH715FPT-GP
CH715FPT-GP
83.R0304.B81
83.R0304.B81
10MR2J-L-GP
10MR2J-L-GP
3
RTC_PW R
R6011
R6011
1 2
2
RTC_PW R
1
1 2
R6002 1KR2J-1-GPR6002 1KR2J-1-GP
+RTC_VCC
Width=20mils
AFTP6002AFTP6002
AFTP6001AFTP6001
4
+RTC_VCC
1
GND
1
RTC14
RTC14
3
1
2
4
ACES-CON2-11-GP
ACES-CON2-11-GP
20.F0772.002
20.F0772.002
Q6002
Q6002
G
S
2N7002K-2-GP
2N7002K-2-GP
DY
D
2
RTC_DET# 20
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
Date: Sheet of
Flash/RTC
Flash/RTC
Flash/RTC
LA480
LA480
LA480
Taipei Hsien 221, Taiwan, R.O.C.
60 103
60 103
60 103
1
SD
SD
SD
Page 61
5
4
3
2
1
USB Board CONN.
D D
Support 2A
5V_USB4_S35V_S5
U6102
U6102
OUT
GND
OC#
1
2
3
C6103
C6103
5
IN
12
SC
SC
DY
DY
D1U10V2KX-5GP
D1U10V2KX-5GP
4
EN/EN#
SY6288CAAC-GP
SY6288CAAC-GP
74.06288.07F
74.06288.07F
Place U6102 close to USBCN1
C C
at least 80 milat least 80 mil
USB_OC#2_3 18USB_PW R_EN_R27,62,82
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
USB Connector
USB Connector
USB Connector
A3
A3
A3
Taipei Hsien 221, Taiwan, R.O.C.
LA480
LA480
LA480
61 103Friday, January 06, 2012
61 103Friday, January 06, 2012
61 103Friday, January 06, 2012
1
SD
SD
SD
Page 62
5
USB3.0 Port1 USB3.0 Port2
5V_S5
C6205
C6205
USB_PWR _EN_R27,61,82
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
D D
5V_USB1_S3
USB_PN1_R
12
USB_PP1_R
TC6201
TC6201
SE2
SE2
20U6D3VM-30-GP
20U6D3VM-30-GP
TC6201 place near
the USB1 connector
USB3_TX1_P18
C C
USB3_TX1_N18 USB3_TX3_N18
USB3_RX1_P18
USB1
USB1
1
STDA_SSRX-
VBUS
STDA_SSRX+
2
STDA_SSTX-
D-
3
STDA_SSTX+
D+
10
10
11
11
12
12
13
GND_DRAIN
13
SKT-USB13-77- GP
SKT-USB13-77- GP
22.10339.K61
22.10339.K61
USB3_TX1_P_C
1 2
C6206 SCD1U16V2KX- 3GPC6206 SCD1U16V2K X-3GP
USB3_TX1_N_C U SB3_TX1_N_R
1 2
C6208 SCD1U16V2KX- 3GPC6208 SCD1U16V2K X-3GP
USB3_RX1_P U SB3_RX1_P_R
GND
R6201
R6201
1 2
0R0402-PAD
0R0402-PAD
R6202
R6202
1 2
0R0402-PAD
0R0402-PAD
R6203
R6203
1 2
0R0402-PAD
0R0402-PAD
5
6
8
9
4
7
USB3_RX1_N_R
USB3_RX1_P_R
USB3_TX1_N_R
USB3_TX1_P_R
USB3_TX1_P_R
2A
U6201
U6201
1
GND
2
IN
3
EN1#
4
EN2#
TPS2064DGNR -GP-U
TPS2064DGNR -GP-U
9
GND
8
OC1#
7
OUT1
6
OUT2
5
OC2#
5V_USB2_S3
TC6202 place near
the USB2 connector
4
USB_OC#0_1 18
USB_OC#4_5 18
USB_PN3_R
12
USB_PP3_R
TC6202
TC6202
SE220U6D3VM-30-GP
SE220U6D3VM-30-GP
USB3_TX3_P18
USB3_RX3_P18
at least 80 mil
USB2
USB2
1
VBUS
2
D-
3
D+
10
10
11
11
12
12
13
13
SKT-USB13-77- GP
SKT-USB13-77- GP
22.10339.K61
22.10339.K61
USB3_TX3_P_C
1 2
C6209 SCD1U16V2KX- 3GPC6209 SCD1U16V2K X-3GP
USB3_TX3_N_C
1 2
C6210 SCD1U16V2KX- 3GPC6210 SCD1U16V2K X-3GP
STDA_SSRXSTDA_SSRX+
STDA_SSTX-
STDA_SSTX+
GND_DRAIN
1 2
1 2
1 2
5V_USB1_S3
5V_USB2_S3
GND
R6207
R6207
0R0402-PAD
0R0402-PAD
R6208
R6208
0R0402-PAD
0R0402-PAD
R6210
R6210
0R0402-PAD
0R0402-PAD
5
6
8
9
4
7
USB3_RX3_N_R
USB3_RX3_P_R
USB3_TX3_N_R
USB3_TX3_P_R
USB3_TX3_P_R
USB3_TX3_N_R
USB3_RX3_P_R
3
USB3_RX1_N_R
USB3_RX1_P_R
USB3_TX1_N_R
USB3_TX1_P_R
USB3_TX3_N_R
USB3_TX3_P_R
USB3_RX3_N_R
USB3_RX3_P_R
USB3.0 Port3
D6204
D6204
1
8
L1#1
L1#8
2
7
L2#2
L2#7
G1
G2
GND
GND
3
L3#3
L4#44L4#5
RCLAMP0524P-G P
RCLAMP0524P-G P
1st = 83.3V3U4.0A0
1st = 83.3V3U4.0A0
D6201
D6201
1
L1#1
2
L2#2
G1
GND
3
L3#3
L4#44L4#5
RCLAMP0524P-G P
RCLAMP0524P-G P
1st = 83.3V3U4.0A0
1st = 83.3V3U4.0A0
USB3_TX1_N_R
6
L3#6
5
8
L1#8
7
L2#7
G2
GND
6
L3#6
5
USB3_RX1_N_R
USB3_RX1_P_R
USB3_TX1_P_R
USB3_RX3_N_R
USB3_RX3_P_R
USB3_TX3_N_R
USB3_TX3_P_R
2
1
USB3.0 Port4
R6209
R6204
USB3_RX1_N18
B B
A A
USB3_RX1_N USB3_RX1_N_R
USB_PP1_R
USB_PN118
USB_PP118
5
R6204
1 2
0R0402-PAD
0R0402-PAD
1
2 3
R6205
R6205
1 2
0R0402-PAD
0R0402-PAD
R6206
R6206
1 2
0R0402-PAD
0R0402-PAD
5V_USB1_S3
4
D6202
D6202
PRTR5V0U2X -GP
PRTR5V0U2X -GP
DY
DY
USB_PN1_R
USB_PN1_R
USB_PP1_R
USB3_RX3_N18
USB_PP3_R USB _PN3_R
USB_PN318
USB_PP318
4
1 2
1
2 3
1 2
1 2
R6209
0R0402-PAD
0R0402-PAD
4
D6203
D6203
PRTR5V0U2X -GP
PRTR5V0U2X -GP
DY
DY
R6211
R6211
0R0402-PAD
0R0402-PAD
R6212
R6212
0R0402-PAD
0R0402-PAD
USB3_RX3_N_R
5V_USB2_S3
USB_PN3_R
USB_PP3_R
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
USB 3.0 Port*2
USB 3.0 Port*2
USB 3.0 Port*2
LA480
LA480
LA480
1
62 103
62 103
62 103
SD
SD
SD
Page 63
5
4
3
2
1
SSID = User.Interface
D D
Bluetooth conn.
3D3V_BT_S0
U6301
U6301
1
OUT
12
EC6302
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C C
EC6302
DY
DY
2
GND
OC#3EN/EN#
SY6288CAAC-GP
SY6288CAAC-GP
74.06288.07F
74.06288.07F
DY
DY
IN
5
4
3D3V_BT_IN
BLUETOOTH_EN 27,65
74.06288.07F SY6288CAAC
DIODES
BT Module pin definition is same as LA470
BT1
BT1
B B
7
1
2
3
4
5
6
8
3D3V_BT_S0
BT_LED
USB_PN4 18
USB_PP4 18
UPI
GMT
AFTP6302AFTP6302
AFTP6303AFTP6303
AFTP6304AFTP6304
AFTP6305AFTP6305
AFTP6306AFTP6306
74.02171.07F AP2171WG-7 High Active
74.07534.A7F OBS
74.05240.A7F OBS
3D3V_BT_S0
1
USB_PP4
1
USB_PN4
1
BT_LED
1
GND
1
1 2
R6301
R6301
0R0805-PAD
0R0805-PAD
High ActiveSILERGY
High Active
High Active
3D3V_S0
12
C6302
C6302
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
DY
DY
ACES-CON6-42-GP
ACES-CON6-42-GP
20.F1705.006
20.F1705.006
DY
DY
A A
5
4
3
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Bluetooth
Bluetooth
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
Bluetooth
LA480
LA480
LA480
63 103
63 103
63 103
1
SD
SD
SD
Page 64
5
4
3
2
1
Finger Printer Connector
D D
3D3V_S0
1 2
R6403
R6403
0R0805-PAD
0R0805-PAD
C C
USB_PP1018
USB_PN1018
B B
1 2
R6401 0R0402-PADR6401 0R0402-PAD
1 2
R6402 0R0402-PADR6402 0R0402-PAD
3V_FP_S0
12
C6401
C6401
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AFTP6401AFTP6401
Biometric_USBPP
Biometric_USBPN
1
AFTP6402AFTP6402
AFTP6403AFTP6403
AFTP6404AFTP6404
FPCN1
FPCN1
7
1
2
3
4
5
6
8
ACES-CON6-13-GP
ACES-CON6-13-GP
20.K0320.006
20.K0320.006
1
1
1
3V_FP_S0
Biometric_USBPN
Biometric_USBPP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
Finger Printer Connector
Finger Printer Connector
Finger Printer Connector
LA480
LA480
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
2
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
64 103
64 103
64 103
1
SD
Page 65
5
SSID = Wireless
4
3
Mini Card Connector(802.11a/b/g/n)
2
1
D D
3D3V_S5
12
R6521
R6521
10KR2J-3-GP
10KR2J-3-GP
PCIE_WLAN_WAKE#27
PCIE_WAKE#19,31,66
BLUETOOTH_EN27,63
PCIE_CLK_WLAN_REQ#20
CLK_PCIE_WLAN#20
E51_RXD27
B
12
100KR2J-1-GP
100KR2J-1-GP
AOAC
AOAC
Q6502
Q6502
R1
R1
E51_TXD27
AOAC
AOAC
R6515
R6515
AOAC_EN_2
R2
R2
C
E
BLUETOOTH_EN
54
12
R6518
R6518
10KR2J-3-GP
10KR2J-3-GP
AOAC_EN_1
5V_S5
6
321
AOAC
AOAC
C C
B B
Reserve for AOAC
3D3V_S5 +3V_MINI_WLAN
AOAC
AOAC
12
C6508
C6508
D1U10V2KX-5GP
D1U10V2KX-5GP
SC
SC
A A
AOAC_EN27
PDTC115EE-1-GP
PDTC115EE-1-GP
84.00115.C1K
84.00115.C1K
2nd = 84.09115.011
2nd = 84.09115.011
3rd = 84.00015.01H
3rd = 84.00015.01H
5
1 2
R6520 0R2J-2-GPR6520 0R2J-2-GP
1 2
R6511 0R2J-2-GP
R6511 0R2J-2-GP
R6513 0R2J-2-GPR6513 0R2J-2-GP
R6501 0R0402-PADR6501 0R0402-PAD
R6502 0R0402-PADR6502 0R0402-PAD
7
DY
DY
1 2
CLK_PCIE_WLAN20
1 2
1 2
PCIE_RXN220
PCIE_RXP220
PCIE_TXN220
PCIE_TXP220
+3V_MINI_WLAN
1 2
R6503 0R3J-0-U-GP
R6503 0R3J-0-U-GP
1 2
R6519 0R2J-2-GPR6519 0R2J-2-GP
8
AOAC
AOAC
U6501
U6501
TPCF8105-GP
TPCF8105-GP
12
DY
DY
DY
DY
R6517
R6517
10KR2J-3-GP
10KR2J-3-GP
4
PCIE_WAKE#_1
BT_ENABLE
E51_RXD_R
E51_TXD_R
+3V_MINI_WLAN
+5V_MINI_DEBUG
+1D5V_MINI_WLAN
WLAN1
WLAN1
53
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
54
TYCO-CONN52A-2-GP
TYCO-CONN52A-2-GP
20.F1743.052
20.F1743.052
LPC_AD0_C
LPC_AD1_C
LPC_AD2_C
LPC_AD3_C
LPC_FRAME#_C
CLK_PCI_LPC_C
NP1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
NP2
1D5V_S0 3D3V_S0
12
0R0805-PAD
0R0805-PAD
R6516
R6516
LPC_AD0_C
LPC_AD1_C
LPC_AD2_C
LPC_AD3_C
LPC_FRAME#_C
PLT_RST#_WLAN
G6501
G6501
G6502
G6502
G6503
G6503
G6504
G6504
G6505
G6505
G6511
G6511
3
R6510 0R0402-PADR6510 0R0402-PAD
WLAN_LED#
CLK_PCI_LPC_C
21
GAP-OPEN
GAP-OPEN
21
GAP-OPEN
GAP-OPEN
21
GAP-OPEN
GAP-OPEN
21
GAP-OPEN
GAP-OPEN
21
GAP-OPEN
GAP-OPEN
21
GAP-OPEN
GAP-OPEN
+3V_MINI_WLAN+1D5V_MINI_WLAN
+3V_MINI_WLAN
1 2
PCH_SMBCLK 14,15,20,66
PCH_SMBDATA 14,15,20,66
USB_PN11 18
USB_PP11 18
LPC_AD0 21,27,71
LPC_AD1 21,27,71
LPC_AD2 21,27,71
LPC_AD3 21,27,71
LPC_FRAME# 21,27,71
CLK_PCI_LPC 18,71
12
WIFI_RF_EN 27
PLT_RST# 5,18,27,31,36,66,71,80,82,83,97
+3V_MINI_WLAN
1
R6512
R6512
0R5J-5-GP
0R5J-5-GP
AOAC-DY
AOAC-DY
12
C6502
C6502
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C6505
C6505
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
TP6501TP6501
G6506~G6511
placememt close close WLAN1
in bottom side
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
MINICARD(WLAN)/ITP CONN
MINICARD(WLAN)/ITP CONN
MINICARD(WLAN)/ITP CONN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
Place near MINI Card CONN
2
Date: Sheet of
+3V_MINI_WLAN
12
C6503
C6503
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
+1D5V_MINI_WLAN
12
C6506
C6506
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
5V_S5
12
C6501
C6501
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
LA480
LA480
LA480
12
C6504
C6504
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C6507
C6507
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
65 103
65 103
65 103
1
SD
SD
SD
Page 66
5
SSID = Wireless
4
3
2
1
D D
mSATA for V Series Only
Place near MINI Card CONN
+3V_MINI_WWAN
C6619
C6618
C6618
12
C C
B B
C6619
SC
SC
4D7U6D3V3KX-GP
4D7U6D3V3KX-GP
12
C6606
C6606
SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
12
C6609
C6609
SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
12
C6601
C6601
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
12
C6607
C6607
SC33P50V2JN-3GP
SC33P50V2JN-3GP
12
+1D5V_MINI_WWAN
C6610
C6610
SC33P50V2JN-3GP
SC33P50V2JN-3GP
12
C6603
C6603
C6602
C6602
12
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
12
DY
DY
Place near Pin 24
+3V_MINI_WWAN+1D5V_MINI_WW AN
C6608
C6608
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C6604
C6604
12
SC33P50V2JN-3GP
SC33P50V2JN-3GP
PCIE_WAKE#19,31,65
C6611 SCD01U50V2KX-1GPC6611 SCD01U50V2KX-1GP
SATA_RXP021
SATA_RXN021
SATA_TXN021
SATA_TXP021
-MSATA_DET27
1 2
C6612 SCD01U50V2KX-1GPC6612 SCD01U50V2KX-1GP
1 2
C6614 SCD01U50V2KX-1GPC6614 SCD01U50V2KX-1GP
1 2
C6620 SCD01U50V2KX-1GPC6620 SCD01U50V2KX-1GP
1 2
Mini Card Connector(Full Card)
1D5V_S0 3D3V_S0
12
0R0805-PAD
0R0805-PAD
R6607
R6607
+1D5V_MINI_WWAN
WLAN2
WLAN2
R6604 0R2J-2-GP
R6604 0R2J-2-GP
+3V_MINI_WWAN
1 2
DY
DY
SATA_RXP0_C
SATA_RXN0_C
SATA_TXN0_C
SATA_TXP0_C
+3V_MINI_WWAN
1 2
R6608
R6608
0R0402-PAD
0R0402-PAD
53
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
54
NP1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
NP2
TYCO-CONN52A-2-GP
TYCO-CONN52A-2-GP
20.F1743.052
20.F1743.052
+3V_MINI_WWAN
PLT_RST#_WAN
PCH_SMBCLK
PCH_SMBDATA
USB_P8USB_P8+
3G_LED#
+3V_MINI_WWAN
TP6602TP6602
1
+3V_MINI_WWAN+1D5V_MINI_WWAN
1 2
R6605
R6605
0R0402-PAD
0R0402-PAD
PCH_SMBCLK 14,15,20,65
PCH_SMBDATA 14,15,20,65
12
0R0805-PAD
0R0805-PAD
R6606
R6606
PLT_RST# 5,18,27,31,36,65,71,80,82,83,97
R6603 0R3J-0-U-GP
R6603 0R3J-0-U-GP
1 2
DY
R6601 0R3J-0-U-GP
R6601 0R3J-0-U-GP
DY
1 2
DY
DY
USB_PN8 18
USB_PP8 18
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
Date: Sheet of
WWAN Connector
WWAN Connector
WWAN Connector
LA480
LA480
LA480
Taipei Hsien 221, Taiwan, R.O.C.
66 103
66 103
66 103
1
SD
SD
SD
Page 67
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
67 103
67 103
67 103
1
SD
Page 68
5
4
3
2
1
SSID = User.Interface
R6824
R6824
DY
DY
1 2
0R2J-2-GP
0R2J-2-GP
Q6810
Q6810
R2
R2
D D
C C
SATA_LED#21
APS_LED21
B
E
R1
R1
C
PDTA143ET-GP
PDTA143ET-GP
84.00143.M11
84.00143.M11
2nd = 84.02143.011
2nd = 84.02143.011
Q6802
Q6802
34
2
5
1
6
2N7002KDW-GP
2N7002KDW-GP
Q6801
Q6801
R1
R1
1
R2
R2
LTC043ZUB-FS8-GP
LTC043ZUB-FS8-GP
84.00043.011
84.00043.011
3
2
SATA_LED#_Q
12
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
NUM_LED_Q
CAP_LED 27NUM_LED27
CAP_LED_Q
APS_LED#_Q
EC6808
EC6808
NUM_LED_Q
CAP_LED_Q
SATA_LED#_Q
APS_LED#_Q
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
EC6806
EC6806
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
EC6811
EC6811
3D3V_S0
1 2
R6813 470R2J-2-GPR6813 470R2J-2-GP
1 2
R6812 470R2J-2-GPR6812 470R2J-2-GP
1 2
R6810 100R2J-2-GPR6810 100R2J-2-GP
1 2
R6818 470R2J-2-GP
R6818 470R2J-2-GP
V Series-APS
V Series-APS
12
12
EC6809
EC6809
EC6807
EC6807
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
V Series-APS
V Series-APS
NUM_LED_R
CAP_LED_R
SATA_LED#_R
APS_LED#_R
AFTP6801AFTP6801
AFTP6803AFTP6803
AFTP6804AFTP6804
AFTP6805AFTP6805
AFTP6806AFTP6806
C6813
C6813
12
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
DY
DY
1
1
1
1
1
1
LEDCN1
LEDCN1
10
8
7
6
5
4
3
2
1
9
ACES-CON8-15-GP
ACES-CON8-15-GP
20.K0315.008
20.K0315.008
AFTP6808AFTP6808
3D3V_S0
NUM_LED_R
CAP_LED_R
SATA_LED#_R
APS_LED#_R
Q6804
Q6804
34
2
DC_BATFULL27 CHARGE_LED 27
B B
KBC_PW RBTN#27
KBC_NOVO_BTN#27
PWRLED27
A A
5
5
6
2N7002KDW-GP
2N7002KDW-GP
EC6801
EC6801
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
EC6802
EC6802
1
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
DC_BATFULL#_Q
CHARGE_LED#_Q
G6801
G6801
GAP-OPEN
GAP-OPEN
2 1
1 2
R6809 100R2J-2-GPR6809 100R2J-2-GP
1 2
R6807 100R2J-2-GPR6807 100R2J-2-GP
12
12
EC6804
EC6804
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
3D3V_S5
4
DC_BATFULL#_Q
CHARGE_LED#_Q
AFTP6814AFTP6814
AFTP6813AFTP6813
KBC_PW RBTN#_R
KBC_NOVO_BTN#_R
PWRLED
12
EC6805
EC6805
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
1
1
1
2
3
4
5
6
CHARGER LED
LED2
LED2
GREEN
Yellow
1
BTNCN1
BTNCN1
7
8
ACES-CON6-22-GP-U
ACES-CON6-22-GP-U
20.K0487.006
20.K0487.006
LED-GY-8-GP-U
LED-GY-8-GP-U
83.00326.070
83.00326.070
AFTP6809AFTP6809
AFTP6810AFTP6810
AFTP6811AFTP6811
AFTP6812AFTP6812
32
CHARGE_LED#_R
1
1
1
1
3
1 2
R6802 100R2J-2-GPR6802 100R2J-2-GP
3D3V_S5
PWRLED
KBC_NOVO_BTN#_R
KBC_PW RBTN#_R
3D3V_S5
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
LED Bard/Power Button
LED Bard/Power Button
LED Bard/Power Button
LA480
LA480
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
LA480
Taipei Hsien 221, Taiwan, R.O.C.
68 103
68 103
68 103
1
SD
SD
SD
Page 69
A
B
C
D
E
Normal Pad for B Series 5V
SSID = KBC
Internal KeyBoard Connector
KROW[0..7] 27
KCOL[0..15] 27
4 4
KB14
KB14
25
KCOL15
1
KCOL10
2
KCOL11
3
KCOL14
4
KCOL13
5
KCOL12
6
KCOL3
7
KCOL6
8
KCOL8
9
KCOL7
10
KCOL4
11
KCOL2
12
KROW0
13
KCOL1
14
KCOL5
15
KROW3
16
KROW2
17
KCOL0
18
KROW5
19
KROW4
20
KCOL9
21
KROW6
22
KROW7
23
KROW1
24
26
ACES-CON 24-7-GP
ACES-CON 24-7-GP
20.K0320.024
20.K0320.024
2nd = 20.K0391.024
2nd = 20.K0391.024
3 3
KCOL15
KCOL10
KCOL11
KCOL14
KCOL13
KCOL12
KCOL3
KCOL6
KCOL8
KCOL7
KCOL4
KCOL2
KROW0
KCOL1
KCOL5
KROW3
KROW2
KCOL0
KROW5
KROW4
KCOL9
KROW6
KROW7
KROW1
GND
KB14 for 14" VB480 & VB485
KB15 for 15" VB580 & VB585
AFTP6904AFT P6904
1
AFTP6905AFT P6905
1
AFTP6906AFT P6906
1
AFTP6907AFT P6907
1
AFTP6908AFT P6908
1
AFTP6909AFT P6909
1
AFTP6910AFT P6910
1
AFTP6911AFT P6911
1
AFTP6912AFT P6912
1
AFTP6913AFT P6913
1
AFTP6914AFT P6914
1
AFTP6915AFT P6915
1
AFTP6916AFT P6916
1
AFTP6917AFT P6917
1
AFTP6918AFT P6918
1
AFTP6919AFT P6919
1
AFTP6920AFT P6920
1
AFTP6921AFT P6921
1
AFTP6922AFT P6922
1
AFTP6923AFT P6923
1
AFTP6924AFT P6924
1
AFTP6925AFT P6925
1
AFTP6926AFT P6926
1
AFTP6927AFT P6927
1
AFTP6928AFT P6928
1
SSID = Touch.Pad
5V_S0
1
23
RN6901
RN6901
SRN10KJ-5-G P
SRN10KJ-5-G P
4
TPCLK
TPCLK27
TPDATA
TPDATA27
SB 1015 Swap data and clk
56
1 2
TP_PIN6
1
TP_PIN5
1
TP_PIN4
1
TP_PIN1
1
TP_PIN2
1
TP_PIN3
1
TP_SW_L
1
TP_SW_R
1
TPSW1
TPSW1
SW-TAC T4-14-GP
SW-TAC T4-14-GP
62.40009.D71
62.40009.D71
B Series-TP
B Series-TP
43
1
AFTP6901AFT P6901
AFTP6930AFT P6930
AFTP6929AFT P6929
AFTP6931AFT P6931
AFTP6932AFT P6932
AFTP6939AFT P6939
AFTP6902AFT P6902
AFTP6903AFT P6903
RN6902
RN6902
1
2 3
SRN33J-5-G P-U
SRN33J-5-G P-U
TP_SW_L TP_SW_R
AFTP6940AFT P6940
4
TP_DATA
TP_CLK
1 2
C6903
C6903
DY
DY
TP_CLK
TP_DATA
SC100P50V2JN-3GP
SC100P50V2JN-3GP
C6904
C6904
DY
DY
1 2
SC100P50V2JN-3GP
SC100P50V2JN-3GP
1 2
TPSW2
TPSW2
SW-TAC T4-14-GP
SW-TAC T4-14-GP
56
62.40009.D71
62.40009.D71
B Series-TP
B Series-TP
5V_S0
3D3V_S0
43
1
AFTP6941AF TP6941
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
TP_SW_R
TP_SW_L
TP_DATA
12
C6901
C6901
B Series-TP
B Series-TP
12
C6902
C6902
V Series-TP
V Series-TP
ClickPad for V Series 3.3V
RN6903
RN6903
TP_PIN5
1
4
TP_PIN4
23
SRN100J-3-G P
SRN100J-3-G P
B Series-TP
B Series-TP
RN6904
RN6904
TP_PIN6
1
4
TP_PIN3
23
SRN0J-6-GP
SRN0J-6-GP
B Series-TP
B Series-TP
RN6905
RN6905
TP_PIN2TP_CLK
1
4
TP_PIN1
23
SRN0J-6-GP
SRN0J-6-GP
B Series-TP
B Series-TP
RN6906
RN6906
TP_PIN1
1
4
TP_PIN2TP_CLK
23
SRN0J-6-GP
SRN0J-6-GP
V Series-TP
V Series-TP
RN6907
TP_DATA
RN6907
4
SRN0J-6-GP
SRN0J-6-GP
V Series-TP
V Series-TP
TP_PIN3
1
TP_PIN4
23
TP_PIN1
TP_PIN2
TP_PIN3
TP_PIN4
TP_PIN5
TP_PIN6
12
TPAD1
TPAD1
7
1
2
3
4
5
6
8
ACES-CON 6-13-GP
ACES-CON 6-13-GP
20.K0320.006
20.K0320.006
R6901
R6901
0R2J-2-GP
0R2J-2-GP
DY
DY
1
AFTP6942AF TP6942
PCH_SMBCLK 14,15,20,66
PCH_SMBDAT A 14,15,20,66
2 2
1 1
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
TOUCH PAD CONNECTOR
TOUCH PAD CONNECTOR
TOUCH PAD CONNECTOR
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
LA480
LA480
LA480
E
SD
SD
69 103Friday, January 06, 2012
69 103Friday, January 06, 2012
69 103Friday, January 06, 2012
SD
Page 70
5
D D
C C
4
3
2
1
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Hall Sensor
Hall Sensor
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Hall Sensor
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
70 103
70 103
70 103
1
SD
Page 71
5
D D
C C
4
3D3V_S0
LPC_AD021,27,65
LPC_AD121,27,65
LPC_AD221,27,65
LPC_AD321,27,65
LPC_FRAME#21,27,65
PLT_RST#5,18,27,31,36,65,66,80,82,83,97
CLK_PCI_LPC18,65
3
DB1
DB1
1
2
3
4
5
6
7
8
9
10
11
12
MLX-CON10-7-GP
MLX-CON10-7-GP
20.D0183.110
DY
DY
2
1
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Dubug connector
Dubug connector
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Dubug connector
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
71 103
71 103
71 103
1
SD
Page 72
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
72 103
72 103
72 103
1
SD
Page 73
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
73 103
73 103
73 103
1
SD
Page 74
5
D D
C C
4
3
2
1
B B
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
CARD Reader CONN
CARD Reader CONN
CARD Reader CONN
LA480
LA480
LA480
1
74 103
74 103
74 103
SD
SD
SD
Page 75
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
New Card
New Card
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
New Card
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
75 103
75 103
75 103
1
SD
Page 76
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
76 103
76 103
76 103
1
SD
Page 77
5
D D
C C
4
3
2
1
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
77 103
77 103
77 103
1
SD
Page 78
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
78 103
78 103
78 103
1
SD
Page 79
5
3D3V_S5
VCC3M_Q34
EBC
D D
R2
R2
Q7901
Q7901
PDTA114EE-3-GP-U
PDTA114EE-3-GP-U
84.00114.H1K
84.00114.H1K
R1
R1
2nd = 84.09114.A11
2nd = 84.09114.A11
3rd = 84.00014.01H
3rd = 84.00014.01H
4
1 2
R7901
R7901
10R2J-2-GP
10R2J-2-GP
VCC3_ACC
12
C7901
C7901
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
3
C7902
12
C7902
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
G-Sensor
2
1
V Series Only
8
10
12
11
13
16
ANALOG_AGND
GSENSE_Z
GSENSE_Y_R
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
GSENSE_X_R
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
12
C7904
C7904
ANALOG_AGND
12
C7905
C7905
ANALOG_AGND
TP7901TP7901
1 2
R7906 56KR2J-L1-GPR7906 56KR2J-L1-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2
R7907 56KR2J-L1-GPR7907 56KR2J-L1-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C7907
C7907
C7908
C7908
12
12
GSENSE_Y 27
GSENSE_X 27
GSENSE_ON#27
100KR2J-1-GP
100KR2J-1-GP
C C
TP7902TP7902
100KR2J-1-GP
100KR2J-1-GP
R7903
R7903
1
12
ROHM-KIONIX
B B
KXTC8-2850-GP
12
R7902
R7902
DY
DY
ANALOG_AGND
74.KXTC8.0BZ
GSENSE_TST
12
R7904
R7904
0R0402-PAD
0R0402-PAD
15
14
U7901
U7901
2
ST
3
GND
5
GND
6
GND
7
GND
1
NC#1
4
NC#4
9
NC#9
LIS34ALTR-GP
LIS34ALTR-GP
2nd = 74.KXTC8.0BZ
2nd = 74.KXTC8.0BZ
RES
VDD
VOUTZ
VOUTY
VOUTX
NC#11
NC#13
NC#16
<Core Design>
<Core Design>
<Core Design>
A A
5
Layout Comment :
(1) Place C483, C484, Q46, R528, R530,
C479, C476, R509, R508 close to U55.
(2) Avoid routing under DCDC switching area.
4
3
Title
Title
Title
G-Sensor
G-Sensor
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
G-Sensor
LA480
LA480
LA480
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
79 103
79 103
79 103
1
SD
Page 80
5
D D
4
3
2
1
RFID
3D3V_S0
Q8001
C C
Q8001
R1
R1
B
PDTC115TE-GP
PDTC115TE-GP
84.00115.E1K
84.00115.E1K
2nd = 84.09115.A11
2nd = 84.09115.A11
3rd = 84.00015.B1H
3rd = 84.00015.B1H
C
E
3D3V_S5
12
R8001
R8001
4K7R2J-2-GP
4K7R2J-2-GP
PROT_EEPROM
PLT_RST# 5,18,27,31,36,65,66,71,82,83,97
U8001
U8001
1
NC#1
2
NC#2
3
PROT#
4
GND
BUL08-1FVJ-WGE2-GP
BUL08-1FVJ-WGE2-GP
72.BUL08.A0Q
72.BUL08.A0Q
2nd = 72.24S08.A0Q
2nd = 72.24S08.A0Q
3rd = 72.26C08.00R
3rd = 72.26C08.00R
VCC
WP
SCL
SDA
3D3V_S5
8
7
6
5
SMB_CLK 20
SMB_DATA 20
12
C8001
C8001
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
Table 80.1- Transistor multi-source
Supplier
B B
ROHM
Panasonic
Description Lenovo P/N Wistron P/N
PDTC115TE
LTC015TEB
DRC9115T0L
N/A
N/A
N/A
84.00115.E1KNXP
84.00015.B1H
84.09115.A11
Table 80.2- EEPROM multi-source
Supplier
ROHM
A A
NXP
SANYO
5
Description Lenovo P/N Wistron P/N
BUL08-1FVJ-WGE2
PCA24S08ADP
LE26CAP08TT-TLM-H 72.26C08.00R
N/A
N/A
N/A
72.BUL08.A0Q
72.24S08.A0Q
4
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
RF ID
RF ID
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
3
Date: Sheet of
2
RF ID
LA480
LA480
LA480
80 103
80 103
80 103
1
SD
SD
SD
Page 81
5
D D
4
3
2
1
C C
B B
A A
5
BLANK
4
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
81 103
81 103
81 103
1
SD
SD
SD
Page 82
5
R8201 and R8203 Dual layout with TR8201
D D
USB_PW R_EN_R27,61,62
C C
CHG_USB_OC#27
USB_CHG_EN27
4
RN8202
RN8202
USB_OC#8_918
1
2 3
SRN0J-6-GP
SRN0J-6-GP
B Series-USB PWR
B Series-USB PWR
RN8201
RN8201
1
2 3
SRN0J-6-GP
SRN0J-6-GP
V Series-USB PWR
V Series-USB PWR
4
4
USB_PW R_OC#
USB_PW R_EN
USB_PW R_OC#
USB_PW R_EN
3
USB_PN218
34
2
TR8202
TR8202
FILTER-130-GP
FILTER-130-GP
1st = 68.11900.20A
1st = 68.11900.20A
USB_PP218
1
USB_PN2_R
USB_PP2_R
2
3D3V_AUX_S5
ADP_LED27
AFTP8201AFTP8201
AFTP8202AFTP8202
AFTP8203AFTP8203
AFTP8204AFTP8204
AFTP8205AFTP8205
AFTP8210AFTP8210
AFTP8213AFTP8213
AFTP8223AFTP8223
AFTP8212AFTP8212
AFTP8209AFTP8209
12
EC8202
EC8202
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
USB_PN2_R
USB_PP2_R
AFTP8206AFTP8206
5V_USB4_S3
5V_USB4_S3
1
3D3V_AUX_S5
1
ADP_LED
1
USB_PN2_R
1
USB_PP2_R
1
HPOUT_JD
1
USB_PW R_OC#
1
USB_PW R_EN
1
USB_AO_SEL0
1
AUD_MIC1_COMBO_R
1
1
USBCN1
USBCN1
11
1
2
3
4
5
6
7
8
9
1
10
12
ACES-CON10-19-GP
ACES-CON10-19-GP
20.K0420.010
20.K0420.010
USB_PN918
34
2
TR8201
TR8201
FILTER-130-GP
FILTER-130-GP
1st = 68.11900.20A
1st = 68.11900.20A
1
USB_PP918
B B
USB_PN518
USB_PP518
A A
5
1 2
1 2
R82060R0402-PAD R82060R0402-PAD
R82070R0402-PAD R82070R0402-PAD
USB_PN9_R
USB_PP9_R
USB_PN5_R
USB_PP5_R
CDRCN1
CDRCN1
32
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
31
ACES-CON30-9-GP-U
ACES-CON30-9-GP-U
20.K0510.030
20.K0510.030
4
AUD_HPOUT_R 29
AUD_HPOUT_L 29
AUD_MIC1_COMBO_R 29
HPOUT_JD 29
USB_PW R_OC#
USB_PP5_R
USB_PN5_R
USB_PP9_R
USB_PN9_R
USB_PW R_EN
12
EC8201
EC8201
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
3
USB_AO_SEL0 27
AU_GND
Cardreader
USB Port3
CLK_PCH_48M 20
PLT_RST# 5,18,27,31,36,65,66,71,80,83,97
3D3V_S0_CARD
5V_S5
2
AFTP8207AFTP8207
AFTP8208AFTP8208
AFTP8211AFTP8211
AFTP8214AFTP8214
AFTP8215AFTP8215
AFTP8216AFTP8216
AFTP8217AFTP8217
AFTP8218AFTP8218
AFTP8219AFTP8219
AFTP8220AFTP8220
AFTP8221AFTP8221
AFTP8224AFTP8224
AFTP8222AFTP8222
AFTP8225AFTP8225
1 2
R8202
R8202
0R0805-PAD
0R0805-PAD
CLK_PCH_48M
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
AUD_HPOUT_R
1
AUD_HPOUT_L
1
AU_GND
1
USB_PP5_R
1
USB_PN5_R
1
USB_PP9_R
1
USB_PN9_R
1
CLK_PCH_48M
1
PLT_RST#
1
3D3V_S0_CARD
1
5V_S5
1
1
GND
1
1
3D3V_S0_CARD3D3V_S0
12
EC8203
EC8203
DY
DY
SC22P50V2JN-4GP
SC22P50V2JN-4GP
IO Board Connector
IO Board Connector
IO Board Connector
LA480
LA480
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
LA480
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
82 103
82 103
82 103
1
SD
SD
SD
Page 83
5
4
3
2
1
PCI Express PEX_IOVVD/Q Combined (DG-05587-001_v03_p.72_Table 10)
Footprint PopulationCapacitor Type Location
1.0uF
X6S
SPEC. (DG-05587-001_v03_p.70)
PEX_CLK_REQ_N is an open-drain bi-directional signal;
by default it should have a 10 kΩ pull-up to 3.3V.
D D
PEG_CLKREQ#20
C C
SPEC. (DG-05587-001_v03_p.70)
For PCI ECPRESS connection,
please use 0.22uF,20%,0402,X5R
or better AC couplimg capacitors.
PEG_TXP[0..15]4
PEG_TXN[0..15]4
OPS
OPS
Q8301
Q8301
D
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
0.22uF(X5R)
K0402
3D3V_VGA_S0
G
S
B B
PEG_RXP[0..15] 4
PEG_RXN[0..15] 4
PEG_RXP0 PEG_C_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXN2
PEG_RXP3
PEG_RXN3
PEG_RXP4
PEG_RXN4
PEG_RXP5
PEG_RXN5
PEG_RXP6
PEG_RXN6
PEG_RXP7
PEG_RXN7
PEG_RXP8
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15
A A
5
This signal is an active low signal.
3D3V_VGA_S0
OPS
OPS
12
12
DY
DY
R8303
R8303
R8302
R8302
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
VGA_RST#
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
VGA_PEG_CLKR EQ#
C8301SCD22U10V2KX -1GP
C8301SCD22U10V2KX -1GP
PEG_C_RXN0
C8302SCD22U10V2KX -1GP
C8302SCD22U10V2KX -1GP
PEG_TXP0
PEG_TXN0
PEG_C_RXP1
C8304SCD22U10V2KX -1GP
C8304SCD22U10V2KX -1GP
PEG_C_RXN1
C8303SCD22U10V2KX -1GP
C8303SCD22U10V2KX -1GP
PEG_TXP1
PEG_TXN1
PEG_C_RXP2
C8306SCD22U10V2KX -1GP
C8306SCD22U10V2KX -1GP
PEG_C_RXN2
C8305SCD22U10V2KX -1GP
C8305SCD22U10V2KX -1GP
PEG_TXP2
PEG_TXN2
PEG_C_RXP3
C8308SCD22U10V2KX -1GP
C8308SCD22U10V2KX -1GP
PEG_C_RXN3
C8307SCD22U10V2KX -1GP
C8307SCD22U10V2KX -1GP
PEG_TXP3
PEG_TXN3
PEG_C_RXP4
C8310SCD22U10V2KX -1GP
C8310SCD22U10V2KX -1GP
PEG_C_RXN4
C8309SCD22U10V2KX -1GP
C8309SCD22U10V2KX -1GP
PEG_TXP4
PEG_TXN4
PEG_C_RXP5
C8312SCD22U10V2KX -1GP
C8312SCD22U10V2KX -1GP
PEG_C_RXN5
C8311SCD22U10V2KX -1GP
C8311SCD22U10V2KX -1GP
PEG_TXP5
PEG_TXN5
PEG_C_RXP6
C8314SCD22U10V2KX -1GP
C8314SCD22U10V2KX -1GP
PEG_C_RXN6
C8313SCD22U10V2KX -1GP
C8313SCD22U10V2KX -1GP
PEG_TXP6
PEG_TXN6
PEG_C_RXP7
C8316SCD22U10V2KX -1GP
C8316SCD22U10V2KX -1GP
PEG_C_RXN7
C8315SCD22U10V2KX -1GP
C8315SCD22U10V2KX -1GP
PEG_TXP7
PEG_TXN7
PEG_C_RXP8
C8318SCD22U10V2KX -1GP
C8318SCD22U10V2KX -1GP
PEG_C_RXN8
C8317SCD22U10V2KX -1GP
C8317SCD22U10V2KX -1GP
PEG_TXP8
PEG_TXN8
PEG_C_RXP9
C8320SCD22U10V2KX -1GP
C8320SCD22U10V2KX -1GP
PEG_C_RXN9
C8319SCD22U10V2KX -1GP
C8319SCD22U10V2KX -1GP
PEG_TXP9
PEG_TXN9
PEG_C_RXP10
C8322SCD22U10V2KX -1GP
C8322SCD22U10V2KX -1GP
PEG_C_RXN10
C8321SCD22U10V2KX -1GP
C8321SCD22U10V2KX -1GP
PEG_TXP10
PEG_TXN10
PEG_C_RXP11
C8324SCD22U10V2KX -1GP
C8324SCD22U10V2KX -1GP
PEG_C_RXN11
C8323SCD22U10V2KX -1GP
C8323SCD22U10V2KX -1GP
PEG_TXP11
PEG_TXN11
PEG_C_RXP12
C8326SCD22U10V2KX -1GP
C8326SCD22U10V2KX -1GP
PEG_C_RXN12
C8325SCD22U10V2KX -1GP
C8325SCD22U10V2KX -1GP
PEG_TXP12
PEG_TXN12
PEG_C_RXP13
C8328SCD22U10V2KX -1GP
C8328SCD22U10V2KX -1GP
PEG_C_RXN13
C8327SCD22U10V2KX -1GP
C8327SCD22U10V2KX -1GP
PEG_TXP13
PEG_TXN13
PEG_C_RXP14
C8330SCD22U10V2KX -1GP
C8330SCD22U10V2KX -1GP
PEG_C_RXN14
C8329SCD22U10V2KX -1GP
C8329SCD22U10V2KX -1GP
PEG_TXP14
PEG_TXN14
PEG_C_RXP15
C8332SCD22U10V2KX -1GP
C8332SCD22U10V2KX -1GP
PEG_C_RXN15
C8331SCD22U10V2KX -1GP
C8331SCD22U10V2KX -1GP
PEG_TXP15
PEG_TXN15
CLK_PCIE_VGA20
CLK_PCIE_VGA#20
1 OF 17
1 OF 17
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_PLL_HVDD
PEX_SVDD_3V3
VDD_SENSE
GND_SENSE
NC_3V3AUX
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
PEX_PLLVDD
TESTMODE
PEX_TERMP
SPEC. (DG-05587-001_v03_p.214)
By default, pull-down the TESTMODE pin to GND with a 10kΩ resistor.
For XOR tree testing, TESTMODE should be pulled up to 3v3 with a 10 kΩ resistor.
SPEC. (DG-05587-001_v03_p.70)
PEX_TERMP is used for internal calibration;
pull-down this signal with 2.49 kΩ,1% resistor.
AK12
AK13
AK14
AN12
AM12
AH14
AG14
AN14
AM14
AK15
AP14
AP15
AK16
AN15
AM15
AK17
AN17
AM17
AH17
AG17
AP17
AP18
AK18
AN18
AM18
AK19
AN20
AM20
AK20
AP20
AP21
AH20
AG20
AN21
AM21
AK21
AN23
AM23
AK22
AP23
AP24
AK23
AN24
AM24
AH23
AG23
AN26
AM26
AK24
AP26
AP27
AK25
AN27
AM27
AJ11
AJ12
AL13
AJ14
AJ15
AL16
AJ17
AJ18
AL19
AJ20
AJ21
AL22
AJ23
AJ24
AL25
VGA1A
VGA1A
1/17 PCI_EXPRESS
1/17 PCI_EXPRESS
PEX_WAKE#
PEX_RST#
PEX_CLKREQ#
PEX_REFCLK
PEX_REFCLK#
PEX_TX0
PEX_TX0#
PEX_RX0
PEX_RX0#
PEX_TX1
PEX_TX1#
PEX_RX1
PEX_RX1#
PEX_TX2
PEX_TX2#
PEX_RX2
PEX_RX2#
PEX_TX3
PEX_TX3#
PEX_RX3
PEX_RX3#
PEX_TX4
PEX_TX4#
PEX_RX4
PEX_RX4#
PEX_TX5
PEX_TX5#
PEX_RX5
PEX_RX5#
PEX_TX6
PEX_TX6#
PEX_RX6
PEX_RX6#
PEX_TX7
PEX_TX7#
PEX_RX7
PEX_RX7#
PEX_TX8
PEX_TX8#
PEX_RX8
PEX_RX8#
PEX_TX9
PEX_TX9#
PEX_RX9
PEX_RX9#
PEX_TX10
PEX_TX10#
PEX_RX10
PEX_RX10#
PEX_TX11
PEX_TX11#
PEX_RX11
PEX_RX11#
PEX_TX12
PEX_TX12#
PEX_RX12
PEX_RX12#
PEX_TX13
PEX_TX13#
PEX_RX13
PEX_RX13#
PEX_TX14
PEX_TX14#
PEX_RX14
PEX_RX14#
PEX_TX15
PEX_TX15#
PEX_RX15
PEX_RX15#
N13P-GS-A1-G P
N13P-GS-A1-G P
OPS-BOM CTRL
OPS-BOM CTRL
4
4.7uF
10uF
22uF
X6S (+/-22%、-55~105℃)
X5R (+/-15%、-55~85℃)
OPS
OPS
12
C8333
C8333
AG19
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
AG21
AG22
AG24
AH21
AH25
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
1uF(X5R)
K0402 ×4
OPS
OPS
12
C8340
C8340
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
Under GPU
PCI Express PEX_SVDD/PLL_HVDD Connected to NV3V3 (DG-05587-001_v03_p.72_Table 12)
0.1uF
4.7uF
X5R (+/-15%、-55~85℃)
AH12
AG12
0.1uF(X5R)
K0402 ×1
OPS
OPS
12
C8347
C8347
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Near GPU
L4
L5
P8
SPEC. (DG-05587-001_v03_p.70)
PEX_TSTCLK_OUT should be
terminated with a 200Ω resistor.
PEX_TSTCLK_O UT
AJ26
PEX_TSTCLK_O UT#
AK26
OPS
OPS
TESTMODE
1 2
R8307 10KR 2J-3-GP
R8307 10KR 2J-3-GP
OPS
OPS
PEX_TERMP
1 2
R8309 2K49R2F-GP
R8309 2K49R2F-GP
VCC1R05VIDEO _PEX_PLLVDD
AG26
AK11
AP29
0402
X6S
0603
X5R
0805
X5R
0805
OPS
OPS
12
C8334
C8334
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
4.7uF(X5R)
K0603 ×2
OPS
OPS
12
C8341
C8341
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
Near GPU
Footprint PopulationCapacitor Type Location
X5R
0402
X5R
0603
OPS
OPS
12
C8348
C8348
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1 2
R8304 0R2J-2-GP
R8304 0R2J-2-GP
12
R8305
R8305
0R2J-2-GP
0R2J-2-GP
DY
DY
OPS
OPS
R8306 200R2F-L-GP
R8306 200R2F-L-GP
12
DY
DY
1 2
R8308 10KR2J-3- GP
R8308 10KR2J-3- GP
3
4
Under GPU
2
Near GPU
4
Midway Between GPU and Power Supply
4
Midway Between GPU and Power Supply
OPS
OPS
12
C8335
C8335
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
OPS
OPS
12
C8342
C8342
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
OPS
OPS
12
C8336
C8336
SC10U6D3V3MX- GP
SC10U6D3V3MX- GP
10uF(X5R)
M0805 ×4
OPS
OPS
12
C8343
C8343
SC10U6D3V3MX- GP
SC10U6D3V3MX- GP
Midway Between GPU and Power Supply
12Near GPU
Near GPU
3.3V ±10% 210mA total
(DG-05587-001_v03_p.71_Table 9)
OPS
OPS
12
4.7uF(X5R)
C8349
C8349
K0603 ×2
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
VGA_CORE
DY
DY
NVVDD_SEN SE 92
NVGND_SEN SE 92
3D3V_VGA_S0
PCI Express PEX_PLLVDD (DG-05587-001_v03_p.72_Table 11)
100nF
1.0uF
4.7uF
X6S (+/-22%、-55~105℃)
X5R (+/-15%、-55~85℃)
3D3V_VGA_S0
100nF(X7R)
K0402 ×1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1.0nF(X5R)
K0402 ×1
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
OPS
OPS
C8350
C8350
Under GPU Near GPU
1.05V ±30mV 3300mA total
OPS
OPS
12
C8339
C8339
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
22uF(X5R)
M0805 ×4
OPS
OPS
OPS
OPS
12
12
C8346
C8346
C8345
C8345
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
X6S
X5R
X5R
4.7nF(X5R)
K0603 ×1
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
OPS
OPS
C8351
C8351
12
1D05V_VGA_S0
(DG-05587-001_v03_p.71_Table 9)
dGPU reset
PLT_RST#5,18,27,31,36,65,66,71,80,82,97
DGPU_HOLD _RST#1 8
PopulationFootprint
0402
0603
0805
1.05V ±30mV 150mA total
(DG-05587-001_v03_p.71_Table 9)
OPS
OPS
C8352
C8352
R8310 0R2J-2-G P
R8310 0R2J-2-G P
PLT_RST#
LocationCapacitor Type
Under GPU
1
Near GPU
1
Near GPU
1
Stuff 0 ohm(63.00000.00L) for N13P-GS/N13M-GS,
Stuff bead(68.00082.001) for N13P-GL/N13M-GE
2
DY
DY
VGA_RST#
1 2
U8301
U8301
1
B
VCC
2
A
Y
3
GND
74LVC1G08GW -1-GP
74LVC1G08GW -1-GP
73.01G08.L04
73.01G08.L04
OPS
OPS
1st = 73.01G08.DHG
1st = 73.01G08.DHG
2nd = 73.7SZ08.DAH
2nd = 73.7SZ08.DAH
3rd = 73.01G08.FHG
3rd = 73.01G08.FHG
3D3V_S0
5
VGA_RST#
4
OPS-BOM CTRL
OPS-BOM CTRL
R8311
R8311
R8319
R8319
OPS
OPS
10KR2J-3-GP
10KR2J-3-GP
1 2
1D05V_VGA_S0
12
0R3J-0-U-G P
0R3J-0-U-G P
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
N13P_GPU (1/5): PEG
N13P_GPU (1/5): PEG
N13P_GPU (1/5): PEG
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
LA48
LA48
LA48
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C
1
SD
SD
83 103Friday, January 06, 2012
83 103Friday, January 06, 2012
83 103Friday, January 06, 2012
SD
Page 84
A
LVDS Interface
TP8402TP8402
12
R8403
R8403
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
IFPEF_IOVDD
12
R8404
R8404
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
TP8401TP8401
IFPEF_PLLVDD
IFPF_REST
1
4 4
SPEC. (DG-05587-001_v03_p.160)
Pull down IFPxy IOVDD with 10kΩ resistor.
Pull down IFPxy PLLVDD with 10kΩ resistor.
The other IO pins can be NC, this includes unused data lines.
3 3
2 2
1 1
IFPAB_RSET
1
IFPAB_PLLVDD
12
R8401
R8401
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
IFPAB_IOVDD
12
R8402
R8402
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
AB8
AD6
AC7
AC8
B
VGA1M
VGA1M
8/17 IFPEF
8/17 IFPEF
IFPEF_PLLVDD
IFPEF_RSET
IFPE
IFPE
IFPE_IOVDD
IFPF_IOVDD
IFPF
IFPF
N13P-GS-A1-G P
N13P-GS-A1-G P
OPS-BOM CTRL
OPS-BOM CTRL
VGA1J
VGA1J
5/17 IFPAB
5/17 IFPAB
ALL PINS NC FOR GF117
ALL PINS NC FOR GF117
AJ8
IFPAB_RSET
AH8
IFPAB_PLLVDD
AG8
IFPA_IOVDD
AG9
IFPB_IOVDD
IFPAB
IFPAB
N13P-GS-A1-G P
N13P-GS-A1-G P
OPS-BOM CTRL
OPS-BOM CTRL
ALL PINS NC FOR GF117
ALL PINS NC FOR GF117
DVI-DL DVI-SL/HDMI DP
DVI-DL DVI-SL/HDMI DP
I2CY_SDA
I2CY_SDA
I2CY_SCL I2CY_SCL
I2CY_SCL I2CY_SCL
TXC
TXC
TXC
TXC
TXD0
TXD0
TXD0
TXD0
TXD1
TXD1
TXD1
TXD1
TXD2
TXD2
TXD2
TXD2
HPD_E
HPD_E
TXD3
TXD3
TXD3
TXD3
TXD4
TXD4
TXD4
TXD4
TXD5
TXD5
TXD5
TXD5
I2CY_SDA
I2CY_SDA
TXC
TXC
TXC
TXC
TXD0
TXD0
TXD0
TXD0
TXD1
TXD1
TXD1
TXD1
TXD2
TXD2
TXD2
TXD2
HPD_E
HPD_E
I2CZ_SDA
I2CZ_SDA
I2CZ_SCL
I2CZ_SCL
TXC
TXC
TXC
TXC
TXD0
TXD0
TXD0
TXD0
TXD1
TXD1
TXD1
TXD1
TXD2
TXD2
TXD2
TXD2
HPD_F
HPD_F
10 OF 17
10 OF 17
IFPA_TXC#
IFPA_TXC
IFPA_TXD0#
IFPA_TXD0
IFPA_TXD1#
IFPA_TXD1
IFPA_TXD2#
IFPA_TXD2
IFPA_TXD3#
IFPA_TXD3
IFPB_TXC#
IFPB_TXC
IFPB_TXD4#
IFPB_TXD4
IFPB_TXD5#
IFPB_TXD5
IFPB_TXD6#
IFPB_TXD6
IFPB_TXD7#
IFPB_TXD7
GPIO14
13 OF 17
13 OF 17
IFPE_AUX_I2CY_SDA#
IFPE_AUX_I2CY_SCL
IFPE_L3#
IFPE_L3
IFPE_L2#
IFPE_L2
IFPE_L1#
IFPE_L1
IFPE_L0#
IFPE_L0
GPIO18
IFPF_AUX_I2CZ_SDA#
IFPF_AUX_I2CZ_SCL
IFPF_L3#
IFPF_L3
IFPF_L2#
IFPF_L2
IFPF_L1#
IFPF_L1
IFPF_L0#
IFPF_L0
GPIO19
C
AN6
AM6
AN3
AP3
AM5
AN5
AK6
AL6
AH6
AJ6
AH9
AJ9
AP5
AP6
AL7
AM7
AM8
AN8
AL8
AK8
N4
TP8403TP8403
1
12
R8405
R8405
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
12
R8406
R8406
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
IFPC_RSET
IFPC_PLLVDD
IFPC_IOVDD
HDMI Interface
1
12
12
IFPD_RSET
IFPD_PLLVDD
R8407
R8407
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
IFPD_IOVDD
R8408
R8408
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
AB4
AB3
AC5
AC4
AC3
AC2
AC1
AD1
AD3
AD2
R1
AF2
AF3
AF1
AG1
AD5
AD4
AF5
AF4
AE4
AE3
P3
TP8404TP8404
VGA1K
VGA1K
6/17 IFPC
6/17 IFPC
AF8
IFPC_RSET
AF7
IFPC_PLLVDD
AF6
IFPC_IOVDD
N13P-GS-A1-G P
N13P-GS-A1-G P
OPS-BOM CTRL
OPS-BOM CTRL
VGA1L
VGA1L
7/17 IFPD
7/17 IFPD
AN2
IFPD_RSET
AG7
IFPD_PLLVDD
AG6
IFPD_IOVDD
N13P-GS-A1-G P
N13P-GS-A1-G P
OPS-BOM CTRL
OPS-BOM CTRL
D
ALL PINS NC FOR GF117
ALL PINS NC FOR GF117
DVI/HDMI DP
DVI/HDMI DP
I2CW_SDA
I2CW_SDA
I2CW_SCL
I2CW_SCL
TXC
TXC
TXC
TXC
TXD0
TXD0
IFPC
IFPC
TXD0
TXD0
TXD1
TXD1
TXD1
TXD1
TXD2
TXD2
TXD2
TXD2
ALL PINS NC FOR GF117
ALL PINS NC FOR GF117
DVI/HDMI
DVI/HDMI
I2CX_SDA
I2CX_SDA
I2CX_SCL
I2CX_SCL
TXC
TXC
TXC
TXC
TXD0
TXD0
IFPD
IFPD
TXD0
TXD0
TXD1
TXD1
TXD1
TXD1
TXD2
TXD2
TXD2
TXD2
11 OF 17
11 OF 17
IFPC_AUX_I2CW_SDA#
IFPC_AUX_I2CW_SCL
IFPC_L3#
IFPC_L3
IFPC_L2#
IFPC_L2
IFPC_L1#
IFPC_L1
IFPC_L0#
IFPC_L0
GPIO15
12 OF 17
12 OF 17
DP
DP
IFPD_AUX_I2CX_SDA#
IFPD_AUX_I2CX_SCL
IFPD_L3#
IFPD_L3
IFPD_L2#
IFPD_L2
IFPD_L1#
IFPD_L1
IFPD_L0#
IFPD_L0
GPIO17
E
AG2
AG3
AG4
AG5
AH4
AH3
AJ2
AJ3
AJ1
AK1
P2
AK2
AK3
AK5
AK4
AL4
AL3
AM4
AM3
AM2
AM1
M6
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
N13P_GPU (2/5): DIGITALOUT
N13P_GPU (2/5): DIGITALOUT
N13P_GPU (2/5): DIGITALOUT
Size Docu ment Numbe r Rev
Size Docu ment Numbe r Rev
Size Docu ment Numbe r Rev
A2
A2
A2
LA48
LA48
LA48
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
E
SD
SD
84 103Friday, Januar y 06, 2012
84 103Friday, Januar y 06, 2012
84 103Friday, Januar y 06, 2012
SD
Page 85
5
VGA1B
VGA1B
2/17 FBA
FBA_D[63..0]
D D
C C
B B
TP8507TP8507
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_DQM088
FBA_DQM188
FBA_DQM288
FBA_DQM388
FBA_DQM489
FBA_DQM589
FBA_DQM689
FBA_DQM789
FBA_DQS_W P088
FBA_DQS_W P188
FBA_DQS_W P288
FBA_DQS_W P388
FBA_DQS_W P489
FBA_DQS_W P589
FBA_DQS_W P689
FBA_DQS_W P789
FBA_DQS_RN 088
FBA_DQS_RN 188
FBA_DQS_RN 288
FBA_DQS_RN 388
FBA_DQS_RN 489
FBA_DQS_RN 589
FBA_DQS_RN 689
FBA_DQS_RN 789
FB_VREF FB_PLLVDD
1
2/17 FBA
L28
FBA_D0
M29
FBA_D1
L29
FBA_D2
M28
FBA_D3
N31
FBA_D4
P29
FBA_D5
R29
FBA_D6
P28
FBA_D7
J28
FBA_D8
H29
FBA_D9
J29
FBA_D10
H28
FBA_D11
G29
FBA_D12
E31
FBA_D13
E32
FBA_D14
F30
FBA_D15
C34
FBA_D16
D32
FBA_D17
B33
FBA_D18
C33
FBA_D19
F33
FBA_D20
F32
FBA_D21
H33
FBA_D22
H32
FBA_D23
P34
FBA_D24
P32
FBA_D25
P31
FBA_D26
P33
FBA_D27
L31
FBA_D28
L34
FBA_D29
L32
FBA_D30
L33
FBA_D31
AG28
FBA_D32
AF29
FBA_D33
AG29
FBA_D34
AF28
FBA_D35
AD30
FBA_D36
AD29
FBA_D37
AC29
FBA_D38
AD28
FBA_D39
AJ29
FBA_D40
AK29
FBA_D41
AJ30
FBA_D42
AK28
FBA_D43
AM29
FBA_D44
AM31
FBA_D45
AN29
FBA_D46
AM30
FBA_D47
AN31
FBA_D48
AN32
FBA_D49
AP30
FBA_D50
AP32
FBA_D51
AM33
FBA_D52
AL31
FBA_D53
AK33
FBA_D54
AK32
FBA_D55
AD34
FBA_D56
AD32
FBA_D57
AC30
FBA_D58
AD33
FBA_D59
AF31
FBA_D60
AG34
FBA_D61
AG32
FBA_D62
AG33
FBA_D63
P30
FBA_DQM0
F31
FBA_DQM1
F34
FBA_DQM2
M32
FBA_DQM3
AD31
FBA_DQM4
AL29
FBA_DQM5
AM32
FBA_DQM6
AF34
FBA_DQM7
M31
FBA_DQS_WP0
G31
FBA_DQS_WP1
E33
FBA_DQS_WP2
M33
FBA_DQS_WP3
AE31
FBA_DQS_WP4
AK30
FBA_DQS_WP5
AN33
FBA_DQS_WP6
AF33
FBA_DQS_WP7
M30
FBA_DQS_RN0
H30
FBA_DQS_RN1
E34
FBA_DQS_RN2
M34
FBA_DQS_RN3
AF30
FBA_DQS_RN4
AK31
FBA_DQS_RN5
AM34
FBA_DQS_RN6
AF32
FBA_DQS_RN7
THE FBA_WCKBxx
THE FBA_WCKBxx
PINS ARE USED
PINS ARE USED
ONLY ON GK107
ONLY ON GK107
THEY ARE NC
THEY ARE NC
FOR GF108
FOR GF108
AND FOR GF117
AND FOR GF117
H26
FB_VREF
N13P-GS-A1-G P
N13P-GS-A1-G P
OPS-BOM CTRL
OPS-BOM CTRL
FBx_PLL_AVDD, FB_DLL_AVDD and PLLVDD combined
(DG-05587-001_v03_p.88_Table 26)
FB_CLAMP
FB_DLL_AVDD
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD_RFU0
FBA_CMD_RFU1
FBA_DEBUG0
FBA_DEBUG1
FBA_CLK0#
FBA_CLK1#
FBA_WCK1
FBA_WCK1#
FBA_WCK23
FBA_WCK23#
FBA_WCK45
FBA_WCK45#
FBA_WCK67
FBA_WCK67#
FBA_WCKB1
FBA_WCKB1#
FBA_WCKB23
FBA_WCKB23#
FBA_WCKB45
FBA_WCKB45#
FBA_WCKB67
FBA_WCKB67#
FBA_PLL_AVDD
Capacitor Type Footprint Population Location
X7R
100nF
22uF
Bead Type
30Ω @100MHz
(ESR=0.01Ω)
X7R (+/-15%、-55~125℃)
A A
X5R (+/-15%、-55~85℃)
0402
X5R
0805
0603 1 Near GPU
1 per pin
1
5
E1 (DA-05691-001_v03_p.4_Table 2)
N13P-GL NC
2 OF 17
2 OF 17
N13M_GE1 NC
N13M-GS Pull down FB_CLAMP with a 10kΩ
N13P-GS Pull down FB_CLAMP with a 10kΩ
PS_FB_CLAMP
E1
K27
(DG-05587-001_v03_p.88_Table 25)
FB CMD mapping
Mode D-N13x
U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31
R32
AC32
R28
AC28
R30
FBA_CLK0
R31
AB31
FBA_CLK1
AC31
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
U27
1 2
R8522 10KR 2F-2-GP
R8522 10KR 2F-2-GP
DY
DY
FB_PLLVDD
35mA
FBA_CS0# 88
FBA_ODT0 88
FBA_CKE0 88
FBA_RST 88,89
FBA_A9 88,89
FBA_A7 88,89
FBA_A2 88,89
FBA_A0 88,89
FBA_A4 88,89
FBA_A1 88,89
FBA_BA0 88,8 9
FBA_WE# 88,89
FBA_A15 88,89
FBA_CAS# 88,89
FBA_CS1# 89
FBA_ODT1 89
FBA_CKE1 89
FBA_A13 88,89
FBA_A8 88,89
FBA_A6 88,89
FBA_A11 88,89
FBA_A5 88,89
FBA_A3 88,89
FBA_BA2 88,8 9
FBA_BA1 88,8 9
FBA_A12 88,89
FBA_A10 88,89
FBA_RAS# 88,89
1 2
DY
DY
1 2
DY
DY
FBA_CLK0 88
FBA_CLK0# 88
FBA_CLK1 89
FBA_CLK1# 89
1D5V_VGA_S0
R8518 60D4R 2F-GP
R8518 60D4R 2F-GP
R8519 10KR2 J-3-GP
R8519 10KR2 J-3-GP
(DG-05587-001_v03_p.88_Table 25)
66mA
OPS
OPS
12
C8517
C8517
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Under GPU
Under GPU
Near GPU
4
Mode D Command Mapping
(DG-05587-001_v03_p.78_Table 16)
N13x DDR3
Data Bits
mode D
[31:0]
FBx_CMD0
FBx_CMD1
FBx_CMD2
FBx_CMD3
FBx_CMD4
FBx_CMD5
FBx_CMD6
FBx_CMD7
FBx_CMD8
FBx_CMD9
FBx_CMD10
FBx_CMD11
FBx_CMD12
FBx_CMD13
FBx_CMD14
FBx_CMD15
FBx_CMD16
FBx_CMD17
FBx_CMD18
FBx_CMD19
FBx_CMD20
FBx_CMD21
FBx_CMD22
FBx_CMD23
FBx_CMD24
FBx_CMD25
FBx_CMD26
FBx_CMD27
FBx_CMD28
FBx_CMD29
FBx_CMD30
FBx_CMD31
1.05V ±30mV 167mA total
100nF(X7R)
K0402 ×3
OPS
OPS
12
12
C8518
C8518
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
OPS
OPS
C8519
C8519
CS0#
ODT
CKE
A14
RST
A9
A7
A2
A0
A4
A1
BA0
WE#
A15
CAS#
A13
A8
A6
A11
A5
A3
BA2
BA1
A12
A10
RAS#
Memory ODTx, CKEx and RST Termination
FBA_CKE0
FBA_RST
FBA_ODT1
4
Data Bits
[63:32]
A14
RST
A9
A7
A2
A0
A4
A1
BA0
WE#
A15
CAS#
CS0#
ODT
CKE
A13
A8
A6
A11
A5
A3
BA2
BA1
A12
A10
RAS#
12
OPS
OPS
R8508
R8508
10KR2J-3-GP
10KR2J-3-GP
FBB_D[63..0]90,91
OPS-BOM CTRL
OPS-BOM CTRL
R8523
R8523
0R3J-0-U-G P
0R3J-0-U-G P
1 2
12
OPS
OPS
R8509
R8509
10KR2J-3-GP
10KR2J-3-GP
3
VGA1C
VGA1C
3/17 FBB
3/17 FBB
FBB_D0
G9
FBB_D0
FBB_D1
E9
FBB_D1
FBB_D2
G8
FBB_D2
FBB_D3
F9
FBB_D3
FBB_D4
F11
FBB_D4
FBB_D5
G11
FBB_D5
FBB_D6
F12
FBB_D6
FBB_D7
G12
FBB_D7
FBB_D8
G6
FBB_D8
FBB_D9
F5
FBB_D9
FBB_D10
E6
FBB_D10
FBB_D11
F6
FBB_D11
FBB_D12
F4
FBB_D12
FBB_D13
G4
FBB_D13
FBB_D14
E2
FBB_D14
FBB_D15
F3
FBB_D15
FBB_D16
C2
FBB_D16
FBB_D17
D4
FBB_D17
FBB_D18
D3
FBB_D18
FBB_D19
C1
FBB_D19
FBB_D20
B3
FBB_D20
FBB_D21
C4
FBB_D21
FBB_D22
B5
FBB_D22
FBB_D23
C5
FBB_D23
FBB_D24
A11
FBB_D24
FBB_D25
C11
FBB_D25
FBB_D26
D11
FBB_D26
FBB_D27
B11
FBB_D27
FBB_D28
D8
FBB_D28
FBB_D29
A8
FBB_D29
FBB_D30
C8
FBB_D30
FBB_D31
B8
FBB_D31
FBB_D32
F24
FBB_D32
FBB_D33
G23
FBB_D33
FBB_D34
E24
FBB_D34
FBB_D35
G24
FBB_D35
FBB_D36
D21
FBB_D36
FBB_D37
E21
FBB_D37
FBB_D38
G21
FBB_D38
FBB_D39
F21
FBB_D39
FBB_D40
G27
FBB_D40
FBB_D41
D27
FBB_D41
FBB_D42
G26
FBB_D42
FBB_D43
E27
FBB_D43
FBB_D44
E29
FBB_D44
FBB_D45
F29
FBB_D45
FBB_D46
E30
FBB_D46
FBB_D47
D30
FBB_D47
FBB_D48
A32
FBB_D48
FBB_D49
C31
FBB_D49
FBB_D50
C32
FBB_D50
FBB_D51
B32
FBB_D51
FBB_D52
D29
FBB_D52
FBB_D53
A29
FBB_D53
FBB_D54
C29
FBB_D54
FBB_D55
B29
FBB_D55
FBB_D56
B21
FBB_D56
FBB_D57
C23
FBB_D57
FBB_D58
A21
FBB_D58
FBB_D59
C21
FBB_D59
FBB_D60
B24
FBB_D60
FBB_D61
C24
FBB_D61
FBB_D62
B26
FBB_D62
FBB_D63
C26
FBB_D63
E11
FBB_DQM090
FBB_DQM190
FBB_DQM290
FBB_DQM390
FBB_DQM491
FBB_DQM591
FBB_DQM691
FBB_DQM791
FBB_DQS_W P090
FBB_DQS_W P190
FBB_DQS_W P290
FBB_DQS_W P390
FBB_DQS_W P491
FBB_DQS_W P591
FBB_DQS_W P691
FBB_DQS_W P791
FBB_DQS_RN 090
FBB_DQS_RN 190
FBB_DQS_RN 290
FBB_DQS_RN 390
FBB_DQS_RN 491
FBB_DQS_RN 591
FBB_DQS_RN 691
FBB_DQS_RN 791
1D05V_VGA_S0
FBB_DQM0
E3
FBB_DQM1
A3
FBB_DQM2
C9
FBB_DQM3
F23
FBB_DQM4
F27
FBB_DQM5
C30
FBB_DQM6
A24
FBB_DQM7
D10
FBB_DQS_WP0
D5
FBB_DQS_WP1
C3
FBB_DQS_WP2
B9
FBB_DQS_WP3
E23
FBB_DQS_WP4
E28
FBB_DQS_WP5
B30
FBB_DQS_WP6
A23
FBB_DQS_WP7
D9
FBB_DQS_RN0
E4
FBB_DQS_RN1
B2
FBB_DQS_RN2
A9
FBB_DQS_RN3
D22
FBB_DQS_RN4
D28
FBB_DQS_RN5
A30
FBB_DQS_RN6
B23
FBB_DQS_RN7
THE FBB_WCKBxx
THE FBB_WCKBxx
PINS ARE USED
PINS ARE USED
ONLY ON GK107
ONLY ON GK107
THEY ARE NC
THEY ARE NC
FOR GF108
FOR GF108
AND FOR GF117
AND FOR GF117
N13P-GS-A1-G P
N13P-GS-A1-G P
OPS-BOM CTRL
OPS-BOM CTRL
Stuff 0 ohm(63.00000.00L) for N13P-GS/N13M-GS,
Stuff bead(68.00084.H41) for N13P-GL/N13M-GE
(DG-05587-001_v03_p.84_Table 20)
12
OPS
OPS
R8510
R8510
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
OPS
OPS
R8512
R8512
R8511
R8511
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
12
12
12
OPS
OPS
10KR2J-3-GP
10KR2J-3-GP
3
R8513
R8513
FBB_CMD_RFU0
FBB_CMD_RFU1
FBB_PLL_AVDD
12
OPS
OPS
R8514
R8514
10KR2J-3-GP
10KR2J-3-GP
3 OF 17
3 OF 17
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_DEBUG0
FBB_DEBUG1
FBB_CLK0
FBB_CLK0#
FBB_CLK1
FBB_CLK1#
FBB_WCK1
FBB_WCK1#
FBB_WCK23
FBB_WCK23#
FBB_WCK45
FBB_WCK45#
FBB_WCK67
FBB_WCK67#
FBB_WCKB1
FBB_WCKB1#
FBB_WCKB23
FBB_WCKB23#
FBB_WCKB45
FBB_WCKB45#
FBB_WCKB67
FBB_WCKB67#
12
OPS
OPS
10KR2J-3-GP
10KR2J-3-GP
FB CMD mapping
Mode D-N13x
D13
FBB_CS0# 90
E14
F14
FBB_ODT0 90
A12
FBB_CKE0 90
B12
C14
FBB_RST 90,91
B14
FBB_A9 90,91
G15
FBB_A7 90,91
F15
FBB_A2 90,91
E15
FBB_A0 90,91
D15
FBB_A4 90,91
A14
FBB_A1 90,91
D14
FBB_BA0 90,9 1
A15
FBB_WE# 90,91
B15
FBB_A15 90,91
C17
FBB_CAS# 90,91
D18
FBB_CS1# 91
E18
F18
FBB_ODT1 91
A20
FBB_CKE1 91
B20
FBB_A13 90,91
C18
FBB_A8 90,91
B18
FBB_A6 90,91
G18
FBB_A11 90,91
G17
FBB_A5 90,91
F17
FBB_A3 90,91
D16
FBB_BA2 90,9 1
A18
FBB_BA1 90,9 1
D17
FBB_A12 90,91
A17
FBB_A10 90,91
B17
FBB_RAS# 90,91
E17
C12
C20
R8520 60D4R2F-GP
R8520 60D4R2F-GP
G14
1 2
G20
1 2
R8521 10KR2J-3-GP
R8521 10KR2J-3-GP
D12
E12
E20
F20
F8
E8
A5
A6
D24
D25
B27
C27
D6
D7
C6
B6
F26
E26
A26
A27
H17
12
OPS
OPS
R8515
R8515
R8516
R8516
10KR2J-3-GP
10KR2J-3-GP
2
VGA1D
VGA1D
14/17 FBVDDQ
14/17 FBVDDQ
AA27
FBVDDQ_1
AA30
FBVDDQ_2
AB27
FBVDDQ_3
AB33
FBVDDQ_4
AC27
FBVDDQ_5
AD27
FBVDDQ_6
AE27
FBVDDQ_7
AF27
FBVDDQ_8
AG27
FBVDDQ_9
B13
FBVDDQ_10
B16
FBVDDQ_11
B19
FBVDDQ_12
E13
FBVDDQ_13
E16
FBVDDQ_14
E19
FBVDDQ_15
H10
FBVDDQ_16
H11
FBVDDQ_17
H12
FBVDDQ_18
H13
FBVDDQ_19
H14
FBVDDQ_20
H15
FBVDDQ_21
H16
FBVDDQ_22
H18
FBVDDQ_23
H19
FBVDDQ_24
H20
FBVDDQ_25
H21
FBVDDQ_26
H22
FBVDDQ_27
H23
FBVDDQ_28
H24
FBVDDQ_29
H8
FBVDDQ_30
H9
FBVDDQ_31
L27
FBVDDQ_32
M27
FBVDDQ_33
N27
FBVDDQ_34
P27
FBVDDQ_35
R27
FBVDDQ_36
T27
FBVDDQ_37
T30
FBVDDQ_38
T33
FBVDDQ_39
V27
FBVDDQ_40
W27
FBVDDQ_41
W30
FBVDDQ_42
W33
FBVDDQ_43
Y27
FBVDDQ_44
FB_VDDQ_SENSE
FB_GND_SENSE
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
N13P-GS-A1-G P
N13P-GS-A1-G P
OPS-BOM CTRL
OPS-BOM CTRL
DY
DY
DY
DY
FBB_CLK0 90
FBB_CLK0# 90
FBB_CLK1 91
FBB_CLK1# 91
1D5V_VGA_S0
(DG-05587-001_v03_p.88_Table 25)
66mA
FB_PLLVDD
FBCLK Termination placed at each VRAM
FBA_CLK1
FBA_CLK1#
FBB_CKE0
FBB_CKE1FBA_CKE1
FBB_RST
FBB_ODT0FBA_ODT0
FBB_ODT1
12
OPS
OPS
R8517
R8517
10KR2J-3-GP
10KR2J-3-GP
2
GPU FBVDDQ Decoupling (DG-05587-001_v03_p.86_Table 22)
1
Capacitor Type Footprint Population Location
0.1uF
X7R
4 OF 17
4 OF 17
OPS
OPS
12
C8502
C8502
X7R
X6S
X5R
0402
0603
0603
0805
OPS
OPS
12
C8503
C8503
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1uF
4.7uF
10uF
X7R (+/-15%、-55~125℃)
X6S (+/-22%、-55~105℃)
X5R (+/-15%、-55~85℃)
OPS
OPS
12
C8501
C8501
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
OPS
OPS
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
8
2
2
4
C8504
C8504
8
2
2
4
0.1uF(X7R)
K0402 ×8
OPS
OPS
12
C8505
C8505
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
OPS
OPS
12
C8506
C8506
Under GPU
Under GPU
Under GPU
Near GPU
OPS
OPS
12
C8507
C8507
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Under GPU
OPS
OPS
OPS
OPS
12
12
C8511
C8511
C8510
C8510
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
OPS
OPS
12
C8514
C8514
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1D5V_VGA_S0
OPS
OPS
1 2
R8501 40D 2R2F-GP
R8501 40D 2R2F-GP
OPS
OPS
OPS
OPS
12
12
R8502
R8502
51D1R2F-GP
51D1R2F-GP
42D2R2F-GP
42D2R2F-GP
OPS
OPS
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
OPS
OPS
12
C8515
C8515
10uF(X5R)
M0805 ×2
R8503
R8503
C8512
C8512
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1uF(X7R)
K0603 ×4
OPS
OPS
12
C8516
C8516
Near GPU
F1
F2
FB_CAL_PD_VD DQ
J27
FB_CAL_PU_GN D
H27
FB_CAL_TERM _GND
H25
OPS
OPS
12
C8509
C8509
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
OPS
OPS
12
C8513
C8513
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
4.7uF(X5R)
K0603 ×2
Default GPU Drive Calibration for DDR3 (DG-05587-001_v03_p.82_Table 17)
Memory/PKG FBVDDQ FBCAL_PU_GND FBCAL_PU_VDDQ
FBCAL_TERM_GND
DDR3 42.2Ω 40.2Ω 51.1Ω1.5V
*Use only 1% resistors for driver calibration.
(DG-05587-001_v03_p.83_Table 19)
12
R8504
R8504
160R2F-GP
160R2F-GP
OPS
OPS
FBA_CLK0
FBA_CLK0#
12
R8505
R8505
160R2F-GP
160R2F-GP
OPS
OPS
FBB_CLK1
FBB_CLK0
12
R8506
R8506
160R2F-GP
160R2F-GP
OPS
OPS
<Core Desig n>
<Core Desig n>
<Core Desig n>
Title
Title
Title
N13P_GPU (3/5): VRAM I/F
N13P_GPU (3/5): VRAM I/F
N13P_GPU (3/5): VRAM I/F
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
LA48
LA48
LA48
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
R8507
R8507
160R2F-GP
160R2F-GP
OPS
OPS
FBB_CLK0#FBB_CLK1#
1
1D5V_VGA_S0
OPS
OPS
12
C8508
C8508
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
85 103Friday, January 06, 2012
85 103Friday, January 06, 2012
85 103Friday, January 06, 2012
SD
SD
SD
Page 86
5
17 OF 17
VGA1Q
VGA1Q
10/19 MISC1
10/19 MISC1
K4
THERMDN
K3
N13P_TCK
N13P_TMS
N13P_TDI
N13P_TDO
N13P_TRST
AM10
AP11
AM11
AP12
AN11
THERMDP
JTAG_T CK
JTAG_T MS
JTAG_T DI
JTAG_T DO
JTAG_T RST#
N13P-GS-A1-GP
N13P-GS-A1-GP
OPS-BOM CTRL
OPS-BOM CTRL
R8619
R8619
1 2
DY
TP8603TP8603
TP8604TP8604
TP8605TP8605
D D
DY
10KR2J-3-GP
10KR2J-3-GP
1
1
1
1 2
OPS
OPS
R8620
R8620
10KR2J-3-GP
10KR2J-3-GP
17 OF 17
I2CS_S CL
I2CS_S DA
I2CC_S CL
I2CC_S DA
I2CB_S CL
I2CB_S DA
GPIO10
GPIO11
GPIO12
GPIO13
GPIO16
GPIO20
GPIO21
T4
T3
R2
R3
R7
R6
P6
GPIO0
M3
GPIO1
VGA_LBKLT_CTL
L6
GPIO2
VGA_LCDVDD_EN
P5
GPIO3
VGA_BLEN
P7
GPIO4
L7
GPIO5
M7
GPIO6
N8
GPIO7
M1
GPIO8
M2
GPIO9
L1
M5
N3
M4
R8
P4
P1
SMBC_Therm_NV
SMBD_Therm_NV
GPU_LVDS_CLK
GPU_LVDS_DATA
I2CB_SCL_G3
I2CB_SDA_G2
-VIDEO_THERM_OVERT
-VIDEO_THERM_ALERT
N13P_GPIO12_H7
3D3V_VGA_S0
1 2
R2813 0R0402-PADR2813 0R0402-PAD
-VIDEO_THERM_OVERT
3D3V_VGA_S0
3V_VGA_S0_R
4
RN8606
RN8606
SRN2K2J-1-GP
SRN2K2J-1-GP
OPS
OPS
1
2 3
1
2 3
SRN10KJ-5-GP
SRN10KJ-5-GP
1st = 84.2N702.031
1st = 84.2N702.031
2ND = 84.2N702.J31
2ND = 84.2N702.J31
3D3V_VGA_S0
2 3
RN8603
RN8603
OPS
OPS
4
1 2
R8623 10KR2J-3-GP
R8623 10KR2J-3-GP
NV_VID4 92
NV_VID3 92
NV_VID1 92
NV_VID2 92
NV_VID0 92
NV_VID5 92
Q8602
Q8602
G
S
2N7002K-2-GP
2N7002K-2-GP
OPS
OPS
4
RN8604
RN8604
SRN2K2J-1-GP
SRN2K2J-1-GP
OPS
OPS
1
DY
DY
SRN10KJ-5-GP
SRN10KJ-5-GP
R8611 10KR2J-3-GP
R8611 10KR2J-3-GP
D
OPS
OPS
RN8607
RN8607
1
2 3
1 2
OPS
OPS
PURE_HW_SHUTDOWN# 27,28,36
C C
SPEC. (DG-05587-001_v03_p.162)
Adding a pull down to the DACA_VDD with a 10kΩ resistor to GND.
All other DAC I/O pins (including DACA_VREF, DACA_REST)
can be left floating.
VGA1N
VGA1N
4/17 DACA
4/17 DACA
GF108/GKx GF117
GF108/GKx GF117
DACA_VDD
1 2
R8629
R8629
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
TP8620TP8620
TP8621TP8621
1
DACA_RSET
1
AP9
AP8
N13P-GS-A1-GP
N13P-GS-A1-GP
OPS-BOM CTRL
OPS-BOM CTRL
DACA_V REF
DACA_R SET
AG10
DACA_V DD
DACA_VREF
TSEN_VREF
TSEN_VREF
NCNC
NCNC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GF108/GKxGF117
GF108/GKxGF117
DACA_HS YNC
DACA_V SYNC
DACA_G REEN
DACA_B LUE
14 OF 17
14 OF 17
I2CA_S CL
I2CA_S DA
DACA_R ED
3D3V_VGA_S0
R4
R5
AM9
AN9
AK9
AL10
AL9
VGA_CRT_BLUE
VGA_CRT_GREEN
VGA_CRT_RED
4
RN8601
RN8601
SRN2K2J-1-GP
SRN2K2J-1-GP
OPS
OPS
1
2 3
VGA_CRT_DDCCLK
VGA_CRT_DDCDATA
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_CRT_RED
VGA_CRT_GREEN
VGA_CRT_BLUE
RN8602
RN8602
1
2
3
4 5
SRN75J-1-GP
SRN75J-1-GP
OPS
OPS
1
1
1
1
8
7
6
B B
4
3D3V_VGA_S0
4
GPIO Description (DG-05587-001_v03_p.82_Tale 98)
GPIO pin
Normal
Name
Function
GPIO0
GPU_VID4
GPIO1
GPU_VID3
GPIO2
LCD_BL_PWM
GPIO3
LCD_VCC
GPIO4
LCD_BLEN
GPIO5
GPU_VID1
GPIO6
GPU_VID2
GPIO7
3D Vision
GPIO8
OVERT
GPIO9
ALERT
GPIO10
MEM_VREF_CTL
GPIO11
GPU_VID0
GPIO12
PWR_LEVEL
GPIO13
GPU_VID5
GPIO14
HPD_AB
GPIO15
HPD_C
GPIO16
MEM_VDD_CTL
GPIO17
HPD_D
GPIO18
HPD_E
GPIO19
HPD_F
GPIO20
Reserved
GPIO21
Reserved
TP8611TP8611
TP8612TP8612
TP8613TP8613
TP8614TP8614
MULTI_STRAP_REF2_GND
12
OPS
OPS
R8313
R8313
40K2R2F-GP
40K2R2F-GP
SPEC. (DG-05587-001_v03_p.191_Table 102)
Multi_Strap_Ref0_GND 40.2kΩ 1% to GND
3D3V_VGA_S0
4
1
2 3
I/O
O
O
O
O
O
O
O
O
I/O
I/O
O
O
I
O
I
I
O
I
I
I
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
I2CA=>CRT, I2CC=>LVDS.
RN8605
RN8605
SRN4K7J-8-GP
SRN4K7J-8-GP
OPS
OPS
SMBC_Therm_NV
SMBD_Therm_NV
Q8601
Q8601
OPS
OPS
1
6
2
5
3 4
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
Function
Description
GPU Core VDD VID4
GPU Core VDD VID3
Panel Backlught PWM Brightness Control
Panel Power Enable
panel Backlight Enale
GPU Core VDD VID1
GPU Core VDD VID2
3D Vision Left/Right signal
Active Low Thermal Catastrophic Over Temperature
Active Low Thermal Alert
Memory VREF Control
GPU Core VDD VID0
AC Power Detect Input. High = AC, Low = Battery
GPU Core VDD VID5
Hot Plog Detect for IFPAB
Hot Plog Detect for IFPC
Memory VDD VID
Hot Plog Detect for IFPD
Hot Plog Detect for IFPE
Hot Plog Detect for IFPF
16 OF 17
VGA1P
VGA1P
12/17 MISC2
12/17 MISC2
J2
STRAP0
J7
STRAP1
J6
STRAP2
J5
STRAP3
J3
STRAP4
J1
MULTI_STR AP_RE F0_GND
N13P-GS-A1-GP
N13P-GS-A1-GP
OPS-BOM CTRL
OPS-BOM CTRL
16 OF 17
ROM_CS#
ROM_SI
ROM_SO
ROM_SCL K
BUFRST#
CEC
3
SMBC_Therm 27,28
SMBD_Therm 27,28
3D3V_VGA_S0
12
R8624
R8624
2KR2F-3-GP
2KR2F-3-GP
DY
DY
H6
ROM_SI_H5
H5
ROM_SO_H7
H7
ROM_SLK_H4
H4
12
R8627
R8627
15KR2F-GP
15KR2F-GP
OPS-BOM CTRL
OPS-BOM CTRL
L2
L3
CEC_L3
L3 (DA-05691-001_v04_p.3_Table 2)
N13P-GL 10kΩ pull-up to 3.3V
N13M_GE1 NC
N13M-GS NC
N13P-GS NC
TABLE VIDEO MEMORY
ROM_SI
PD
R8627
3D3V_VGA_S0
R8628
R8628
1 2
10KR2F-2-GP
10KR2F-2-GP
OPS-BOM CTRL
OPS-BOM CTRL
HYNIX
128Mx16
0110
1-007155
34.8Kohm 15Kohm 20Kohm
64.34825.6DL
12
R8625
R8625
10KR2F-2-GP
10KR2F-2-GP
DY
DY
12
R8617
R8617
30KR2F-GP
30KR2F-GP
OPS-BOM CTRL
OPS-BOM CTRL
SAMSUNG
128Mx16
0111
72.42164.D0U72.52G63.A0U
45.3Kohm
64.45325.6DL
1D05V_VGA_S0
(DG-05587-001_v03_p.177_Table 95)
1.05V ±30mV 90mA total
(DG-05587-001_v03_p.177_Table 95)
12
R8626
R8626
15KR2F-GP
15KR2F-GP
OPS-BOM CTRL
OPS-BOM CTRL
12
R8618
R8618
15KR2F-GP
15KR2F-GP
OPS-BOM CTRL
OPS-BOM CTRL
HYNIX
64Mx16
0010
72.51G63.H0U900MHz 72.41164.Q0U
1-007157
64.15025.6DL
1.05V ±30mV 60mA
PLL Power Rail Filter-PLL_VDD
(DG-05587-001_v03_p.177_Table 96)
Capacitor Type Footprint Population Location
X7R
100nF
X7R
22uF
Bead Type
30Ω(ESR=0.05) 0402 Near GPU
X7R (+/-15%、-55~125℃)
PLL Power Rail Filter-SP_PLLVDD and VIDPLLVDD Combined
(DG-05587-001_v03_p.178_Table 97)
Capacitor Type Footprint Population Location
X7R
100nF
X7R
4.7uF
X7R
22uF
Bead Type
180Ω(ESR=0.2) 0603 Near GPU
X7R (+/-15%、-55~125℃)
Samsung
64Mx16
0011
(
(
L8601
L8601
BLM18KG300TN1D-GP
BLM18KG300TN1D-GP
OPS
OPS
1 2
L8602
L8602
BLM18PG181SN1D-GP
BLM18PG181SN1D-GP
OPS
OPS
0402
0805
0402
0402
0805
(
(
1-0073561-007156
64.20025.6DL
21
22uF(X5R)
M0805 ×1
1
1
1
2
1
1
1
2
22uF(X5R)
M0805 ×1
100nF(X7R)
K0402 ×1
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
OPS
OPS
C8601
C8601
100nF(X7R)
4.7uF(X5R)
K0402 ×2
K0603 ×1
OPS
OPS
OPS
OPS
12
12
C8604
C8604
C8605
C8605
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
Under GPUNear GPU
Under GPU
Near GPU
Under GPU
Near GPU
Near GPU
The GB4-128 package is available in a 29 mm × 29mm footprint.
128-bit memory interfaces respectively.
Recommended NVVDD Voltage Regulator Phase Coount
GPU SKU
N13M-GE1
N13M-GS
N13P-GL
N13P-GS
29 x 29 PACKAGE
V: N13P-GS/GL (25~30W)
B: N13M-GS/GE (15~20W)
128Mx16:
hynix - H5TQ2G63BFR-11C
Samsung - K4W2G1646C-HC11
64Mx16:
Hynix - H5TQ1G63DFR-11C
Samsung - K4W1G1646G-BC11
PLLVDD
OPS
OPS
12
C8602
C8602
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PLLVDD_PWR
OPS
OPS
12
C8606
C8606
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VIDEO_CLK_XTAL_SS
12
R8601
R8601
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
12
SPEC. (DG-05587-001_v03_p.176)
XTALOUTBUFF signal should be pull down using a 10kΩ resistor.
XTALSSIN signal should be pull down using a 10kΩ resistor.
REmember to place components as close ti the GPU as possible.
Phase Count Target
Single phase
Two phase
Two phase
Two phase
VGA1O
VGA1O
11/17 XTAL_PLL
11/17 XTAL_PLL
AD8
PLLVDD
AE8
SP_PLLV DD
AD7
VID_PL LVDD
GF108/GKx GF117
GF108/GKx GF117
H1
XTAL_SS IN
H3
XTAL_I N
N13P-GS-A1-GP
N13P-GS-A1-GP
OPS-BOM CTRL
OPS-BOM CTRL
20PF 5% 50V +/-0.25PF 0402
R8603 1MR2F-GP
R8603 1MR2F-GP
X8601_GND
27MHZ_IN
82.30034.351
82.30034.351
C8607
C8607
SC12P50V2JN-3GP
SC12P50V2JN-3GP
OPS
OPS
R8636 is reserved for Metal Xta l
NC
NC
1 2
DY
DY
X8601
X8601
XTAL-27MHZ-46-GP
XTAL-27MHZ-46-GP
4
1 2
OPS
OPS
3
15 OF 17
15 OF 17
XTAL_OUT BUFF
XTAL_OUT
27MHZ_OUT_R
X8601_GND
R8636
R8636
0R2J-2-GP
0R2J-2-GP
DY
DY
J4
H2
1 2
1
N12P_XTAL_OUTBUFF
10KR2J-3-GP
10KR2J-3-GP
R8604
R8604
0R2J-2-GP
0R2J-2-GP
OPS
OPS
1 2
12
C8608
C8608
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
OPS
OPS
12
R8602
R8602
OPS
OPS
N12P-GV
DEV ID:
0x0DF7(ES)
DYDY
35Kohm
64.34825.6DL
64.45325.6DL
DY DY
N12M-GE
DEV ID:
0xA7A
1010
35Kohm
64.34825.6DL
DY
15Kohm45Kohm
64.15025.6DL
STRAP0
STRAP1
STRAP2
R8630
R8630
45K3R2F-L-GP
45K3R2F-L-GP
OPS
OPS
R8631
R8631
2KR2F-3-GP
2KR2F-3-GP
DY
DY
12
12
R8632
R8632
34K8R2F-1-GP
34K8R2F-1-GP
DY
DY
R8633
R8633
34K8R2F-1-GP
34K8R2F-1-GP
OPS-BOM CTRL
OPS-BOM CTRL
12
12
3D3V_VGA_S0
R8634
R8634
45K3R2F-L-GP
45K3R2F-L-GP
OPS-BOM CTRL
OPS-BOM CTRL
R8635
R8635
30KR2F-GP
30KR2F-GP
DY
DY
20100702_NV
12
R8314
R8314
45K3R2F-L-GP
45K3R2F-L-GP
DY
DY
STRAP3
STRAP4
12
R8315
R8315
5K1R2F-2-GP
5K1R2F-2-GP
OPS-BOM CTRL
OPS-BOM CTRL
3D3V_VGA_S0
12
12
R8316
R8316
34K8R2F-1-GP
34K8R2F-1-GP
DY
DY
12
12
R8317
R8317
20KR2F-L-GP
20KR2F-L-GP
OPS-BOM CTRL
OPS-BOM CTRL
STRAP1
STRAP2
TABLE
NVIDIA
R8632
R8633
R8634
R8635
N12P-GE
DEV ID:
0xDF5
0101
35Kohm
64.34825.6DL
DY
30Kohm
64.30025.6DL
A A
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
N13P_GPU (4/5): GPIO/STRAP
N13P_GPU (4/5): GPIO/STRAP
N13P_GPU (4/5): GPIO/STRAP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A1
A1
A1
LA48
LA48
LA48
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
86 103Friday, January 06, 2012
86 103Friday, January 06, 2012
86 103Friday, January 06, 2012
SD
SD
SD
Page 87
5
OPS
OPS
OPS
4.7uF(X5R)
K0603 ×15
D D
0.1uF(X7R)
K0402 ×8
C C
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
OPS
OPS
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C8701
C8701
C8716
C8716
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
OPS
OPS
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
C8702
C8702
C8709
C8709
DY
DY
C8717
C8717
OPS
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
OPS
OPS
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C8703
C8703
DY
DY
C8710
C8710
C8718
C8718
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
OPS
OPS
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Under GPU
OPS
22uF(X5R)
M0805 ×1
4.7uF(X5R)
K0805 ×5
OPS
12
C8724
C8724
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
B B
NVVDD Decoupling Requirement
(DG-05587-001_v03_p.56_Table 7)
Capacitor Type
4.7uF
0.1uF
47uF
22uF
4.7uF
X7R (+/-15%、-55~125℃)
X6S (+/-22%、-55~105℃)
X5R (+/-15%、-55~85℃)
Footprint Population Location
0603
0402
0805
0805
0805
15
8
1
1
5
10
4
1
1
5
X6S
X7R
X5R
X5R
X5R
Under GPU
Under GPU
Near GPU
Near GPU
Near GPU
A A
DY
DY
C8704
C8704
C8711
C8711
DY
DY
C8719
C8719
4
OPS
OPS
OPS
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
OPS
OPS
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C8705
C8705
DY
DY
C8712
C8712
C8720
C8720
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
OPS
OPS
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
C8706
C8706
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C8713
C8713
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
DY
DY
C8721
C8721
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
47uF(X5R)
M0805 ×1
OPS
12
OPS
OPS
12
OPS
OPS
12
C8707
C8707
C8714
C8714
C8722
C8722
OPS
OPS
12
C8708
C8708
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
OPS
OPS
12
C8715
C8715
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
DY
DY
12
C8723
C8723
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VGA_CORE
3
VGA1F
VGA1F
AA12
VDD_1
AA14
VDD_2
AA16
VDD_3
AA19
VDD_4
AA21
VDD_5
AA23
VDD_6
AB13
VDD_7
AB15
VDD_8
AB17
VDD_9
AB18
VDD_10
AB20
VDD_11
AB22
VDD_12
AC12
VDD_13
AC14
VDD_14
AC16
VDD_15
AC19
VDD_16
AC21
VDD_17
AC23
VDD_18
M12
VDD_19
M14
VDD_20
M16
VDD_21
M19
VDD_22
M21
VDD_23
M23
VDD_24
N13
VDD_25
N15
VDD_26
N17
VDD_27
N18
VDD_28
N20
VDD_29
N22
VDD_30
P12
VDD_31
P14
VDD_32
P16
VDD_33
P19
VDD_34
P21
VDD_35
P23
VDD_36
R13
VDD_37
R15
VDD_38
R17
VDD_39
R18
VDD_40
R20
VDD_41
R22
VDD_42
T12
VDD_43
T14
VDD_44
T16
VDD_45
T19
VDD_46
T21
VDD_47
T23
VDD_48
U13
VDD_49
U15
VDD_50
U17
VDD_51
U18
VDD_52
U20
VDD_53
U22
VDD_54
V13
VDD_55
V15
VDD_56
V17
VDD_57
V18
VDD_58
V20
VDD_59
V22
VDD_60
W12
VDD_61
W14
VDD_62
W16
VDD_63
W19
VDD_64
W21
VDD_65
W23
VDD_66
Y13
VDD_67
Y15
VDD_68
Y17
VDD_69
Y18
VDD_70
Y20
VDD_71
Y22
VDD_72
N13P-GS-A1-GP
N13P-GS-A1-GP
OPS-BOM CTRL
OPS-BOM CTRL
6 OF 17
6 OF 17
13/17 NVVDD
13/17 NVVDD
VGA1I
VGA1I
A2
GND_1
AA17
GND_5
AA18
GND_6
AA20
GND_7
AA22
GND_8
AB12
GND_9
AB14
GND_10
AB16
GND_11
AB19
GND_12
AB2
GND_13
AB21
GND_14
A33
GND_2
AB23
GND_15
AB28
GND_16
AB30
GND_17
AB32
GND_18
AB5
GND_19
AB7
GND_20
AC13
GND_21
AC15
GND_22
AC17
GND_23
AC18
GND_24
AA13
GND_3
AC20
GND_25
AC22
GND_26
AE2
GND_27
AE28
GND_28
AE30
GND_29
AE32
GND_30
AE33
GND_31
AE5
GND_32
AE7
GND_33
AH10
GND_34
AA15
GND_4
AH13
GND_35
AH16
GND_36
AH19
GND_37
AH2
GND_38
AH22
GND_39
AH24
GND_40
AH28
GND_41
AH29
GND_42
AH30
GND_43
AH32
GND_44
AH33
GND_45
AH5
GND_46
AH7
GND_47
AJ7
GND_48
AK10
GND_49
AK7
GND_50
AL12
GND_51
AL14
GND_52
AL15
GND_53
AL17
GND_54
AL18
GND_55
AL2
GND_56
AL20
GND_57
AL21
GND_58
AL23
GND_59
AL24
GND_60
AL26
GND_61
AL28
GND_62
AL30
GND_63
AL32
GND_64
AL33
GND_65
AL5
GND_66
AM13
GND_67
AM16
GND_68
AM19
GND_69
AM22
GND_70
N13P-GS-A1-GP
N13P-GS-A1-GP
OPS-BOM CTRL
OPS-BOM CTRL
15/17 GND_1/2
15/17 GND_1/2
9 OF 17
9 OF 17
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
2
VGA1H
VGA1H
N19
GND_141
N2
GND_142
N21
GND_143
N23
GND_144
N28
GND_145
N30
GND_146
N32
GND_147
N33
GND_148
N5
GND_149
N7
GND_150
P13
GND_151
P15
GND_152
P17
GND_153
P18
GND_154
P20
GND_155
P22
GND_156
R12
GND_157
R14
GND_158
R16
GND_159
R19
GND_160
R21
GND_161
R23
GND_162
T13
GND_163
T15
GND_164
T17
GND_165
T18
GND_166
T2
GND_167
T20
GND_168
T22
GND_169
AG11
GND_F
N13P-GS-A1-GP
N13P-GS-A1-GP
OPS-BOM CTRL
OPS-BOM CTRL
16/17 GND_2/2
16/17 GND_2/2
Optional CMD GNDs (2)
Optional CMD GNDs (2)
NC for 4-Lyr cards
NC for 4-Lyr cards
8 OF 17
8 OF 17
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_H
GND_OPT_1
GND_OPT_2
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32
1
VGA1E
VGA1E
9/17 XVDD
9/17 XVDD
CONFIGURABLE
CONFIGURABLE
POWER
POWER
CHANNELS
CHANNELS
N13P-GS-A1-GP
N13P-GS-A1-GP
OPS-BOM CTRL
OPS-BOM CTRL
5 OF 17
5 OF 17
XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38
U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
VDD33 Decoupling (DG-05587-001_v03_p.57_Table 8)
Footprint PopulationCapacitor Type Location
3D3V_VGA_S0
OPS
OPS
12
C8736
C8736
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
0.1uF
1uF
4.7uF
X7R (+/-15%、-55~125℃)
X5R (+/-15%、-55~85℃)
X7R
0402
X5R
0402
X5R
0603
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
N13P_GPU (5/5): PWR/GND
N13P_GPU (5/5): PWR/GND
N13P_GPU (5/5): PWR/GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA48
LA48
LA48
Date: Sheet of
Date: Sheet of
Date: Sheet of
3
2
1
3
2
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Under GPU
Near GPU
Near GPU
87 103Friday, January 06, 2012
87 103Friday, January 06, 2012
87 103Friday, January 06, 2012
SD
SD
SD
VGA1G
VGA1G
17/17 NC/VDD33
17/17 NC/VDD33
AC6
NC#AC6
AJ28
NC#AJ28
AJ4
NC#AJ4
AJ5
NC#AJ5
AL11
NC#AL11
C15
NC#C15
D19
NC#D19
D20
NC#D20
D23
NC#D23
D26
NC#D26
H31
NC#H31
T8
NC#T8
V32
NC#V32
N13P-GS-A1-GP
N13P-GS-A1-GP
OPS-BOM CTRL
OPS-BOM CTRL
7 OF 17
7 OF 17
VDD33_1
VDD33_2
VDD33_3
VDD33_4
0.1uF(X7R)
K0402 ×3
J8
K8
L8
M8
OPS
OPS
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C8731
C8731
OPS
OPS
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C8732
C8732
OPS
OPS
12
C8733
C8733
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1uF(X5R)
K0402 ×2
OPS
OPS
12
C8734
C8734
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
4.uF(X5R)
K0603 ×2
OPS
OPS
12
C8735
C8735
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
Near GPUUnder GPU
Page 88
A
VRAM1
VRAM1
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
4 4
12
OPS
OPS
R8801
R8801
R2F-2-GP
R2F-2-GP
243
243
3 3
FB CMD mapping
Mode D-N13x
2 2
VRAM_CH_A_ZQ_1
FBA_A085,89
FBA_A185,89
FBA_A285,89
FBA_A385,89
FBA_A485,89
FBA_A585,89
FBA_A685,89
FBA_A785,89
FBA_A885,89
FBA_A985,89
FBA_A1085,89
FBA_A1185,89
FBA_A1285,89
FBA_A1385,89
FBA_A1585,89
FBA_BA085,89
FBA_BA185,89
FBA_BA285,89
FBA_CLK085
FBA_CLK0#85
FBA_CKE085
FBA_DQM085
FBA_DQM185
FBA_WE#85,89
FBA_CAS#85,89
FBA_RAS#85,89
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ1G63BFR-12C-GP
H5TQ1G63BFR-12C-GP
BOM CTRL
BOM CTRL
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B
VIDEO FRAME BUFFER PORT A
FBA_D11
E3
FBA_D13
F7
FBA_D9
F2
FBA_D12
F8
FBA_D8
H3
FBA_D15
H8
FBA_D10
G2
FBA_D14
H7
FBA_D3
D7
FBA_D5
C3
FBA_D0
C8
FBA_D6
C2
FBA_D2
A7
FBA_D7
A2
FBA_D1
B8
FBA_D4
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
FBA_D[63..0] 85,89 FBA_D[63..0] 85,89
FBA_DQS_WP0 85
FBA_DQS_RN0 85
FBA_DQS_WP1 85
FBA_DQS_RN1 85
FBA_ODT0 85
FBA_CS0# 85
FBA_RST 85,89
FB CMD mapping
Mode D-N13x
12
OPS
OPS
243R2F-2-GP
243R2F-2-GP
VRAM_CH_A_ZQ_2
R8802
R8802
C
1D5V_VGA_S01D5V_VGA_S0
FBA_VREF_0FBA_VREF_0
FBA_A085,89
FBA_A185,89
FBA_A285,89
FBA_A385,89
FBA_A485,89
FBA_A585,89
FBA_A685,89
FBA_A785,89
FBA_A885,89
FBA_A985,89
FBA_A1085,89
FBA_A1185,89
FBA_A1285,89
FBA_A1385,89
FBA_A1585,89
FBA_BA085,89
FBA_BA185,89
FBA_BA285,89
FBA_CLK085
FBA_CLK0#85
FBA_CKE085
FBA_DQM385
FBA_DQM285
FBA_WE#85,89
FBA_CAS#85,89
FBA_RAS#85,89
VRAM2
VRAM2
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ1G63BFR-12C-GP
H5TQ1G63BFR-12C-GP
BOM CTRL
BOM CTRL
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
D
FBA_D23
E3
FBA_D22
F7
FBA_D21
F2
FBA_D20
F8
FBA_D16
H3
FBA_D17
H8
FBA_D18
G2
FBA_D19
H7
FBA_D26
D7
FBA_D25
C3
FBA_D31
C8
FBA_D28
C2
FBA_D29
A7
FBA_D27
A2
FBA_D30
B8
FBA_D24
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
128 X 16
72.52G63.A0U
72.42164.D0U IC VRAM K4W2G1646C-HC11 FBGA96
64 X 16
72.51G63.H0U IC VRAM H5TQ1G63DFR-11C FBGA 96BALLS
72.41646.Q0U IC VRAM K4W1G1646G-BC11 FBGA 96BALLS
FBA_DQS_WP3 85
FBA_DQS_RN3 85
FBA_DQS_WP2 85
FBA_DQS_RN2 85
FBA_ODT0 85
FBA_CS0# 85
FBA_RST 85,89
128Mx16:
hynix - H5TQ2G63BFR-11C
Samsung - K4W2G1646C-HC11
64Mx16:
Hynix - H5TQ1G63DFR-11C
Samsung - K4W1G1646G-BC11
E
0.1uF(X7R)
K0402 ×4
OPS
OPS
12
C8801
C8801
1U10V2KX-5GP
1U10V2KX-5GP
SCD
SCD
1 1
OPS
OPS
12
C8805
C8805
U6D3V3KX-2GP
U6D3V3KX-2GP
SC1
SC1
OPS
OPS
12
C8802
C8802
1U10V2KX-5GP
1U10V2KX-5GP
SCD
SCD
OPS
OPS
12
C8806
C8806
U6D3V3KX-2GP
U6D3V3KX-2GP
SC1
SC1
1D5V_VGA_S0
OPS
OPS
OPS
12
C8803
C8803
1U10V2KX-5GP
1U10V2KX-5GP
SCD
SCD
OPS
OPS
12
C8807
C8807
U6D3V3KX-2GP
U6D3V3KX-2GP
SC1
SC1
OPS
12
C8804
C8804
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
OPS
OPS
12
C8808
C8808
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
Close to VRAM(For VRAM1 & VRAM2)
A
Combined Memory FBVDD/Q Decoupling DDR3×16 with Clamshell Layout
(DG-05587-001_v03_p.87_Table 23)
Capacitor Type Footprint Population Location
0.1uF
1uF
X7R (+/-15%、-55~125℃)
*Per clamshell pair
1.0uF(X7R)
K0603 ×8
OPS
OPS
12
C8809
C8809
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
X7R
X7R
OPS
OPS
12
C8810
C8810
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
0402
0603
OPS
OPS
OPS
12
C8811
C8811
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
OPS
12
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
B
C8812
C8812
4
8
Close to VRAM
Close to VRAM
1D5V_VGA_S0
12
OPS
OPS
R8803
R8803
1K33R2F-GP
1K33R2F-GP
FBA_VREF_0
<Core Design>
<Core Design>
12
OPS
OPS
R8804
R8804
1K33R2F-GP
1K33R2F-GP
C
OPS
OPS
12
C8813
C8813
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
D
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CHANNEL-A_VRAM1,2 (1/4)
CHANNEL-A_VRAM1,2 (1/4)
CHANNEL-A_VRAM1,2 (1/4)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA48
LA48
LA48
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
88 103Friday, January 06, 2012
88 103Friday, January 06, 2012
88 103Friday, January 06, 2012
E
SD
SD
SD
Page 89
A
VRAM3
VRAM3
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
4 4
FBA_VREF_1 FBA_VREF_1
VRAM_CH_A_ZQ_3
OPS
OPS
12
3R2F-2-GP
3R2F-2-GP
R8901
R8901
24
24
3 3
FB CMD mapping
Mode D-N13x
2 2
FBA_A085,88
FBA_A185,88
FBA_A285,88
FBA_A385,88
FBA_A485,88
FBA_A585,88
FBA_A685,88
FBA_A785,88
FBA_A885,88
FBA_A985,88
FBA_A1085,88
FBA_A1185,88
FBA_A1285,88
FBA_A1385,88
FBA_A1585,88
FBA_BA085,88
FBA_BA185,88
FBA_BA285,88
FBA_CLK185
FBA_CLK1#85
FBA_CKE185
FBA_DQM685
FBA_DQM485
FBA_WE#85,88
FBA_CAS#85,88
FBA_RAS#85,88
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ1G63BFR-12C-GP
H5TQ1G63BFR-12C-GP
BOM CTRL
BOM CTRL
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B
VIDEO FRAME BUFFER PORT A
FBA_D35
E3
FBA_D38
F7
FBA_D33
F2
FBA_D34
F8
FBA_D32
H3
FBA_D37
H8
FBA_D36
G2
FBA_D39
H7
FBA_D49
D7
FBA_D54
C3
FBA_D48
C8
FBA_D55
C2
FBA_D51
A7
FBA_D53
A2
FBA_D50
B8
FBA_D52
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
FBA_D[63..0] 85,88 FBA_D[63..0] 85,88
FBA_DQS_WP6 85
FBA_DQS_RN6 85
FBA_DQS_RN4 85
FBA_ODT1 85
FBA_CS1# 85
FBA_RST 85,88
C
OPS
OPS
12
R8902
R8902
243R2F-2-GP
243R2F-2-GP
FB CMD mapping
Mode D-N13x
1D5V_VGA_S01D5V_VGA_S0
VRAM_CH_A_ZQ_4
FBA_A085,88
FBA_A185,88
FBA_A285,88
FBA_A385,88
FBA_A485,88
FBA_A585,88
FBA_A685,88
FBA_A785,88
FBA_A885,88
FBA_A985,88
FBA_A1085,88
FBA_A1185,88
FBA_A1285,88
FBA_A1385,88
FBA_A1585,88
FBA_BA085,88
FBA_BA185,88
FBA_BA285,88
FBA_CLK185
FBA_CLK1#85
FBA_CKE185
FBA_DQM785
FBA_DQM585
FBA_WE#85,88
FBA_CAS#85,88
FBA_RAS#85,88
D
VRAM4
VRAM4
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ1G63BFR-12C-GP
H5TQ1G63BFR-12C-GP
BOM CTRL
BOM CTRL
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E
FBA_D44
E3
FBA_D43
F7
FBA_D47
F2
FBA_D45
F8
FBA_D42
H3
FBA_D40
H8
FBA_D46
G2
FBA_D41
H7
FBA_D56
D7
FBA_D62
C3
FBA_D61
C8
FBA_D60
C2
FBA_D57
A7
FBA_D59
A2
FBA_D58
B8
FBA_D63
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
FBA_DQS_WP7 85
FBA_DQS_RN7 85
FBA_DQS_WP5 85FBA_DQS_WP4 85
FBA_DQS_RN5 85
FBA_ODT1 85
FBA_CS1# 85
FBA_RST 85,88
0.1uF(X7R)
K0402 ×4
OPS
OPS
OPS
12
C8901
C8901
D1U10V2KX-5GP
D1U10V2KX-5GP
SC
SC
1 1
OPS
OPS
12
C8905
C8905
1U6D3V3KX-2GP
1U6D3V3KX-2GP
SC
SC
OPS
12
C8902
C8902
D1U10V2KX-5GP
D1U10V2KX-5GP
SC
SC
OPS
OPS
12
C8906
C8906
1U6D3V3KX-2GP
1U6D3V3KX-2GP
SC
SC
1D5V_VGA_S0
OPS
OPS
OPS
12
C8903
C8903
D1U10V2KX-5GP
D1U10V2KX-5GP
SC
SC
OPS
OPS
12
C8907
C8907
1U6D3V3KX-2GP
1U6D3V3KX-2GP
SC
SC
OPS
12
C8904
C8904
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
OPS
OPS
12
C8908
C8908
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
Close to VRAM(For VRAM3 & VRAM4)
A
Combined Memory FBVDD/Q Decoupling DDR3×16 with Clamshell Layout
(DG-05587-001_v03_p.87_Table 23)
Capacitor Type Footprint Population Location
0.1uF
1uF
X7R (+/-15%、-55~125℃)
*Per clamshell pair
1.0uF(X7R)
K0603 ×8
OPS
OPS
12
C8909
C8909
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
X7R
X7R
OPS
OPS
12
C8910
C8910
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
0402
0603
OPS
OPS
12
C8911
C8911
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
OPS
OPS
12
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
B
C8912
C8912
4
8
Close to VRAM
Close to VRAM
1D5V_VGA_S0
12
OPS
OPS
R8903
R8903
1K33R2F-GP
1K33R2F-GP
FBA_VREF_1
<Core Design>
<Core Design>
12
OPS
OPS
R8904
R8904
1K33R2F-GP
1K33R2F-GP
C
OPS
OPS
12
C8913
C8913
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
D
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CHANNEL-A_VRAM3,4 (2/4)
CHANNEL-A_VRAM3,4 (2/4)
CHANNEL-A_VRAM3,4 (2/4)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA48
LA48
LA48
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
89 103Friday, January 06, 2012
89 103Friday, January 06, 2012
89 103Friday, January 06, 2012
E
SD
SD
SD
Page 90
A
1D5V_VGA_S0
4 4
FBB_VREF_0
VRAM_CH_C_ZQ_1
12
OPS
OPS
3R2F-2-GP
3R2F-2-GP
R9001
R9001
24
24
3 3
FB CMD mapping
Mode D-N13x
FBB_A085,91
FBB_A185,91 FBB_A285,91
FBB_A285,91
FBB_A385,91
FBB_A485,91
FBB_A585,91
FBB_A685,91
FBB_A785,91
FBB_A885,91
FBB_A985,91
FBB_A1085,91
FBB_A1185,91
FBB_A1285,91
FBB_A1385,91
FBB_A1585,91
FBB_BA085,91
FBB_BA185,91
FBB_BA285,91
FBB_CLK0#85
FBB_CKE085
FBB_DQM185
FBB_DQM085
FBB_WE#85,91
FBB_CAS#85,91
FBB_RAS#85,91
VRAM5
VRAM5
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ1G63BFR-12C-GP
H5TQ1G63BFR-12C-GP
BOM CTRL
BOM CTRL
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B
VIDEO FRAME BUFFER PORT C
FBB_D1
E3
FBB_D3
F7
FBB_D0
F2
FBB_D2
F8
FBB_D5
H3
FBB_D4
H8
FBB_D7
G2
FBB_D6
H7
FBB_D13
D7
FBB_D11
C3
FBB_D14
C8
FBB_D10
C2
FBB_D12
A7
FBB_D8
A2
FBB_D15
B8
FBB_D9
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
FBB_D[63..0] 85,91
FBB_DQS_WP1 85
FBB_DQS_RN1 85
FBB_DQS_WP0 85
FBB_DQS_RN0 85
FBB_ODT0 85
FBB_CS0# 85
FBB_RST 85,91
C
FBB_VREF_0
VRAM_CH_C_ZQ_2
OPS
OPS
12
R9002
R9002
243R2F-2-GP
243R2F-2-GP
FB CMD mapping
Mode D-N13x
FBB_A085,91
FBB_A185,91
FBB_A385,91
FBB_A485,91
FBB_A585,91
FBB_A685,91
FBB_A785,91
FBB_A885,91
FBB_A985,91
FBB_A1085,91
FBB_A1185,91
FBB_A1285,91
FBB_A1385,91
FBB_A1585,91
FBB_BA085,91
FBB_BA185,91
FBB_BA285,91
FBB_CLK085
FBB_CLK0#85FBB_CLK085
FBB_CKE085
FBB_DQM285
FBB_DQM385
FBB_WE#85,91
FBB_CAS#85,91
FBB_RAS#85,91
1D5V_VGA_S0
VRAM6
VRAM6
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ1G63BFR-12C-GP
H5TQ1G63BFR-12C-GP
BOM CTRL
BOM CTRL
D
FBB_D[63..0] 85,91
FBB_DQS_WP2 85
FBB_DQS_RN2 85
FBB_DQS_WP3 85
FBB_DQS_RN3 85
FBB_ODT0 85
FBB_CS0# 85
FBB_RST 85,91
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
CS#
FBB_D29
E3
FBB_D31
F7
FBB_D28
F2
FBB_D24
F8
FBB_D27
H3
FBB_D30
H8
FBB_D25
G2
FBB_D26
H7
FBB_D20
D7
FBB_D17
C3
FBB_D23
C8
FBB_D18
C2
FBB_D21
A7
FBB_D16
A2
FBB_D22
B8
FBB_D19
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
E
2 2
0.1uF(X7R)
K0402 ×4
OPS
OPS
OPS
12
C9001
C9001
D1U10V2KX-5GP
D1U10V2KX-5GP
SC
SC
1 1
OPS
OPS
12
C9005
C9005
1U6D3V3KX-2GP
1U6D3V3KX-2GP
SC
SC
OPS
12
C9002
C9002
D1U10V2KX-5GP
D1U10V2KX-5GP
SC
SC
OPS
OPS
12
C9006
C9006
1U6D3V3KX-2GP
1U6D3V3KX-2GP
SC
SC
1D5V_VGA_S0
OPS
OPS
12
C9003
C9003
D1U10V2KX-5GP
D1U10V2KX-5GP
SC
SC
OPS
OPS
12
C9007
C9007
1U6D3V3KX-2GP
1U6D3V3KX-2GP
SC
SC
OPS
OPS
12
C9004
C9004
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
OPS
OPS
12
C9008
C9008
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
Close to VRAM(For VRAM5 & VRAM6)
A
Combined Memory FBVDD/Q Decoupling DDR3×16 with Clamshell Layout
(DG-05587-001_v03_p.87_Table 23)
Capacitor Type Footprint Population Location
0.1uF
1uF
X7R (+/-15%、-55~125℃)
*Per clamshell pair
1.0uF(X7R)
K0603 ×8
OPS
OPS
12
C9009
C9009
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
X7R
X7R
OPS
OPS
12
C9010
C9010
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
0402
0603
OPS
OPS
12
C9011
C9011
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
OPS
OPS
12
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
B
C9012
C9012
4
8
Close to VRAM
Close to VRAM
1D5V_VGA_S0
12
OPS
OPS
R9003
R9003
1K33R2F-GP
1K33R2F-GP
FBB_VREF_0
<Core Design>
<Core Design>
12
OPS
OPS
R9004
R9004
1K33R2F-GP
1K33R2F-GP
C
OPS
OPS
12
C9013
C9013
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
D
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CHANNEL-C_VRAM5,6 (3/4)
CHANNEL-C_VRAM5,6 (3/4)
CHANNEL-C_VRAM5,6 (3/4)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA48
LA48
LA48
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
90 103Friday, January 06, 2012
90 103Friday, January 06, 2012
90 103Friday, January 06, 2012
E
SD
SD
SD
Page 91
A
B
C
D
E
1D5V_VGA_S0
4 4
FBB_VREF_1
VRAM_CH_C_ZQ_3
12
OPS
OPS
3R2F-2-GP
3R2F-2-GP
R9101
R9101
24
24
3 3
FB CMD mapping
Mode D-N13x
2 2
FBB_A085,90
FBB_A185,90
FBB_A385,90
FBB_A485,90
FBB_A585,90
FBB_A685,90
FBB_A785,90
FBB_A885,90
FBB_A985,90
FBB_A1085,90
FBB_A1185,90
FBB_A1285,90
FBB_A1385,90
FBB_A1585,90
FBB_BA085,90
FBB_BA185,90
FBB_BA285,90
FBB_CLK185
FBB_CLK1#85
FBB_CKE185
FBB_DQM685
FBB_DQM485
FBB_WE#85,90
FBB_CAS#85,90
FBB_RAS#85,90
VRAM7
VRAM7
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ1G63BFR-12C-GP
H5TQ1G63BFR-12C-GP
BOM CTRL
BOM CTRL
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBB_A085,90
FBB_A185,90FBB_A285,90
FBB_A385,90
FBB_A485,90
FBB_A585,90
FBB_A685,90
FBB_A785,90
FBB_A885,90
FBB_A985,90
FBB_A1085,90
FBB_A1185,90
FBB_A1285,90
FBB_A1385,90
FBB_A1585,90
FBB_BA085,90
FBB_BA185,90
FBB_BA285,90
FBB_CLK185
FBB_CLK1#85
FBB_CKE185
FBB_DQM585
FBB_DQM785
FBB_WE#85,90
FBB_CAS#85,90
FBB_RAS#85,90
1D5V_VGA_S0
VRAM8
VRAM8
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
H5TQ1G63BFR-12C-GP
H5TQ1G63BFR-12C-GP
BOM CTRL
BOM CTRL
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBB_D60
E3
FBB_D58
F7
FBB_D62
F2
FBB_D57
F8
FBB_D63
H3
FBB_D59
H8
FBB_D61
G2
FBB_D56
H7
FBB_D40
D7
FBB_D47
C3
FBB_D41
C8
FBB_D44
C2
FBB_D42
A7
FBB_D46
A2
FBB_D43
B8
FBB_D45
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
FBB_D[63..0] 85,90
FBB_DQS_WP5 85
FBB_DQS_RN5 85
FBB_DQS_WP7 85
FBB_DQS_RN7 85
FBB_ODT1 85
FBB_CS1# 85
FBB_RST 85,90
FBB_D35
E3
FBB_D37
F7
FBB_D32
F2
FBB_D39
F8
FBB_D36
H3
FBB_D38
H8
FBB_D33
G2
FBB_D34
H7
FBB_D51
D7
FBB_D53
C3
FBB_D48
C8
FBB_D54
C2
FBB_D49
A7
FBB_D55
A2
FBB_D50
B8
FBB_D52
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
FBB_D[63..0] 85,90
VIDEO FRAME BUFFER PORT C
FBB_DQS_WP6 85
FBB_DQS_RN6 85
FBB_DQS_WP4 85
FBB_DQS_RN4 85
FBB_ODT1 85
FBB_CS1# 85
FBB_RST 85,90 FBB_A285,90
12
OPS
OPS
243R2F-2-GP
243R2F-2-GP
FBB_VREF_1
VRAM_CH_C_ZQ_4
R9102
R9102
FB CMD mapping
Mode D-N13x
0.1uF(X7R)
K0402 ×4
OPS
OPS
12
C9101
C9101
D1U10V2KX-5GP
D1U10V2KX-5GP
SC
SC
1 1
OPS
OPS
12
C9105
C9105
1U6D3V3KX-2GP
1U6D3V3KX-2GP
SC
SC
OPS
OPS
12
C9102
C9102
D1U10V2KX-5GP
D1U10V2KX-5GP
SC
SC
OPS
OPS
12
C9106
C9106
1U6D3V3KX-2GP
1U6D3V3KX-2GP
SC
SC
1D5V_VGA_S0
OPS
OPS
OPS
12
C9103
C9103
D1U10V2KX-5GP
D1U10V2KX-5GP
SC
SC
OPS
OPS
12
C9107
C9107
1U6D3V3KX-2GP
1U6D3V3KX-2GP
SC
SC
OPS
12
C9104
C9104
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
OPS
OPS
12
C9108
C9108
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
Close to VRAM(For VRAM7 & VRAM8)
A
Combined Memory FBVDD/Q Decoupling DDR3×16 with Clamshell Layout
(DG-05587-001_v03_p.87_Table 23)
Capacitor Type Footprint Population Location
0.1uF
1uF
X7R (+/-15%、-55~125℃)
*Per clamshell pair
1.0uF(X7R)
K0603 ×8
OPS
OPS
12
C9109
C9109
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
X7R
X7R
OPS
OPS
12
C9110
C9110
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
0402
0603
OPS
OPS
12
C9111
C9111
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
OPS
OPS
12
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
B
C9112
C9112
4
8
Close to VRAM
Close to VRAM
1D5V_VGA_S0
12
OPS
OPS
R9103
R9103
1K33R2F-GP
1K33R2F-GP
FBB_VREF_1
<Core Design>
<Core Design>
12
OPS
OPS
R9104
R9104
1K33R2F-GP
1K33R2F-GP
C
OPS
OPS
12
C9113
C9113
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
D
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CHANNEL-C_VRAM7,8 (4/4)
CHANNEL-C_VRAM7,8 (4/4)
CHANNEL-C_VRAM7,8 (4/4)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA48
LA48
LA48
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
91 103Friday, January 06, 2012
91 103Friday, January 06, 2012
91 103Friday, January 06, 2012
E
SD
SD
SD
Page 92
5
4
3
2
1
SSID = PWR.Plane.Regulator_GFX
PWR_DC BATOUT_VG A_CORE
DCBATOUT PWR_D CBATOUT_V GA_CORE
PG9201
PG9201
1 2
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
PG9202
D D
C C
B B
PG9202
1 2
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
PG9203
PG9203
1 2
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
PG9204
PG9204
1 2
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
PG9205
PG9205
1 2
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
PG9206
PG9206
1 2
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
NV_VID086
NV_VID186
NV_VID286
NV_VID386
NV_VID486
NV_VID586
NVVDD
Boot Voltage
NV_VID1
NV_VID3
NV_VID4
PR9221 0R0402- PADPR9221 0R0402-PAD
1 2
PR9222 0R0402- PADPR9222 0R0402-PAD
1 2
PR9223 0R0402- PADPR9223 0R0402-PAD
1 2
PR9224 0R0402- PADPR9224 0R0402-PAD
1 2
PR9257 0R0402- PADPR9257 0R0402-PAD
1 2
PR9258 0R0402- PADPR9258 0R0402-PAD
1 2
PWR_VGA _CORE_AGND
3D3V_VGA_S0
12
DY
DY
PR9214
PR9214
10KR2J-3-GP
10KR2J-3-GP
12
OPS
OPS
PR9229
PR9229
10KR2J-3-GP
10KR2J-3-GP
PR9215
PR9215
PR9230
PR9230
PR9215
PR9230
PR9217
PR9232
PR9218
PR9233
12
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
12
DY
DY
10KR2J-3-GP
10KR2J-3-GP
N13P-GS
71.0N13P.00U
0.9V
VID[6:0]=0110000
DY
63.10334.1DL
DY
63.10334.1DL
63.10334.1DL
DY DY63.10334.1DL DY
OPS-BOM CTRL
OPS-BOM CTRL
12
12
12
DY
DY
PR9217
PR9217
PR9218
PR9218
PR9216
PR9216
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
OPS-BOM CTRL
OPS-BOM CTRL
12
12
12
OPS
OPS
PR9232
PR9232
PR9233
PR9233
PR9231
PR9231
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
OPS-BOM CTRL
OPS-BOM CTRL
OPS-BOM CTRL
OPS-BOM CTRL
12
OPS
OPS
PR9219
PR9219
PR9220
PR9220
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
12
DY
DY
PR9235
PR9235
PR9234
PR9234
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
N13P-GL
71.0N13P.B0U
0.975V
VID[6:0]=0101010
63.10334.1DL
DY
63.10334.1DL
DY
DY
12
DY
DY
12
OPS
OPS
N13M-GS
71.0N13M.E0U
0.9V
VID[6:0]=0110000
DY
63.10334.1DL
DY
63.10334.1DL
63.10334.1DL
NVGND_SEN SE83
NVVDD_SEN SE83
3D3V_VGA_S0
PR9256 10KR2J- 3-GP
PR9256 10KR2J- 3-GP
PWR_VGA_CORE_CSP1
12
DY
DY
PC9221
PC9221
SC330P50V2KX-3GP
SC330P50V2KX-3GP
1 2
OPS
OPS
SCD1U50V3KX- GP
SCD1U50V3KX- GP
N13M-GE1
71.0N13M.C0U
0.875V
VID[6:0]0110010
63.10334.1DL
DY
DY
63.10334.1DL
63.10334.1DL
OPS
OPS
PC9208 SC2D2U 10V3KX-1GP
PC9208 SC2D2U 10V3KX-1GP
1 2
PC9209 SC2D2U 10V3KX-1GP
PC9209 SC2D2U 10V3KX-1GP
1 2
OPS
OPS
PC9214 SCD22U 10V2KX-1GP
PC9214 SCD22U 10V2KX-1GP
1 2
OPS
PWR_VGA _CORE_AGN D
VGA_CSP1_R
VGA_CSN1_R
VGA_CSP2_R PWR_VGA _CORE_CSP2
VGA_CSN2_R
PWR_VGA _CORE_IMON
PC9225
PC9225
OPS
OPS
PWR_VGA_CORE_CSN1
12
DY
DY
PC9223
PC9223
PC9222
PC9222
SC330P50V2KX-3GP
SC330P50V2KX-3GP
SC330P50V2KX-3GP
SC330P50V2KX-3GP
OPS
PR9226 0R0402- PADPR9226 0R0402-PAD
1 2
PR9227 0R0402- PADPR9227 0R0402-PAD
1 2
PR9236 0R0402- PADPR9236 0R0402-PAD
1 2
PR9237 0R0402- PADPR9237 0R0402-PAD
1 2
PR9239 0R0402- PADPR9239 0R0402-PAD
1 2
PR9241 0R0402- PADPR9241 0R0402-PAD
1 2
PC9217 SC3300P5 0V2KX-1GP
PC9217 SC3300P5 0V2KX-1GP
1 2
PR9243 11K8R2F -GP
PR9243 11K8R2F -GP
1 2
12
3D3V_VGA_S0
PWR_VGA_CORE_CSP2
PWR_VGA_CORE_CSN2
12
12
DY
DY
DY
DY
PC9224
PC9224
PWR_VGA _CORE_AGN D
SC330P50V2KX-3GP
SC330P50V2KX-3GP
OPS
OPS
OPS
OPS
PWR_VGA _CORE_VR_O N
1 2
PR9249
PR9249
0R0402-PAD
0R0402-PAD
PR9252
PR9252
DY
DY
0R2J-2-GP
0R2J-2-GP
1 2
PWR_VGA _CORE_SLP
PR9254
PR9254
0R0402-PAD
0R0402-PAD
1 2
5V_S0
PWR_VGA _CORE_VBST1
PWR_VGA _CORE_VBST2
PWR_VGA _CORE_VREF
PWR_VGA _CORE_VID0
PWR_VGA _CORE_VID1
PWR_VGA _CORE_VID2
PWR_VGA _CORE_VID3
PWR_VGA _CORE_VID4
PWR_VGA _CORE_VID5
PWR_VGA _CORE_VID6
PWR_VGA _CORE_CSP1
PWR_VGA _CORE_CSN 1
PWR_VGA _CORE_CSN 2
PWR_VGA _CORE_GFB
PWR_VGA _CORE_VFB
PWR_VGA_CORE_PCNT
PWR_VGA _CORE_AGN D
PWR_VGA _CORE_SLEW
12
PU9202
PU9206
PU9201
PU9201
26
38
22
29
40
20
19
18
17
16
15
14
6
5
3
4
7
8
12
13
35
37
TPS51728RHAR -GP
TPS51728RHAR -GP
PR9253
PR9253
124KR2F-GP
124KR2F-GP
OPS
OPS
0R0402-PAD
0R0402-PAD
V5IN
V5FILT
VBST1
VBST2
VREF
VID0
VID1
VID2
VID3
VID4
VID5
VID6
CSP1
CSN1
CSP2
CSN2
GFB
VFB
SLP
PCNT
EN
SLEW
OPS
OPS
84.03606.037
FDMS3606S-GP-U
84.03606.037
FDMS3606S-GP-U
PWR_VGA _CORE_V5FILT
PR9207
PR9207
1 2
DY
DY
PR9210
PR9210
0R2J-2-GP
0R2J-2-GP
1 2
PWR_VGA _CORE_AGN D
PWR_VGA _CORE_TRIPSE L
TRIPSEL
TONSEL
DRVH1
DRVL1
DRVH2
DRVL2
THAL#
IMON
OSRSEL
PGD
PG#
DROOP
LL1
LL2
THRM
PU
PGND
GND
GND
PWR_VGA _CORE_AGN D
PR9251
PR9251
0R2J-2-GP
0R2J-2-GP
DY
DY
1 2
PWR_VGA_CORE_VREF
DY
DY
PR9208
PR9208
1 2
1 2
31
36
21
24
30
27
10
11
32
33
34
39
23
28
9
1
25
2
41
Main source
2nd source
0R2J-2-GP
0R2J-2-GP
0R0402-PAD
0R0402-PAD
PR9211
PR9211
3D3V_VGA_S0
PWR_VGA _CORE_VREFPW R_VGA_C ORE_V5FILT
PWR_VGA _CORE_THA L#
PWR_VGA _CORE_IMON
PWR_VGA _CORE_OSR SEL
DGPU_PW ROK 22,93
PWR_VGA _CORE_DR OOP
PWR_VGA _CORE_LL1
PWR_VGA _CORE_LL2
PWR_VGA _CORE_THR M
PWR_VGA _CORE_V5FILT
PR9238
PR9238
OPS
OPS
PR9244
PR9244
1 2
2KR2F-3-GP
2KR2F-3-GP
PC9219
PC9219
SC220P50V2KX-3GP
SC220P50V2KX-3GP
OPS
OPS
PWR_VGA _CORE_UGA TE1
PWR_VGA_CORE_VBST1
12
PR9213
PR9213
56R2J-4-GP
56R2J-4-GP
OPS
OPS
PWR_VGA _CORE_VBST2
OPS
OPS
NTC-150K-GP
NTC-150K-GP
1 2
PWR_VGA _CORE_THR M_R
PWR_VGA _CORE_LGATE 2
12
PR9248
PR9248
9K09R2F-GP
9K09R2F-GP
OPS
OPS
12
VGA_VREF_L
12
OPS
OPS
PC9220
PC9220
SC3300P50V2KX-1G P
SC3300P50V2KX-1G P
PWR_VGA _CORE_VREF
BOM control
VGA_VBST1_R
1 2
PR9209
PR9209
2D2R2J-GP
2D2R2J-GP
OPS
OPS
Q1: Id=11A, Qg=10~14nC,
Rdson=7.5~9.8 mohm
Q2: Id=23A, Qg=27~38nC,
Rdson=1.7~2.1 mohm
PWR_VGA _CORE_UGA TE2
PR9225
PR9225
1 2
OPS
OPS
2D2R2J-GP
2D2R2J-GP
1 2
PC9206
PC9206
SCD1U50V3KX- GP
SCD1U50V3KX- GP
OPS
OPS
PWR_VGA _CORE_LGATE 1
VGA_VBST2_R
1 2
PC9215
PC9215
SCD1U50V3KX- GP
SCD1U50V3KX- GP
OPS
OPS
OPS
OPS
12
PC9202
PC9202
OPS
OPS
OPS
OPS
12
12
PC9204
PC9204
PC9203
PC9203
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
PU9202
PU9202
2
3
1
4
10
9
7
6
8
5
FDMS3600-02-R JK0215-COLAY-G P
FDMS3600-02-R JK0215-COLAY-G P
84.03606.037
84.03606.037
PR9212
PR9212
2D2R3J-2-GP
2D2R3J-2-GP
DY
DY
1 2
PWR_VGA _CORE_TER 1
12
PC9207
PC9207
SC470P50V2KX-3GP
SC470P50V2KX-3GP
DY
DY
PWR_DC BATOUT_VG A_CORE
OPS
OPS
OPS
OPS
PC9211
PC9211
PC9210
PC9210
12
12
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
PU9206
PU9206
2
3
1
4
10
9
7
6
8
5
FDMS3600-02-R JK0215-COLAY-G P
FDMS3600-02-R JK0215-COLAY-G P
84.03606.037
84.03606.037
PR9242
PR9242
2D2R3J-2-GP
2D2R3J-2-GP
DY
DY
1 2
PWR_VGA _CORE_TER 2
12
PC9216
PC9216
SC470P50V2KX-3GP
SC470P50V2KX-3GP
DY
DY
1 2
PR9201
PR9201
30K9R2F-GP
30K9R2F-GP
OPS
OPS
PR9203
PR9203
76K8R2F-GP
76K8R2F-GP
OPS
OPS
PL9201
PL9201
1 2
COIL-D36UH- 5-GP
COIL-D36UH- 5-GP
Panasonic. 0.36uH 10*11.5*4
DCR=1.1mohm
Idc=17A, Isat=24A
OPS
OPS
PC9212
PC9212
12
SC10U25V5KX-GP
SC10U25V5KX-GP
OPS
OPS
PL9202
PL9202
1 2
COIL-D36UH- 5-GP
COIL-D36UH- 5-GP
1 2
PR9250
PR9250
30K9R2F-GP
30K9R2F-GP
OPS
OPS
OPS
OPS
PG9211
PG9211
OPS
OPS
PR9246
PR9246
12
42K2R2F-L-GP
42K2R2F-L-GP
12
1 2
PG9213
PG9213
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 2
PR9240
PR9240
12
76K8R2F-GP
76K8R2F-GP
PR9247
PR9247
OPS
OPS
VGA_CSP1_R
OPS
OPS
PR9202
PR9202
12
PWR_VGA _CORE_PN1
OPS
OPS
OPS
OPS
PR9204
PR9204
NTC-150K-G P
NTC-150K-G P
VGA_CSN1_R
VGA_CORE
PT9201
PT9201
ST330U2VDM-4-GP
ST330U2VDM-4-GP
OPS
OPS
12
VGA_CORE
12
OPS
OPS
NTC-150K-GP
NTC-150K-GP
12
PWR_VGA _CORE_PN2
1 2
VGA_CSP2_R
42K2R2F-L-GP
42K2R2F-L-GP
PC9201
PC9201
PT9202
PT9202
OPS
OPS
12
PT9203
PT9203
OPS
OPS
12
VGA_CSN2_R
PC9218
PC9218
OPS
OPS
SCD012U25V2KX-GP
SCD012U25V2KX-GP
ST330U2VDM-4-GP
ST330U2VDM-4-GP
ST330U2VDM-4-GP
ST330U2VDM-4-GP
SCD012U25V2KX-GP
SCD012U25V2KX-GP
PWR_VGA _CORE_AGND
12
PR9255
PR9255
0R0402-PAD
0R0402-PAD
A A
5
4
PWR_VGA _CORE_AGN D
3
DGPU_PW ROK
3D3V_VGA_S0
12
PR9228
PR9228
10KR2J-3-GP
10KR2J-3-GP
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
TPS51728_VGA_CORE
TPS51728_VGA_CORE
TPS51728_VGA_CORE
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
<Doc>
<Doc>
<Doc>
1
SD
SD
SD
103Friday, January 06, 2012
103Friday, January 06, 2012
103Friday, January 06, 2012
92
92
92
Page 93
5
4
3
2
1
+3VS to 3.3V_DELAY Transfer
DY
DY
1 2
R9301 0R5J-5-GP
R9301 0R5J-5-GP
OPS
OPS
D
3D3V_S0
D D
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C C
B B
DY
DY
C9309
C9309
3D3V_S0
DGPU_PW R_EN#18
12
12
R9302
R9302
100KR2J-1-GP
100KR2J-1-GP
OPS
OPS
2nd = 84.2N702.A3F
2nd = 84.2N702.A3F
1 2
R9308
R9308
30KR2F-GP
30KR2F-GP
OPS
OPS
S
3.3V_ALW _1
Q9301
Q9301
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
OPS
OPS
Q9305
Q9305
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.J31
2ND = 84.2N702.J31
OPS
OPS
Q9302
Q9302
AO3419L-GP
AO3419L-GP
G
84.03419.031
84.03419.031
2nd = 84.00048.031
2nd = 84.00048.031
3rd = 84.03334.031
3rd = 84.03334.031
5
6
123 4
DGPU_PWR_EN
D
3D3V_VGA_S0
3.3V_RUN_VGA_1
C9308
C9308
12
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
OPS
OPS
12
R9304
R9304
100R2J-2-GP
100R2J-2-GP
OPS
OPS
DCBATOUT
RUN_ENABLE
DGPU_PW ROK22,92
3D3V_VGA_S0
1 2
R9315
R9315
0R2J-2-GP
0R2J-2-GP
OPS
OPS
1 2
R9316
R9316
0R2J-2-GP
0R2J-2-GP
DY
DY
AO4468, SO-8
Id=11.6A, Qg=9~12nC
Rdson=17.4~22m ohm
DCBATOUT_RUN
1 2
PR9315
PR9315
10KR2J-3-GP
10KR2J-3-GP
DY
DY
1 2
R9310
R9310
0R2J-2-GP
0R2J-2-GP
OPS
OPS
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
R9317
R9317
1 2
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
1 2
R9305
R9305
330KR2J-L1-GP
330KR2J-L1-GP
OPS
OPS
2ND = 84.2N702.J31
2ND = 84.2N702.J31
DGPU_PW ROK_R
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
3D3V_S0
12
C9301
C9301
OPS
OPS
RUN_ENABLE_1
DIS_EN_1D5_RUN_R
84.2N702.J31
84.2N702.J31
C9304
C9304
DY
DY
R9318
R9318
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
DGPU_PW ROK# DGPU_PWROK_R
1D5V_S3 1D5V_VGA_S0
12
100KR2J-1-GP
100KR2J-1-GP
OPS
OPS
Q9304
Q9304
2N7002K-2-GP
2N7002K-2-GP
12
2nd = 84.04168.037
2nd = 84.04168.037
S D
G
2ND = 84.00610.C31
2ND = 84.00610.C31
12
R9306
R9306
OPS
OPS
DIS_EN_1D5_RUN
D
G
1D5V_VGA_S0
U9301
U9301
S
D
S
D
8
D
D
7
D
D
6
AO4494L-GP
AO4494L-GP
84.04494.037
84.04494.037
OPS
OPS
Q9303
Q9303
NDS0610-NL-GP
NDS0610-NL-GP
84.S0610.B31
84.S0610.B31
OPS
OPS
S
S
S
S
S
GD
GD
RUNON_R
5K1R2F-2-GP
5K1R2F-2-GP
Q9309
Q9309
5
6
2N7002KDW-GP
2N7002KDW-GP
OPS
OPS
1
2
3
45
R9307
R9307
OPS
OPS
34
2
1
12
R9313
R9313
0R2J-2-GP
0R2J-2-GP
TC9301
TC9301
12
SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
OPS
OPS
RUNON_R_1
1 2
R9303
R9303
5K1R2F-2-GP
5K1R2F-2-GP
OPS
OPS
D9301
D9301
MMPZ5239BPT-GP
MMPZ5239BPT-GP
83.9R103.D3F
83.9R103.D3F
OPS
OPS
A K
1 2
DY
DY
1.05V to 1.05V_VGA_S0 Transfer
12
C9302
C9302
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
OPS
OPS
C9303
C9303
12
SCD1U50V3KX-GP
SCD1U50V3KX-GP
OPS
OPS
1D05V_VTT 1D05V_VGA_S0
2nd = 84.08882.037
2nd = 84.08882.037
R9314
R9314
30KR2F-GP
30KR2F-GP
OPS
OPS
2N7002KDW-GP
2N7002KDW-GP
D
D
8
D
D
7
D
D
6
AO4468-GP
AO4468-GP
84.04468.037
84.04468.037
OPS
OPS
1 2
R9311
R9311
75R2F-2-GP
75R2F-2-GP
OPS
OPS
Q9308
Q9308
OPS
OPS
check layout
U9302
U9302
S
S
S
S
S
S
GD
GD
RUNON_R_2RUNON_R
12
1D5V_VGA_S0
12
DIS_FBVDD_L
6
123 4
1
2
3
45
C9310
C9310
SCD1U50V3KX-GP
SCD1U50V3KX-GP
OPS
OPS
DGPU_PWROK#DGPU_PWROK#
5
3.6A
R9312
R9312
75R2F-2-GP
75R2F-2-GP
OPS
OPS
1D05V_VGA_S0
12
DIS_1D05V_NV_L
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
DISCRETE VGA POWER
DISCRETE VGA POWER
DISCRETE VGA POWER
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
LA480
LA480
LA480
1
93 103Friday, January 06, 2012
93 103Friday, January 06, 2012
93 103Friday, January 06, 2012
SD
SD
SD
Page 94
5
DCCBBAA
4
3
2
1
D
BLANK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LA480 SD
A4
LA480 SD
A4
LA480 SD
A4
Date: Sheet of
Date: Sheet of
Date: Sheet of
94 103Friday, January 06, 2012
94 103Friday, January 06, 2012
94 103Friday, January 06, 2012
Page 95
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
95 103
95 103
95 103
1
SD
Page 96
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
TOUCH PANEL
TOUCH PANEL
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
TOUCH PANEL
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
96 103
96 103
96 103
1
SD
Page 97
5
4
3
2
1
CPU Plate
H16
H14
H14
HOLET157B276R134-GP
HOLET157B276R134-GP
ZZ.SCREW.091
ZZ.SCREW.091
D D
1
H15
H15
HOLET157B276R134-GP
HOLET157B276R134-GP
ZZ.SCREW.091
ZZ.SCREW.091
1
H16
HOLET157B276R134-GP
HOLET157B276R134-GP
ZZ.SCREW.091
ZZ.SCREW.091
1
H17
H17
HOLET157B276R134-GP
HOLET157B276R134-GP
ZZ.SCREW.091
ZZ.SCREW.091
1
VGA Std-Off
H2
H1
H1
STF237R128H42-1-GP
STF237R128H42-1-GP
1
34.4GD01.001
34.4GD01.001
H2
STF237R128H42-1-GP
STF237R128H42-1-GP
1
34.4GD01.001
34.4GD01.001
H21
H21
STF237R128H42-1-GP
STF237R128H42-1-GP
1
34.4GD01.001
34.4GD01.001
MINI PCIE
H18
H18
STF256R89H178-GP
STF256R89H178-GP
34.4B417.001
34.4B417.001
1
DCBATOUT VCCSA
12
EC9729
EC9729
12
EC9727
EC9727
SCD1U25V2KX-GP
SCD1U25V2KX-GP
12
12
EC9728
EC9728
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
EC9730
EC9730
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
DY
DY
12
EC9731
EC9731
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
DY
12
EC9732
EC9732
XDP_DBRESET# 5,19
H_CPUPW RGD 5,22
DY
DY
12
EC9733
EC9733
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
PLT_RST# 5,18,27,31,36,65,66,71,80,82,83
14" Structure boss
H7
12
EC9713
EC9713
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
DY
H7
HOLE355X355R111-S1-GP
HOLE355X355R111-S1-GP
ZZ.00PAD.571
ZZ.00PAD.571
1
12
EC9714
EC9714
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
DY
H5
12
EC9709
EC9709
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
DY
H5
HOLE315X315R91-S1-GP
HOLE315X315R91-S1-GP
ZZ.00PAD.581
ZZ.00PAD.581
1
12
12
EC9711
EC9711
EC9710
EC9710
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
12
EC9712
EC9712
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
DY
H4
H4
HOLE256R115-GP
SC
SC
D1U25V2KX-GP
D1U25V2KX-GP
HOLE256R115-GP
ZZ.00PAD.D11
ZZ.00PAD.D11
12
EC9707
EC9707
SC
SC
D1U25V2KX-GP
D1U25V2KX-GP
1
DY
DY
12
EC9708
EC9708
H3
H3
HOLE256R115-GP
HOLE256R115-GP
ZZ.00PAD.D11
ZZ.00PAD.D11
1
C C
12
12
EC9705
EC9705
EC9706
EC9706
SC
SC
DY
DY
D1U25V2KX-GP
D1U25V2KX-GP
12
EC9715
EC9715
H8
H8
HOLE335R115-GP
HOLE335R115-GP
ZZ.00PAD.D01
ZZ.00PAD.D01
SCD1U25V2KX-GP
SCD1U25V2KX-GP
H12
DY
DY
12
EC9719
EC9719
H12
HOLE335R115-GP
HOLE335R115-GP
ZZ.00PAD.D01
ZZ.00PAD.D01
1
SCD1U25V2KX-GP
SCD1U25V2KX-GP
H11
DY
DY
12
EC9718
EC9718
H11
HOLE237R95-GP
HOLE237R95-GP
ZZ.00PAD.921
ZZ.00PAD.921
1
SCD1U25V2KX-GP
SCD1U25V2KX-GP
H10
H10
HOLE237R95-GP
HOLE237R95-GP
ZZ.00PAD.921
ZZ.00PAD.921
1
3D3V_AUX_KBC ODD_PW R_5V 5V_S53D3V_AUX_S5 3D3V_VGA_S0 VCC_CORE3D3V_S0_CAMERADCBATOUT
DY
DY
12
EC9716
EC9716
12
EC9717
EC9717
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
DY
1
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
DY
12
EC9720
EC9720
H13
H13
HOLE237R95-GP
HOLE237R95-GP
ZZ.00PAD.921
ZZ.00PAD.921
1
12
EC9721
EC9721
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
DY
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
DY
12
EC9722
EC9722
H19
H19
HOLE315R95-GP
HOLE315R95-GP
ZZ.00PAD.911
ZZ.00PAD.911
1
12
EC9723
EC9723
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
DY
DY
DY
12
EC9724
EC9724
SCD1U25V2KX-GP
SCD1U25V2KX-GP
PS_S3CNTRL
R9704
R9704
100R2J-2-GP
100R2J-2-GP
Q9704
Q9704
2N7002A-7-GP
2N7002A-7-GP
DY
DY
G
3D3V_S0 5V_S0
DY
DY
12
3D3V_RUNPWR
PS_S3CNTRL
S D
R9705
R9705
100R2J-2-GP
100R2J-2-GP
Q9705
Q9705
2N7002A-7-GP
2N7002A-7-GP
DY
DY
G
DY
DY
12
5V_RUNPWR
S D
R9701
R9701
100R2J-2-GP
100R2J-2-GP
DY
DY
Q9701
Q9701
DY
DY
G
97 103
97 103
97 103
1
1D05V_VTT
12
VTT_RUNPWR
S D
SD
SD
SD
B B
AD+
12
EC9702
EC9702
SCD1U25V2KX-GP
SCD1U25V2KX-GP
3
12
EC9703
EC9703
SCD1U25V2KX-GP
SCD1U25V2KX-GP
PM_SLP_S4#19,27,46
12
DY
DY
EC9704
EC9704
SCD1U25V2KX-GP
SCD1U25V2KX-GP
2N7002A-7-GP
2N7002A-7-GP
R9707
R9707
100R2J-2-GP
100R2J-2-GP
Q9707
Q9707
2N7002A-7-GP
2N7002A-7-GP
DY
DY
G
VCC_GFXCORE
12
DY
DY
GFX_RUNPWR
S D
PS_S3CNTRL
2N7002A-7-GP
2N7002A-7-GP
VCC_CORE
12
R9706
R9706
100R2J-2-GP
100R2J-2-GP
DY
DY
CO
RE_RUNPWR
Q9706
Q9706
2N7002A-7-GP
PS_S3CNTRL
2N7002A-7-GP
DY
DY
G
PS_S3CNTRL
S D
5
A A
VCCSA 1D5V_S3
12
R9709
R9709
100R2J-2-GP
100R2J-2-GP
DY
DY
1D05V_RUNPWR
Q9709
Q9709
DY
DY
G
4
S D
PS_S3CNTRL
2N7002A-7-GP
2N7002A-7-GP
R9702
R9702
100R2J-2-GP
100R2J-2-GP
DY
DY
Q9702
Q9702
DY
DY
G
1D8V_S0
12
1D8V_RUNPWR
S D
For Discharge
3D3V_S5
12
R9710
R9710
100KR2J-1-GP
100KR2J-1-GP
DY
DY
PM_SLP_S4
Q9710
Q9710
DY
DY
G
S D
R9711
R9711
100R2J-2-GP
100R2J-2-GP
Q9711
Q9711
2N7002A-7-GP
2N7002A-7-GP
DY
DY
G
2
DY
DY
12
1D5V_RUNPWR
S D
5V_USB2_S3 5V_USB1_S3
12
EC9725
EC9725
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
UNUSED PARTS/EMI Capacitors
UNUSED PARTS/EMI Capacitors
UNUSED PARTS/EMI Capacitors
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
EC9726
EC9726
SCD1U25V2KX-GP
SCD1U25V2KX-GP
PS_S3CNTRL36,37
SCD1U25V2KX-GP
SCD1U25V2KX-GP
LA480
LA480
LA480
2N7002A-7-GP
2N7002A-7-GP
PS_S3CNTRL
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Page 98
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Change History
Change History
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Change History
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
98 103
98 103
98 103
1
SD
Page 99
5
Intel-Power Sequence
(S5-to-S0-to-S5)
S5
3D3V_AUX_S5
D D
PM_PWRBTN#
SLP_A#
SLP_LAN#
SLP_S5#
(TEST POINT)
SLP_S4#
SLP_S3#
VccASW/
VccSPI
+3V_MINI_WLAN
S0_PWR_GOOD T11 >1ms ( VccASW to APWROK )
CL_ RST#(TEST POINT) T12 >500Us ( APWROK to CL_RST# )
1D8V_S0
1D5V_S0
VDDPWRGOOD
VCCSA
D85V_PWRGD
C C
VCC_CORE
VCC_GFXCORE
IMVP_PWRGD
SYS_PWROK
S0_PWR_GOOD
PM_DRAM_PWRGD
H_CPUPWRGD
PLT_RST#
Wake Event
Minimum duration of PWRBTN# assertion = 16mS
T09 >30us ( SLP_S5# t0 SLP_S4# )
T10 >30us ( SLP_S4# t0 SLP_S3# )
T29 >0s ( VccSUS to VccASW )
T13 >5ms<650ms ( VCCPLL to UNCOREPWRGOOD )
T17 >2ms<650ms ( VCCPLL to DRAMPWROK )
T17 >2ms<650ms ( VDDQ to DRAMPWROK )
T17 >2ms<650ms ( VCCSA to DRAMPWROK )
S0
T12 >100ms ( APWROK to PLTRST# )
T20 >100ms ( PWROK to UNCOREPWRGOOD)
T25 >1ms<100ms
( UNCOREPOWERGOOD to PLTRST# )
4
S5
Te >0s ( SLP_A# to APWROK )
Ta >30us ( SLP_S4# t0 SLP_S5# )
Tb >30us ( SLP_S3# t0 SLP_S4# )
Tc >40ns
(APWROK# to VCCASW/VCCSPI)
Tf <500ms
(SLP_3# to VCCCORE/VCCAWG)
Tk >100ns (DRAMPWROK to SLP_S4# )
Tn >30us
(PLTRST# to UNCOREPOWERGOOD )
3
Intel PCH
Pin Name
(5V/3V )
SLP_LAN# SLP_LAN#
VccASW/
VccSPI
Vcc_WLAN +3V_MINI_WLAN
PWROK/APWROK S0_PWR_GOOD
CL_ RST# CL_ RST#
VCCPLL 1D8V_S0
VR_VDDQPWRGOOD VDDPWRGOOD
VCCSA VCCSA
VccCore
IMVP7_PWRGD
SYS_PWROK SYS_PWROK
PWROK S0_PWR_GOOD
Main board PCH
Pin Name
3D3V_AUX_S5VccSUS
PM_PWRBTN#PWRBTN#
SLP_A#SLP_A#
PM_SLP_S5#SLP_S5#
PM_SLP_S4#SLP_S4#
PM_SLP_S3#SLP_S3#
VccASW/
VccSPI
1D5V_S0VDDQ
D85V_PWRGDIMVP7_VR_EN
VCC_CORE
VCC_GFXCOREVccAXG
IMVP_PWRGD
PM_DRAM_PWRGDDRAMPWROK
H_CPUPWRGDUNCOREPWRGOOD
PLT_RST#PLTRST#
(S3-to-S0-to-S3)
S3
3D3V_AUX_S5
PM_PWRBTN#
SLP_A#
SLP_LAN#
SLP_S5#
(TEST POINT)
SLP_S4#
SLP_S3#
VccASW/
VccSPI
+3V_MINI_WLAN
S0_PWR_GOOD
CL_ RST#(TEST POINT)
1D8V_S0
1D5V_S0
VDDPWRGOOD
VCCSA
D85V_PWRGD
VCC_CORE
VCC_GFXCORE
IMVP_PWRGD
SYS_PWROK
S0_PWR_GOOD
PM_DRAM_PWRGD
H_CPUPWRGD
PLT_RST#
Wake Event
2
S0
T11 >1ms ( VccASW to APWROK )
T12 >500Us ( APWROK to CL_RST# )
T13 >5ms<650ms ( VCCPLL to UNCOREPWRGOOD )
T12 >100ms ( APWROK to PLTRST# )
T20 >100ms ( PWROK to UNCOREPWRGOOD)
T25 >1ms<100ms
( UNCOREPOWERGOOD to PLTRST# )
1
S3
Te >0s ( SLP_A# to APWROK )
Tc >40ns
(APWROK# to VCCASW/VCCSPI)
Tf <500ms
(SLP_3# to VCCCORE/VCCAWG)
Tn >30us
(PLTRST# to UNCOREPOWERGOOD )
B B
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
Change History
Change History
Change History
LA480
LA480
LA480
1
99 103
99 103
99 103
SD
SD
SD
Page 100
A
D85V_PWRGD RUNPWROK PM_SLP_S4# 0D75V_EN3D3V_VGA_S0
B
C
1.05VTT_PWRGD
D
E
-4
Adapter
38
4 4
AO4407A
Battery
39
41
3 3
-2
R2707
-2
DCBATOUT
Charger
BQ24707ARGRR
+PBATT
40
0
TPS51225RUKR
61
-3
PU4201
TPS51640RSLR
42,43,44
VCC_CORE
IMVP_PWRGD PWR_GFX_PWRGD
5V_S5 3D3V_S53D3V_AUX_S5 5V_AUX_S5
U6102
UP7534BRA8
5V_USB4_S3
6
45
VCC_GFXCORE 1D5V_S31D05V_VTT
-1
U3601
AO4468-GP
36
1
5V_S0
PU4501
TPS51219
4
1.05VTT_PWRGD
U9302
AO4494L(MOS)
5
1D05V_VGA_S0
-1
U3602
AO4468-GP
3D3V_S03D3V_AUX_KBC
-1
PU9201
TPS51728RHAR
VGA_CORE
DGPU_PWROK
LAN_PWR_ON
Q3103
AO3419L
PM_SLP_S3#
PU4701
RT8068AZQW
473641
1D8V_VGA_S0
RUNPWROK
PU4801
TPS51461RGER
4892
0D85V_S0
VCCSA
D85V_PWRGD
3D3V_LAN_S5
R6010
60
3D3V_SPI
PU4601
46
RT8207MZQW
2 2 3
0D75V_S0DDR_VREF_S3
U9301
AO4494L(MOS)
93
R6516
R6512
R8202
R6403
R6301
R4922
1D5V_VGA_S0
RUNPWROK
LAN
WLAN
Cardreader
Fingerprint
Bluetooth
Camera
56
Q9302
DMP2130L
93
3D3V_VGA_S0
R5603
R2913
C
U4901
SY6288CAAC
F4903
F4902
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
D
LCD
Power Block Diagram
Power Block Diagram
Power Block Diagram
LA480
LA480
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
LA480
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
F4901
100 103
100 103
100 103
E
SD
SD
SD
G5285T11U
49
2 2
ODD
CRT
HDMI
FAN
TouchPad Audio_Codec
R5607
withuot
F5101
R2802
R6903
R5606
R2903
LCDVDD
HDD
R2904
1 1
A
B
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