Wistron LA480 Schematic
5
DCCBBAA
4
3
2
1
UMA & Optimus Schematics Document
D
IVY Bridge(rPGA989)
Intel PCH(Panther Point)
DY :NotInstalled
UMA:UMA platform installed
OPS:Optimus
HR:Huron River
CR:Chief River
V: V-Series installed
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
Cover Page
Cover Page
Cover Page
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
LA480
LA480
LA480
Date: Sheet of
Date: Sheet of
Date: Sheet of
1 103Friday, January 06, 2012
1 103Friday, January 06, 2012
1 103Friday, January 06, 2012
SD
SD
SD
5
##OnMainBoard
VRAM
D D
2GB/1GB/512MB
88,89,90,91
DDR3
800MHz
4
NVIDIA
N13P-GL (V)
N13M-GE1 (B)
83.84,85,86,87
C C
HDMI
LCD
CRT
Finger Print BD
SD/MMC+/MS/
B B
MS Pro/xD
(V only)
(B only)
74
Internal DMIC
Analog DMIC
Combo
Jack
A A
2CH SPEAKER
51
49
50
Bluetooth
CAMERA
Finger Print
CardReader
ALCOR
AU6435B52
63
49
64
Azalia
CODEC
REALTEK
ALC269Q-VC2
(Discrete only)
29
4
3
Block Diagram
(UMA/Optimus co-lay)
LA480 LA580
PCIe x 16
HDMI
LVDS
RGB CRT
USB2.0 x 3
USB 2.0 x 1
AZALIA
Intel CPU
IVY Bridge
DDRIII: 1066/1333/1600 MHz
FDI x 4 x 2
(UMA only)
PCH
Panther Point
USB 3.0/2.0 ports (14)
ETHERNET (10/100/1000Mb)
High Definition Audio
17,18,19,20,21,22,23,24,25
SPI
Flash ROM
8MB
G-Sensor
(V only)
79
4,5,6,7,8,9,10
DMI x 4
Intel
SATA ports (6)
PCIE ports (8)
LPC I/F
ACPI 1.1
60
KBC
NUVOTON
NPCE885G
Touch
PAD
69
PCIE x 1/USB2.0 x 1
SATA x 1/USB2.0 x 1
USB 3.0 x 2
USB 2.0 x 2
LPC Bus
27
KB
69 25
Project Code
PCB P/N
Revision
DDRIII 1066/1333/1600 Channel A
DDRIII 1066/1333/1600 Channel B
71.08111.N03, IC PCIE CTRL RTL8111F-CGT QFN 48P
PCIE x 1
SATA x 2
LPC debug port
SMBus
EMC2103-2-AP
71
ThermalInt.
28
91.4TD01.001
11264
SC
GLAN
REALTEK
RTL8111F
Mini-Card
WLAN
Mini-Card
USB x 2
USB x 2
Fan
28
DDRIII
1066/1333/1600
1066/1333/1600
31
65
66
HDD
ODD
RJ45
CONN
56
56
2
91.4TE01.001
11273
SC
Slot 0
14
Slot 1DDRIII
15
59
1
CPU DC/DC
TPS51640
INPUTS
DCBATOUT
SYSTEM DC/DC
TPS51219
INPUTS
DCBATOUT
SYSTEM DC/DC
TPS51225
INPUTS
DCBATOUT 5V_S5
SYSTEM DC/DC
RT8207M
INPUTS
DCBATOUT
SYSTEM DC/DC
TPS51640
INPUTS
DCBATOUT
VGA
TPS51728
INPUTS
DCBATOUT
TI CHARGER
BQ24737
INPUTS
+DC_IN_S5
26
SYSTEM DC/DC
RT8068A
INPUTS OUTPUTS
3D3V_S5 1D8V_S0
LDO
RT8207
INPUTS OUTPUTS
26
5V_S5
42~43
OUTPUTS
VCC_CORE
OUTPUTS
1D05V_VTT
OUTPUTS
3D3V_AUX_S5
3D3V_S5
OUTPUTS
0D75V_S0
1D5V_S3
DDR_VREF_S3
OUTPUTS
VCC_GFXCORE
OUTPUTS
VGA_CORE
OUTPUTS
DCBATOUT+PBATT
0D75V_S0
45
41
46
44
92
40
47
46
PCB LAYER
L1:Top
L2:GND
L3:Signal
L4:Signal
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA480
LA480
LA480
Date: Sheet of
Date: Sheet of
Date: Sheet of
L5:VCC
L6:Signal
L7:GND
L8:Signal
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
2 103Friday, January 06, 2012
2 103Friday, January 06, 2012
2 103Friday, January 06, 2012
SD
SD
SD
5
PCH Strapping
Chief River Schematic Checklist Rev0.72
Name Schematics Notes
SPKR
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
GNT3#/GPIO55
D D
GNT2#/GPIO53
GNT1#/GPIO51
SPI_MOSI
NV_ALE
Reboot option at power-up
Internal weak Pull-down.
Default Mode:
Connect to Vcc3_3 with 8.2-kΩ
No Reboot Mode with TCO Disabled:
- 10-kΩ weak pull-up resistor.
GNT[3:0]# functionality is not available on Mobile.
Mobile: Used as GPIO only
Pull-up resistors are not required on these signals.
If pull-ups are used, they should be tied to the Vcc3_3power rail.
Enable Danbury:
Disable Danbury:
Enable Danbury:
Disable Danbury:
Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.
Left floating, no pull-down required.
Connect to +NVRAM_VCCQ with 8.2-kohm
weak pull-up resistor [CRB has it pulled up
with 1-kohm no-stuff resistor]
Leave floating (internal pull-down)
4
3
Processor Strapping
Pin Name Strap Description Configuration (Default value for each bit is
CFG[2]
PCI-Express Static
Lane Reversal
CFG[4]
CFG[6:5]
CFG[7]
PCI-Express
Port Bifurcation
Straps
PEG DEFER TRAINING
1 unless specified otherwise)
1:
Normal Operation.
Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
0:
Disabled - No Physical Display Port attached to
1:
Embedded DisplayPort.
Enabled - An external Display Port device is
0:
connectd to the EMBEDDED display Port
11 : x16 - Device 1 functions 1 and 2 disabled
10 : x8, x8 - Device 1 function 1 enabled ;
function 2 disabled
01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
enabled
1:
PEG Train immediately following xxRESETB de assertion
PEG Wait for BIOS for training
0:
2
Chief River Schematic Checklist Rev0.72
Default
Value
1
0
11
1
1
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features.
HAD_DOCK_EN#
/GPIO[33]
C C
High (1) - Security measure defined in the Flash Descriptor will be enabled.
Platform design should provide appropriate pull-up or pull-down depending on
the desired settings. If a jumper option is used to tie this signal to GND as
required by the functional strap, the signal should be pulled low through a weak
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently.
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for
strapping functions.
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
HDA_SYNC
GPIO15
GPIO8
B B
GPIO27
PCIe Routing
LANE1
LANE2
LANE3 Card Reader
LANE4
A A
LANE5
LANE6
LANE7
LANE8 Express Card
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low(0) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no
confidentiality. High(1) - Intel ME Crypto Transport Layer Security (TLS) cipher
suite with confidentiality.
Note : This is an un-muxed signal.
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low.
Sampled at rising edge of RSMRST#.
CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
X
Mini Card2(WWAN)
Mini Card1(WLAN)
X
Intel GBE LAN / LAN
X
5
USB Table
Pair
USB3.0 ext port 1
0
USB3.0 ext port 2
1
USB3.0 ext port 3
2
USB3.0 ext port 4
3
BLUETOOTH (USB1.1)
4
Fingerprint (USB1.1)
5
X
6
X
7
Mini Card2 (WWAN)
8
USB ext. port 4 / E-SATA /USB CHARGER
9
CARD READER
10
Mini Card1 (WLAN)
11
CCD
12
New Card
13
port9 is debug port
Device
4
POWER PLANE
5V_S0
3D3V_S0
1D8V_S0
1D5V_S0
1D05V_VTT
1D0V_S0
VCCSA
0D75V_S0
VCC_CORE
VCC_GFXCORE
1D8V_VGA_S0
3D3V_VGA_S0
1V_VGA_S0
5V_USBX_S3
1D5V_S3
DDR_VREF_S3
BT+
DCBATOUT
5V_S5
5V_AUX_S5
3D3V_S5
3D3V_AUX_S5
3D3V_M
1D05V_M 1.05V S0/M0, SX/M3, WOL_EN
3D3V_AUX_KBC 3.3V
3D3V_AUX_S5
VOLTAGE DESCRIPTION
5V
3.3V
1.8V
1.5V
1.05V
1.0V
0.9 - 0.675V
0.75V
0.35V to 1.5V
0.4 to 1.25V
1.8V
3.3V
1V
5V
1.5V
0.75V
6V-14.1V
6V-14.1V
5V
5V
3.3V
3.3V
3.3V
3.3V
SMBus ADDRESSES
2
I C / SMBus Addresses
Device
EC SMBus 1
Battery
CHARGER
EC SMBus 2
PCH
eDP
PCH SMBus
SO-DIMMA (SPD)
SO-DIMMB (SPD)
Digital Pot
G-Sensor
MINI
3
Voltage Rails
ACTIVE IN
S0
S3
All S states
DSW, Sx ON for supporting Deep Sleep states
G3, Sx
Ref Des
Address Hex Bus
CPU Core Rail
Graphics Core Rail
AC Brick Mode only
ON whenever iAMT is active1D05V_LAN 1.05V S0/M0, SX/M3
ON for iAMTLegacy WOL
Powered by Li Coin Cell in G3
and 3D3V_S5 in Sx
Chief River CRV
BAT_SCL/BAT_SDA
BAT_SCL/BAT_SDA
BAT_SCL/BAT_SDA
SML1_CLK/SML1_DATA
SML1_CLK/SML1_DATA
SML1_CLK/SML1_DATA
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
2
SATA Table
SATA
Pair
0
1
2
3
4
5
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Table of Content
Table of Content
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Table of Content
Taipei Hsien 221, Taiwan, R.O.C.
LA480
LA480
LA480
HDD1
mSATA
N/A
N/A
ODD
ESATA
1
Device
3 103Friday, January 06, 2012
3 103Friday, January 06, 2012
3 103Friday, January 06, 2012
SD
SD
SD
5
4
3
2
1
SSID = CPU
Note:
Intel DMI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
D D
Note:
Intel FDI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
C C
enabled via a soft strap.
Note:
Lane reversal does not apply to
FDI sideband signals.
1D05V_VTT
B B
NOTE:
Select a Fast FET similar to 2N7002E whose rise/
fall time is less than 6 ns. If HPD on eDP interface is
disabled, connect it to CPU VCCIO via a 10-kΩ pull-Up
resistor on the motherboard.
DMI_TXN[3:0]19
DMI_TXP[3:0]19
DMI_RXN[3:0]19
DMI_RXP[3:0]19
FDI_TXN[7:0]19
FDI_TXP[7:0]19
FDI_FSYNC019
FDI_FSYNC119
FDI_INT19
FDI_LSYNC019
FDI_LSYNC119
R402 24D9R2F-L-GPR402 24D9R2F-L-GP
1 2
R403 10KR2J-3-GP
R403 10KR2J-3-GP
1 2
DY
DY
01.00IVY.000 IVY BRIDGE ORCAD SYMBOL.
CPU1A
CPU1A
SANDY
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
DP_COMP
eDP_HPD
B27
B25
A25
B24
B28
B26
A24
B23
G21
E22
F21
D21
G22
D22
F20
C21
A21
H19
E19
F18
B21
C20
D18
E17
A22
G19
E20
G18
B20
C19
D19
F17
J18
J17
H20
J19
H17
A18
A17
B16
C15
D15
C17
F16
C16
G15
C18
E16
D16
F15
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
DMI_RX#0
DMI_RX#1
DMI_RX#2
DMI_RX#3
DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3
DMI_TX#0
DMI_TX#1
DMI_TX#2
DMI_TX#3
DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3
FDI0_TX#0
FDI0_TX#1
FDI0_TX#2
FDI0_TX#3
FDI1_TX#0
FDI1_TX#1
FDI1_TX#2
FDI1_TX#3
FDI0_TX0
FDI0_TX1
FDI0_TX2
FDI0_TX3
FDI1_TX0
FDI1_TX1
FDI1_TX2
FDI1_TX3
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
EDP_COMPIO
EDP_ICOMPO
EDP_HPD
EDP_AUX
EDP_AUX#
EDP_TX0
EDP_TX1
EDP_TX2
EDP_TX3
EDP_TX#0
EDP_TX#1
EDP_TX#2
EDP_TX#3
SANDY
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
SKT-BGA989C470395-1H180
SKT-BGA989C470395-1H180
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1 OF 9
1 OF 9
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PEG_TX#11
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_IRCOMP_R
PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0
PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0
PEG_C_TXN15
PEG_C_TXN14
PEG_C_TXN13
PEG_C_TXN12
PEG_C_TXN11
PEG_C_TXN10
PEG_C_TXN9
PEG_C_TXN8
PEG_C_TXN7
PEG_C_TXN6
PEG_C_TXN5
PEG_C_TXN4
PEG_C_TXN3
PEG_C_TXN2
PEG_C_TXN1
PEG_C_TXN0
PEG_C_TXP15
PEG_C_TXP14
PEG_C_TXP13
PEG_C_TXP12
PEG_C_TXP11
PEG_C_TXP10
PEG_C_TXP9
PEG_C_TXP8
PEG_C_TXP7
PEG_C_TXP6
PEG_C_TXP5
PEG_C_TXP4
PEG_C_TXP3
PEG_C_TXP2
PEG_C_TXP1
PEG_C_TXP0
R401
R401
1 2
24D9R2F-L-GP
24D9R2F-L-GP
C401 SCD22U10V2KX-1GP
C401 SCD22U10V2KX-1GP
1 2
C402 SCD22U10V2KX-1GP
C402 SCD22U10V2KX-1GP
1 2
C403 SCD22U10V2KX-1GP
C403 SCD22U10V2KX-1GP
1 2
C404 SCD22U10V2KX-1GP
C404 SCD22U10V2KX-1GP
1 2
C405 SCD22U10V2KX-1GP
C405 SCD22U10V2KX-1GP
1 2
C406 SCD22U10V2KX-1GP
C406 SCD22U10V2KX-1GP
1 2
C407 SCD22U10V2KX-1GP
C407 SCD22U10V2KX-1GP
1 2
C408 SCD22U10V2KX-1GP
C408 SCD22U10V2KX-1GP
1 2
C409 SCD22U10V2KX-1GP
C409 SCD22U10V2KX-1GP
1 2
C410 SCD22U10V2KX-1GP
C410 SCD22U10V2KX-1GP
1 2
C411 SCD22U10V2KX-1GP
C411 SCD22U10V2KX-1GP
1 2
C412 SCD22U10V2KX-1GP
C412 SCD22U10V2KX-1GP
1 2
C413 SCD22U10V2KX-1GP
C413 SCD22U10V2KX-1GP
1 2
C414 SCD22U10V2KX-1GP
C414 SCD22U10V2KX-1GP
1 2
C415 SCD22U10V2KX-1GP
C415 SCD22U10V2KX-1GP
1 2
C416 SCD22U10V2KX-1GP
C416 SCD22U10V2KX-1GP
1 2
C417 SCD22U10V2KX-1GP
C417 SCD22U10V2KX-1GP
1 2
C418 SCD22U10V2KX-1GP
C418 SCD22U10V2KX-1GP
1 2
C419 SCD22U10V2KX-1GP
C419 SCD22U10V2KX-1GP
1 2
C420 SCD22U10V2KX-1GP
C420 SCD22U10V2KX-1GP
1 2
C421 SCD22U10V2KX-1GP
C421 SCD22U10V2KX-1GP
1 2
C422 SCD22U10V2KX-1GP
C422 SCD22U10V2KX-1GP
1 2
C423 SCD22U10V2KX-1GP
C423 SCD22U10V2KX-1GP
1 2
C424 SCD22U10V2KX-1GP
C424 SCD22U10V2KX-1GP
1 2
C425 SCD22U10V2KX-1GP
C425 SCD22U10V2KX-1GP
1 2
C426 SCD22U10V2KX-1GP
C426 SCD22U10V2KX-1GP
1 2
C427 SCD22U10V2KX-1GP
C427 SCD22U10V2KX-1GP
1 2
C428 SCD22U10V2KX-1GP
C428 SCD22U10V2KX-1GP
1 2
C429 SCD22U10V2KX-1GP
C429 SCD22U10V2KX-1GP
1 2
C430 SCD22U10V2KX-1GP
C430 SCD22U10V2KX-1GP
1 2
C431 SCD22U10V2KX-1GP
C431 SCD22U10V2KX-1GP
1 2
C432 SCD22U10V2KX-1GP
C432 SCD22U10V2KX-1GP
1 2
1D05V_VTT
PEG_RXN[0..15] 83
PEG_RXP[0..15] 83
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
NOTE.
If PEG is not implemented, the RX&TX pairs can be left as No Connect
PEG Static Lane Reversal
PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0
PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0
PEG_TXN[0..15] 83
PEG_TXP[0..15] 83
Signal Routing Guideline:
EDP_ICOMPO keep W/S=12/15 mils and routing
A A
length less than 500 mils.
EDP_COMPIO keep W/S=4/15 mils and routing
length less than 500 mils.
NOTE.
Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
CPU (PCIE/DMI/FDI)
CPU (PCIE/DMI/FDI)
CPU (PCIE/DMI/FDI)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA480
LA480
LA480
Date: Sheet of
Date: Sheet of
Date: Sheet of
4 103Friday, January 06, 2012
4 103Friday, January 06, 2012
4 103Friday, January 06, 2012
SD
SD
SD
SSID = CPU
5
R509
R509
750R2F-GP
750R2F-GP
H_SNB_IVB#22
TP501TP501
TP502TP502
1 2
R513 56R2J-4-GPR513 56R2J-4-GP
H_THERMTRIP#22,36
H_PM_SYNC19
1 2
R504 0R0402-PADR504 0R0402-PAD
1 2
R503 10KR2J-3-GPR503 10KR2J-3-GP
12
1
1
12
1D05V_VTT
1 2
R501
R501
62R2J-GP
62R2J-GP
D D
Intel
recommends
43pf
H_PROCHOT#
12
C502
C502
SC47P50V2JN-3GP
SC47P50V2JN-3GP
H_PECI22,27
H_PROCHOT#27,42
Connect EC to PROCHOT# through inverting OD buffer.
If PROCHOT# is not used, then it must
be terminated with a 68ohm ±5%
pull-up resistor to VTT.
H_CPUPW RGD22,97
C C
VDDPWRGOOD37
PLT_RST#18,27,31,36,65,66,71,80,82,83,97
0511-CHECK
1 2
R510
R510
1K5R2F-2-GP
1K5R2F-2-GP
DEL U501
4
SKTOCC#_R
H_CATERR#
H_PROCHOT#_R
H_CPUPW RGD_R
BUF_CPU_RST#
C501
C501
SC220P50V2KX-3GP
SC220P50V2KX-3GP
DY
DY
CPU1B
CPU1B
C26
SNB_IVB#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWROK
AR33
RESET#
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
SANDY
SANDY
3
2 OF 9
2 OF 9
A28
BCLK
A27
BCLK#
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
DBR#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
A16
A15
R8
AK1
A5
A4
AP29
AP27
AR26
AR27
AP30
AR28
TDI
AP26
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
SKT-BGA989C470395-1H180
SKT-BGA989C470395-1H180
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR3
DDR3
MISC
MISC
JTAG & BPM
JTAG & BPM
2
Need Add Test PointC26: PROC_SELECT#
CLK_EXP_P 20
CLK_EXP_N 20
CLK_DP_P_R
CLK_DP_N_R
SM_DRAMRST# 37
SM_DRAMRST#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
Signal Routing Guideline:
SM_RCOMP keep routing length less than 500 mils.
XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
XDP_DBRESET#
R502 4K99R2F-L-GPR502 4K99R2F-L-GP
R506 140R2F-GPR506 140R2F-GP
R507 25D5R2F-GPR507 25D5R2F-GP
R508 200R2F-L-GPR508 200R2F-L-GP
1 2
1 2
1 2
TP511TP511
1
TP512TP512
1
TP513TP513
1
TP516TP516
1
12
0511-CHECK
Disabling Guidelines:
If motherboard only supports external graphics:
Connect DPLL_REF_SSCLK on Processor to GND through
1K +/- 5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP
through 1K +/- 5% resistorpower (~15 mW) may be
wasted.
1D05V_VTT
RN502
RN502
SRN1KJ-7-GP
CLK_DP_N_R
CLK_DP_P_R
In order to minimize resistance, use thick traces to
route all COMP signals, use 10-mils wide trace for
routing less than 500 mils, or 20-mils wide trace
for routing between 500 mils and 1000 mils. Keep
20-mils spacing to any other signals in order to
minimize crosstalk.
XDP_TDO
XDP_TMS
XDP_TDI
XDP_TCLK
XDP_TRST#
XDP_DBRESET#19
XDP_DBRESET#
SRN1KJ-7-GP
1
4
2 3
R523 51R2J-2-GPR523 51R2J-2-GP
1 2
RN501
RN501
1
8
2
7
3
6
4 5
SRN51J-1-GP
SRN51J-1-GP
1 2
R516 1KR2J-1-GPR516 1KR2J-1-GP
1
1D05V_VTT
3D3V_S0
DEL R519
B B
DEL C503
DEL R517
DEL R515
ASM R510
ASM R509
<Core Design>
<Core Design>
A A
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
CPU (THERMAL/CLOCK/PM )
CPU (THERMAL/CLOCK/PM )
CPU (THERMAL/CLOCK/PM )
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
LA480
LA480
LA480
Date: Sheet of
Date: Sheet of
Date: Sheet of
5 103Friday, January 06, 2012
5 103Friday, January 06, 2012
5 103Friday, January 06, 2012
SD
SD
SD
5
4
3
2
1
SSID = CPU
3 OF 9
CPU1C
CPU1C
SANDY
SANDY
M_A_DQ[63:0]14 M_B_DQ[63:0]15
D D
C C
B B
M_A_BS014
M_A_BS114
M_A_BS214
M_A_CAS#14
M_A_RAS#14
M_A_WE#14
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AE8
AD9
AF9
C5
SA_DQ0
D5
SA_DQ1
D3
SA_DQ2
D2
SA_DQ3
D6
SA_DQ4
C6
SA_DQ5
C2
SA_DQ6
C3
SA_DQ7
F10
SA_DQ8
F8
SA_DQ9
SA_DQ10
G9
SA_DQ11
F9
SA_DQ12
F7
SA_DQ13
G8
SA_DQ14
G7
SA_DQ15
K4
SA_DQ16
K5
SA_DQ17
K1
SA_DQ18
J1
SA_DQ19
J5
SA_DQ20
J4
SA_DQ21
J2
SA_DQ22
K2
SA_DQ23
M8
SA_DQ24
SA_DQ25
N8
SA_DQ26
N7
SA_DQ27
SA_DQ28
M9
SA_DQ29
N9
SA_DQ30
M7
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
AJ5
SA_DQ38
AJ6
SA_DQ39
AJ8
SA_DQ40
SA_DQ41
AJ9
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
V6
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_BS0
SA_BS1
SA_BS2
SA_CAS#
SA_RAS#
SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
3 OF 9
SA_CLK0
SA_CLK#0
SA_CKE0
SA_CLK1
SA_CLK#1
SA_CKE1
SA_CLK2
SA_CLK#2
SA_CKE2
SA_CLK3
SA_CLK#3
SA_CKE3
SA_CS#0
SA_CS#1
SA_CS#2
SA_CS#3
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DIM0_CLK_DDR0 14
M_A_DIM0_CLK_DDR#0 14
M_A_DIM0_CKE0 14
M_A_DIM0_CLK_DDR1 14
M_A_DIM0_CLK_DDR#1 14
M_A_DIM0_CKE1 14
M_A_DIM0_CS#0 14
M_A_DIM0_CS#1 14
M_A_DIM0_ODT0 14
M_A_DIM0_ODT1 14
M_A_DQS#[7:0] 14
M_A_DQS[7:0] 14
M_A_A[15:0] 14
CPU1D
CPU1D
SANDY
SANDY
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_BS015
M_B_BS115
M_B_BS215
M_B_CAS#15
M_B_RAS#15
M_B_WE#15
D10
K10
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
AA10
AB8
AB9
C9
SB_DQ0
A7
SB_DQ1
SB_DQ2
C8
SB_DQ3
A9
SB_DQ4
A8
SB_DQ5
D9
SB_DQ6
D8
SB_DQ7
G4
SB_DQ8
F4
SB_DQ9
F1
SB_DQ10
G1
SB_DQ11
G5
SB_DQ12
F5
SB_DQ13
F2
SB_DQ14
G2
SB_DQ15
J7
SB_DQ16
J8
SB_DQ17
SB_DQ18
K9
SB_DQ19
J9
SB_DQ20
J10
SB_DQ21
K8
SB_DQ22
K7
SB_DQ23
M5
SB_DQ24
N4
SB_DQ25
N2
SB_DQ26
N1
SB_DQ27
M4
SB_DQ28
N5
SB_DQ29
M2
SB_DQ30
M1
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
R6
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BS0
SB_BS1
SB_BS2
SB_CAS#
SB_RAS#
SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
4 OF 9
4 OF 9
SB_CLK0
SB_CLK#0
SB_CKE0
SB_CLK1
SB_CLK#1
SB_CKE1
SB_CLK2
SB_CLK#2
SB_CKE2
SB_CLK3
SB_CLK#3
SB_CKE3
SB_CS#0
SB_CS#1
SB_CS#2
SB_CS#3
SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
AE2
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DIM0_CLK_DDR0 15
M_B_DIM0_CLK_DDR#0 15
M_B_DIM0_CKE0 15
M_B_DIM0_CLK_DDR1 15
M_B_DIM0_CLK_DDR#1 15
M_B_DIM0_CKE1 15
M_B_DIM0_CS#0 15
M_B_DIM0_CS#1 15
M_B_DIM0_ODT0 15
M_B_DIM0_ODT1 15
M_B_DQS#[7:0] 15
M_B_DQS[7:0] 15
M_B_A[15:0] 15
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
A A
5
4
3
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU (DDR)
CPU (DDR)
CPU (DDR)
LA480
LA480
LA480
1
6 103Friday, January 06, 2012
6 103Friday, January 06, 2012
6 103Friday, January 06, 2012
SD
SD
SD
5
4
3
2
1
SSID = CPU
CFG2
D D
12
R702
R702
1KR2J-1-GP
1KR2J-1-GP
OPS
OPS
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
1: Normal Operation; Lane #
definition matches socket pin map definition
TP717TP717
TP702TP702
TP703TP703
0:Lane Reversed
CFG4
C C
B B
12
R703
R703
1KR2J-1-GP
1KR2J-1-GP
DY
DY
Display Port Presence Strap
CFG4
1: Disabled; No Physical Display Port
attached to Embedded Display Port
0: Enabled; An external Display Port device is
connected to the Embedded Display Port
TP704TP704
DDR_WR_VREF0112
DDR_WR_VREF0212
TP705TP705
CFG0
1
CFG1
1
CFG2
CFG3
1
CFG4
CFG5
CFG6
CFG7
CFG16
1
H_VCCP_SEL
1
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
AJ31
AH31
AJ33
AH33
AJ26
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
B18
A19
B4
D1
J20
J15
CPU1E
CPU1E
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
RSVD#AJ31
RSVD#AH31
RSVD#AJ33
RSVD#AH33
RSVD#AJ26
RSVD#B4
RSVD#D1
RSVD#F25
RSVD#F24
RSVD#F23
RSVD#D24
RSVD#G25
RSVD#G24
RSVD#E23
RSVD#D23
RSVD#C30
RSVD#A31
RSVD#B30
RSVD#B29
RSVD#D30
RSVD#B31
RSVD#A30
RSVD#C29
RSVD#J20
RSVD#B18
RSVD#A19
RSVD#J15
SANDY
SANDY
RESERVED
RESERVED
5 OF 9
5 OF 9
RSVD#L7
RSVD#AG7
RSVD#AE7
RSVD#AK2
RSVD#W8
RSVD#AT26
RSVD#AM33
RSVD#AJ27
RSVD#T8
RSVD#J16
RSVD#H16
RSVD#G16
RSVD#AR35
RSVD#AT34
RSVD#AT33
RSVD#AP35
RSVD#AR34
RSVD#B34
RSVD#A33
RSVD#A34
RSVD#B35
RSVD#C35
RSVD#AJ32
RSVD#AK32
RSVD#AH27
RSVD#AN35
RSVD#AM35
RSVD#AT2
RSVD#AT1
RSVD#AR1
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AH27
AN35
AM35
AT2
AT1
AR1
TP713
CLK_XDP_ITP_P
CLK_XDP_ITP_N
TP720TP720
1
TP718TP718
1
TP719TP719
1
SANDY
SANDY
62.10055.421
CFG5
CFG6
CFG7
A A
DY
DY
12
12
R701
R701
1KR
1KR
DY
DY
2J-1-GP
2J-1-GP
12
R705
R705
1KR2J-1-GP
1KR2J-1-GP
DY
DY
PCIE Port Bifurcation Straps
R704
R704
1KR
1KR
CFG[6:5]
2J-1-GP
2J-1-GP
11: x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PEG DEFER TRAINING
CFG7
5
1: PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
4
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
3
SKT-BGA989C470395-1H180
SKT-BGA989C470395-1H180
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU (RESERVED)
CPU (RESERVED)
CPU (RESERVED)
LA480
LA480
LA480
7 103Friday, January 06, 2012
7 103Friday, January 06, 2012
7 103Friday, January 06, 2012
1
SD
SD
SD
5
0511-CHECK CAP.
VCC_CORE
C802
C802
C801
D D
C C
B B
A A
C801
12
C815
C815
12
C816
C816
12
C837
C837
12
SC
DY
SC
DY
SC
SC
12
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
C817
C817
SC
SC
SC
SC
12
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
C821
C821
SC
SC
SC
SC
12
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
C836
C836
SC
SC
SC
SC
12
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
10U6D3V5KX-1GP
5
VCC CORE:53A
C803
C803
C804
C804
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
SC10U6D3V5KX-1GP
DY
12
12
C819
C819
C818
C818
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C823
C823
C822
C822
DY
DY
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C834
C834
C835
C835
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C811
C811
12
C820
C820
12
C824
C824
12
C833
C833
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C825
C825
C826
C826
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C832
C832
DY
DY
12
SC10U6D3V5KX-1GP
12
C831
C831
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C827
C827
12
C828
C828
12
4
POWER
CPU1F
CPU1F
VCC_CORE
AG35
VCC
AG34
VCC
AG33
VCC
AG32
VCC
AG31
VCC
AG30
VCC
AG29
VCC
AG28
VCC
AG27
VCC
AG26
VCC
AF35
VCC
AF34
VCC
AF33
VCC
AF32
VCC
AF31
VCC
AF30
VCC
AF29
VCC
AF28
VCC
AF27
VCC
AF26
VCC
AD35
VCC
AD34
VCC
AD33
VCC
AD32
VCC
AD31
VCC
AD30
VCC
AD29
VCC
AD28
VCC
AD27
VCC
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
4
AD26
VCC
AC35
VCC
AC34
VCC
AC33
VCC
AC32
VCC
AC31
VCC
AC30
VCC
AC29
VCC
AC28
VCC
AC27
VCC
AC26
VCC
AA35
VCC
AA34
VCC
AA33
VCC
AA32
VCC
AA31
VCC
AA30
VCC
AA29
VCC
AA28
VCC
AA27
VCC
AA26
VCC
Y35
VCC
Y34
VCC
Y33
VCC
Y32
VCC
Y31
VCC
Y30
VCC
Y29
VCC
Y28
VCC
Y27
VCC
Y26
VCC
V35
VCC
V34
VCC
V33
VCC
V32
VCC
V31
VCC
V30
VCC
V29
VCC
V28
VCC
V27
VCC
V26
VCC
U35
VCC
U34
VCC
U33
VCC
U32
VCC
U31
VCC
U30
VCC
U29
VCC
U28
VCC
U27
VCC
U26
VCC
R35
VCC
R34
VCC
R33
VCC
R32
VCC
R31
VCC
R30
VCC
R29
VCC
R28
VCC
R27
VCC
R26
VCC
P35
VCC
P34
VCC
P33
VCC
P32
VCC
P31
VCC
P30
VCC
P29
VCC
P28
VCC
P27
VCC
P26
VCC
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
POWER
SANDY
SANDY
CORE SUPPLY
CORE SUPPLY
3
6 OF 9
6 OF 9
AH13
VCCIO
AH10
VCCIO
AG10
VCCIO
AC10
VCCIO
Y10
VCCIO
U10
VCCIO
P10
VCCIO
L10
VCCIO
J14
VCCIO
J13
VCCIO
J12
VCCIO
J11
VCCIO
H14
VCCIO
H12
VCCIO
H11
VCCIO
G14
VCCIO
G13
VCCIO
G12
VCCIO
F14
VCCIO
F13
VCCIO
F12
VCCIO
F11
VCCIO
E14
VCCIO
E12
VCCIO
E11
VCCIO
D14
VCCIO
D13
VCCIO
D12
VCCIO
D11
VCCIO
C14
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VIDALERT#
VIDSCLK
VIDSOUT
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
PEG AND DDR
PEG AND DDR
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSSIO_SENSE
SENSE LINES SVID
SENSE LINES SVID
3
2
0511-CHECK CAP.
C805
C805
12
C812
C812
12
For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7
For CRB VIDALERT# need to pull high 75 ohm close to CPU
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
0511-CHECK
VCCIO:8.5A
C806
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C808
C808
C807
C807
C806
Reserve C846 & C847
C829
C813
C813
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
1 2
R803 43R2J-GPR803 43R2J-GP
1 2
R804 130R2F-1-GPR804 130R2F-1-GP
VCCIO_SENSE 45
VSSIO_SENSE 45
C829
C814
C814
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
R807 75R2F-2-GPR807 75R2F-2-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
VCC_CORE
12
12
2
C810
C810
C809
C809
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C842
C842
C830
C830
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
VR_SVID_ALERT# 42
H_CPU_SVIDCLK 42
H_CPU_SVIDDAT 42
1D05V_VTT
R801
R801
100R2F-L1-GP-U
100R2F-L1-GP-U
VCCSENSE 42
VSSSENSE 42
R802
R802
100R2F-L1-GP-U
100R2F-L1-GP-U
C838
C838
C839
C839
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1D05V_VTT
SC10U6D3V5KX-1GP
12
12
1D05V_VTT
C844
C844
C843
C843
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
DY
12
12
check
Place neer PCU pin.
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
0511-CHECK
1D05V_VTT
C841
C841
C840
C840
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
SC10U6D3V5KX-1GP
DY
12
12
C845
C845
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
1D05V_VTT
12
R808
R808
10R2F-L-GP
10R2F-L-GP
VCCIO_SENSE
VSSIO_SENSE
12
R809
R809
10R2F-L-GP
10R2F-L-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU (VCC_CORE)
CPU (VCC_CORE)
CPU (VCC_CORE)
LA480
LA480
LA480
1
SD
SD
8 103Friday, January 06, 2012
8 103Friday, January 06, 2012
8 103Friday, January 06, 2012
1
SD
5
4
3
2
1
C914
C914
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCC_GFXCORE
12
R906
R906
100R2F-L1-GP-U
100R2F-L1-GP-U
12
R907
R907
100R2F-L1-GP-U
100R2F-L1-GP-U
1D5V_S0
0511-CHECK CAP
POWER
CPU1G
D D
C C
B B
VCC_GFXCORE
C901
C901
12
C907
C907
12
PROCESSOR VAXG: 24A
C902
C902
C903
C903
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC
SC
12
C908
C908
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1D8V_S0
12
C918
C918
12
C926
C926
12
10U6D3V5KX-1GP
10U6D3V5KX-1GP
SC
SC
10U6D3V5KX-1GP
10U6D3V5KX-1GP
C904
C904
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C919
C919
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
VCCPLL:1.2A
C923
C923
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C905
C905
12
C920
C920
12
C922
C922
12
0511-CHECK
RC901
C906
C906
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C921
C921
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C924
C924
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
RC901
SC33P50V2JN-3GP
DY
DY
DY
DY
12
RC902
RC902
12
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
CPU1G
AT24
VAXG
AT23
VAXG
AT21
VAXG
AT20
VAXG
AT18
VAXG
AT17
VAXG
AR24
VAXG
AR23
VAXG
AR21
VAXG
AR20
VAXG
AR18
VAXG
AR17
VAXG
AP24
VAXG
AP23
VAXG
AP21
VAXG
AP20
VAXG
AP18
VAXG
AP17
VAXG
AN24
VAXG
AN23
VAXG
AN21
VAXG
AN20
VAXG
AN18
VAXG
AN17
VAXG
AM24
VAXG
AM23
VAXG
AM21
VAXG
AM20
VAXG
AM18
VAXG
AM17
VAXG
AL24
VAXG
AL23
VAXG
AL21
VAXG
AL20
VAXG
AL18
VAXG
AL17
VAXG
AK24
VAXG
AK23
VAXG
AK21
VAXG
AK20
VAXG
AK18
VAXG
AK17
VAXG
AJ24
VAXG
AJ23
VAXG
AJ21
VAXG
AJ20
VAXG
AJ18
VAXG
AJ17
VAXG
AH24
VAXG
AH23
VAXG
AH21
VAXG
AH20
VAXG
AH18
VAXG
AH17
VAXG
B6
VCCPLL
A6
VCCPLL
A2
VCCPLL
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
POWER
SANDY
SANDY
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
SENSE
SENSE
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
7 OF 9
7 OF 9
VAXG_SENSE
VSSAXG_SENSE
LINES
LINES
SM_VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA_SENSE
FC_C22
VCCSA_VID1
AK35
AK34
Refer to the latest Huron River Mainstream PDG
(Doc# 436735) for more details on S3 power
reduction implementation.
VCC_AXG_SENSE 42
VSS_AXG_SENSE 42
+V_SM_VREF_CNT should have 10 mil trace width
AL1
Routing Guideline:
Power from DDR_VREF_S3 and +V_SM_VREF_CNT
should have 10 mils trace width.
+V_SM_VREF_CNT 37
VDDQ:5A
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
VCCA:6A
C916
C916
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C909
C909
DY
DY
12
4
1
2 3
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C915
C915
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
RN901
RN901
SRN1KJ-7-GP
SRN1KJ-7-GP
C910
C910
C911
C911
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C917
C917
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
VCCSA_SENSE 48
VCCSA_SELECT0 48
VCCSA_SELECT1 48
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCCSA
+V0.85S - VCCSA - System Agent rail voltage can be
[0.9, 0.725, 0.8, 0.675] V for IVB
[0.9, 0.8] V for SNB
C912
C912
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCC_AXG_SENSE
VSS_AXG_SENSE
C913
C913
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (VCC_GFXCORE)
CPU (VCC_GFXCORE)
CPU (VCC_GFXCORE)
Taipei Hsien 221, Taiwan, R.O.C.
LA480
LA480
LA480
9 103Friday, January 06, 2012
9 103Friday, January 06, 2012
9 103Friday, January 06, 2012
1
SD
SD
SD
5
4
3
2
1
SSID = CPU
9 OF 9
8 OF 9
CPU1H
CPU1H
AT35
VSS
AT32
VSS
AT29
VSS
AT27
VSS
AT25
VSS
AT22
VSS
D D
C C
B B
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SANDY
SANDY
VSS
VSS
8 OF 9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
H33
H30
H27
H24
H21
H18
H15
H13
H10
G35
G32
G29
G26
G23
G20
G17
G11
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
L33
L30
L27
K35
K32
K29
K26
J34
J31
F34
F31
F29
CPU1I
CPU1I
SANDY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P9
VSS
P8
VSS
P6
VSS
P5
VSS
P3
VSS
P2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L9
VSS
L8
VSS
L6
VSS
L5
VSS
L4
VSS
L3
VSS
L2
VSS
L1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H9
VSS
H8
VSS
H7
VSS
H6
VSS
H5
VSS
H4
VSS
H3
VSS
H2
VSS
H1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SANDY
VSS
VSS
9 OF 9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
SANDY
SANDY
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
A A
5
4
3
SANDY
62.10055.421
62.10055.421
2nd = 62.10040.771
2nd = 62.10040.771
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU (VSS)
CPU (VSS)
CPU (VSS)
LA480
LA480
LA480
SD
SD
10 103Friday, January 06, 2012
10 103Friday, January 06, 2012
10 103Friday, January 06, 2012
1
SD
5
DCCBBAA
4
3
2
1
D
BLANK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LA480 SD
A4
LA480 SD
A4
LA480 SD
A4
Date: Sheet of
Date: Sheet of
Date: Sheet of
11 103Friday, January 06, 2012
11 103Friday, January 06, 2012
11 103Friday, January 06, 2012
5
4
3
2
VREF circuit -M1 (Voltage Driver Network) & M3 (Driven by Processor) Implementation
CAD Note: All VREF traces should have 20:20 mil trace geometry. Note that while 20 mil trace width is optimal, short violations is acceptable if
required due to tight routing constraints.
1
1 2
DY
D D
C C
B B
Driven by process (PIN#B4) Driven by process (PIN#D1)
DDR_WR_VREF017
1KR2F-3-GP
1KR2F-3-GP
DRAMRST_CNTRL_PCH20,37
DDR_VREF_S3 DDR_VREF_S3
R1228
R1228
1 2
R1207
R1207
0R0402-PAD
0R0402-PAD
12
DY
DY
1 2
R1203
R1203
0R0402-PAD
0R0402-PAD
SA_DIMM_VREFDQ SB_DIMM_VREFDQ
DY
R1226 0R2J-2-GP
R1226 0R2J-2-GP
U1201
U1201
S
D
G
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
DDR_WR_VREF01_B4
12
R1204
R1204
0R0402-PAD
0R0402-PAD
12
R1209
R1209
0R2J-2-GP
0R2J-2-GP
DY
DY
+V_VREF_PATH1
12
R1225
R1225
0R2J-2-GP
0R2J-2-GP
DY
DY
12
R1210
R1210
0R0402-PAD
0R0402-PAD
CLOSE PIN1
M_VREF_DQ_DIMM0
12
C1201
C1201
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
M_VREF_DQ_DIMM1
12
C1202
C1202
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SODDIM1
DDR_WR_VREF027
SODDIM0
M_VREF_CA_DIMM0
1KR2F-3-GP
1KR2F-3-GP
DRAMRST_CNTRL_PCH20,37
M_VREF_CA_DIMM1
12
R1227
R1227
DY
DY
12
C1203
C1203
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
CLOSE PIN
12
C1204
C1204
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2
DY
DY
R1208 0R2J-2-GP
R1208 0R2J-2-GP
U1202
U1202
S
D
G
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
DDR_VREF_S3DDR_VREF_S3
1 2
R1216
R1216
0R2J-2-GP
0R2J-2-GP
DDR_WR_VREF01_D1DDR_WR_VREF01_B4
0R0402-PAD
0R0402-PAD
DY
DY
R1232
R1232
1 2
12
R1218
R1218
0R0402-PAD
0R0402-PAD
+V_VREF_PATH3
12
R1217
R1217
0R0402-PAD
0R0402-PAD
1 2
R1222
R1222
0R0402-PAD
0R0402-PAD
1 2
DY
DY
R1219
R1219
0R2J-2-GP
0R2J-2-GP
+V_SM_VREF 37
DDR_WR_VREF01_D1
12
R1221
R1221
0R0402-PAD
0R0402-PAD
CLOSE PIN
CLOSE PIN
+V_VREF_PATH2
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
M3
M3
M3
LA480
LA480
LA480
12 103Friday, January 06, 2012
12 103Friday, January 06, 2012
12 103Friday, January 06, 2012
1
SD
SD
SD
5
DCCBBAA
4
3
2
1
D
BLANK
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LA480 SD
A4
LA480 SD
A4
LA480 SD
A4
Date: Sheet of
Date: Sheet of
Date: Sheet of
13 103Friday, January 06, 2012
13 103Friday, January 06, 2012
13 103Friday, January 06, 2012
5
DIMM1
SSID = MEMORY
D D
C C
Place these caps
C1419
C1419
12
SC1
SC1
U6D3V2KX-GP
U6D3V2KX-GP
close to VTT1 and
VTT2.
C1420
C1420
SC1
SC1
12
U6D3V2KX-GP
U6D3V2KX-GP
DY
DY
C1421
C1421
12
C1422
C1422
SC1
SC1
SC1
SC1
12
U6D3V2KX-GP
U6D3V2KX-GP
U6D3V2KX-GP
U6D3V2KX-GP
DY
DY
0D75V_S0
B B
M_A_DQ[63:0]6
C1418
C1418
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
DY
DY
M_A_DQS#[7:0] 6
M_A_DQS[7:0] 6
M_A_DIM0_ODT06
M_A_DIM0_ODT16
M_VREF_CA_D IMM0
M_VREF_DQ_D IMM0
DDR3_DR AMRST#15,37
M_A_A[15:0] 6
M_A_BS26
M_A_BS06
M_A_BS16
0D75V_S0
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
DIMM1
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12
119
A13
80
A14
78
A15
79
A16/BA2
109
BA0
108
BA1
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
10
DQS0#
27
DQS1#
45
DQS2#
62
DQS3#
135
DQS4#
152
DQS5#
169
DQS6#
186
DQS7#
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
116
ODT0
120
ODT1
126
VREF_CA
1
VREF_DQ
30
RESET#
203
VTT1
204
VTT2
DDR3-204P- 96-GP-U1
DDR3-204P- 96-GP-U1
62.10017.V61
62.10017.V61
2ND = *62.10017.X51
2ND = *62.10017.X51
3RD = *62.10017.V61
3RD = *62.10017.V61
(H=8mm)
4
RAS#
CAS#
CS0#
CS1#
CKE0
CKE1
CK0#
CK1#
EVENT#
VDDSPD
NC#77
NC#122
NC#125/TEST
3
NP1
NP1
NP2
NP2
110
113
WE#
115
114
121
73
74
101
CK0
103
102
CK1
104
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
200
SDA
202
SCL
198
199
SA0_DIM0
197
SA0
SA1_DIM0
201
SA1
77
122
125
75
VDD
76
VDD
81
VDD
82
VDD
87
VDD
88
VDD
93
VDD
94
VDD
99
VDD
100
VDD
105
VDD
106
VDD
111
VDD
112
VDD
117
VDD
118
VDD
123
VDD
124
VDD
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
44
VSS
48
VSS
49
VSS
54
VSS
55
VSS
60
VSS
61
VSS
65
VSS
66
VSS
71
VSS
72
VSS
127
VSS
128
VSS
133
VSS
134
VSS
138
VSS
139
VSS
144
VSS
145
VSS
150
VSS
151
VSS
155
VSS
156
VSS
161
VSS
162
VSS
167
VSS
168
VSS
172
VSS
173
VSS
178
VSS
179
VSS
184
VSS
185
VSS
189
VSS
190
VSS
195
VSS
196
VSS
205
VSS
206
VSS
1D5V_S3
M_A_RAS# 6
M_A_WE# 6
M_A_CAS# 6
M_A_DIM0_CS#0 6
M_A_DIM0_CS#1 6
M_A_DIM0_CKE0 6
M_A_DIM0_CKE1 6
M_A_DIM0_CLK_DDR 0 6
M_A_DIM0_CLK_DDR #0 6
M_A_DIM0_CLK_DDR 1 6
M_A_DIM0_CLK_DDR #1 6
PCH_SMBDAT A 15,20,65,66
PCH_SMBCLK 15,20,65,66
TS#_DIMM0_1 15
C1401
C1401
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
Layout Note:
Place these Caps near
SO-DIMMB.
12
3D3V_S0
12
C1402
C1402
SC2D2U10V3KX- 1GP
SC2D2U10V3KX- 1GP
DY
DY
1D5V_S3
0511-CHECK
TC1401
TC1401
12
DY
DY
C1414
C1414
12
C1403
C1403
ST330U2VDM-4-GP
ST330U2VDM-4-GP
12
C1415
C1415
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
SODIMM A DECOUPLING
C1404
C1404
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
DY
DY
C1416
C1416
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
SA0_DIM0
SA1_DIM0
12
R1401
R1401
10KR2J-3-GP
10KR2J-3-GP
Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
If SA0 DIM0 = 1, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32
Thermal EVENT
TS#_DIMM0_1
1 2
R1403
R1403
10KR2J-3-GP
10KR2J-3-GP
C1405
C1405
12
C1417
C1417
12
C1406
C1406
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1407
C1407
12
C1408
C1408
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
DY
DY
R1402
R1402
10KR2J-3-GP
10KR2J-3-GP
3D3V_S0
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
DY
DY
C1409
C1409
12
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
DY
12
C1410
C1410
2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
DDR3-SODIMM1
DDR3-SODIMM1
DDR3-SODIMM1
LA480
LA480
LA480
1
14 103
14 103
14 103
SD
SD
SD
5
SSID = MEMORY
D D
C C
Place these caps
close to VTT1 and
0D75V_S0
VTT2.
C1520
C1519
C1519
12
C1520
C1521
C1521
SC1
SC1
SC1
SC1
U6D3V2KX-GP
U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
U6D3V2KX-GP
U6D3V2KX-GP
DY
DY
C1518
C1518
SC1
SC1
12
U6D3V2KX-GP
U6D3V2KX-GP
DY
DY
B B
M_B_A[15:0] 6
M_B_BS26
M_B_BS06
M_B_BS16
M_B_DQ[63:0]6
M_B_DQS#[7:0] 6
M_B_DQS[7:0] 6
M_B_DIM0_ODT06
M_B_DIM0_ODT16
M_VREF_CA_D IMM1
M_VREF_DQ_D IMM1
DDR3_DR AMRST#14,37
0D75V_S0
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
(H=4mm)
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
109
108
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
10
27
45
62
135
152
169
186
12
29
47
64
137
154
171
188
116
120
126
1
30
203
204
DDR3-204P- 144-GP-U1
DDR3-204P- 144-GP-U1
62.10024.G21
62.10024.G21
2nd = *62.10017.X41
2nd = *62.10017.X41
3rd = *62.10017.V51
3rd = *62.10017.V51
DIMM2
DIMM2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2
4
RAS#
CAS#
CS0#
CS1#
CKE0
CKE1
CK0#
CK1#
EVENT#
VDDSPD
NC#1
NC#2
NC#/TEST
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
3
NP1
NP1
NP2
NP2
110
113
WE#
115
114
121
73
74
101
CK0
103
102
CK1
104
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
200
SDA
202
SCL
198
199
SA0_DIM1
197
SA0
SA1_DIM1
201
SA1
77
122
125
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
44
VSS
48
VSS
49
VSS
54
VSS
55
VSS
60
VSS
61
VSS
65
VSS
66
VSS
71
VSS
72
VSS
127
VSS
128
VSS
133
VSS
134
VSS
138
VSS
139
VSS
144
VSS
145
VSS
150
VSS
151
VSS
155
VSS
156
VSS
161
VSS
162
VSS
167
VSS
168
VSS
172
VSS
173
VSS
178
VSS
179
VSS
184
VSS
185
VSS
189
VSS
190
VSS
195
VSS
196
VSS
205
VSS
206
VSS
1D5V_S3
M_B_RAS# 6
M_B_WE# 6
M_B_CAS# 6
M_B_DIM0_CS#0 6
M_B_DIM0_CS#1 6
M_B_DIM0_CKE0 6
M_B_DIM0_CKE1 6
M_B_DIM0_CLK_DDR 0 6
M_B_DIM0_CLK_DDR #0 6
M_B_DIM0_CLK_DDR 1 6
M_B_DIM0_CLK_DDR #1 6
PCH_SMBDAT A 14,20,65,66
PCH_SMBCLK 14,20,65,66
TS#_DIMM0_1 14
C1501
C1501
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
12
1D5V_S3
DY
DY
12
C1502
C1502
SC2D2U10V3KX- 1GP
SC2D2U10V3KX- 1GP
DY
DY
3D3V_S0
0511-CHECK
SODIMM B DECOUPLING
C1504
C1504
C1505
C1503
C1503
12
C1511
C1511
12
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1505
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
DY
DY
C1512
C1512
C1513
C1513
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
3D3V_S0
12
R1501
R1501
10KR2J-3-GP
10KR2J-3-GP
SA1_DIM1
SA0_DIM1
12
R1502
R1502
10KR2J-3-GP
10KR2J-3-GP
Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
SO-DIMMB is placed farther from
the Processor than SO-DIMMA
C1508
C1507
C1507
12
C1508
C1509
C1509
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
DY
DY
C1506
C1506
12
C1514
C1514
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1510
C1510
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
DY
DY
2
1
62.10017.X41
3RD:62.10017.V51
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
DDR3-SODIMM2
DDR3-SODIMM2
DDR3-SODIMM2
LA480
LA480
LA480
1
15 103
15 103
15 103
SD
SD
SD
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
DDR3-SODIMM2
DDR3-SODIMM2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
DDR3-SODIMM2
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
16 103
16 103
16 103
1
SD
A
B
C
D
E
3D3V_S0
4 4
3 3
2 2
RN1701
RN1701
1
2 3
SRN2K2J-1-GP
SRN2K2J-1-GP
RN1702
RN1702
2 3
1
SRN100KJ-6-GP
SRN100KJ-6-GP
0511-CHECK 0511-CHECK
EC1701
EC1701
12
DY
DY
L_CTRL_DATA
4
L_CTRL_CLK
L_BKLT_EN49
L_DDC_DATA(K47):
This signal is on the LVDS interface.
This signal needs to be left NC if eDP is
used for the local flat panel display
L_BKLT_EN
LVDS_VDD_EN LVDS_VREFH
4
Close to PCH
Close to PCH and keep 20mil
away from other signal.
CRT_RED
CRT_BLUE
CRT_GREEN
678
RN1705
RN1705
SRN150F-1-GP
SRN150F-1-GP
123
4 5
Close to PCH
CRT_BLUE
CRT_GREEN
CRT_RED
EC1702
EC1702
EC1703
EC1703
SC
SC
SC
SC
12
D1U50V3KX-GP
D1U50V3KX-GP
DY
DY
SCD1U50V3KX-GP
SCD1U50V3KX-GP
12
D1U50V3KX-GP
D1U50V3KX-GP
DY
DY
12
R1701
R1701
2K37R2F-GP
2K37R2F-GP
CRT_BLUE50
CRT_GREEN50
CRT_RED50
LVDS_VDD_EN49
L_BKLT_CTRL49
LVDS_DDC_CLK_R49
LVDS_DDC_DATA_R49
RN1704
RN1704
2 3
1
SRN0J-6-GP
SRN0J-6-GP
LVDSA_CLK#49
LVDSA_CLK49
LVDSA_DATA0#49
LVDSA_DATA1#49
LVDSA_DATA2#49
LVDSA_DATA049
LVDSA_DATA149
LVDSA_DATA249
CRT_DDC_CLK50
CRT_DDC_DATA50
CRT_HSYNC50
CRT_VSYNC50
R1702
R1702
1KR2D-1-GP
1KR2D-1-GP
4 OF 10
PCH1D
PCH1D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_CTRL_CLK
L_CTRL_DATA
LVDS_IBG
LVDS_VREFL
4
12
DAC_IREF_R
T45
P39
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
N48
P49
T49
T39
M40
M47
M49
T43
T42
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
PANTHER-GP-NF
PANTHER-GP-NF
LVDS
LVDS
Digital Display Interface
Digital Display Interface
CRT
CRT
4 OF 10
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
RN1706
RN1706
SRN2K2J-1-GP
SRN2K2J-1-GP
3D3V_S0
DDI Port B Detect:(SDVO_CTRL_ DATA)
1: Port B detected
4
0: Port B not detected
1
2 3
PCH_HDMI_CLK 51
PCH_HDMI_DATA 51
HDMI_PCH_DET 51
HDMI_DATA2_R# 51
HDMI_DATA2_R 51
HDMI_DATA1_R# 51
HDMI_DATA1_R 51
HDMI_DATA0_R# 51
HDMI_DATA0_R 51
HDMI_CLK_R# 51
HDMI_CLK_R 51
PORT
PORT-B
DDI PCH Pin
Names
DDPB_[0]P
DDPB_[0]N
DDPB_[1]P
DDPB_[1]N
DDPB_[2]P
DDPB_[2]N
DDPB_[3]P
DDPB_[3]N
DDPB_AUXP
DDPB_AUXN
DDPB_HPD
SDVO_CTRLCLK
SDVO_CTRLDATA
HDMI/DVI
Mapping
TMDSB_DATA2
TMDSB_DATA2#
TMDSB_DATA1
TMDSB_DATA1#
TMDSB_DATA0
TMDSB_DATA0#
TMDSB_CLK
TMDSB_CLK#
NA
NA
HDMIB_HPD
HDMIB_CTRLCLK
HDMIB_CTRLDATA
HDMI
Notes:
1K 0.5% 0402
1 1
A
B
The recommended value for this external resistor is 1.0 k ±0.5%. The CRT DAC outputs may be
measured when the display is completely white. If CRT DAC signal voltage value is between 665
mV to 770 mV, then the video level is within VESA specification and the reference resistor
value is optimal for the motherboard design.
C
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
PCH : LVDS/CRT/DDI
PCH : LVDS/CRT/DDI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
PCH : LVDS/CRT/DDI
Taipei Hsien 221, Taiwan, R.O.C.
LA480
LA480
LA480
SD
SD
17 103Friday, January 06, 2012
17 103Friday, January 06, 2012
17 103Friday, January 06, 2012
E
SD
A
B
C
D
E
4 4
3 3
2 2
SSID = PCH
INT_PIRQH#
INT_PIRQB#
INT_PIRQF#
3D3V_S0
PCI_GNT#3 Low = A16 swap
3D3V_S0
R1817
R1817
8K2R2J-3-GP
8K2R2J-3-GP
DY
DY
1 2
DGPU_PW M_SELECT#
RN1801
RN1801
1
2
3
4
5 6
A16 swap override Strap/Top-Block
Swap Override jumper
DGPU_HOLD _RST#
DGPU_PW R_EN#
10
INT_PIRQD#
9
LCD_DET#
8
INT_PIRQC#INT_PIRQA#
7
PCI_GNT3#
12
R1801
R1801
4K7R2J-2-GP
4K7R2J-2-GP
1 2
3D3V_S0
1 2
1 2
R1814
R1814
10KR2F-2-GP
10KR2F-2-GP
DY
DY
R1815
R1815
10KR2F-2-GP
10KR2F-2-GP
INT_PIRQG#
SRN8K2J-2-G P-U
SRN8K2J-2-G P-U
DY
DY
override/Top-Block
Swap Override enabled
High = Default
R1819 10KR2J-3-GPR1819 10KR 2J-3-GP
3D3V_S0
For PPT USB3.0 feature
USB3_RX1_N62
USB3_RX3_N62
USB3_RX1_P62
USB3_RX3_P62
USB3_TX1_N62
USB3_TX3_N62
USB3_TX1_P62
USB3_TX3_P62
3D3V_S0
R1818
R1818
INT_PIRQA#
8K2R2J-3-GP
8K2R2J-3-GP
INT_PIRQB#
INT_PIRQC#
DY
DY
INT_PIRQD#
1 2
1 2
1 2
1 2
1
TP1813TP1813
DGPU_HOLD _RST#
DGPU_SELEC T#
DGPU_PW R_EN#
BBS_BIT1
DGPU_PW M_SELECT#
PCI_GNT3#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
PCI_PME#
1
PCI_PLTRST#
CLK_PCI_LPC_R
CLK_PCI_FB_R
CLK_PCI_KBC_R
DGPU_HOLD _RST#8 3
TP1805TP1805
DGPU_PW R_EN#93
LCD_DET#49
SATA_ODD_D A#27,56
CLK_PCI_LPC65,71
CLK_PCI_FB20
CLK_PCI_KBC27
1 2
R1813
R1813
0R2J-2-GP
0R2J-2-GP
R1804 22R2J-2-GPR1804 22R2J-2-GP
R1805 22R2J-2-GPR1805 22R2J-2-GP
R1806 22R2J-2-GPR1806 22R2J-2-GP
BG26
BH25
BG16
AH38
AH37
AK43
AK45
AH12
AB46
AB45
AY16
BG46
BE28
BC30
BE32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
BJ26
BJ16
C18
N30
H3
AM4
AM5
Y13
K24
L24
B21
M20
BJ32
K40
K38
H38
G38
C46
C44
E40
D47
E42
F46
G42
G40
C42
D44
K10
C6
H49
H43
J48
K42
H40
PCH1E
PCH1E
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24
USB3RN1
USB3RN2
USB3RN3
USB3RN4
USB3RP1
USB3RP2
USB3RP3
USB3RP4
USB3TN1
USB3TN2
USB3TN3
USB3TN4
USB3TP1
USB3TP2
USB3TP3
USB3TP4
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PME#
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
PANTHER- GP-NF
PANTHER- GP-NF
RSVD
RSVD
PCI
PCI
USB
USB
5 OF 10
5 OF 10
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
NV_ALE
AV5
NV_RCOMP
AV10
AT8
AY5
BA2
AT12
BF3
Utilize Port 9 for USB debug
USB_PN0
C24
USB_PP0
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USB_RBIAS
C33
B33
USB_OC#0_1
A14
USB_OC#2_3
K20
USB_OC#4_5
B17
USB_OC#6_7
C16
USB_OC#8_9
L16
USB_OC#10_11
A16
USB_OC#12_13
D14
PCH_GPIO14
C14
OC[3:0]# for Device 29 (Ports 0-7)
OC[7:4]# for Device 26 (Ports 8-13)
1
1
1
1
1 2
R1811
R1811
22D6R2F-L1-G P
22D6R2F-L1-G P
USB_OC#0_1 62
USB_OC#2_3 61
USB_OC#4_5 62
USB_OC#8_9 82
TP1814TP1814
TP1812TP1812
TP1819TP1819
TP1820TP1820
USB_PN1 62
USB_PP1 62
USB_PN2 82
USB_PP2 82
USB_PN3 62
USB_PP3 62
USB_PN4 63
USB_PP4 63
USB_PN5 82
USB_PP5 82
USB_PN8 66
USB_PP8 66
USB_PN9 82
USB_PP9 82
USB_PN10 64
USB_PP10 64
USB_PN11 65
USB_PP11 65
USB_PN12 49
USB_PP12 49
GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19
Mini Card2 (WWAN)
USB3.0 ext port 1
USB2.0 ext port 4
USB3.0 ext port 2
BLUETOOTH
CARD READER
USB2.0 ext port 3
Fingerprint
Mini Card1 (WLAN)
CAMERA
USB 2.0 Overcurrent Pin Default Usage
Pin
OC0#
OC1#
OC2#
OC3#
DY
1KR2J-1-GP
1KR2J-1-GP
BBS_BIT0 21
BBS_BIT1
R1802
R1802
1 2
DY
DY
1KR2J-1-GP
1KR2J-1-GP
R1803
R1803
1 2
DY
BOOT BIOS Strap
0 0 LPC
0 1 Reserved
11
Default Port
Mapping
Port 0, Port 1
Port 2, Port 3
Port 4, Port 5
Port 6, Port 7
Pin
OC4#
OC5#
OC6#
OC7#
Reserved 01
SPI(Default)
Default Port
Mapping
Port 8, Port 9
Port 10, Port 11
Port 12, Port 13
Not Used
Gx8 USB Table
Pair
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Device
X
USB3.0, ext port1
USB2.0, ext port4
USB3.0, ext port2
Bluetooth
CARD READER
X
X
3G
USB2.0, ext. port 3
Finger Print
Mini Card1 (WLAN)
CAMERA
X
Reserve Buffer or not?
PLT_RST#5,27,31,36,65,66,71,80,82,83,97
R1816
R1816
100KR2J-1-GP
100KR2J-1-GP
1 1
A
1 2
R1807
R1807
0R2J-2-GP
0R2J-2-GP
12
C1801
C1801
12
SC220P50V2KX-3GP
SC220P50V2KX-3GP
DY
DY
DY
DY
B
3D3V_S5
USB_OC#2_3
PCH_GPIO14
RN1802
RN1802
1
2
3
4
5 6
SRN8K2J-2-G P-U
SRN8K2J-2-G P-U
C
10
9
8
7
USB_OC#12_13
USB_OC#8_9USB_OC#6_7
USB_OC#10_11USB_OC#0_1PCI_PLTRST#
USB_OC#4_5
3D3V_S5
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
PCH : PCI/USB/NVRAM/RSVD
PCH : PCI/USB/NVRAM/RSVD
PCH : PCI/USB/NVRAM/RSVD
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
LA480
LA480
LA480
E
SD
SD
18 103Friday, January 06, 2012
18 103Friday, January 06, 2012
18 103Friday, January 06, 2012
SD
A
B
C
D
E
SSID = PCH
For platforms not supporting Deep S4/S5
1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)
4 4
3 OF 10
PCH1C
Signal Routing Guideline:
DMI_ZCOMP keep W=4 mils and
routing length less than 500
mils.
DMI_IRCOMP keep W=4 mils and
routing length less than 500
mils.
SYS_PWROK
1 2
DY
DY
R1926 10KR 2J-3-GP
R1926 10KR 2J-3-GP
PWROK
1 2
R1904 100KR 2J-1-GPR 1904 100KR2J- 1-GP
R1905
R1905
Platforms supporting Deep S4/S5, but not wishing
to participate in the handshake during wake and Deep S4/S5
entry may tie SUSACK# to SUSWARN#.
3 3
2 2
SUSPWRDNACK : No longer requires a 10-K pull-up to VccSUS
(3.3 V).
3D3V_S0
10KR2J-3-GP
10KR2J-3-GP
SYS_PWROK: the system is ready to start the exit from
reset (de-asserts PLT_RST# to the processor)
PWROK: it indicates to PCH that
its CORE well power is stable.
Active Sleep Well
(ASW) Power OK
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
SYS_RESET#
1 2
DY
DY
MPWROK45
3D3V_S5
RN1901
RN1901
8
7
6
SRN10KJ-6-G P
SRN10KJ-6-G P
R1909 10KR2J-3-GPR1909 10KR2J- 3-GP
DY
DY
R1922 10KR2J-3-GP
R1922 10KR2J-3-GP
R1908
R1908
10KR2J-3-GP
10KR2J-3-GP
1
2
3
45
12
12
12
XDP_DBRESE T#5
S0_PWR_G OOD27
BATLOW#
PM_RI#
SUS_PWR _ACK
PCIE_WAKE#
1D05V_VTT
SUS_ACK#: For non-DWS platforms, this signal can be left unconnected.
Due to the internal pull-up on this signal it will be pulled high
in order for the boot sequence to proceed.
SYS_PWROK36
1 2
R1931 0R 2J-2-GP
R1931 0R 2J-2-GP
SBA
SBA
AC_PRESENT
PM_PWRBT N#
PM_RSMRST#
DMI_RXN[3:0]4
DMI_RXP[3:0]4
DMI_TXN[3:0]4
DMI_TXP[3:0]4
R1901
R1901
49D9R2F-GP
49D9R2F-GP
1 2
R1902
R1902
1 2
750R2F-GP
750R2F-GP
1 2
DY
DY
R1915 0R 2J-2-GP
R1915 0R 2J-2-GP
R1916 0R0402-PADR1916 0R0402-PAD
1 2
1 2
R1914 0R 0402-PADR1914 0R0402- PAD
1 2
R1930 0R 2J-2-GP
R1930 0R 2J-2-GP
Non-SBA
Non-SBA
PM_DRAM_PW RGD37
PM_PWRBT N#27,97
AC_PRESENT27
PCH_WAKE#
CRB : 1K
CHKLIST: 10K
DMI_COMP_R
RBIAS_CPY
1 2
DY
DY
R1923
R1923
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
SUSACK#SUS_PWR _ACK
SYS_RESET#
0R2J-2-GP
0R2J-2-GP
PWROK
MEPWROK
PM_RSMRST#
SUS_PWR _ACK
PM_PWRBT N#
BATLOW#
PM_RI#
PCH1C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT/GPIO31
E10
BATLOW#/GPIO72
A10
RI#
PANTHER- GP-NF
PANTHER- GP-NF
DMI
DMI
System Power Management
System Power Management
3D3V_AUX_S5
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI
FDI
FDI_RXP7
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
CLKRUN#/GPIO32
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
SLP_SUS#
PMSYNCH
SLP_LAN#/GPIO29
R1925 100K R2J-1-GPR 1925 100KR 2J-1-GP
R1924
R1924
10KR2J-3-GP
10KR2J-3-GP
1 2
3V_5V_POK_#
3 OF 10
FDI_INT
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
12
2N7002KDW -GP
2N7002KDW -GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
6
Q1901
Q1901
2.DPWROK and RSMRST# will rise at the same time (connected on board)
3.SLP_SUS# and SUSACK# are left as ‘no connect’
4.SUSWARN# used as SUSPWRDNACK/GPIO30
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
DSWOD VREN
PCH_DPW ROK
PM_SUS_STAT#
SUS_CLK
PM_SLP_S5#
PM_SLP_SUS#
PM_SLP_LAN#
2345
1
FDI_TXN[7:0] 4
FDI_TXP[7:0] 4
FDI_INT 4
FDI_FSYNC0 4
FDI_FSYNC1 4
FDI_LSYNC0 4
FDI_LSYNC1 4
1 2
R1992 0R0402- PADR1992 0R0402-PAD
1 2
R1911
R1911
10KR2J-3-GP
10KR2J-3-GP
TP1901TP1901
1
R1913
R1913
1 2
0R0402-PAD
0R0402-PAD
TP1902TP1902
1
TP1904TP1904
1
TP1905TP1905
1
PM_RSMRST#
1 2
R1921
R1921
1KR2J-1-GP
1KR2J-1-GP
DY
DY
PM_RSMRST#
RTC_AUX_S5
PCIE_WAKE# 31,65,66
PM_CLKRUN # 27
PCH_SUSC LK_KBC 27
PM_SLP_S4# 27,46,97
PM_SLP_S3# 27,36,37,47
PM_SLP_A# 27,45
H_PM_SYNC 5
RSMRST#_KBC 27
3V_5V_POK 41
DSWODVREN - On Die DSW VR Enable
HIGH Enabled (DEFAULT)
LOW Disabled
DSWOD VREN
PM_CLKRUN #
This signal is used to control power planes to the IntelR ME
sub-system. This signal will be asserted in M-off state. If M3
is not supported then SLP_A# will have the same timings as
SLP_S3#.
For platforms supporting DEEP S4/S5 state, a low on this
signal indicates that PCH is in Deep Sleep state and that
EC/platform logic does not need to keep the Suspend Rails
ON.
If high means EC must keep SUS rails ON.
If DEEP S4/S5 is not supported, then this pin can be left
unconnected.
R1917 330KR2J-L1-G PR1917 330KR2J-L1-GP
1 2
R1918 330KR2J-L1-G P
R1918 330KR2J-L1-G P
1 2
DY
DY
R1919 8K2R2J-3-GPR1919 8K2R2J- 3-GP
1 2
RTC_AUX_S5
3D3V_S0
1 1
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
PCH : DMI/FDI/PM
PCH : DMI/FDI/PM
PCH : DMI/FDI/PM
LA480
LA480
LA480
E
SD
SD
19 103Friday, January 06, 2012
19 103Friday, January 06, 2012
19 103Friday, January 06, 2012
SD
A
B
C
D
E
3D3V_S5
RN2003
RN2003
1
SRN2K2J-1-G P
SRN2K2J-1-G P
23
RN2004
RN2004
1
SRN2K2J-1-G P
SRN2K2J-1-G P
23
RN2005
RN2005
SRN2K2J-1-G P
SRN2K2J-1-G P
4
RN2006
RN2006
4
SRN10KJ-5-G P
SRN10KJ-5-G P
R2009
R2009
1KR2J-1-GP
1KR2J-1-GP
PCH_SMBDAT A 14,15,65,66
PCH_SMBCLK 14,15,65,66
12
C2008
C2008
SC15P50V2JN-2- GP
SC15P50V2JN-2- GP
C2007
C2007
SC15P50V2JN-2- GP
SC15P50V2JN-2- GP
12
SBA_Support# 22
CLK_PCIE_NEW _REQ#
PCIE_CLK_LAN_R EQ#
PCIE_CLK_RQ5#
PCIE_CLK_RQ4#
EC_SWI#
PCIE_CLK_RQ0#
PEG_B_CLKRQ#
10KR2J-3-GP
10KR2J-3-GP
PEG_CLKREQ#_ R
10KR2J-3-GP
10KR2J-3-GP
4
4
4
3D3V_S5
12
R2004
R2004
12
R2005
R2005
DY
DY
SMB_DATA
SMB_CLK
XTAL25_IN
XTAL25_OUT
3D3V_S0 3D3V_S0
12
R2012
R2012
10KR2J-3-GP
10KR2J-3-GP
Non-SBA
Non-SBA
12
R2010
R2010
10KR2J-3-GP
10KR2J-3-GP
SBA
SBA
CLK_PCH_48M 82
SMB_CLK
SMB_DATA
SML0_DATA
SML0_CLK
SML1_CLK
SML1_DATA
PCIE_CLK_RQ6#
PCH_GPIO74
DRAMRST_C NTRL_PCH
3D3V_S0
RN2007
RN2007
2 3
1
SRN2K2J-1-G P
SRN2K2J-1-G P
Q2001
Q2001
6
2N7002KDW -GP
2N7002KDW -GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
R2006
R2006
1M1R2J-GP
1M1R2J-GP
1 2
12
12
4
1
2345
X2001
X2001
2 3
XTAL-25MHZ- 155-GP
XTAL-25MHZ- 155-GP
82.30020.D41
82.30020.D41
2nd = 82.30020.G71
2nd = 82.30020.G71
3rd = 82.30020.G61
3rd = 82.30020.G61
R2013
R2013
10KR2J-3-GP
10KR2J-3-GP
UMA
UMA
DGPU_PRSN T#
R2011
R2011
10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
3D3V_S5
RN2001
RN2001
1
2
3
4 5
SRN10KJ-6-G P
SRN10KJ-6-G P
RN2002
RN2002
1
2
3
4 5
SRN10KJ-6-G P
SRN10KJ-6-G P
4
4
2 3
1
1
2 3
1 2
41
UMA_DISCRETE#
UMA: 1 1
DIS :0 1
SG(PX) : 0 0
Optimus(Muxless) : 1 0
8
7
6
8
7
6
4 4
3 3
2 2
12
EC2001
EC2001
DY
DY
U16V2KX-3GP
U16V2KX-3GP
SCD1
SCD1
WLAN CLK
LAN CLK
SSID = PCH
If PCIE port 1 is disabled, it will
cause all PCIE port disabled
PCIE_RXN265
PCIE_RXP265
PCIE_TXN265
PCIE_TXP265
PCIE_RXN431
PCIE_RXP431
PCIE_TXN431
PCIE_TXP431
CLK_PCIE_WLA N#65
CLK_PCIE_WLA N65
PCIE_CLK_WL AN_REQ#65
CLK_PCIE_LAN#31
CLK_PCIE_LAN31
PCIE_CLK_LAN_R EQ#31
PCIE_CLK_WL AN_REQ#PCIE_CLK_LAN_R EQ#
12
EC2002
EC2002
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
3D3V_S0
RN2018
RN2018
PCIE_CLK_CR_R EQ#
1
4
PCIE_CLK_WL AN_REQ#
2 3
SRN10KJ-5-G P
SRN10KJ-5-G P
PCIECLKRQ1# and PCIECLKRQ2#
Support S0 power only
C2016 SCD 1U10V2KX-5GPC2016 SCD1U 10V2KX-5GP
1 2
C2015 SCD 1U10V2KX-5GPC2015 SCD1U 10V2KX-5GP
1 2
C2005 SCD 1U10V2KX-5GPC2005 SCD1U 10V2KX-5GP
1 2
C2006 SCD 1U10V2KX-5GPC2006 SCD1U 10V2KX-5GP
1 2
RN2012 SRN0J-6-GPRN2012 SRN0J-6-GP
1
4
2 3
RN2016 SRN 0J-6-GPRN2016 SRN0J -6-GP
1
4
2 3
TP2010TP2010
1
TP2011TP2011
1
PCIE_TXN2_C
PCIE_TXP2_C
PCIE_TXN4_C
PCIE_TXP4_C
PCIE_CLK_RQ0#
CLK_PCH_SR C1_N
CLK_PCH_SR C1_P
PCIE_CLK_WL AN_REQ#
PCIE_CLK_CR_R EQ#
CLK_PCH_SR C3_N
CLK_PCH_SR C3_P
PCIE_CLK_LAN_R EQ#
PCIE_CLK_RQ4#
PCIE_CLK_RQ5#
PEG_B_CLKRQ#
PCIE_CLK_RQ6#
CLK_PCIE_NEW _REQ#
PCIE_CLK_XDP_N
PCIE_CLK_XDP_P
2 OF 10
PCH1B
PCH1B
BG34
PERN1
BJ34
PERP1
AV32
WWAN
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
WLAN
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
Card Reader
PETN3
AU34
PETP3
BF36
PERN4
BE36
LAN
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0#/GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1#/GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2#/GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3#/GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4#/GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5#/GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ#/GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6#/GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7#/GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
PANTHER- GP-NF
PANTHER- GP-NF
– Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3
– Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2
if more than 2 PCI clocks + PCI loopback are routed.
PCI-E*
PCI-E*
CLOCKS
CLOCKS
SMBUSController
SMBUSController
SML1ALERT#/PCHHOT#/GPIO74
Link
Link
FLEX CLOCKS
FLEX CLOCKS
2 OF 10
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
PEG_A_CLKRQ#/GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
EC_SWI#
E12
SMB_CLK
H14
SMB_DATA
C9
DRAMRST_C NTRL_PCH
A12
SML0_CLK
C8
SML0_DATA
G12
PCH_GPIO74
C13
SML1_CLK
E14
SML1_DATA
M16
CL_CLK
M7
CL_DATA
T11
CL_RST#
P10
PEG_CLKREQ#_ R
M10
AB37
AB38
AV22
AU22
CLK_DP_N
AM12
CLK_DP_P
AM13
CLK_BUF_EXP_N
BF18
CLK_BUF_EXP_P
BE18
CLK_BUF_CP YCLK_N
BJ30
CLK_BUF_CP YCLK_P
BG30
CLK_BUF_DO T96_N
G24
CLK_BUF_DO T96_P
E24
CLK_BUF_CK SSCD_N
AK7
CLK_BUF_CK SSCD_P
AK5
CLK_BUF_RE F14
K45
CLK_PCI_FB
H45
XTAL25_IN
V47
XTAL25_OUT
V49
XCLK_RCOMP
Y47
JTAG_TCK
K43
CLK_PCH_48M_L
F47
CLK_27M_VGA_R
H47
DGPU_PRSN T#
K49
1 2
R2003 0R 0402-PADR2003 0R0402- PAD
CLK_PCI_FB 18
+VCCDIFFC LKN
1 2
R2007
R2007
90D9R2F-1-G P
90D9R2F-1-G P
SMB_CLK 80
SMB_DATA 80
DRAMRST_C NTRL_PCH 12,37
SML1_CLK 27
SML1_DATA 27
TP2001TP2001
1
TP2002TP2002
1
TP2003TP2003
1
CLK_PCIE_VGA# 83
CLK_PCIE_VGA 83
serial 0ohm RN?
CLK_EXP_N 5
CLK_EXP_P 5
TP2006TP2006
1
TP2007TP2007
1
RN2008
RN2008
2 3
1
4
SRN10KJ-5-G P
SRN10KJ-5-G P
PL 10K FOR Integrated CLOCK GEN mode.
CLK_BUF_DO T96_N
CLK_BUF_DO T96_P
CLK_BUF_CK SSCD_N
CLK_BUF_CK SSCD_P
CLK_BUF_EXP_N
CLK_BUF_EXP_P
CLK_BUF_RE F14
TP2004TP2004
1
1 2
R2016 22R2J-2-GP
R2016 22R2J-2-GP
TP2005TP2005
1
0511-CHECK
PEG_CLKREQ# 83
DY
DY
0511-CHECK
RN2020 SRN10KJ- 5-GPRN2020 SRN 10KJ-5-GP
1
2 3
RN2021 SRN10KJ- 5-GPRN2021 SRN 10KJ-5-GP
1
2 3
RN2019 SRN10KJ- 5-GPRN2019 SRN 10KJ-5-GP
1
2 3
1 2
R2008
R2008
10KR2J-3-GP
10KR2J-3-GP
12
EC2003
EC2003
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 1
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
PCH : PCIE/SMBUS/CLK
PCH : PCIE/SMBUS/CLK
PCH : PCIE/SMBUS/CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
LA480
LA480
LA480
E
SD
SD
20 103Friday, January 06, 2012
20 103Friday, January 06, 2012
20 103Friday, January 06, 2012
SD
A
SSID = PCH
RTC_X1
1 2
R2101 10MR2J-L-GPR2101 10MR2J- L-GP
X2101
X2101
C2101
C2101
4 4
+3VS_+1.5VS_HDA _IO
3D3V_S0
3 3
1 2
SC1
SC1
12
XTAL-32D768KH Z-15-GP
XTAL-32D768KH Z-15-GP
5P50V2JN-2-GP
5P50V2JN-2-GP
82.30001.C21
82.30001.C21
HDA_CODE C_SYNC29
HDA_CODE C_SDOUT29
HDA_CODE C_RST#29
HDA_CODE C_BITCLK29
1 2
DY
DY
R2102 1KR2J-1-GP
R2102 1KR2J-1-GP
NO REBOOT STRAP
1 2
DY
DY
R2106 1KR2J-1-GP
R2106 1KR2J-1-GP
+3VS_+1.5VS_HDA _IO
R2103 1KR2J-1-GPR2103 1KR2J-1- GP
1 2
This signal has a weak internal pull down.
On Die PLL VR is supplied by 1.5V when
sampled high, 1.8 V when sampled low.
Needs to be pulled High for Huron River platform.
co-operate with R2310
PLL ODVR VOLTAGE
HDA_SYNC
This signal has a weak internal pull-down.
On Die PLL VR is supplied by 1.5 V from VccVRM when
sampled high, 1.8 V from VccVRM when sampled low.
2 2
RTC_X2
C2102
C2102
SC1
SC1
12
5P50V2JN-2-GP
5P50V2JN-2-GP
RTCRST_O N27
1 2
DY
DY
R2131 0R2J-2-G P
R2131 0R2J-2-G P
0511-CHECK ADD BLOCK FET IN CODEC PAGE.
R212233R2J-2-GP
R212233R2J-2-GP
12
DY
DY
R212333R2J-2-GP R212333R2J-2- GP
12
R212633R2J-2-GP R212633R2J-2- GP
12
R212933R2J-2-GP R212933R2J-2- GP
12
Flash Descriptor Security Overide
HDA_SDOU T
HDA_SDOUT
HDA_SPKR
Low = 1.8V (Default)
High = 1.5V
No Reboot Strap
HDA_SPKR
HDA_SYNC
HDA_SYNC
HDA_SDOU T
HDA_RST#
HDA_BITCLK
Low = Default
High = Enable
Low = Default
High = No Reboot
CHECK
RTC_AUX_S5
SRN20KJ-GP -U
SRN20KJ-GP -U
1
2 3
RN2104
RN2104
Q2102
Q2102
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
R2130
R2130
0R2J-2-GP
0R2J-2-GP
1 2
DY
DY
4
12
C2103
C2103
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
D
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
1
3
HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to
sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this
signal on the board. Signal may have leakage paths via powered off devices (Audio
Codec) and hence contend with the external pull-up. A blocking FET is
recommended in such a case to isolate HDA_SYNC from the Audio Codec device
until after the Strap sampling is complete.
21
G2101
G2101
12
C2104
C2104
GAP-OPEN
GAP-OPEN
RTC_AUX_S5
2
D2130
D2130
BAS16-6-GP
BAS16-6-GP
83.00016.K11
83.00016.K11
2nd = 83.00016.M11
2nd = 83.00016.M11
3rd = 83.00016.N11
3rd = 83.00016.N11
KBC_RTCR ST# 27
Notes:
ME_UNLOCK (HDA_SDO) connect to EC.
Make sure EC drive this pin "low" all the time.
ME_UNLOCK27
B
INTVRMEN- Integrated SUS
1.05V VRM Enable
High - Enable internal VRs
Low - Enable external VRs
R2104 1M1R2J -GPR2104 1M1R2J -GP
1 2
R2105 330KR 2F-L-GPR2105 330KR2F -L-GP
HDA_SPKR29
HDA_SDIN029
R2107 1KR2J-1-GPR 2107 1KR2J-1-GP
1 2
TP2105TP2105
TP2102TP2102
TP2103TP2103
TP2104TP2104
CHECK
1 2
R2108 33R2J -2-GPR 2108 33R2J-2 -GP
1 2
R2109 0R2J -2-GPR2109 0R2J -2-GP
1 2
R2117 0R2J -2-GP
R2117 0R2J -2-GP
1 2
R2110 33R2J -2-GPR 2110 33R2J-2 -GP
CHECK 4.7K PD
R2134 51R2J-2-GPR2134 51R2J-2-GP
SPI_CLK_R27,60
SPI_CS0#_R27,60
SPI_CS1#_R60
SPI_SI_R2 7,60
SPI_SO_R27,60
PCH_JTAG_T CK_BUF
12
1
1
1
1
SBA
SBA
1 2
RTC_X1
RTC_X2
RTC_RST#
SRTC_RST #
SM_INTRUDER #
PCH_INTVRME N
HDA_BITCLK
HDA_SYNC
HDA_RST#
HDA_SDOU T
PCH_GPIO33
PCH_JTAG_T CK_BUF
PCH_JTAG_T MS
PCH_JTAG_T DI
PCH_JTAG_T DO
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_SI
PCH1A
PCH1A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN#/GPIO33
N32
HDA_DOCK_RST#/GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
PANTHER- GP-NF
PANTHER- GP-NF
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
PCH_SPI_CLK
12
EC2104
EC2104
DY
DY
JTAG
JTAG
RTCIHDA
RTCIHDA
SPI
SPI
DY
DY
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
LPC
LPC
FWH4/LFRAME#
LDRQ1#/GPIO23
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA 6G
SATA 6G
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP/GPIO21
SATA1GP/GPIO19
EC2102
EC2102
1 2
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
1 OF 10
1 OF 10
LDRQ0#
SERIRQ
C
LPC_AD0_TPM
C38
LPC_AD1_TPM
A38
LPC_AD2_TPM
B37
LPC_AD3_TPM
C37
LPC_FRAME#_L
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
SATA_LED#
P3
SATA_DET#0
V14
P1
HDA_CODE C_SDOUT
EC2103
EC2103
DY
DY
1 2
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
0511-CHECK
R2111 22R2F-1-GPR 2111 22R2F-1-GP
R2118 22R2F-1-GPR 2118 22R2F-1-GP
R2119 22R2F-1-GPR 2119 22R2F-1-GP
R2120 22R2F-1-GPR 2120 22R2F-1-GP
R2121 22R2F-1-GPR 2121 22R2F-1-GP
SATA_COMP
SATA3_COMP
RBIAS_SATA3
OD
SPI_CS0#_RHDA_CODE C_BITCLK
EC2101
EC2101
DY
DY
1 2
1 2
1 2
1 2
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
SATA_LED# 68
BBS_BIT0 18
1 2
1 2
1 2
1 2
1 2
APS_LED 68
R2112 37D4R2F-G PR2112 37D4R2F- GP
R2113 49D9R2F-G PR2113 49D9R2F- GP
R2114 750R2F-GPR2114 750R2F-GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
INT_SERIRQ 27
SATA_RXN0 66
SATA_RXP0 66
SATA_TXN0 66
SATA_TXP0 66
SATA_RXN1 56
SATA_RXP1 56
SATA_TXN1 56
SATA_TXP1 56
SATA_RXN4 56
SATA_RXP4 56
SATA_TXN4 56
SATA_TXP4 56
1D05V_VTT
1D05V_VTT
SATA_LED#
SATA_DET#0
S_GPIO22
INT_SERIRQ
LPC_AD[0..3] 27,65,71
LPC_FRAME# 27,6 5,71
RN2103
RN2103
1
2
3
4 5
SRN10KJ-6-G P
SRN10KJ-6-G P
R2125
R2125
8K2R2J-3-GP
8K2R2J-3-GP
1 2
APS_LED
m-SATA
HDD1
mSATA, CRV USE PORT2
ODD
E-SATA
3D3V_S0
8
7
6
D
Check with SW
3D3V_S0
R2128
R2128
10KR2J-3-GP
10KR2J-3-GP
DY
DY
1 2
10K?
E
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
Q2101
R2127
R2127
Q2101
S
12
G
2N7002K-2-GP
2N7002K-2-GP
HDA_SYNC
D
Vth?
5V_S0
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
PCH : HDA/JTAG/SATA
PCH : HDA/JTAG/SATA
PCH : HDA/JTAG/SATA
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
B
C
D
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
LA480
LA480
LA480
E
SD
SD
21 103Friday, January 06, 2012
21 103Friday, January 06, 2012
21 103Friday, January 06, 2012
SD
HDA_CODE C_SYNC HDA_CO DEC_SYNC_L
1 1
R2124
R2124
33R2J-2-GP
33R2J-2-GP
12
1MR2F-GP
1MR2F-GP
A
A
R2202
HR:200K (64.20035.6DL)
3D3V_S0
4 4
G-Sensor ST KIXNOK
R2226 DY 10K
CRV:10K (63.10334.1DL)
1 2
R2202 10KR2J-3- GPR2202 10KR2J- 3-GP
3D3V_S0
2 3
1
GPIO27 has a weak[20K] internal pull up.
To enable on-die PLL Voltage regurator,
should not place external pull down.
RN2203
RN2203
SRN10KJ-5-G P
SRN10KJ-5-G P
4
SATA_ODD_PR SNT#
H_A20GATE
H_RCIN#
DGPU_PW ROK92,93
SATA_ODD_PR SNT#56
R2221 10K DY
3D3V_S0
3D3V_S5
PCH_GPIO48
FP_DET#
3 3
2 2
PCH_TEMP_ALE RT#
EC_SMI#
EC_SCI#
DGPU_HPD _INTR#
PCH_GPIO22
PSW_CLR #
MFG_MODE
PCH_GPIO27
RTC_DET#
USB3_PWR _ON
PCH_GPIO15
PLL_ODVR_EN
INTERNAL GFX EXTERNAL GFX
R2205 DY 10K
1 2
R2220 10KR2 J-3-GPR 2220 10KR2J- 3-GP
1 2
DY
DY
R2224 10KR2 J-3-GP
R2224 10KR2 J-3-GP
1 2
R2222 10KR2 J-3-GPR 2222 10KR2J- 3-GP
RN2201
RN2201
1
8
2
7
3
6
4 5
SRN10KJ-6-G P
SRN10KJ-6-G P
R2225
R2225
10KR2J-3-GP
10KR2J-3-GP
1 2
1 2
R2228 10KR 2J-3-GPR 2228 10KR 2J-3-GP
1 2
R2229 10KR 2J-3-GPR 2229 10KR 2J-3-GP
RN2204 SRN10KJ-5-G PR N2204 SRN10KJ-5-GP
1
4
23
1 2
R2201 1KR2J -1-GPR2201 1 KR2J-1-GP
1 2
R2234 10KR2 J-3-GP
R2234 10KR2 J-3-GP
DY
DY
3D3V_S5
R2206 100K DY
3D3V_S0
12
R2205
R2205
10KR2J-3-GP
10KR2J-3-GP
DY
DY
GFX_CRB_D ET
12
R2206
R2206
100KR2J-1-GP
100KR2J-1-GP
R2221
R2221
10KR2J-3-GP
10KR2J-3-GP
1 2
Gsensor_ID
R2226
R2226
10KR2J-3-GP
10KR2J-3-GP
1 2
3D3V_S0
DY
DY
12
B
Note:
For PCH debug with XDP, need to NO STUFF R2218
1 2
R2218 100R2J-2-GPR221 8 100R2J-2-GP
EC_SCI#27
RTC_DET#60
1 2
R2215 0R2J-2-GPR2215 0R2J-2-GP
DGPU_PW ROK_C
TP2206TP2206
TP2212TP2212
TP2207TP2207
TP2208TP2208
TP2209TP2209
EC_SMI#
DGPU_HPD _INTR#
EC_SCI#
ICC_EN#
PCH_GPIO15
PCH_GPIO16
PCH_GPIO22
Gsensor_ID
PCH_GPIO27
PLL_ODVR_EN
PSW_CLR #
FP_DET#
DMI_OVRVLTG
FDI_OVRVLTG
MFG_MODE
GFX_CRB_D ET
PCH_GPIO48
PCH_TEMP_ALE RT#
USB3_PWR _ON
PCH_NCT F_1
1
PCH_NCT F_7
1
PCH_NCT F_2
1
PCH_NCT F_3
1
PCH_NCT F_4
1
1 2
R2216 0R2J-2-GPR2216 0R2J-2-GP
DY
DY
A K
D2201
D2201
CH751H-40-1 -GP
CH751H-40-1 -GP
FP_DET#
12
R2230
R2230
10KR2J-3-GP
10KR2J-3-GP
DY
DY
S_GPIO21
SATA_ODD_PR SNT#
G2201
G2201
GAP-OPEN
GAP-OPEN
21
R2223
R2223
10KR2J-3-GP
10KR2J-3-GP
12
R2232
R2232
10KR2J-3-GP
10KR2J-3-GP
DY
DY
VRAM_SIZE1
VRAM_SIZE2
GPIO0
BD49
BE49
BF49
A42
H36
E38
C10
G2
D40
E16
M5
M3
V13
A44
A45
A46
B47
BD1
BE1
BF1
PCH1F
PCH1F
T7
BMBUSY#/GPIO0
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
C4
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
U2
SATA4GP/GPIO16
TACH0/GPIO17
T5
SCLOCK/GPIO22
E8
GPIO24
GPIO27
P8
GPIO28
K1
STP_PCI#/GPIO34
K4
GPIO35
V8
SATA2GP/GPIO36
SATA3GP/GPIO37
N2
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
V3
SATA5GP/GPIO49/TEMP_ALERT#
D6
GPIO57
A4
VSS_NCTF_1#A4
VSS_NCTF_2#A44
VSS_NCTF_3#A45
VSS_NCTF_4#A46
A5
VSS_NCTF_5#A5
A6
VSS_NCTF_6#A6
B3
VSS_NCTF_7#B3
VSS_NCTF_8#B47
VSS_NCTF_9#BD1
VSS_NCTF_10#BD49
VSS_NCTF_11#BE1
VSS_NCTF_12#BE49
VSS_NCTF_13#BF1
VSS_NCTF_14#BF49
PANTHER- GP-NF
PANTHER- GP-NF
C
6 OF 10
6 OF 10
C40
TACH4/GPIO68
B41
TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71
PROCPWRGD
THRMTRIP#
GPIO
GPIO
CPU/MISC
CPU/MISC
VSS_NCTF_15#BG2
VSS_NCTF_16#BG48
VSS_NCTF_17#BH3
VSS_NCTF_18#BH47
VSS_NCTF_19#BJ4
VSS_NCTF_20#BJ44
VSS_NCTF_21#BJ45
NCTF
NCTF
VSS_NCTF_22#BJ46
VSS_NCTF_23#BJ5
VSS_NCTF_24#BJ6
VSS_NCTF_25#C2
VSS_NCTF_26#C48
VSS_NCTF_27#D1
VSS_NCTF_28#D49
VSS_NCTF_29#E1
VSS_NCTF_30#E49
NCTF TEST PIN:
A4,A44,A45,A46,A5,A6,B3,B47,
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
D49,E1,E49,F1,F49
NCTF TEST PIN:
A4,A44,A45,A46,A5,A6,B3,B47,
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
D49,E1,E49,F1,F49
VSS_NCTF_31#F1
VSS_NCTF_32#F49
A20GATE
RCIN#
INIT3_3V#
DF_TVS
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
VRAM_SIZE1
C41
VRAM_SIZE2
A40
P4
H_PECI_R
AU16
PECI
P5
AY11
PCH_THER MTRIP_R
AY10
INIT3_3V#
NV_CLE
TS_VSS
PCH_NCT F_9
PCH_NCT F_10
PCH_NCT F_5
PCH_NCT F_8
PCH_NCT F_6
1
1 2
R2219
R2219
0R0402-PAD
0R0402-PAD
1
1
1
1
1
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
PLL ON DIE VR ENABLE
NOTE:This signal has a weak internal pull-up 20K
ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT
DISABLED -- LOW (R2212 STUFFED)
PLL_ODVR_EN
1 2
DY
DY
R2212
R2212
1KR2J-1-GP
1KR2J-1-GP
SATA_ODD_PW RGT 56
SBA_Support# 20
H_A20GATE 27
1 2
DY
DY
R2203 0R2J-2-GP
R2203 0R2J-2-GP
H_RCIN# 27
H_CPUPW RGD 5,97
1 2
R2204
R2204
390R2J-1-GP
390R2J-1-GP
TP2201TP2201
TS Signal Disable Guideline:
TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4
should not float on the motherboard. They
should be tied to GND directly.
TP2214TP2214
TP2215TP2215
TP2210TP2210
TP2213TP2213
TP2211TP2211
R2211 BOM CTRL
HR:1K
CRV:DY
D
1D8V_S0
12
R1808
R1808
2K2R2J-2-GP
2K2R2J-2-GP
NV_CLE
1 2
R1809 1KR2J-1-GPR1809 1KR2J-1 -GP
DMI & FDI Termination Voltage
Set to Vss when LOW
NV_CLE
Set to Vcc when HIGH
H_PECI 5,27
H_THERMT RIP# 5,36
3D3V_S0
3D3V_S0
ICC_EN#
12
DY
DY
12
12
DY
DY
12
R2207
R2207
10KR2J-3-GP
10KR2J-3-GP
FDI_OVRVLTG
R2208
R2208
10KR2J-3-GP
10KR2J-3-GP
R2209
R2209
10KR2J-3-GP
10KR2J-3-GP
DMI_OVRVLTG
R2210
R2210
10KR2J-3-GP
10KR2J-3-GP
DY
DY
1 2
R2211
R2211
1KR2J-1-GP
1KR2J-1-GP
FDI TERMINATION VOLTAGE OVERRIDE
GPIO37
(FDI_OVRVLTG)
DMI TERMINATION VOLTAGE OVERRIDE
GPIO36
(DMI_OVRVLTG)
Integrated Clock Enable functionality is achieved
via soft-strap. The default is integrated clock
enable.
Integrated Clock Chip Enable
ICC_EN#
GPIO8 has a weak[20K] internal pull up.
Integrated Clock Enable functionality is achieved
via soft-strap. The default is integrated clock
enable.
H_SNB_IVB# 5
PROCPWRGD (PCH) --> UNCOREPOWRGOOD (CPU)
Indicates that VccSA, VDDQ, VccA (1.8V) and VccIO power
supplies are stable. This signal will be asserted only after
PWROK assertion.
LOW - Tx, Rx terminated to same voltage
(DC Coupling Model DEFAULT)
LOW - Tx, Rx terminated to same voltage
(DC Coupling Model DEFAULT)
HIGH (R2211 DY)- DISABLED [DEFAULT]
LOW (R2211)- ENABLED
E
1 1
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
PCH : GPIO/NTCF/MISC
PCH : GPIO/NTCF/MISC
PCH : GPIO/NTCF/MISC
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
LA480
LA480
LA480
E
SD
SD
22 103Friday, January 06, 2012
22 103Friday, January 06, 2012
22 103Friday, January 06, 2012
SD
5
SSID = PCH
4
3
2
1
6A
R2301 0R2J-2-GP
R2301 0R2J-2-GP
7 OF 10
POWER
PCH1G
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
AN19
BJ22
AN16
AN17
AN21
AN26
AN27
AP21
AP23
AP24
AP26
AT24
AN33
AN34
BH29
AP16
BG6
AP17
AU20
PCH1G
VCCCORE1
VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE5
VCCCORE6
VCCCORE7
VCCCORE8
VCCCORE9
VCCCORE10
VCCCORE11
VCCCORE12
VCCCORE13
VCCCORE14
VCCCORE15
VCCCORE16
VCCCORE17
VCCIO28
VCCAPLLEXP
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCC3_3_3
VCCVRM2
VCCAFDIPLL
VCCIO27
VCCDMI2
PANTHER-GP-NF
PANTHER-GP-NF
D D
C C
C2327
C2327
12
C2328
C2328
SC
SC
12
1U6D3V2KX-GP
1U6D3V2KX-GP
C2311
C2311
SC
SC
12
1U6D3V2KX-GP
1U6D3V2KX-GP
1D05V_VTT
SC
SC
1U6D3V2KX-GP
1U6D3V2KX-GP
C2312
C2312
12
SC
SC
1U6D3V2KX-GP
1U6D3V2KX-GP
1D05V_VTT
1.3A(Total current of VCCCORE)
C2302
C2302
C2304
C2304
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
12
1D05V_VTT
1
(10uF x1)
C2308
C2308
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
TP2301TP2301
2.925A(Total current of VCCIO)
C2307
C2307
C2306
C2306
SC
SC
12
12
1U6D3V2KX-GP
1U6D3V2KX-GP
C2303
C2303
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
VCCAPLLEXP
C2309
C2309
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
0.266A (Totally VCC3_3 current)
3D3V_S0
B B
0.159A(Totally current of VCCVRM)
(0.1uF x1)
+VCCAFDI_VRM
TP2302TP2302
1D05V_VTT
0.042A (Totally current of VCCDMI)
VCCVRM(Internal PLL and VRMs):
A.1.5V for Mobile
B.1.8 V for Desktop
12
C2310
C2310
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VCCFDIPLL
1
+1.05VS_VCC_DMI
POWER
VCC CORE
VCC CORE
VCCIO
VCCIO
FDI
FDI
CRTLVDS
CRTLVDS
DMI
DMI
DFT / SPI HVCMOS
DFT / SPI HVCMOS
7 OF 10
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCCTX_LVDS1
VCCTX_LVDS2
VCCTX_LVDS3
VCCTX_LVDS4
VCC3_3_6
VCC3_3_7
VCCVRM3
VCCDMI1
VCCCLKDMI
VCCDFTERM1
VCCDFTERM2
VCCDFTERM3
VCCDFTERM4
VCCSPI
0.001A
+VCCA_DAC_1_2
U48
U47
0.001A
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
0.16A
AT16
0.042A
AT20
AB36
AG16
AG17
AJ16
AJ17
0.02A
V1
+1.05VS_VCC_DMI
C2313
C2313
C2314
C2314
12
12
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
+3VS_VCCA_LVDS
0.06A
+1.8VS_VCCTX_LVDS
C2316
C2316
12
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
0.266A
C2319
C2319
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2320
C2320
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
0.02A
+1.05VS_VCC_DMI_CCI
12
C2321
C2321
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
0.19A
12
C2322
C2322
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VCCSPI_3D3V
12
C2323
C2323
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
(1uFx1)
L2301
L2301
1 2
BLM18PG181SN1D-GP
C2315
C2315
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2317
C2317
12
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
(0.1uFx1)
R2306 0R0402-PADR2306 0R0402-PAD
1 2
BLM18PG181SN1D-GP
C2333
C2333
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
(0.01uF x2)
(22uF x1)
1 2
3D3V_S0
Reserve 0ohm for power measurement?
R2308
R2308
0R0402-PAD
0R0402-PAD
(1uF x1)
R2307
R2307
1 2
0R0402-PAD
0R0402-PAD
R2309
R2309
1 2
0R0402-PAD
0R0402-PAD
1D05V_VTT
(1uFx1)
(10uFx1)
1D8V_S0
Reserve 0ohm for power measurement?
(0.1uFx1)
3D3V_S5
+VCCA_DAC_3V
R2302 0R2J-2-GPR2302 0R2J-2-GP
12
C2326
C2326
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1 2
R2304
R2304
0R0603-PAD
0R0603-PAD
1 2
R2305
R2305
0R0603-PAD
0R0603-PAD
1D5V_S0+VCCAFDI_VRM
1D05V_VTT
DY
DY
1 2
1 2
3D3V_DAC_S0
3D3V_S0
3D3V_S0
1D8V_S0
C2330
C2330
C2329
C2329
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
3.3V CRT LDO
5V_S0 3D3V_DAC_S0
12
DY
DY
C2325
C2325
SC1U10V2KX-1GP
SC1U10V2KX-1GP
74.09091.J3F GMT OBS REASON:G9091
series is going to EOL and no room for further cost reduction.
Pls help to use AME AME8818 , TI TLV702 and GMT G9090 for replacement.
74.09198.G7F OBS
U2302
U2302
DY
DY
1
IN
OUT
2
GND
EN3NC#4
AME8818BEEV330Z-GP
AME8818BEEV330Z-GP
74.08818.B3F
74.08818.B3F
5
4
12
DY
DY
C2324
C2324
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
A A
5
4
Refer to NPCE795 shared SPI flash architecture
3
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
PCH : POWER1
PCH : POWER1
PCH : POWER1
LA480
LA480
LA480
1
SD
SD
23 103Friday, January 06, 2012
23 103Friday, January 06, 2012
23 103Friday, January 06, 2012
SD
A
B
C
D
E
(0.1uFx1)
0.001A
1
(1uFx1)
1D05V_VTT
(1uFx1)
3D3V_S5
3D3V_S5
(0.1uFx1)
0.001A
TP2403TP2403
3D3V_S5
(1uFx1)
(0.1uFx2)
12
C2431
C2431
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
(0.1uFx1)
(1uFx1)
TP2407TP2407
1D05V_VTT
3D3V_S5
D2401
D2401
21
CH751H-40PT-GP
CH751H-40PT-GP
83.R0304.A8F
83.R0304.A8F
2nd = 83.R2004.B8F
2nd = 83.R2004.B8F
R2408
R2408
1 2
10R2J-2-GP
10R2J-2-GP
12
C2426
C2426
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3D3V_S0
D2402
D2402
21
CH751H-40PT-GP
CH751H-40PT-GP
83.R0304.A8F
83.R0304.A8F
2nd = 83.R2004.B8F
2nd = 83.R2004.B8F
R2407
R2407
1 2
10R2J-2-GP
10R2J-2-GP
12
C2427
C2427
SC1U10V2KX-1GP
SC1U10V2KX-1GP
3D3V_S0
3D3V_S0
1D05V_VTT
+3VS_+1.5VS_HDA_IO
1 2
R2409
R2409
0R0603-PAD
0R0603-PAD
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH : POWER2
PCH : POWER2
PCH : POWER2
Taipei Hsien 221, Taiwan, R.O.C.
LA480
LA480
LA480
(0.1uFx1)
(1uFx1)
3D3V_S5
E
5V_S5
5V_S0
24 103Friday, January 06, 2012
24 103Friday, January 06, 2012
24 103Friday, January 06, 2012
SD
SD
SD
10 OF 10
POWER
PCH1J
SSID = PCH
3D3V_S5
0.002A
(0.1uFx1)
(10uFx1)
+V3.3S_VCC_CLKF33
12
C2401
C2401
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
+VCCDIFFCLK
12
12
+V1.05S_SSCVCC
12
12
A
(1uFx1)
+1.05VS_VCCA_A_DPL
12
C2443
C2443
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
DY
DY
(1uFx1)
(220uFx1)
+1.05VS_VCCA_B_DPL
12
C2444
C2444
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
DY
DY
(1uFx1)
(220uFx1)
(0.1uFx2)
(4.7uFx1_0603)
12
C2402
C2402
SC1U10V2KX-1GP
SC1U10V2KX-1GP
1D05V_VTT
(1uFx1)
(0.1uFx2)
(1uFx1)
1D05V_M
C2403
C2403
12
12
C2409
C2409
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C2410
C2410
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1D05V_VTT
0R0402-PAD
0R0402-PAD
C2436
C2436
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C2411
C2411
(0.1uFx1)
1 2
R2406
R2406
0R0603-PAD
0R0603-PAD
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
(0.1uFx1)
R2413
R2413
RTC_AUX_S5
(10uFx1)
0.08A
0.08A
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
3D3V_S0
4 4
3 3
1D05V_VTT
2 2
1D05V_VTT
1D05V_VTT
1 1
L2401
L2401
1 2
IND-10UH-218-GP
IND-10UH-218-GP
68.10050.10Y
68.10050.10Y
2nd = 68.1001E.10N
2nd = 68.1001E.10N
L2402
L2402
1 2
IND-10UH-218-GP
IND-10UH-218-GP
68.10050.10Y
68.10050.10Y
2nd = 68.1001E.10N
2nd = 68.1001E.10N
L2403
L2403
1 2
IND-10UH-218-GP
IND-10UH-218-GP
68.10050.10Y
68.10050.10Y
2nd = 68.1001E.10N
2nd = 68.1001E.10N
R2404
R2404
0R0402-PAD
0R0402-PAD
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
R2405
R2405
0R0402-PAD
0R0402-PAD
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C2412
C2412
C2413
C2413
TP2401TP2401
1 2
R2403
R2403
0R0603-PAD
0R0603-PAD
TP2405TP2405
TP2404TP2404
1D05V_VTT
TP2402TP2402
1.01A (Total current of VCCASW)
C2406
C2406
C2437
C2437
12
C2414
C2414
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
+VCCRTCEXT
0.16A (Totally current of VCCVRM
12
+VCCDIFFCLKN
0.055A
12
C2415
C2415
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
(1uFx1)
C2417
C2417
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
12
C2418
C2418
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2416
C2416
B
1
1
1
1
C2407
C2407
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
+VCCAFDI_VRM
(1uFx1)
12
TP2406TP2406
V_PROC_IO_R
12
C2421
C2421
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VCCACLK
+VCCPDSW
DCPSUSBYP
+V3.3S_VCC_CLKF33
+VCCAPLL_CPY_PCH
+VCCSUS1
C2408
C2408
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
+1.05VS_VCCA_A_DPL
+1.05VS_VCCA_B_DPL
+VCCDIFFCLK
+V1.05S_SSCVCC
(1uFx1)
+VCCSST
DCPSUS
1
0.001A
12
C2419
C2419
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
6uA
AD49
T16
V12
T38
BH23
AL29
AL24
AA19
AA21
AA24
AA26
AA27
AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31
W21
W23
W24
W26
W29
W31
W33
N16
Y49
BD47
BF47
AF17
AF33
AF34
AG34
0.095A
AG33
V16
T17
V19
BJ8
A22
12
C2422
C2422
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PCH1J
VCCACLK
VCCDSW3_3
DCPSUSBYP
VCC3_3_5
VCCAPLLDMI2
VCCIO14
DCPSUS3
VCCASW1
VCCASW2
VCCASW3
VCCASW4
VCCASW5
VCCASW6
VCCASW7
VCCASW8
VCCASW9
VCCASW10
VCCASW11
VCCASW12
VCCASW13
VCCASW14
VCCASW15
VCCASW16
VCCASW17
VCCASW18
VCCASW19
VCCASW20
DCPRTC
VCCVRM4
VCCADPLLA
VCCADPLLB
VCCIO7
VCCDIFFCLKN1
VCCDIFFCLKN2
VCCDIFFCLKN3
VCCSSC
DCPSST
DCPSUS1
DCPSUS2
V_PROC_IO
VCCRTC
PANTHER-GP-NF
PANTHER-GP-NF
POWER
Clock and Miscellaneous
Clock and Miscellaneous
CPURTC
CPURTC
C
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
SATA USB
SATA USB
HDA
HDA
10 OF 10
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCSUS3_3_7
VCCSUS3_3_8
VCCSUS3_3_9
VCCSUS3_3_10
VCCSUS3_3_6
VCCIO34
V5REF_SUS
DCPSUS4
VCCSUS3_3_1
V5REF
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCC3_3_1
VCC3_3_8
VCC3_3_4
VCC3_3_2
VCCIO5
VCCIO12
VCCIO13
VCCIO6
VCCAPLLSATA
VCCVRM1
VCCIO2
VCCIO3
VCCIO4
VCCASW22
VCCASW23
VCCASW21
VCCSUSHDA
N26
P26
P28
T27
T29
0.097A (Totally current of VCCSUS3_3)
T23
T24
V23
V24
P24
T26
M26
AN23
AN24
P34
N20
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
AF14
AK1
AF11
AC16
AC17
AD17
T21
V21
T19
P32
1D05V_VTT
+5VA_PCH_VCC5REFSUS
+VCCA_USBSUS
+5VS_PCH_VCC5REF
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
+V1.05S_VCCAPLL_SATA3
+VCCAFDI_VRM
1D05V_M
+3VS_+1.5VS_HDA_IO
0.01A
C2433
C2433
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3D3V_S5
12
C2428
C2428
C2430
C2430
C2429
C2429
C2432
C2432
(0.1uFx1)
12
C2423
C2423
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2424
C2424
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2425
C2425
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
12
12
12
12
12
C2435
C2435
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
D
A
B
C
D
E
SSID = PCH
4 4
3 3
2 2
1 1
A
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
H5
PCH1H
PCH1H
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
PANTHER-GP-NF
PANTHER-GP-NF
B
8 OF 10
8 OF 10
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
C
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
B7
D3
D8
F3
PCH1I
PCH1I
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
PANTHER-GP-NF
PANTHER-GP-NF
9 OF 10
9 OF 10
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS328
VSS329
VSS330
VSS331
VSS333
VSS334
VSS335
VSS337
VSS338
VSS340
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
PCH : VSS
PCH : VSS
PCH : VSS
LA480
LA480
LA480
25 103Friday, January 06, 2012
25 103Friday, January 06, 2012
25 103Friday, January 06, 2012
E
SD
SD
SD
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
26 103
26 103
26 103
1
SD
5
SSID = KBC
1 2
R2702
R2702
0R0603-PAD
D D
3D3V_AUX_KBC
12
R2707
100KR2F-L1-GP
100KR2F-L1-GP
3D3V_AUX_S5
12
10KR2F-2-GP
10KR2F-2-GP
ADT_TYPE
R2701
R2701
R2776
R2776
100KR2J-1-GP
100KR2J-1-GP
R2707
DY
DY
-MSATA_DET
C2713
C2713
12
12
65W: 1.7V
90W: 3.3V
RC2702
RC2702
SC33P50V2JN-3GP
SC33P50V2JN-3GP
12
DY
DY
SC
SC
D1U10V2KX-5GP
D1U10V2KX-5GP
C C
0R0603-PAD
C2704
C2704
C2706
USB_CHG_EN82
AC_PRESENT19
-MSATA_DET66
RSMRST#_KBC19
PM_SLP_S4#19,46,97
12
GSENSE_X79
GSENSE_Y79
CAMERA_EN49
CAP_LED68
AOAC_EN65
S5_ENABLE36,97
ADP_LED82
LID_CLOSE#49,70
WIFI_RF_EN65
SPI_CS1#_R21,60
SPI_CS0#_R21,60
SPI_CLK_R21,60
SPI_SI_R21,60
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AD_IA40
AD_OFF38
BAT_IN#39
SPI_SO_R21,60
C2706
C2705
C2705
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
DY
DY
33R2J-2-GP R2744
33R2J-2-GP R2744
33R2J-2-GP R2736
33R2J-2-GP R2736
33R2J-2-GP R271933R2J-2-GP R2719
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2701
C2701
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
12
VGA_CURRENT42 NUM_LED68
CPU_CURRENT42
PCIE_WLAN_WAKE#65
BLUETOOTH_EN63,65
S0_PWR_GOOD19
KBC_RTCRST#21
PM_PWRBTN#19,97
USB_PWR_EN_R61,62,82
TP2704TP2704
C2707
C2707
12
Non-SBA
Non-SBA
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2708
C2708
12
C2714
C2714
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
TP2703TP2703
SBA
SBA
C2709
C2709
C2710
C2710
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
1 2
DY
DY
PCB_VER_AD LPC_AD3
ADT_TYPE
MODEL_ID_AD
3G_EN
1
NC_KBC_GPIO51
1
12
EC_SPI_CS#_C
12
EC_SPI_CLK_C
12
EC_SPI_DI_C
R27370R2J-2-GP R27370R2J-2-GP
12
EC_SPI_DO_C
R272233R2J-2-GP R272233R2J-2-GP
12
VBAT
U2701A
U2701A
104
VREF
97
GPIO90 /AD0
98
GPIO91 /AD1
99
GPIO92 /AD2
100
GPIO93 /AD3
108
GPIO5/A D4
96
GPIO4/A D5
95
GPIO3/A D6
94
GPIO7/A D7
101
GPIO94 /DA0
105
GPIO95 /DA1
106
GPIO96 /DA2
107
GPIO97 /DA3
79
GPIO2
6
GPIO24
109
GPIO30 /F_WP#
14
GPIO34 /CIRRXL
15
GPIO36
80
GPIO41 /F_WP#
17
GPIO42 /TCK
20
GPIO43 /TMS
21
GPIO44 /TDI
26
GPIO51 /N2TCK
123
GPIO67 N2TMS
82
GPIO75
83
GPIO76
84
GPIO77
90
F_CS0#
92
F_SCK
86
F_SDI_ F_SDIO 1
87
F_SDI_ F_SDIO 0
91
GPIO81 /F_WP#
117
GPIO20 /TA2/IOX _DIN_DI O
112
GP/I/O84 /IOX_SC LK/XORT R#
110
GPO82/I OX_LDS H/TEST#
NPCE885GA0DX-GP
NPCE885GA0DX-GP
VCC119VCC246VCC376VCC488VCC5
4
3D3V_S0_KBC3D3V_AUX_KBC
C2703
C2703
12
12
12
C2702
C2702
SC2D2U10V3KX-1GP
1 2
R2743 0R0402-PADR2743 0R0402-PAD
1 2
R2739 0R0402-PADR2739 0R0402-PAD
114
VBKUP
LRESET #/GPIOF 7
LCLK/GP IOF5
LFRAME# /GPIOF6
LAD3/GP IOF4
LAD2/GP IOF3
LAD1/GP IOF2
LAD0/GP IOF1
SERIRQ /GPIOF0
GPIO11 /CLKRUN#
GPIO65 /SMI#
ECSCI# /GPIO54
GPIO10 /LPCPD#
GPIO85 /GA20
KBRST# /GPIO86
GPIO52 /PSDAT3 /RDY#
GPIO50 /PSCLK3 /TDO
GPIO27 /PSDAT2
GPIO26 /PSCLK2
GPIO35 /PSDAT1
GPIO37 /PSCLK1
GPIO17 /SCL1/N2T CK
GPIO22 /SDA1/N2T MS
GPIO73 /SCL2
GPIO74 /SDA2
GPIO23 /SCL3
GPIO31 /SDA3
GPIO47 /SCL4
GPIO53 /SDA4
PSL_OUT _GPIO7 1#
PSL_IN2 _GPI6#
PSL_IN1 _GPI70 #
VCORF
103
EC_AGND
1 OF 2
1 OF 2
SC2D2U10V3KX-1GP
DY
DY
7
2
3
1
128
127
126
125
8
9
29
124
121
122
27
25
11
10
71
72
70
69
67
68
119
120
24
28
74
93
73
44
DY
DY
PLT_RST#_EC
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
ECSCI#_KBC
SATA_ODD_DA#_R
PROCHOT_EC
NC_EC_ENABLE
KBC_PWRBTN_EC#
AC_IN_KBC
KBC_VCORF
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
115
102
4
75
VDD
VSBY
AVCC
GND118GND245GND378GND489GND5
GND65AGND
116
R2711
R2711
1 2
0R0402-PAD
0R0402-PAD
RC2701
RC2701
SC33P50V2JN-3GP
SC33P50V2JN-3GP
3D3V_AUX_KBC
RTC_AUX_S5
1 2
R2709
R2709
0R0805-PAD
0R0805-PAD
1
C2711
C2711
SC220P50V2KX-3GP
SC220P50V2KX-3GP
BLON_OUT 49
PM_SLP_A# 19,45
GSENSE_ON# 79
CHG_USB_OC# 82
TPDATA 69
TPCLK 69
BAT_SCL 39,40
BAT_SDA 39,40
SML1_CLK 20
SML1_DATA 20
LAN_PWR_ON 31
CHG_ON# 40
12
3D3V_S0
DY
DY
1 2
1 2
R2735 0R0402-PADR2735 0R0402-PAD
R2730 33R2J-2-GPR2730 33R2J-2-GP
1 2
0R0402-PAD
0R0402-PAD
R2740
R2740
1 2
0R0402-PAD
0R0402-PAD
R2741
R2741
1 2
0R0402-PAD
0R0402-PAD
R2742
R2742
1 2
1 2
R2729 33R2J-2-GPR2729 33R2J-2-GP
1 2
R2738 0R2J-2-GPR2738 0R2J-2-GP
<------ TP
<------ BATTERY / CHARGER
<------PCH / eDP
RTCRST_ON 21
TP2705TP2705
C2712
C2712
SC1U10V2KX-1GP
SC1U10V2KX-1GP
LPC_AD2
LPC_AD1
LPC_AD0LPC_AD0_R
LPC_AD[0..3] 21,65,71
INT_SERIRQ 21
PM_CLKRUN# 19
PANEL_BLEN 49
SATA_ODD_DA# 18,56
H_A20GATE 22
H_RCIN# 22
3
PLT_RST# 5,18,31,36,65,66,71,80,82,83,97
CLK_PCI_KBC 18
LPC_FRAME# 21,65,71
3D3V_AUX_S5
12
KBC_NOVO_BTN#68
PCH_SUSCLK_KBC19
R2775
R2775
100KR2J-1-GP
100KR2J-1-GP
HDD_DET#56
USB_AO_SEL082ADT_TYPE38
PM_SLP_S3#19,36,37,47
DC_BATFULL68
KBC_BEEP29
STOP_CHG#40
AD_DETECT38
CHARGE_LED68
ME_UNLOCK21
AMP_MUTE#29
1D05V_VTT
HDD_DET#
PWRLED68
E51_RxD65
E51_TxD65
ECRST#41
H_PECI5,22
R2721 43R2J-GPR2721 43R2J-GP
1 2
R2720 0R2J-2-GPR2720 0R2J-2-GP
1 2
R2720 and C2716
Need very close to EC
1 2
R2725
R2725
0R0805-PAD
0R0805-PAD
12
3D3V_AUX_S53D3V_AUX_KBC
118
113
111
ECRST#
EC_VTT
C2716
C2716
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2
U2701B
U2701B
31
GPIO56 /TA1
63
GPIO14 /TB1
64
GPIO1/TB 2
32
GPIO15 /A_PWM
GPIO21 /B_PWM
62
GPIO13 /C_PWM
65
GPIO32 /D_PWM
22
GPIO45 /E_PWM
81
GPIO66 /G_PWM
66
GPIO33 /H_PWM
16
GPIO40 /F_PWM
23
GPIO46 /CIRRXM/T RIST#
GPIO87 /CIRRXM/S IN_CR
GP/I/O83/S OUT_CR/T RIST#
77
GPIO0/EX TCLK
30
GPIO55 /CLKOUT/I OX_DIN_ DIO
85
VCC_PO R#
13
PECI
12
VTT
NPCE885GA0DX-GP
NPCE885GA0DX-GP
KBSOUT0/G POB0/JE NK#
KBSOUT1/G PIOB1/T CK
KBSOUT2/G PIOB2/T MS
KBSOUT3/G PIOB3/T DI
KBSOUT4/G POB4/JE N0#
KBSOUT5/G PIOB5/T DO
KBSOUT6/G PIOB6/R DY#
KBSOUT7/G PIOB7
KBSOUT8/G PIOC0
KBSOUT9/G POC1/SD P_VIS #
KBSOUT10 _P80_ CLK/GPI OC2
KBSOUT11 _P80_ DAT/GPI OC3
KBSOUT12 /GPIO64
KBSOUT13 /GPIO63
KBSOUT14 /GPIO62
KBSOUT15 /GPIO61 /XOR_O UT
GPIO60 /KBSOUT16
GPIO57 /KBSOUT17
KBSIN0/GP IOA0/N2T CK
KBSIN1/GP IOA1/N2T MS
KBSIN2/GP IOA2
KBSIN3/GP IOA3
KBSIN4/GP IOA4
KBSIN5/GP IOA5
KBSIN6/GP IOA6
KBSIN7/GP IOA7
1
Code change to Low Active on 8/19
2 OF 2
2 OF 2
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
54
55
56
57
58
59
60
61
KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6PECI
KROW7
KCOL[0..15] 69
TP2707TP2707
1
TP2708TP2708
1
KROW[0..7] 69
3D3V_AUX_KBC
3D3V_AUX_KBC
12
R2717
R2717
10KR2J-3-GP
10KR2J-3-GP
12
R2714
R2714
10KR2J-3-GP
10KR2J-3-GP
12
R2773
R2773
100KR2J-1-GP
100KR2J-1-GP
AC_IN_KBC
12
R2706
R2706
100KR2J-1-GP
100KR2J-1-GP
DY
DY
DY
DY
PM_SLP_A#
KBC_NOVO_BTN#
EC_SPI_DI_C
R2712
R2712
1 2
0R0402-PAD
0R0402-PAD
AC_IN# 40
EC_GPIO47 High Active
12
ECRST#_B
MMBT3906-4-GP
MMBT3906-4-GP
84.03906.F11
84.03906.F11
KBC_PWRBTN#68
ECRST#
E
DY
DY
B
Q2701
Q2701
C
G2701
G2701
GAP-OPEN
GAP-OPEN
Q2702
R2732
R2732
12
Q2702
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.031
84.2N702.031
2ND = 84.2N702.J31
2ND = 84.2N702.J31
H_PROCHOT#_EC
D
1 2
R2733
R2733
0R0402-PAD
0R0402-PAD
H_PROCHOT# 5,42
PURE_HW_SHUTDOWN#28,36,86
R2723
R2723
10KR2J-3-GP
10KR2J-3-GP
2nd = 84.C3906.A11
2nd = 84.C3906.A11
AD_OFF
12
R2770
R2770
1KR2J-1-GP
1KR2J-1-GP
1 2
DY
DY
R2716 0R2J-2-GP
R2716 0R2J-2-GP
D2704
D2704
B B
EC_SCI#22
1
3
2
BAS16-6-GP
BAS16-6-GP
83.00016.K11
83.00016.K11
2ND = 83.00016.F11
2ND = 83.00016.F11
ECSCI#_KBC
PROCHOT_EC
100KR2J-1-GP
100KR2J-1-GP
Reset IC: Prevent BIOS data loss solution
3D3V_AUX_S5
12
C2715
C2715
PURE_HW_SHUTDOWN#
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
3D3V_AUX_S5
12
R2704
R2704
10KR2J-3-GP
10KR2J-3-GP
WHY
KBC_PWRBTN_EC#
12
R2703
R2703
470R2J-2-GP
470R2J-2-GP
12
R2774
R2774
DY
DY
100KR2J-1-GP
100KR2J-1-GP
2 1
12
R2705
R2705
10KR2J-3-GP
10KR2J-3-GP
C2717
C2717
12
SC220P50V2KX-3GP
SC220P50V2KX-3GP
U2702
U2702
1
GND
2
RESET#
G690L293T73UF-GP
G690L293T73UF-GP
74.00690.I7B
74.00690.I7B
3D3V_AUX_S5
DY
DY
3
VCC
EC GPIO standard PH/PL
3D3V_AUX_KBC
RN2701
3D3V_AUX_KBC
SML1_CLK
Q2703
Q2703
SML1_DATA
3D3V_S0
2345
1
6
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
A A
SMBC_THERM
SMBD_THERM
RN48
RN48
SRN10KJ-5-GP
SRN10KJ-5-GP
SMBC_THERM 28,86
SMBD_THERM 28,86
1234
3D3V_S0
MODEL_ID_AD
(Pin100)
UMA
OPTIMUS
12
R2727
R2727
47KR2F-GP
47KR2F-GP
BOM CTRL
BOM CTRL
MODEL_ID_AD
12
R2728
R2728
100KR2F-L1-GP
100KR2F-L1-GP
Pull Down Pull High Voltage
100.0K
33.0K 2.481V
100.0K 47.0K 2.245V
BAT_SCL
BAT_SDA
BAT_IN#
LID_CLOSE#
S5_ENABLE
ECRST#
PCIE_WLAN_WAKE#
E51_RxD
BLUETOOTH_EN
RN2701
SRN4K7J-8-GP
SRN4K7J-8-GP
RN2703
RN2703
SRN100KJ-6-GP
SRN100KJ-6-GP
RN2705
RN2705
SRN10KJ-5-GP
SRN10KJ-5-GP
DY
1 2
R2708
R2708
10KR2J-3-GP
10KR2J-3-GP
R2710
R2710
10KR2J-3-GP
10KR2J-3-GP
1234
1234
1234
12
R271510KR2J-3-GPDYR271510KR2J-3-GP
3D3V_S0
DY
DY
12
DY
DY
3D3V_AUX_KBC
PCB_VER_AD
71.00885.A0G
IC EMB CTRL NPCE885PA0DX LQFP 128P
12
R2724
R2724
64K9R2F-1-GP
64K9R2F-1-GP
BOM CTRL
BOM CTRL
12
R2726
R2726
100KR2F-L1-GP
100KR2F-L1-GP
PCB Version A/D
(Pin98)
SA
SB
SC
-1
Reserved
Reserved
Reserved
Pull-Low Resistor Pull-High Resistor
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
(3D3V_AUX_S5)
10.0K
20.0K
33.0K
47.0K
64.9K
76.8K
100.0K
Voltage
3.0V
2.75V
2.48V
2.24V
2.0V
1.87V
1.65V
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LA480 SD
A1
LA480 SD
A1
LA480 SD
A1
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
Taipei Hsien 221, Taiwan, R.O.C
27 103Friday, January 06, 2012
27 103Friday, January 06, 2012
27 103Friday, January 06, 2012
5
4
3
2
1
SSID = Thermal
Close to SO-DIMM on top side.
SA 0905 change to 390p
3
D D
20110718_Carrey:
C C
B B
For Vendor suggestion, add 10k pull high to 3D3V_S0
3D3V_S0
12
R2812
R2812
10KR2J-3-GP
10KR2J-3-GP
DY
DY
THERM_SCI#
E
C
Q2802
Q2802
MMBT3904WT1G-GP
MMBT3904WT1G-GP
2
E
C
Q2804
Q2804
MMBT3904WT1G-GP
MMBT3904WT1G-GP
between CPU, VGA and DIMM on bottom side
pin6, ALERT# OD
pin7, SYS_SHDN# OD
B
B
H_THERMDA
H_THERMDC
REMOTE2+
REMOTE2-
SMBC_THERM27,86
SMBD_THERM27,86
12
C2803
C2803
SC390P50V2KX-GP
SC390P50V2KX-GP
12
C2804
C2804
SC390P50V2KX-GP
SC390P50V2KX-GP
DY
DY
Thermal sensor
2200p close to smsc2103 chip
3D3V_S0
12
R2805
R2805
68R2-GP
68R2-GP
U2801
2103_VDD
1 2
C2806 SCD1U10V2KX-4GPC2806 SCD1U10V2KX-4GP
THERM_SYS_SHDN# SHDN_SEL
THERM_SCI#
U2801
3
VDD
2
DP1
1
DN1
16
DP2/DN3
15
ND2/DP3
7
SYS_SHDN#
6
ALERT#
9
SMCLK
8
SMDATA
EMC2103-2-AP-GP
EMC2103-2-AP-GP
REMOTE2-
12
C2805
C2805
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
REMOTE2+
GPIO1
GPIO2
TACH
PWM
TRIP_SET
SHDN_SEL
GND
GND
20110718_Carrey:
For Vendor suggestion, add 390pF Cap. as closed to pin B/C and E of Q2803
T8
1
C
B
Q2803
Q2803
E
MMBT3904WT1G-GP
MMBT3904WT1G-GP
CPU backside or inside the socket
CPU TEMP:
H_THERMDA and H_THERMDC routing 10mil trace width
and spacing. Locate Capacity near Thermal diode.
3D3V_S0
12
R2801
R2801
6K8R2J-GP
6K8R2J-GP
SHDN_SEL
SHDN --> 2N3904 ON External diode
2103_4
4
2103_5
5
10
11
TRIP_SET
14
13
TRIP_SET: 649 ohm => 87 dgree C
12
17
TP2802TP2802
1
TP2803TP2803
1
FAN_TACH_1
R2806 649R2F-GPR2806 649R2F-GP
1 2
T8 = 98
RN2801
RN2801
2 3
1
SRN10KJ-5-GP
SRN10KJ-5-GP
D2801
D2801
CH551H-30PT-GP
CH551H-30PT-GP
83.R5003.C8F
83.R5003.C8F
1st = 83.R5003.J8F
1st = 83.R5003.J8F
2ND = 83.R5003.I8F
2ND = 83.R5003.I8F
12
C2808
C2808
SC390P50V2KX-GP
SC390P50V2KX-GP
4
FAN_TACH
21
FAN_PW M
2200p close to smsc2103 chip
4 WIRE PWM Fan Control circuit
FAN_TACH
R2804
R2804
0R0402-PAD
0R0402-PAD
3D3V_S0
C2801
C2801
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
1 2
20100707_EMI
H_THERMDA
12
C2802
C2802
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
H_THERMDC
5V_S0
R2803
R2803
12
10KR2J-3-GP
10KR2J-3-GP
EC2802
EC2802
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
DY
DY
12
R2802
R2802
0R0805-PAD
0R0805-PAD
EC2801
EC2801
12
DY
DY
AFTP2801AFTP2801
AFTP2805AFTP2805
AFTP2806AFTP2806
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
AFTP2807AFTP2807
1
5V_S0_FAN
FAN_PW M_CFAN_PWM
FAN_PW M_C
1
FAN_TACH
1
5V_S0_FAN
1
FAN1
FAN1
6
4
3
2
1
5
ACES-CON4-GP-U1
ACES-CON4-GP-U1
20.F0714.004
20.F0714.004
CHECK PIN DEFINE
3D3V_AUX_S5
3
D2802
D2802
BAT54PT-GP
BAT54PT-GP
83.00054.T81
83.00054.T81
2ND = 83.BAT54.D81
2ND = 83.BAT54.D81
3rd = 83.BAT54.S81
A A
5
PURE_HW _SHUTDOWN#27,36,86
3rd = 83.BAT54.S81
12
R2810
R2810
10KR2J-3-GP
10KR2J-3-GP
DY
DY
1
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
4
DY
DY
C2807
C2807
DY
DY
2
D
84.2N702.031
84.2N702.031
2ND = 84.2N702.J31
2ND = 84.2N702.J31
Q2801
Q2801
2N7002K-2-GP
2N7002K-2-GP
THERM_SYS_SHDN#
S
IMVP_PWRGD_T
G
R2808
R2808
100KR2J-1-GP
100KR2J-1-GP
3D3V_S0 3D3V_S0
12
1 2
3
R2809
R2809
10KR2J-3-GP
10KR2J-3-GP
1 2
R2811
R2811
0R0402-PAD
0R0402-PAD
IMVP_PWRGD 36,42
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
THERMAL SENSOR SMSC EMC2103
THERMAL SENSOR SMSC EMC2103
THERMAL SENSOR SMSC EMC2103
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
LA480
LA480
LA480
Taipei Hsien 221, Taiwan, R.O.C.
28 103
28 103
28 103
1
SD
SD
SD
5
4
3
2
1
R2905 75R2J -1-GPR 2905 75R2J-1 -GP
R2906 75R2J -1-GPR 2906 75R2J-1 -GP
AUD_LDO_C AP
28
29
30
31
LDO-CAP
MIC2-VREFO
MIC1-VREFO-L
MIC1-VREFO-R
AUD_DVDD
AUD_SDATA IN
HDA_CODE C_BITCLK_R
12
C2924
C2924
DY
DY
AUD_5V
12
C2905
C2905
SC10U6D3V3MX- GP
SC10U6D3V3MX- GP
AU_GND
1 2
1 2
AUD_MIC1_VREF O_L
25
26
27
VREF
AVSS1
AVDD1
MONO-OUT
SENSE_B
SENSE_A
12
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
HDA_CODE C_RST#
R2917 22R2J-2-GPR2917 22R2J-2- GP
R2919 0R0402-PADR2919 0R0402-PAD
HDA_CODE C_RST#
SC6D8P50V2DN -GP
SC6D8P50V2DN -GP
1 2
R2904 0R0805-PADR2904 0R0805-PAD
AUD_HPOU T_R 82
AUD_HPOU T_L 82
AUD_MIC2_VREF O 58
1 2
C2907
C2907
SC10U6D3V3MX- GP
SC10U6D3V3MX- GP
12
C2909
C2909
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
AU_GND
12
AU_GND
24
LINE1-R
23
LINE1-L
AUD_PORT B_R
22
MIC1-R
AUD_PORT B_L
21
MIC1-L
20
AUD_JDRE F
19
JDREF
18
AUD_PORT F_R
17
MIC2-R
AUD_PORT F_L
16
MIC2-L
15
LINE2-R
14
LINE2-L
13
AUD_SENSE_A
DIGITAL
AUD_PC_BEEP
C2918
C2918
4K7R2J-2-GP
4K7R2J-2-GP
12
12
12
C2925
C2925
DY
DY
5V_S0
AU_GND
close to pin27
12
C2910
C2910
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
AUD_5V
C2913
C2913
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
AU_GND
C2914 SC4D 7U6D3V3KX-G PC2914 SC4D7U6D 3V3KX-GP
C2915 SC4D 7U6D3V3KX-G PC2915 SC4D7U6D 3V3KX-GP
R2909
R2909
20KR2F-L-GP
20KR2F-L-GP
C2916 SC4D 7U6D3V3KX-G P
C2916 SC4D 7U6D3V3KX-G P
B Series-MIC
B Series-MIC
C2917 SC4D 7U6D3V3KX-G P
C2917 SC4D 7U6D3V3KX-G P
B Series-MIC
B Series-MIC
ANALOG
KBC_BEEP_R
12
12
12
R2915
R2915
HDA_CODE C_RST# 21
HDA_CODE C_SYNC 21
HDA_SDIN0 21
HDA_CODE C_BITCLK 21
HDA_CODE C_BITCLK_R
SC6D8P50V2DN -GP
SC6D8P50V2DN -GP
20100705_AUD
AU_GND
EXT MIC
close to pin27
12
C2901
C2901
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
1 2
1 2
1 2
1 2
1 2
1 2
R2912
R2912
39K2R2F-L-GP
39K2R2F-L-GP
C2921
C2921
SC100P50V2JN-3 GP
SC100P50V2JN-3 GP
12
C2926
C2926
DY
DY
R2902 0R5J-5-GPR2902 0R5J -5-GP
1 2
Tied at one point only under the
ALC269 or near the ALC269
AUD_MIC1_VREF O_L
AUD_MIC1_COMB O
AUD_COMBO JACK
Capacitor Working Voltage
ALC269 having AVDD=5V ±5%, so the capacitors must have a 10V working voltage. A working
voltage of 16V is recommended to provide margin for variations in the application
AU_GND
R2914
R2914
12
10KR2J-3-GP
10KR2J-3-GP
R2916
R2916
12
10KR2J-3-GP
10KR2J-3-GP
AUD_MIC1_COMB O
AUD_MIC2 58
HPOUT_JD 82
HDA_SPKR 21
KBC_BEEP 27
EXT MIC
ANALOG MIC
1 2
R2922 2K2R2J-2-GPR2922 2K2R2J-2-G P
1 2
R2923 1KR2J-1-GPR2923 1KR2J-1- GP
AUD_MIC1_COMB O_R
R2925
R2925
22KR2J-GP
22KR2J-GP
1 2
1 2
12
C2928
C2928
SC10U6D3V3MX- GP
SC10U6D3V3MX- GP
R2924
R2924
22KR2J-GP
22KR2J-GP
AUD_MIC1_COMB O_R 82
5V_S0
1 2
R2903 0R0805-PADR2903 0R0805-PAD
D D
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
R2920
R2920
3D3V_S0
12
R2921
R2921
10KR2J-3-GP
10KR2J-3-GP
12
DY
DY
AUD_SPK_L+58
AUD_SPK_L-58
AUD_SPK_R-58
AUD_SPK_R+58
C C
B B
AMP_MUTE#
4K7R2J-2-GP
4K7R2J-2-GP
12
Close to Codec
C2911
C2911
3D3V_S0
AUD_DMIC_DA TA58
AUD_DMIC_CLK58
HDA_CODE C_SDOUT21
C2902
C2902
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
R2913 0R0805-PADR2913 0R0805-PAD
AMP_MUTE#27
C2904
C2904
C2903
C2903
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
AUD_5V
C2912
C2912
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
AU_GND AU_GND AU_G ND
AUD_PVDD
AUD_PVDD
AUD_COMBO JACK
1 2
R2901 0R0402-PADR2901 0R0402 -PAD
R2918 0R0402-PADR2918 0R0402 -PAD
AUD_DMIC_CLK
C2922
C2922
SC33P50V2JN-3G P
SC33P50V2JN-3G P
For EMI issue.
1A
AUD_PVDD
C2927
C2927
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
<<Attention>>
Surges of PVDD >7V duration 0.1ms when
DY
DY
class D amplifier is working may damage
the amplifier, 10uF tantalum capacitors
are required at PVDD1 and PVDD2 to
suppress the surge.
C2906
C2906
SC2D2U10V3KX- 1GP
SC2D2U10V3KX- 1GP
SC2D2U10V3KX- 1GP
SC2D2U10V3KX- 1GP
Close to Codec
AU_GND
C2920
C2920
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
AUD_DMIC_DA TA
12
SC33P50V2JN-3G P
SC33P50V2JN-3G P
12
C2908
C2908
U2901
U2901
37
AVSS2
38
AVDD2
39
PVDD1
40
SPK-L+
41
SPK-L-
42
PVSS1
43
PVSS2
44
SPK-R-
45
SPK-R+
46
PVDD2
47
EAPD/COMBO_JACK
48
SPDIFO
49
GND
AUD_DVDD
AUD_DMIC_CLK _R
C2923
C2923
AU_GND
12
C2919
C2919
12
1 2
1 2
DY
DY
Close to Codec
AUD_PORT A_R
AUD_PORT A_L
AUD_CPVEE
12
AUD_CBP
AUD_CBN
34
32
33
35
36
CBP
CBN
CPVEE
HP-OUT-L
HP-OUT-R
ALC269Q-VC-GR-GP
ALC269Q-VC-GR-GP
DVDD11GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3PD#4SDATA-OUT5BIT-CLK6DVSS27SDATA-IN8DVDD-IO9SYNC10RESET#11PCBEEP
AUD_SDATA_OUT
AUD_SDATA _OUT
12
SC22P50V2JN-4G P
SC22P50V2JN-4G P
DY
DY
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O .C.
Taipei Hsie n 221, Taiwan, R.O .C.
Title
Title
Title
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
A2
A2
A2
Friday, January 06, 2012
Friday, January 06, 2012
Friday, January 06, 2012
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O .C.
AUDIO CODEC
AUDIO CODEC
AUDIO CODEC
LA480
LA480
LA480
1
29 103
29 103
29 103
SD
SD
SD
5
D D
C C
4
3
2
1
BLANK
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
LA480
LA480
LA480
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
SD
SD
SD
30 103Friday, January 06, 2012
30 103Friday, January 06, 2012
30 103Friday, January 06, 2012
1
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