Wistron Berry GD15 Schematic

5

D D

4

3

2

1

Berry DG15 Discrete/UMA Schematics Document

Arrandale

C C

Intel PCH

2010-02-03
REV : A00

B B

DY :None Installed
UMA:UMA platform installed
PARK:DIS PARK platform installed
M96:DIS M96 platform installed
VRAM_1G:VRAM 128M*16 installed
Colay :Manual modify BOM

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

Cover Page

Cover Page

1

of

192Wednesday, February 10, 2010

of

192Wednesday, February 10, 2010

of

192Wednesday, February 10, 2010

A00

A00

A00

5

##OnMainBoard

1.Park-XT;512MB
(64Mx16b*4)
Dell P/N:9TGTN$AA HYNIX

D D

Dell P/N:C995R$AA SAMSUNG

2.Park-XT;1GB (128Mx16b*4)
Dell P/N:PXFYJ$AA HYNIX
Dell P/N:C09DT$AA SAMSUNG

VRAM

1GB/512MB

85,86,87,88

DDR3
800MHz

(1 and 2 co-lay)

Clock Generator

SLG8SP585

7

AMD Graphic

Park-XT
(Discrete only)

80,81,82,83,84

C C

HDMI

LCD

57

54

CRT

Left Side:
USB x 2

B B

Discreet/UMA Co-lay

LVDS(Dual Channel)

RGB CRT

CRT Board

77

Bluetooth

CAMERA

73

54

4

3

Berry Block Diagram
(Discrete/UMA co-lay)

4

HDMI

PCIe x 16

(Discrete only)

FDIx4x2
(UMA only)

Level

57

shifter

USB2.0 x 4

AZALIA

Intel CPU

Arrandale

8,9,10,11,12,13,14

DMIx4

Intel

PCH

14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6)

PCIE ports (8)

LPC I/F

ACPI 1.1

PCI/PCI BRIDGE

20,21,22,23,24,25,26,27,28

HM57

DDRIII 800/1066 Channel A

DDRIII 800/1066 Channel B

PCIE x 3

SATA x 1

USB 2.0 x 4

USB 2.0 x 1

Project code : 91.4HH01.001
PCB P/N : 48.4HH01.0SA
Revision : 09909-1

I/O Board

CardReader

SATAx1 / USB2.0x1

PCIE x 1,USB x 1

Connector

USB 2.0 x 1

76

Realtek
RTS5159

78

DDRIII
800/1066

DDRIII
800/1066

PCIE x 1
USB x 1

PCIE x 1

2

Slot 0

18

Slot 1

19

10/100 NIC

RTL8103T-VB

ESATA/USB
Combo

Mini-Card

SD/MMC+/MS/
MS Pro/xD

Mini-Card

802.11a/b/g

Realtek

WWAN

Right Side:
USB x 1

RJ45
CONN

SIM

1

CPU DC/DC

ISL62883

INPUTS

+PWR_SRC

OUTPUTS

+VCC_CORE

SYSTEM DC/DC

TPS51218

INPUTS

+PWR_SRC

OUTPUTS

+1.05V_VTT

SYSTEM DC/DC

RT8205B

INPUTS

+PWR_SRC +5V_ALW

OUTPUTS

+5V_ALW2
+3.3V_RTC_LDO

+3.3V_ALW
+15V_ALW

SYSTEM DC/DC

TPS51116

INPUTS

+PWR_SRC

OUTPUTS

+1.5V_SUS
+0.75V_DDR_VTT
+V_DDR_REF

SYSTEM DC/DC

TPS51611

INPUTS

+PWR_SRC

OUTPUTS

+CPU_GFX_CORE

VGA

RT8208B

INPUTS

+PWR_SRC

OUTPUTS

+VGA_CORE

TI CHARGER

BQ24745

INPUTS

+DC_IN
+PBATT

26

SYSTEM DC/DC

OUTPUTS

+PWR_SRC

APL5930

INPUTS

+3.3V_ALW

OUTPUTS

+1.8V_RUN

+1.8V_RUN_VGA

SYSTEM DC/DC

APL5930

INPUTS OUTPUTS

26

+1.5V_SUS +1.0V_RUN_VGA

47

49

46

50

53

89

45

51

90

Switches

INPUTS OUTPUTS

Internal Analog MIC

HP1

MIC IN

A A

Azalia
CODEC

IDT
92HD79B1

SPI

Flash ROM

4MB

30

SPI

LPC Bus

62

KBC

NUVOTON

NPCE781BA0DX

SATA x 2

LPC debug port

SMBus

37

70

HDD

ODD

59

59

<Core Design>

<Core Design>

<Core Design>

2CH SPEAKER

Title

Title

Flash ROM

256kB

62

5

4

Touch
PAD

68

Int.
KB

68 25

Thermal

Main:G7922
Sec.EMC2102

3

Fan

39

58

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

Block Diagram

Block Diagram

Block Diagram

Berry

Berry

Berry

+1.5V_SUS
+5V_ALW

PCB LAYER

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

+1.5V_RUN

+3.3V_RUN+3.3V_ALW

L1:Top
L2:VCC
L3:Signal
L4:Signal
L5:GND
L6:Bottom

of

292Wednesday, February 10, 2010

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292Wednesday, February 10, 2010

of

292Wednesday, February 10, 2010

+5V_RUN

A00

A00

A00

39

5

4

3

2

1

D D

RT8208B

Adapter

+PWR_SRC TPS51116

+VGA_CORE

ISL62883

For Discrete

TPS51218

TPS51611

AO4407A

+1.0V_RUN_VGA

+0.75V_DDR_VTT+V_DDR_REF

APL5930KAI

+1.5V_SUS

Charger

+CPU_GFX_CORE

For UMA

+3.3V_RUN_VGA

For Discrete

+3.3V_ALW

APL5930KAI

+1.8V_RUN

For Discrete

PA102FMG

+3.3V_LAN

AO4468

+1.5V_RUN

+1.5V_RUN_CPU

Battery

BQ24745

+PBATT

+VCC_CORE

+1.05V_VTT

RT8205B

C C

+15V_ALW

+3.3V_RTC_LDO

SI2301CDS

+KBC_PWR

+5V_ALW2

+5V_ALW

UP7534BRA8

+5V_USB1

I/O Board USB Power CRT Board USB Power

AO4468

+5V_RUN

UP7534BRA8

+5V_USB2

AO4468

+3.3V_RUN

RT9198-33PBG

B B

APL5930KAI

SI3456BD

+3.3V_CRT_LDO

+1.8V_RUN_VGA

+LCDVDD

For Discrete

RTS5159

+3.3V_RUN_CARD

RTL8103T-VB

+1.2V_LOM

Power Shape

A A

5

4

Regulator LDO Switch

3

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Power Block Diagram

Power Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

2

Date: Sheet

Power Block Diagram

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

of

392Wednesday, February 10, 2010

of

392Wednesday, February 10, 2010

of

392Wednesday, February 10, 2010

1

A00

A00

A00

A

PCH SMBus Block Diagram

+3.3V_ALW

Θ

SRN2K2J-1-GP

SMBCLK

PCH_SMB_CLK

PCH_SMB_DATA

+3.3V_ALW

Θ

SRN2K2J-8-GP

Θ

Θ

1 1

SMBDATA

+3.3V_RUN

Θ

2N7002SPT

B

+3.3V_RUN

Θ

SRN2K2J-1-GP

PCH_SMBCLK

Θ

PCH_SMBDATA

Θ

DIMM 1

SCL

SDA

SMBus Address:A0

C

D

KBC SMBus Block Diagram

+5V_RUN

Θ

SRN10KJ-5-GP

PSDAT1

PSCLK1

TPDATA

TPCLK

+KBC_PWR

Θ

Θ

TPDATA

TPCLK

TouchPad Conn.

TPDATA

TPCLK

E

Θ

SML1CLK

SML1DATA

SML0CLK

SML0DATA

PCH

2 2

SDVO_CTRLCLK

SDVO_CTRLDATA

L_DDC_CLK

L_DDC_DATA

CRT_DDC_CLK

CRT_DDC_DATA

KBC_SCL1

KBC_SDA1

SML0_CLK

SML0_DATA

+3.3V_RUN

Θ

SRN2K2J-1-GP

UMA

PCH_HDMI_CLK

PCH_HDMI_DATA

SRN2K2J-1-GP

UMA

LDDC_CLK_PCH

LDDC_DATA_PCH

PCH_CRT_DDCCLK

PCH_CRT_DDCDATA

To KBC

Level
Shift

+3.3V_RUN

Θ

UMA

SRN0J-6-GP

2N7002DW-1-GP

PCH_HDMI_CLK

PCH_HDMI_DATA

UMA

+3.3V_RUN_VGA

Θ

SRN2K2J-1-GP

+3.3V_ALW

Θ

SRN2K2J-1-GP

XDP

Θ

Θ

Θ

Θ

Θ

PCH_SMBCLK

Θ

PCH_SMBDATA

PCH_SMBCLK

PCH_SMBDATA

PCH_SMBCLK

PCH_SMBDATA

PCH_SMBCLK

PCH_SMBDATA

DIMM 2

SCL

SDA

SMBus Address:A4

Clock
Generator

SCLK

SDATA

SMBus address:D2

Minicard
WLAN

SMB_CLK

SMB_DATA

Minicard
W-WAN

SMB_CLK

SMB_DATA

KBC

NPCE781BA0DX

GPIO73/SCL2

GPIO74/SDA2

SCL1

SDA1

BAT_SCL

BAT_SDA

KBC_SCL1

KBC_SDA1

SRN4K7J-8-GP

SRN100J-3-GP

PBAT_SMBCLK1

PBAT_SMBDAT1

2N7002DW-1-GP

Battery Conn.

CLK_SMB

SMBus address:16

DAT_SMB

BQ24745

SCL

SDA

SMBus address:12

+3.3V_RUN

Θ

+3.3V_RUN

Θ

Θ

Θ

SRN4K7J-8-GP

THERM_SCL

THERM_SDA

Thermal

SCL

SMBus address:7A

SDA

DIS

3 3

4 4

DDC1CLK

DDC1DATA

DDC2CLK

DDC2DATA

VGA

IFPC_AUX_I2CW_SCL

IFPC_AUX_I2C_SDA#

A

VGA_CRT_DDCCLK

VGA_CRT_DDCDATA

+3.3V_RUN_VGA

SRN2K2J-1-GP

DIS

GPU_HDMI_CLK

GPU_HDMI_DATA

Θ

TSCBTD3305CPWR

+5V_RUN

+5V_RUN

Θ

SRN2K2J-1-GP

B

LCD CONN

+3.3V_RUN

UMA

SRN0J-6-GP

UMA

HDMI CONN

Θ

SRN2K2J-1-GP

SRN0J-6-GP

DIS

2N7002DW-1-GP

UMA

+3.3V_RUN

Θ

+5V_RUN

Θ

SRN2K2J-1-GP

CRT_DDCCLK_CON

CRT_DDCDATA_CON

C

CRT CONN

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A2

A2

A2

Berry

Berry

Berry

Date: Sheet

Date: Sheet

D

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

SMBUS Block Diagram

SMBUS Block Diagram

SMBUS Block Diagram

492Wednesday, Feb ruary 10, 2010

492Wednesday, Feb ruary 10, 2010

E

492Wednesday, Feb ruary 10, 2010

A00

A00

A00

of

of

of

A

B

C

D

E

Thermal Block Diagram

1 1

Audio Block Diagram

SPKR_PORT_D_L-

SPKR_PORT_D_R+

SPEAKER

Codec

DP1

EMC2102_DP1

SC470P50V3JN-2GP

2 2

DN1

EMC2102_DN1

SC470P50V3JN-2GP

MMBT3904-3-GP

Place near CPU

Thermal

PWM CORE

92HD79B1

HP1_PORT_B_L

HP1_PORT_B_R

HP

OUT

G7922R61U

DP2

VGA_THERMDA

DN2

VGA_THERMDC

Place near GPU(DISCRETE only).

3 3

THRMDA

VGA

THRMDC

MMBT3904-3-GP

System Sensor(UMA only)

HP0_PORT_A_L

HP0_PORT_A_R

VREFOUT_A_OR_F

DMIC_CLK/GPIO1

DMIC0/GPIO2

MIC

IN

DP3

EMC2102_DP3

SC470P50V3JN-2GP

DN3

EMC2102_DN3

Put under CPU(T8 HW shutdown)

4 4

A

B

MMBT3904-3-GP

PORTC_L

PORTC_R

VREFOUT_C

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

C

D

Date: Sheet of

Analog
MIC

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Thermal/Audio Block Diagram

Thermal/Audio Block Diagram

Thermal/Audio Block Diagram

Berry

Berry

Berry

592Wednesday, February 10, 2010

592Wednesday, February 10, 2010

592Wednesday, February 10, 2010

E

A00

A00

A00

A

B

C

D

E

Calpella Schematic Checklist Rev.0_7

Name Schematics Notes

SPKR

4 4

INIT3_3V# Weak internal pull-down. Do not pull high.

GNT3#/
GPIO55

INTVRMEN

GNT0#,
GNT1#/GPIO51

GNT2#/
GPIO53

GPIO33

3 3

SPI_MOSI

NV_ALE

NC_CLE Weak internal pull-up. Do not pull low.

HAD_DOCK_EN#
/GPIO[33]

HDA_SDO Weak internal pull-down. Do not pull high.

HDA_SYNC

GPIO15

GPIO8

GPIO27

2 2

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Connect to Vcc3_3 with 8.2-kȍ

No Reboot Mode with TCO Disabled:

- 10-kȍ weak pull-up resistor.

Internal pull-up.

Default Mode:

(Connect to ground with 4.7-kȍ weak

Low (0) = Top Block Swap Mode

pull-down resistor).

High (1) = Integrated VRM is enabled
Low (0) = Integrated VRM is disabled

Left both GNT0# and GNT1# floating. No pull up

Default (SPI):

required.

Connect GNT1# to ground with 1-kȍ pull-down

Boot from PCI:

resistor. Leave GNT0# Floating.

Connect both GNT0# and GNT1# to ground with 1-kȍ

Boot from LPC:

pull-down resistor.

Default - Internal pull-up.

= Configures DMI for ESI compatible operation (for servers

Low (0)

only. Not for mobile/desktops).

Do not pull low.

Default:

Connect to ground with 1-kȍ

Disable ME in Manufacturing Mode:

pull-down resistor.

Connect to Vcc3_3 with 8.2-kȍ weak pull-up resistor.

Enable iTPM:

Left floating, no pull-down required.

Disable iTPM:

Connect to Vcc3_3 with 8.2-kȍ weak pull-up

Enable Danbury:

resistor.
Connect to ground with 4.7-kȍ weak pull-down

Disable Danbury:

resistor.

Flash Descriptor Security will be overridden.

Low (0):

Flash Descriptor Security will be in effect.

High (1) :

Weak internal pull-down. Do not pull high.

Weak internal pull-down. Do not pull high.

Weak internal pull-up. Do not pull low.

Default = Do not connect (floating)

High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.

Pin Name

CFG[4] Disabled - No Physical Display Port attached to

CFG[3]

CFG[0]

CFG[7]

Strap Description Configuration (Default value for each bit is

DisplayPort
Presence

PCI-Express Static
Lane Reversal

PCI-Express
Configuration
Select

Reserved ­Temporarily used
for early
Clarksfield
samples.

1 unless specified otherwise)

1:Embedded

Embedded DisplayPort.

Enabled - An external Display Port device is

0:

connected to the Embedded Display Port.

Normal Operation.

1:

Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Single PCI-Express Graphics

1:

Bifurcation enabled

0:

-

Clarksfield (only for early samples pre-ES1)

Connect to GND with 3.01K Ohm/5% resistor

Only temporary for early CFD samples

Note:

(rPGA/BGA) [For details please refer to the WW33
MoW and sighting report].
For a common motherboard design (for AUB and CFD),
the pull-down resistor should be used. Does not
impact AUB functionality.

Calpella Schematic Checklist Rev.0_7

Default
Value

1

1

1

0

Processor StrappingPCH Strapping

USB TablePCIE Routing

USB

LANE1 RESERVED

LANE2

MiniCard WLAN

LANE3 LAN

LANE4 W-WAN

LANE5

LANE6

1 1

LANE7

LANE8

RESERVED

RESERVED

H55/HM55 no support

H55/HM55 no support

Pair

0

1

2

3

4

5

6

7

8

9

10

11

12

13

Device

USB2 (CRT Board)

USB3 (CRT Board)

WLAN (I/O Board)

RESERVED

CARD READER

BLUETOOTH

HM55 no support

HM55 no support

USB1 (I/O Board)

USB0 (I/O Board ESATA)

RESERVED

W-WAN (I/O Board)

RESERVED

CAMERA

SATA Table

SATA

Pair

0

1

2

3

4

5

Device

HDD

ODD

HM55 no support

HM55 no support

ESATA

RESERVED

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

Table of Content

Table of Content

692Wednesday, February 10, 2010

692Wednesday, February 10, 2010

692Wednesday, February 10, 2010

of

of

of

A00

A00

A00

5

SSID = CLOCK

4

3

2

1

1 2

12

C702

C702

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

CLKIN_DMI#23

CLKIN_DMI23

X02-20091222

R701

R701

0R0603-PAD

0R0603-PAD

12

12

C701

C701

C703

DY

DY

+3.3V_RUN

C703

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

R703

R703

1 2

2K2R2J-2-GP

2K2R2J-2-GP

X02-20091222

RN702

RN702

2 3
1

4

0R4P2R-PAD

0R4P2R-PAD

RN

RN

CLK_CPU_BCLK#23

CLK_CPU_BCLK23

FSC 0 1

SPEED

133MHz

(Default)

12

C704

C704

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

CPU_STOP#

CLK_DREF#23

CLK_DREF23

CLKIN_DMI#_C
CLKIN_DMI_C

RN703

RN703

2 3
1

4

0R4P2R-PAD

0R4P2R-PAD

RN

RN

100MHz

12

C705

C705

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

CLK_PCIE_SATA#_C
CLK_PCIE_SATA_C

+3.3V_RUN_SL585

12

C706

C706

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

U701

U701

4

DOT_96#

3

DOT_96

14

SRC_2#

13

SRC_2

11

SRC_1/SATA#

10

SRC_1/SATA

22

CPU_0#

23

CPU_0

19

CPU_1#

20

CPU_1

SLG8SP585VTR-GP

SLG8SP585VTR-GP

SC12P50V2JN-3GP

SC12P50V2JN-3GP

12

C707

C707

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

+3.3V_RUN_SL585 +1.05V_RUN_SL585_IO

1

VDD_REF

VDD_DOT

VSS_SRC

VSS_CPU

12

X701

X701

1 2

5

VDD_27

VSS_DOT

2

15

18

VDD_SRC_IO

VDD_CPU_IO

CKPWRGD/PD#

REF_0/CPU_SEL

VSS_278VSS_SATA

9

12

27MHZ

27MHZ_SS

CPU_STOP#

XTAL_IN

XTAL_OUT

SDA
SCL

C713

C713
SC12P50V2JN-3GP

SC12P50V2JN-3GP

17

24

29

VDD_SRC

VDD_CPU

VSS_REF

GND

21

26

33

CLK_XTAL_IN CLK_XTAL_OUT

X-14D31818M-37GP

X-14D31818M-37GP

12

82.30005.901

82.30005.901

C712

C712

+1.05V_VTT

C708

C708

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

DY

DY

12

X02-20091222

R702

R702

1 2

0R0603-PAD

0R0603-PAD

12

C709

C709

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

x01 change tolerant 20091117

X01-20091116

DIS

CLK_VGA_27M_NSS_R

6

CLK_VGA_27M_SS_R

7

16
25
30

28
27

31
32

CPU_STOP#
CK_PWRGD
FSC

CLK_XTAL_IN
CLK_XTAL_OUT

+1.05V_VTT

R706

R706
4K7R2J-2-GP

4K7R2J-2-GP

DY

DY

1 2

R707

R707
10KR2J-3-GP

10KR2J-3-GP

1 2

DIS

1 2
1 2

DY

DY

R704

R704

12

33R2J-2-GP

33R2J-2-GP

12

DY

DY

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

PCH_SMBDATA 18,19,23,76

PCH_SMBCLK 18,19,23,76

FSC

33R2J-2-GPR708

33R2J-2-GPR708
33R2J-2-GPR709

33R2J-2-GPR709

EC703

EC703

+1.05V_RUN_SL585_IO

12

C710

C710

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

CLK_PCH_14M 23

12

C711

C711

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

DY

DY

CK_PWRGD

VR_CLKEN#47

CLK_VGA_27M_SS 82

EC701

EC701
SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

+3.3V_RUN_SL585

R705

R705

10KR2J-3-GP

10KR2J-3-GP

.

.

G

.

.

.

.
.

.
.

.

1 2

D

12

DY

DY

Q701

Q701
2N7002E-1-GP

2N7002E-1-GP

S

CLK_VGA_27M_NSS 82

EC702

EC702
SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

+3.3V_RUN

D D

DY

DY

x01 change tolerant 20091117

C C

CLK_PCIE_SATA#23

CLK_PCIE_SATA23

B B

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Clock Generator SLG8SP585

Clock Generator SLG8SP585

Clock Generator SLG8SP585

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

of

792Monday, March 29, 2010

of

792Monday, March 29, 2010

of

792Monday, March 29, 2010

1

A00

A00

A00

5

4

3

2

1

SSID = CPU

D D

1 OF 9

CPU1A

CPU1A

678

RN801

RN801

SRN1KJ-4-GP

SRN1KJ-4-GP

4 5

A24

DMI_RX#0

C23

DMI_RX#1

B22

DMI_RX#2

A21

DMI_RX#3

B24

DMI_RX0

D23

DMI_RX1

B23

DMI_RX2

A22

DMI_RX3

D24

DMI_TX#0

G24

DMI_TX#1

F23

DMI_TX#2

H23

DMI_TX#3

D25

DMI_TX0

F24

DMI_TX1

E23

DMI_TX2

G23

DMI_TX3

E22

FDI_TX#0

D21

FDI_TX#1

D19

FDI_TX#2

D18

FDI_TX#3

G21

FDI_TX#4

E19

FDI_TX#5

F21

FDI_TX#6

G18

FDI_TX#7

D22

FDI_TX0

C21

FDI_TX1

D20

FDI_TX2

C18

FDI_TX3

G22

FDI_TX4

E20

FDI_TX5

F20

FDI_TX6

G19

FDI_TX7

F17

FDI_FSYNC0

E17

FDI_FSYNC1

C17

FDI_INT

F18

FDI_LSYNC0

D17

FDI_LSYNC1

CLARKUNF

CLARKUNF

62.10055.341

62.10055.341

CLARKSFIELD

CLARKSFIELD

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

DMI_PTX_CRXN022
DMI_PTX_CRXN122
DMI_PTX_CRXN222
DMI_PTX_CRXN322

DMI_PTX_CRXP022
DMI_PTX_CRXP122
DMI_PTX_CRXP222
DMI_PTX_CRXP322

DMI_CTX_PRXN022
DMI_CTX_PRXN122
DMI_CTX_PRXN222
DMI_CTX_PRXN322

DMI_CTX_PRXP022
DMI_CTX_PRXP122
DMI_CTX_PRXP222
DMI_CTX_PRXP322

C C

B B

FDI_TXN022
FDI_TXN122
FDI_TXN222
FDI_TXN322
FDI_TXN422
FDI_TXN522
FDI_TXN622
FDI_TXN722

FDI_TXP022
FDI_TXP122
FDI_TXP222
FDI_TXP322
FDI_TXP422
FDI_TXP522
FDI_TXP622
FDI_TXP722

FDI_FSYNC022
FDI_FSYNC122

FDI_INT22

FDI_LSYNC022
FDI_LSYNC122

12

R804

R804

1KR2J-1-GP

1KR2J-1-GP

DIS

DIS

DIS

DIS

123

SEC. 62.10053.561

A A

1 OF 9

PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9

PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8

PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15

PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15

B26
A26
B27
A25

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

DMI

DMI

PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15

Intel(R) FDI

Intel(R) FDI

PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15

PEG_IRCOMP_R

EXP_RBIAS

PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0

PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0

PEG_C_TXN15
PEG_C_TXN14
PEG_C_TXN13
PEG_C_TXN12
PEG_C_TXN11
PEG_C_TXN10
PEG_C_TXN9
PEG_C_TXN8
PEG_C_TXN7
PEG_C_TXN6
PEG_C_TXN5
PEG_C_TXN4
PEG_C_TXN3
PEG_C_TXN2
PEG_C_TXN1
PEG_C_TXN0

PEG_C_TXP15
PEG_C_TXP14
PEG_C_TXP13
PEG_C_TXP12
PEG_C_TXP11
PEG_C_TXP10
PEG_C_TXP9
PEG_C_TXP8
PEG_C_TXP7
PEG_C_TXP6
PEG_C_TXP5
PEG_C_TXP4
PEG_C_TXP3
PEG_C_TXP2
PEG_C_TXP1
PEG_C_TXP0

R801 49D9R2F-GPR801 49D9R2F-GP

1 2

R802 750R2F-GPR802 750R2F-GP

1 2

PEG_RXN[0..15]

PEG_RXP[0..15]

C816 SCD1U10V2KX-5GP

C816 SCD1U10V2KX-5GP

1 2

DIS

DIS

C815 SCD1U10V2KX-5GP

C815 SCD1U10V2KX-5GP

1 2

DIS

DIS

C814 SCD1U10V2KX-5GP

C814 SCD1U10V2KX-5GP

1 2

DIS

DIS

C813 SCD1U10V2KX-5GP

C813 SCD1U10V2KX-5GP

1 2

DIS

DIS

C812 SCD1U10V2KX-5GP

C812 SCD1U10V2KX-5GP

1 2

DIS

DIS

C811 SCD1U10V2KX-5GP

C811 SCD1U10V2KX-5GP

1 2

DIS

DIS

C810 SCD1U10V2KX-5GP

C810 SCD1U10V2KX-5GP

1 2

DIS

DIS

C809 SCD1U10V2KX-5GP

C809 SCD1U10V2KX-5GP

1 2

DIS

DIS

C808 SCD1U10V2KX-5GP

C808 SCD1U10V2KX-5GP

1 2

DIS

DIS

C807 SCD1U10V2KX-5GP

C807 SCD1U10V2KX-5GP

1 2

DIS

DIS

C806 SCD1U10V2KX-5GP

C806 SCD1U10V2KX-5GP

1 2

DIS

DIS

C805 SCD1U10V2KX-5GP

C805 SCD1U10V2KX-5GP

1 2

DIS

DIS

C804 SCD1U10V2KX-5GP

C804 SCD1U10V2KX-5GP

1 2

DIS

DIS

C803 SCD1U10V2KX-5GP

C803 SCD1U10V2KX-5GP

1 2

DIS

DIS

C802 SCD1U10V2KX-5GP

C802 SCD1U10V2KX-5GP

1 2

DIS

DIS

C801 SCD1U10V2KX-5GP

C801 SCD1U10V2KX-5GP

1 2

DIS

DIS

C832 SCD1U10V2KX-5GP

C832 SCD1U10V2KX-5GP

1 2

DIS

DIS

C831 SCD1U10V2KX-5GP

C831 SCD1U10V2KX-5GP

1 2

DIS

DIS

C830 SCD1U10V2KX-5GP

C830 SCD1U10V2KX-5GP

1 2

DIS

DIS

C829 SCD1U10V2KX-5GP

C829 SCD1U10V2KX-5GP

1 2

DIS

DIS

C828 SCD1U10V2KX-5GP

C828 SCD1U10V2KX-5GP

1 2

DIS

DIS

C827 SCD1U10V2KX-5GP

C827 SCD1U10V2KX-5GP

1 2

DIS

DIS

C826 SCD1U10V2KX-5GP

C826 SCD1U10V2KX-5GP

1 2

DIS

DIS

C825 SCD1U10V2KX-5GP

C825 SCD1U10V2KX-5GP

1 2

DIS

DIS

C824 SCD1U10V2KX-5GP

C824 SCD1U10V2KX-5GP

1 2

DIS

DIS

C823 SCD1U10V2KX-5GP

C823 SCD1U10V2KX-5GP

1 2

DIS

DIS

C822 SCD1U10V2KX-5GP

C822 SCD1U10V2KX-5GP

1 2

DIS

DIS

C821 SCD1U10V2KX-5GP

C821 SCD1U10V2KX-5GP

1 2

DIS

DIS

C820 SCD1U10V2KX-5GP

C820 SCD1U10V2KX-5GP

1 2

DIS

DIS

C819 SCD1U10V2KX-5GP

C819 SCD1U10V2KX-5GP

1 2

DIS

DIS

C818 SCD1U10V2KX-5GP

C818 SCD1U10V2KX-5GP

1 2

DIS

DIS

C817 SCD1U10V2KX-5GP

C817 SCD1U10V2KX-5GP

1 2

DIS

DIS

x01 change tolerant 20091117

PEG_RXN[0..15] 80

PEG_RXP[0..15] 80

PEG_TXN[0..15]

PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0

PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

PEG_TXP[0..15]

CPU (PCIE/DMI/FDI)

CPU (PCIE/DMI/FDI)

CPU (PCIE/DMI/FDI)

Berry

Berry

Berry

PEG_TXN[0..15] 80

PEG_TXP[0..15] 80

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

892Monday, March 29, 2010

of

892Monday, March 29, 2010

of

892Monday, March 29, 2010

A00

A00

A00

5

+1.05V_VTT

D D

X01 20091121
VTTPWRGOOD signal must be clean
and close to CPU

For EMI

C C

B B

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

x01 change tolerant 20091117

Processor Pullups

DY

DY

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R924

R924
1K1R2F-GP

1K1R2F-GP

R926

R926

DY

DY

H_PWRGD

H_PWRGD_XDP

PM_DRAM_PWRGD22

1 2

12

EC905

EC905

H_THERMTRIP#25,37,42,82

H_VTTPWRGD49

H_CATERR#

H_PROCHOT#

H_CPURST#

H_PECI25

H_PM_SYNC22

H_PWRGD25,42

EC904

EC904

1 2

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+1.5V_RUN_CPU+1.5V_SUS

12

DY

DY

X01 20091112

SML0_DATA23

R901 49D9R 2F-GPR901 49D9R 2F-GP

1 2

R907 68R2-G PR907 68R2-GP

1 2

R906 68R2-G P

R906 68R2-G P

1 2

DY

DY

XDP_RST#_R
VCCPWRGOOD
VDDPWRGOOD_R
H_VTTPWRGD
PLT_RST#_R
XDP_DBRESET#

EC906

EC906

DY

DY

1 2

x01 change tolerant 20091117

12

DY

DY

VDDPWRGOOD_R

3KR2F-GP

3KR2F-GP

+1.05V_VTT

PM_PWRBTN #_R22

12

C902

C902

DY

DY

DY

DY

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R925

R925
1K1R2F-GP

1K1R2F-GP

R935 1KR2J-1-G P

R935 1KR2J-1-G P
R937 0R2J-2-G P

R937 0R2J-2-G P

R938 0R2J-2-G P

R938 0R2J-2-G P

SML0_CLK23

Processor Compensation Signals

R902 20R2F- GPR902 20R2F- GP

R903 20R2F- GPR903 20R2F- GP

R904 49D9R 2F-GPR904 49D9R 2F-GP

R905 49D9R 2F-GPR905 49D9R 2F-GP

H_PROCHOT#47

X02-20091222

R910

R910

1 2

0R0402-PAD

0R0402-PAD

R912

R912

1 2

0R0402-PAD

0R0402-PAD

PLT_RST#21,37,70,76,78,80

EC902

EC902

EC901

EC903

EC903

1 2

1 2
1 2

1 2

EC901

DY

DY

DY

DY

1 2

1 2

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

DY
DY

DY
DY

DY

1 2

1 2

1 2

1 2

TP901TPAD14-GP TP901TPAD14-GP

1

H_PWRGD_XDP

1 2

R917

R917

1K54R2F-GP

1K54R2F-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

XDP_PREQ#
XDP_PRDY#

XDP_OBS0
XDP_OBS1

XDP_OBS2
XDP_OBS3

XDP_OBS4
XDP_OBS5

XDP_OBS6
XDP_OBS7

H_CPUPWRGD_XDP
PM_PWRBTN #_XDP

PCIE_CLK_XDP_P

XDP_TCLK

SKTOCC#_R

H_CATERR#

H_CPURST#

VCCPWRGOOD

VDDPWRGOOD_R

H_COMP3

H_COMP2

H_COMP1

H_COMP0

PLT_RST#_R

12

R918

R918
750R2F-GP

750R2F-GP

XDP1

XDP1

1 2

3 4
5 6
7 8

9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30

DY

DY

31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60

PAD-60P-GP

PAD-60P-GP

CPU1B

CPU1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

CLARKUNF

CLARKUNF

A00-20100226

0D75V_EN50

NP1
61

62

63
64
NP2

4

SSID = CPU

MISC THERMAL

MISC THERMAL

CLOCKS

CLOCKS

CLARKSFIELD

CLARKSFIELD

DDR3

DDR3

PWR MANAGEMENT

PWR MANAGEMENT

JTAG & BPM

JTAG & BPM

U901

U901

1

A

VCC

2

B
GND3Y

NL17SZ08DFT2G-GP

NL17SZ08DFT2G-GP

VDDPWRGOOD_R

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

PM_EXT_TS#0
PM_EXT_TS#1

MISC

MISC

+3.3V_RUN

5

VTT_PWRGD_C

4

2 OF 9

2 OF 9

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

PRDY#
PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

12

12

+1.05V_VTT

TCK
TMS

TDO

x01 change tolerant 20091117

12

C901

C901

SCD1U10V2KX-5GP

BCLK_ITP_P
BCLK_ITP_N

R939 1KR2J-1-GP

R939 1KR2J-1-GP

XDP_TRST#
XDP_TDI
XDP_TMS

XDP_RST#_R

SCD1U10V2KX-5GP

1 2

DY

DY

DY

DY

H_CPURST#XDP_RST#_R

1 2

DY

DY

R940 0R2J-2-GP

R940 0R2J-2-GP

12

TDI

R927

R927
1K54R2F-GP

1K54R2F-GP

R941

R941

1 2

1K54R2F-GP

1K54R2F-GP

R930

R930
750R2F-GP

750R2F-GP

R936

R936
51R2J-2-GP

51R2J-2-GP

XDP_TDO

BCLK_CPU_C_P

A16

BCLK_CPU_C_N

B16

BCLK_ITP_P

AR30

BCLK_ITP_N

AT30

CLK_EXP_C_P

E16

CLK_EXP_C_N

D16

A18
A17

F6

AL1
AM1
AN1

AN15
AP15

AT28
AP27

AN28
AP28
AT27

AT29
AR27
AR29
AP29

AN25

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

DY

DY

PLT_RST# 21,37,70,76,78,80

X02-20091222

RN901

RN901

1
2 3

0R4P2R-PAD

0R4P2R-PAD

RN902

RN902

1
2 3

0R4P2R-PAD

0R4P2R-PAD

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

PM_EXTTS#0_C
PM_EXTTS#1_C

XDP_PRDY#
XDP_PREQ#

XDP_TCLK
XDP_TMS
XDP_TRST#

XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M

H_DBR#_R

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

VDDPWRGOOD_KBC 37

XDP_DBRESET# 22,23

RN

RN

4

RN

RN

4

X03-20100118

X02-20091222

R911

R911

1 2

0R0402-PAD

0R0402-PAD

3

BCLK_CPU_P 25
BCLK_CPU_N 25

CLK_EXP_P 23
CLK_EXP_N 23

SM_DRAMRST#

PM_EXTTS#0_C 53

RN903

RN903

4

RN

RN

SRN10KJ-5-GP

SRN10KJ-5-GP

1

4

2 3

RN904

RN904

0R4P2R-PAD

0R4P2R-PAD

XDP_DBRESET#

SM_DRAMRST#

X02-20091224

+1.05V_VTT
1
23

+1.5V_RUN_CPU

DY

DY

XDP_TDI_R

XDP_TDO_M

XDP_TDI_M

XDP_TDO_R

Scan Chain
(Default)
CPU Only

GMCH Only

S3_RST_GATE# 25

X01 20091117

Q901

Q901

G

.

.

...

.....

D

S

2N7002E-1-GP

2N7002E-1-GP

DY

DY

1 2

R909 0R2J-2-GP

R909 0R2J-2-GP

x01 change tolerant 20091117

PM_EXTTS#0 18
PM_EXTTS#1 19

12

R915

R915
1KR2J-1-GP

1KR2J-1-GP

DDR3 Compensation Signals

SM_RCOMP_0

SM_RCOMP_1

SM_RCOMP_2

XDP_TMS

XDP_TDI_R

XDP_PREQ#

XDP_TCLK

X01 20091111

12

R921

R921
100KR2J-1-GP

100KR2J-1-GP

1 2

DY

DY

R928 0R2J-2-GP

R928 0R2J-2-GP

1 2

DY

DY

R929 0R2J-2-GP

R929 0R2J-2-GP

12

R931

R931
0R0402-PAD

0R0402-PAD

1 2

DY

DY

R933 0R2J-2-GP

R933 0R2J-2-GP

R934

R934

1 2

0R0402-PAD

0R0402-PAD

X02-20091222

Stuff --> R928, R931, R934
No Stuff --> R929, R933
Stuff --> R928, R929
No Stuff --> R931, R934, R933
Stuff --> R933, R934
No Stuff --> R928, R929, R931

+1.5V_SUS

12

R908

R908
1KR2J-1-GP

1KR2J-1-GP

DDR3_DRAMR ST# 18,19

12

C903

C903
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R913 100R2F-L1-G P-UR913 100R2F-L1-G P-U

1 2

R914 24D9R2F- L-GPR914 24D9R2F- L-GP

1 2

R916 130R2F-1-G PR916 130R2F-1-GP

1 2

1 2

DY

DY

R919 51R2J-2-G P

R919 51R2J-2-G P

1 2

DY

DY

R920 51R2J-2-G P

R920 51R2J-2-G P

1 2

DY

DY

R922 51R2J-2-G P

R922 51R2J-2-G P

1 2

DY

DY

R923 51R2J-2-G P

R923 51R2J-2-G P

XDP_TDI

XDP_TDO

JTAG MAPPING

XDP_TRST#

+1.05V_VTT

12

51R2J-2-GP

51R2J-2-GP

2

R932

R932

1

A00-20100208

A A

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Berry

Berry

Berry

Taipei Hsien 221, Taiw an, R.O.C.

1

A00

A00

A00

of

992Monday, March 29, 2010

of

992Monday, March 29, 2010

of

992Monday, March 29, 2010

Title

Title

Title

CPU (THERMAL/CLOCK/PM )

CPU (THERMAL/CLOCK/PM )

CPU (THERMAL/CLOCK/PM )

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

5

SSID = CPU

CPU1C

CPU1C

4

3 OF 9

3 OF 9

3

CPU1D

CPU1D

2

4 OF 9

4 OF 9

1

W8

AA6

SA_CK0

AA7

M_A_DQ[63..0]18

D D

C C

B B

M_A_DQ[63..0]

M_A_BS018
M_A_BS118
M_A_BS218

M_A_CAS#18
M_A_RAS#18
M_A_WE#18

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

C10

D10

H10

G10

AH5
AF5
AK6
AK7
AF6
AG5

AJ10

AL10
AK12

AK8

AK11

AN8

AM10

AR11
AL11

AM9

AN9
AT11
AP12

AM12

AN12

AM13

AT14
AT12
AL13
AR14
AP14

AC3

AB2

AE1

AB3

AE9

A10

B10

E10

F10

J10

AJ7
AJ6

AJ9

AL7

AL8

SA_DQ0
SA_DQ1

C7

SA_DQ2

A7

SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6

A8

SA_DQ7

D8

SA_DQ8
SA_DQ9

E6

SA_DQ10

F7

SA_DQ11

E9

SA_DQ12

B7

SA_DQ13

E7

SA_DQ14

C6

SA_DQ15
SA_DQ16

G8

SA_DQ17

K7

SA_DQ18

J8

SA_DQ19

G7

SA_DQ20
SA_DQ21

J7

SA_DQ22
SA_DQ23

L7

SA_DQ24

M6

SA_DQ25

M8

SA_DQ26

L9

SA_DQ27

L6

SA_DQ28

K8

SA_DQ29

N8

SA_DQ30

P9

SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SA_BS0
SA_BS1

U7

SA_BS2

SA_CAS#
SA_RAS#
SA_WE#

SA_CK#0

P7

SA_CKE0

Y6

SA_CK1

Y5

SA_CK#1

P6

SA_CKE1

AE2

SA_CS#0

AE8

SA_CS#1

CLARKSFIELD

CLARKSFIELD

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_ODT0
SA_ODT1

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_CLK_DDR0 18
M_CLK_DDR#0 18
M_CKE0 18

M_CLK_DDR1 18
M_CLK_DDR#1 18
M_CKE1 18

M_CS#0 18
M_CS#1 18

M_ODT0 18
M_ODT1 18

M_B_DQ[63..0]19

M_A_DM[7..0] 18

M_A_DQS#[7..0] 18

M_A_DQS[7..0] 18

M_A_A[15..0] 18

M_B_DQ[63..0]

M_B_BS019
M_B_BS119
M_B_BS219

M_B_CAS#19
M_B_RAS#19
M_B_WE#19

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

AF3
AG1

AK1
AG4
AG3

AH4
AK3

AK4
AM6
AN2

AK5

AK2
AM4
AM3

AP3
AN5

AT4
AN6
AN4
AN3

AT5

AT6
AN7

AP6

AP8

AT9

AT7

AP9

AR10

AT10

AB1

AC5

AC6

B5

SB_DQ0

A5

SB_DQ1

C3

SB_DQ2

B3

SB_DQ3

E4

SB_DQ4

A6

SB_DQ5

A4

SB_DQ6

C4

SB_DQ7

D1

SB_DQ8

D2

SB_DQ9

F2

SB_DQ10

F1

SB_DQ11

C2

SB_DQ12

F5

SB_DQ13

F3

SB_DQ14

G4

SB_DQ15

H6

SB_DQ16

G2

SB_DQ17

J6

SB_DQ18

J3

SB_DQ19

G1

SB_DQ20

G5

SB_DQ21

J2

SB_DQ22

J1

SB_DQ23

J5

SB_DQ24

K2

SB_DQ25

L3

SB_DQ26

M1

SB_DQ27

K5

SB_DQ28

K4

SB_DQ29

M4

SB_DQ30

N5

SB_DQ31
SB_DQ32
SB_DQ33

AJ3

SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37

AJ4

SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

SB_BS0

W5

SB_BS1

R7

SB_BS2

SB_CAS#

Y7

SB_RAS#
SB_WE#

CLARKSFIELD

CLARKSFIELD

DDR SYSTEM MEMORY - B

DDR SYSTEM MEMORY - B

SB_CK0
SB_CK#0
SB_CKE0

SB_CK1
SB_CK#1
SB_CKE1

SB_CS#0
SB_CS#1

SB_ODT0
SB_ODT1

SB_DM0

SB_DM1

SB_DM2

SB_DM3

SB_DM4

SB_DM5

SB_DM6

SB_DM7

SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_MA0

SB_MA1

SB_MA2

SB_MA3

SB_MA4

SB_MA5

SB_MA6

SB_MA7

SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

W9
M3

V7
V6
M2

AB8
AD6

AC7
AD1

D4
E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_CLK_DDR2 19
M_CLK_DDR#2 19
M_CKE2 19

M_CLK_DDR3 19
M_CLK_DDR#3 19
M_CKE3 19

M_CS#2 19
M_CS#3 19

M_ODT2 19
M_ODT3 19

M_B_DM[7..0] 19

M_B_DQS#[7..0] 19

M_B_DQS[7..0] 19

M_B_A[15..0] 19

CLARKUNF

CLARKUNF

CLARKUNF

A A

5

4

3

CLARKUNF

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDR)

CPU (DDR)

CPU (DDR)

1

A00

A00

of

10 92Monday, March 29, 2010

of

10 92Monday, March 29, 2010

of

10 92Monday, March 29, 2010

A00

5

4

3

2

1

SSID = CPU

5 OF 9

CPU1E

CPU1E

D D

CFG0

CFG3

C C

CFG4

CFG7

B B

DIS

DIS

DY

DY

DY

DY

DY

DY

12

12

12

12

R1101

R1101
3KR2F-GP

3KR2F-GP

R1104

R1104
3KR2J-2-GP

3KR2J-2-GP

R1105

R1105
3KR2F-GP

3KR2F-GP

R1106

R1106
3KR2F-GP

3KR2F-GP

PCI-Express Configuration Select

1:Single PEG

CFG0

0:Bifurcation enabled

CFG3 - PCI-Express Static Lane Reversal

1 :Normal Operation

CFG3

0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...

CFG4 - Display Port Presence

1:Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port

CFG7(Reserved) - Temporarily used for early
Clarksfield samples.

CFG7 Clarksfield (only for early samples pre-ES1) -

Connect to GND with 3.01K Ohm/5% resistor.

Note: Only temporary for early CFD sample
(rPGA/BGA) [For details please refer to the
WW33 MoW and sighting report].
For a common M/B design (for AUB and CFD),
the pull-down resistor shouble be used. Does
not impact AUB functionality.

TP1101TPAD14-GP TP1101TPAD14-GP

1

TP1102TPAD14-GP TP1102TPAD14-GP

1

TP1103TPAD14-GP TP1103TPAD14-GP

1

TP1104TPAD14-GP TP1104TPAD14-GP

1

TP1105TPAD14-GP TP1105TPAD14-GP

1

TP1106TPAD14-GP TP1106TPAD14-GP

1

TP1107TPAD14-GP TP1107TPAD14-GP

1

TP1108TPAD14-GP TP1108TPAD14-GP

1

TP1109TPAD14-GP TP1109TPAD14-GP

1

TP1110TPAD14-GP TP1110TPAD14-GP

1

TP1111TPAD14-GP TP1111TPAD14-GP

1

TP1112TPAD14-GP TP1112TPAD14-GP

1

TP1113TPAD14-GP TP1113TPAD14-GP

1

TP1114TPAD14-GP TP1114TPAD14-GP

1

TP1115TPAD14-GP TP1115TPAD14-GP

1

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

AP25

AL25
AL24
AL22
AJ33

AM30
AM28
AP31

AL32

AL30
AM31
AN29
AM32
AK32
AK31
AK28

AJ28
AN30
AN32

AJ32

AJ29

AJ30
AK30

AG9
M27

L28
J17

H17
G25
G17

E31

E30

H16

B19

A19

A20

B20

U9
T9

AC9
AB9

J29
J28

RSVD#AP25
RSVD#AL25
RSVD#AL24
RSVD#AL22
RSVD#AJ33
RSVD#AG9
RSVD#M27
RSVD#L28
SA_DIMM_VREF
SB_DIMM_VREF
RSVD#G25
RSVD#G17
RSVD#E31
RSVD#E30

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
RSVD_TP_86

RSVD#B19
RSVD#A19

RSVD#A20
RSVD#B20

RSVD#U9
RSVD#T9

RSVD#AC9
RSVD#AB9

RSVD#J29
RSVD#J28

CLARKUNF

CLARKUNF

CLARKSFIELD

CLARKSFIELD

RESERVED

RESERVED

5 OF 9

RSVD#AJ13
RSVD#AJ12

RSVD#AH25
RSVD#AK26

RSVD#AL26

RSVD_NCTF_37

RSVD#AJ26
RSVD#AJ27

RSVD#AL28
RSVD#AL29
RSVD#AP30
RSVD#AP32
RSVD#AL27
RSVD#AT31
RSVD#AT32
RSVD#AP33
RSVD#AR33

RSVD#AR32

RSVD_TP#E15
RSVD_TP#F15

RSVD#D15

RSVD#C15
RSVD#AJ15
RSVD#AH15

SA_CK2
SA_CK#2
SA_CKE2
SA_CS#2

SA_ODT2

SA_CK3
SA_CK#3
SA_CKE3
SA_CS#3

SA_ODT3

SB_CK2
SB_CK#2

SB_CKE2

SB_CS#2

SB_ODT2

SB_CK3
SB_CK#3

SB_CKE3

SB_CS#3

SB_ODT3

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33

AR32

E15
F15
A2

KEY

D15
C15
AJ15
AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

VSS

VSS (AP34) can be left NC is
CRB implementation; EDS/DG
recommendation to GND.

R1107

RSVD_VSS

R1107

1 2

0R0402-PAD

0R0402-PAD

X02-20091224

A A

5

4

3

2

<Core Design >

<Core Design >

<Core Design >

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (RESERVED)

CPU (RESERVED)

CPU (RESERVED)

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

11 92Wednesday, February 10, 2010

11 92Wednesday, February 10, 2010

11 92Wednesday, February 10, 2010

1

A00

A00

A00

SSID = CPU

5

4

CPU1F

CPU1F

3

6 OF 9

6 OF 9

2

1

+VCC_CORE

PROCESSOR CORE POWER

+VCC_CORE

D D

x01 change tolerant 20091117

C1206

C1206

C1207

C1201

C1201

C1205

C1205

12

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1207

12

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

C1215

C1215

C1208

C1208

12

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

48A

x01 change tolerant 20091117

C1220

C1220

C1219

C1219

12

12

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

C1226

C1226

12

12

C1225

C1225

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

C C

C1222

C1222

C1223

C1223

C1224

C1221

C1221

12

12

DY

DY

12

C1227

C1227

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1228

C1228

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

DY

DY

DY

C1224

12

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

x01 change tolerant 20091117

C1229

C1229

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1231

C1231

C1230

C1230

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

C1232

C1232

12

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5MX-3GP

DY

DY

SC10U6D3V5MX-3GP

DY

DY

x01 change tolerant 20091117

C1235

C1235

C1236

C1236

C1237

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

12

C1243

C1243

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

B B

C1237

12

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

C1238

C1238

12

C1239

C1239

C1240

SC10U6D3V5KX-1GP

DY

DY

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1240

12

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP

C1241

C1241

12

C1242

C1242

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

CLARKSFIELD

CLARKSFIELD

1.1V RAIL POWER

1.1V RAIL POWER

CPU CORE SUPPLY

CPU CORE SUPPLY

PROC_DPRSLPVR

CPU VIDS

CPU VIDS

POWER

POWER

VTT_SELECT

VCC_SENSE

VSS_SENSE_VTT

SENSE LINES

SENSE LINES

VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0

VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0

PSI#

ISENSE

VSS_SENSE

VTT_SENSE

VID
VID
VID
VID
VID
VID
VID

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

H_VID0

AK35

H_VID1

AK33

H_VID2

AK34

H_VID3

AL35

H_VID4

AL33

H_VID5

AM33

H_VID6

AM35
AM34

G15

AN35

AJ34
AJ35

B15

TP_VSS_SENSE_VTT

A15

x01 change tolerant 20091117

H_VTTVID1

H_VTTVID1 = Low, 1.1V
H_VTTVID1 = High, 1.05V

x01 change tolerant 20091117

12

C1209

C1209

12

C1202

C1202

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

DY

DY

12

C1210

C1210

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

DY

DY

x01 change tolerant 20091117

12

12

C1233

C1233

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

PSI# 47

H_VID[6..0] 47

PM_DPRSLPVR 4 7

TP1201 TPAD14-GPTP1201 TPAD14-GP

1

IMVP_IMON 47

VTT_SENSE 49

1

TP1202

TP1202

TPAD14-GP

TPAD14-GP

C1234

C1234

C1211

C1211

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1216

C1216

12

12

C1212

C1212

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

+VCC_CORE

12

C1203

C1203

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1217

C1217

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

DY

12

R1201

R1201
100R2F-L1-GP-U

100R2F-L1-GP-U

12

R1202

R1202
100R2F-L1-GP-U

100R2F-L1-GP-U

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1218

C1218

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+1.05V_VTT

C1204

C1204

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

DY

DY

+1.05V_VTT

12

+1.05V_VTT

12

12

C1214

C1214

C1213

C1213

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

DY

DY

DY

DY

The decoupling capacitors, filter
recommendations and sense resistors on the
CPU/PCH Rails are specific to the CRB
Implementation. Customers need to follow the
recommendations in the Calpella Platform
Design Guide.

Please note that the VTT Rail
Values are Auburndale
VTT=1.05V; Clarksfield
VTT=1.1V

VCC_SENSE 47
VSS_SENSE 47

A A

CLARKUNF

CLARKUNF

5

4

3

2

<Core Design >

<Core Design >

<Core Design >

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (VCC_CORE)

CPU (VCC_CORE)

CPU (VCC_CORE)

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

12 92Monday, March 29, 2010

12 92Monday, March 29, 2010

12 92Monday, March 29, 2010

1

A00

A00

A00

5

4

3

2

1

SSID = CPU

+CPU_GFX_CORE

7 OF 9

CPU1G

AT21
AT19
AT18

AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16

AL21

AL19

AL18

AL16
AK21
AK19
AK18
AK16

AJ21

AJ19

AJ18

AJ16
AH21
AH19
AH18
AH16

J24
J23
H25

K26
J27
J26
J25

H27
G28
G27
G26

F26
E26
E25

CPU1G

VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG

VTT1
VTT1
VTT1

VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1

CLARKUNF

CLARKUNF

SENSE

SENSE

GRAPHICS

GRAPHICS

CLARKSFIELD

CLARKSFIELD

FDI PEG & DMI

FDI PEG & DMI

POWER

POWER

LINES

LINES

GRAPHICS VIDs

GRAPHICS VIDs

22A

D D

C1302

C1302

C1301

C1301

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

DY

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

DY

C1304

C1304

C1303

C1303

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

DY

C1305

C1305

12

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

DY

12

UMA

UMA

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1307

C1307

C1306

C1306

12

UMA

UMA

UMA

UMA

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1308

C1308

12

UMA

UMA

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

Please note that the VTT Rail

C C

+1.05V_VTT

+1.05V_VTT

B B

Values are: Auburndale VTT=1.05V
Clarksfield VTT=1.1V

12

C1316

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1316

x01 change tolerant 20091117

18A

C1321

C1321

12

12

C1320

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1320

DY

DY

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

12

12

DIS

DIS

C1317

C1317

12

C1323

C1323

C1322

C1322

12

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

R1302

R1302

0R3J-0-U-GP

0R3J-0-U-GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

7 OF 9

GFX_VID
GFX_VID
GFX_VID
GFX_VID
GFX_VID
GFX_VID
GFX_VID

GFX_IMON

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VTT0
VTT0
VTT0
VTT0

VTT1
VTT1
VTT1
VTT1
VTT1
VTT1

VCCPLL
VCCPLL
VCCPLL

AR22
AT22

AM22
AP22
AN22
AP23
AM23
AP24
AN24

R1305 4K7R2J-2-GP

R1305 4K7R2J-2-GP

AR25
AT25

GFX_IMON_C

AM24

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

J22
J20
J18
H21

x01 change tolerant 20091117

H20
H19

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

L26
L27
M26

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

VAXG_SENSE

VSSAXG_SENSE

GFX_VR_EN

GFX_DPRSLPVR

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

1.1V1.8V

1.1V1.8V

VCC_AXG_SENSE 53
VSS_AXG_SENSE 53

12

UMA

UMA

1 2

DY

DY

R1304 0R2J-2-GP

R1304 0R2J-2-GP

1 2

DIS

DIS

R1303 1KR2J-1-GP

R1303 1KR2J-1-GP

12

12

C1309

C1309

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C1318

C1318

C1324

C1324

C1326

C1326

12

C1310

C1310

C1311

C1311

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

12

DY

DY

C1327

C1327

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1 2

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

12

C1313

C1313

C1312

C1312

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C1319

C1319
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

C1325

C1325

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

12

C1328

C1328

1 2

GFX_VID0 53
GFX_VID1 53
GFX_VID2 53
GFX_VID3 53
GFX_VID4 53
GFX_VID5 53
GFX_VID6 53

GFX_VR_EN 53
GFX_DPRSLPVR 53
GFX_IMON 53

+1.5V_RUN_CPU

3A

12

12

C1314

C1314

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

x01 change tolerant 20091117

C1315

C1315

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

DY

DY

12

TC1301

TC1301

SE330U2D5VDM-2GP

SE330U2D5VDM-2GP

C1331

C1331

S3 Reduction

12

C1332

C1332

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

DY

x01 change tolerant 20091117

+1.05V_VTT

2.6A

+1.05V_VTT

1.35A

12

C1329

C1329

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

x01 change tolerant 20091117

+1.8V_RUN

12

C1330

C1330

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

12

C1333

C1333

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

DY

DY

DY

+1.5V_SUS

12

C1334

C1334

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

DY

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CPU (VCC_GFXCORE)

CPU (VCC_GFXCORE)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

CPU (VCC_GFXCORE)

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

of

13 92Monday, March 29, 2010

of

13 92Monday, March 29, 2010

of

13 92Monday, March 29, 2010

1

A00

A00

A00

5

4

3

2

1

SSID = CPU

8 OF 9

CPU1H

CPU1H

AT20

VSS

AT17

VSS

AR31

VSS

AR28

VSS

AR26

VSS

AR24

VSS

D D

C C

B B

AR23
AR20
AR17
AR15
AR12

AR9
AR6

AR3
AP20
AP17
AP13
AP10

AP7

AP4

AP2
AN34
AN31
AN23
AN20
AN17

AM29
AM27
AM25
AM20
AM17
AM14
AM11

AM8

AM5

AM2

AL34
AL31
AL23
AL20
AL17
AL12

AK29
AK27
AK25
AK20
AK17

AJ31
AJ23
AJ20
AJ17
AJ14
AJ11

AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13

AH9

AH6

AH3
AG10

AF8

AF4

AF2
AE35

AL9
AL6
AL3

AJ8
AJ5
AJ2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CLARKSFIELD

CLARKSFIELD

VSS

VSS

8 OF 9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

G34
G31
G20

K27

H35
H32
H28
H26
H24
H22
H18
H15
H13
H11

F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11

D33
D30
D26

C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11

A29
A27
A23

CPU1I

CPU1I

VSS

K9

VSS

K6

VSS

K3

VSS

J32

VSS

J30

VSS

J21

VSS

J19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

H8

VSS

H5

VSS

H2

VSS
VSS
VSS
VSS

G9

VSS

G6

VSS

G3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E8

VSS

E5

VSS

E2

VSS
VSS
VSS
VSS

D9

VSS

D6

VSS

D3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B8

VSS

B6

VSS

B4

VSS
VSS
VSS
VSS

A9

VSS

CLARKSFIELD

CLARKSFIELD

VSS

VSS

NCTF

NCTF

NCYF TEST PIN:

A35,AT1,AT35,B1,A3,A33,A34,

AP1,AP35,AR1,AR35,AT2,AT3,

AT33,AT34,C1,C35,B35

NCYF TEST PIN:

A35,AT1,AT35,B1,A3,A33,A34,

AP1,AP35,AR1,AR35,AT2,AT3,

AT33,AT34,C1,C35,B35

9 OF 9

9 OF 9

VSS_NCTF
VSS_NCTF
VSS_NCTF

VSS_NCTF#A35
VSS_NCTF#AT1

VSS_NCTF#AT35

VSS_NCTF#B1

RSVD_NCTF#A3
RSVD_NCTF#A33
RSVD_NCTF#A34
RSVD_NCTF#AP1

RSVD_NCTF#AP35

RSVD_NCTF#AR1

RSVD_NCTF#AR35

RSVD_NCTF#AT2
RSVD_NCTF#AT3

RSVD_NCTF#AT33
RSVD_NCTF#AT34

RSVD_NCTF#C1
RSVD_NCTF#C35
RSVD_NCTF#B35

AR34
B34
B2

A35
AT1
AT35
B1
A3
A33
A34
AP1
AP35
AR1
AR35
AT2
AT3
AT33
AT34
C1
C35
B35

TP_MCP_VSS_NCTF1
TP_MCP_VSS_NCTF2
TP_MCP_VSS_NCTF3
TP_MCP_VSS_NCTF4

TP1401TP1401

1

TP1402TP1402

1

TP1403TP1403

1

TP1404TP1404

1

CLARKUNF

CLARKUNF

A A

5

4

3

CLARKUNF

CLARKUNF

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VSS)

CPU (VSS)

CPU (VSS)

1

A00

A00

of

14 92Wednesday, February 10, 2010

of

14 92Wednesday, February 10, 2010

of

14 92Wednesday, February 10, 2010

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Reserved

Reserved

1

of

15 92Wednesday, February 10, 2010

of

15 92Wednesday, February 10, 2010

of

15 92Wednesday, February 10, 2010

A00

A00

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Reserved

Reserved

1

of

16 92Wednesday, February 10, 2010

of

16 92Wednesday, February 10, 2010

of

16 92Wednesday, February 10, 2010

A00

A00

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Reserved

Reserved

1

of

17 92Wednesday, February 10, 2010

of

17 92Wednesday, February 10, 2010

of

17 92Wednesday, February 10, 2010

A00

A00

A00

5

SSID = MEMORY

D D

M_A_BS210

M_A_BS010
M_A_BS110

M_A_DQ[63..0]10

C C

+V_DDR_REF

B B

+0.75V_DDR_VTT

x01 change tolerant 20091117

x01 change tolerant 20091118

12

C1811

C1811

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+0.75V_DDR_VTT

12

C1818

C1818

DY

DY

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

Place these caps
close to VTT1 and
VTT2.

C1819

C1819

12

12

C1821

C1821

C1820

C1820

DY

DY

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

12

DY

DY

DY

DY

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C1812

C1812

SC2D2U6D3V3KX-G P

SC2D2U6D3V3KX-G P

12

C1822

C1822

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C1813

C1813
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DDR3_DRAMRST#9,19

M_ODT010
M_ODT110

+0.75V_DDR_VTT

+V_DDR_REF

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

4

H =4mm

DM1

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-47-GP

DDR3-204P-47-GP

62.10017.P31

62.10017.P31

RAS#

CAS#

CS0#
CS1#

CKE0
CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1
NC#2

NC#/TEST

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8

VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

3

M_A_DM[7..0] 10

M_A_DQS#[7..0] 10

M_A_DQS[7..0] 10

+1.5V_SUS

M_A_A[15..0] 10

M_A_RAS# 10
M_A_WE# 10
M_A_CAS# 10

M_CS#0 10
M_CS#1 10

M_CKE0 10
M_CKE1 10

M_CLK_DDR0 10
M_CLK_DDR#0 10

M_CLK_DDR1 10
M_CLK_DDR#1 10

PCH_SMBDATA 7,19,23,76
PCH_SMBCLK 7,19,23,76

PM_EXTTS#0 9

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C1801

C1801

12

SA0_DIM0

SA1_DIM0

12

+3.3V_RUN

x01 change tolerant 20091117

12

C1802

C1802

DY

DY

SC2D2U6D3V3KX-G P

SC2D2U6D3V3KX-G P

+1.5V_SUS

Layout Note:
Place these Caps near
SO-DIMMA.

2

S3 Power Reduction

PS_S3CNTRL42,50

R1803

R1803
10KR2J-3-GP

10KR2J-3-GP

Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30

12

If SA0 DIM0 = 1, SA1_DIM0 = 0

R1804

R1804

SO-DIMMA SPD Address is 0xA2

10KR2J-3-GP

10KR2J-3-GP

SO-DIMMA TS Address is 0x32

SODIMM A DECO UPLING

x01 change tolerant 20091117

C1803

C1803

TC1801

TC1801

Q1801

Q1801

2N7002E-1-GP

2N7002E-1-GP

84.2N702.D31

84.2N702.D31

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SE330U2D5VDM-2GP

SE330U2D5VDM-2GP

12

DY

DY

C1814

C1814

12

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+0.75V_DDR_VTT

12

R1806

R1806
22R2J-2-GP

22R2J-2-GP

DISCHARGE_0D75V

D

.

.

.

.
.

.

.

.

.

.

S

G

12

C1815

C1815

12

C1804

C1804

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

C1816

C1816

12

C1805

C1805

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

NP1

NP1

NP2

NP2

110
113

WE#

115

114
121

73
74

101

CK0

103

102

CK1

104

M_A_DM0

11

DM0

M_A_DM1

28

DM1

M_A_DM2

46

DM2

M_A_DM3

63

DM3

M_A_DM4

136

DM4

M_A_DM5

153

DM5

M_A_DM6

170

DM6

M_A_DM7

187

DM7

200

SDA

202

SCL

198

199

SA0_DIM0

197

SA0

SA1_DIM0

201

SA1

77
122
125

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

2

C1810

C1808

C1808

C1810

C1809

C1809

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

12

DY

DY

DY

DY

C1806

C1806

C1807

C1807

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

12

12

DY

DY

C1817

C1817

12

x01 change tolerant 20091117

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

DY

DY

SEC. 62.10017.P11

A A

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

DDR3-SODIMM1

DDR3-SODIMM1

DDR3-SODIMM1

Berry

Berry

Berry

1

A00

A00

A00

of

18 92Monday, March 29, 2010

of

18 92Monday, March 29, 2010

of

18 92Monday, March 29, 2010

5

SSID = MEMORY

D D

C C

B B

+V_DDR_REF

x01 change tolerant 20091118

12

C1915

C1915

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

Place these caps
close to VTT1 and
VTT2.

C1918

C1918

12

C1917

C1917
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+0.75V_DDR_VTT

12

12

C1919

C1919

C1920

C1920

DY

DY

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C1916

C1916

DY

DY

SC2D2U6D3V3KX-G P

SC2D2U6D3V3KX-G P

12

DY

DY

x01 change tolerant 20091117

M_B_BS210

M_B_BS010
M_B_BS110

M_B_DQ[63..0]10

M_ODT210
M_ODT310

+V_DDR_REF

DDR3_DRAMRST#9,18

12

C1921

C1921

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

4

DM2

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

H = 8mm

DDR3-204P-55-GP

DDR3-204P-55-GP

62.10017.Q31

62.10017.Q31

SEC. 62.10017.N71

NP1

NP1

NP2

NP2

110

RAS#

113

WE#

115

CAS#

114

CS0#

121

CS1#

73

CKE0

74

CKE1

101

CK0

103

CK0#

102

CK1

104

CK1#

M_B_DM0

11

DM0

M_B_DM1

28

DM1

M_B_DM2

46

DM2

M_B_DM3

63

DM3

M_B_DM4

136

DM4

M_B_DM5

153

DM5

M_B_DM6

170

DM6

M_B_DM7

187

DM7

200

SDA

202

SCL

198

EVENT#

199

VDDSPD

NC#/TEST

VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

SO-DIMMB is pl aced farther from
the Processor than SO-DIMM A

NC#1
NC#2

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

SA0_DIM1

197

SA0

SA1_DIM1

201

SA1

77
122
125

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

+1.5V_SUS

M_B_RAS# 10
M_B_WE# 10
M_B_CAS# 10

M_CS#2 10
M_CS#3 10

M_CKE2 10
M_CKE3 10

M_CLK_DDR2 10
M_CLK_DDR#2 10

M_CLK_DDR3 10
M_CLK_DDR#3 10

PCH_SMBDATA 7,18,23,76
PCH_SMBCLK 7,18,23,76

PM_EXTTS#1 9

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3

M_B_DM[7..0] 10

M_B_DQS#[7..0] 10

M_B_DQS[7..0] 10

M_B_A[15..0] 10

12

12

C1902

DY

DY

C1902

SC2D2U6D3V3KX-G P

SC2D2U6D3V3KX-G P

C1901

C1901

x01 change tolerant 20091118

+1.5V_SUS

x01 change tolerant 20091117

Layout Note:
Place these Caps near
SO-DIMMB.

+3.3V_RUN

SODIMM B DECO UPLING

C1903

C1903

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

DY

DY

C1912

C1912

C1911

C1911

12

12

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SA1_DIM1

SA0_DIM1

12

R1903

R1903
10KR2J-3-GP

10KR2J-3-GP

x01 change tolerant 20091117

C1905

C1904

C1904

C1913

C1913

C1905

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

12

DY

DY

C1914

C1914

12

12

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C1906

C1906

C1908

C1908

C1907

C1907

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

12

DY

DY

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

2

+3.3V_RUN

12

C1909

C1909

12

R1902

R1902
10KR2J-3-GP

10KR2J-3-GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32

C1910

C1910

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

DY

DY

1

A A

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

DDR3-SODIMM2

DDR3-SODIMM2

DDR3-SODIMM2

Berry

Berry

Berry

1

A00

A00

A00

of

19 92Monday, March 29, 2010

of

19 92Monday, March 29, 2010

of

19 92Monday, March 29, 2010

5

RN2001

D D

R2002

R2002

12

DY

DY

100KR2J-1-GP

100KR2J-1-GP

+3.3V_RUN

GPU_LVDS_CLK54,82
GPU_LVDS_DATA54,82

PCH_LCDVDD_EN

Place near PCH

RN2001

1
2 3

UMA

UMA

SRN0J-6-GP

SRN0J-6-GP

UMA

UMA

4

12

R2001

R2001
2K37R2F-GP

2K37R2F-GP

Impedance:85 ohm

123

45

RN2002

C C

B B

UMA

UMA

678

RN2002
SRN2K2J-4-GP

SRN2K2J-4-GP

LCTRL_DATA

LCTRL_CLK
LDDC_CLK_PCH
LDDC_DATA_PCH

PCH_CRT_BLUE77

PCH_CRT_GREEN77

PCH_CRT_RED77

Close to ball <600mil

RN2005

RN2005

SRN150F-1-GP

SRN150F-1-GP

678

UMA

UMA

4 5

123

4

PCH_VGA_BLEN55

PCH_LCDVDD_EN55

PCH_LBKLT_CTL55

LVDS_VBG

TP2001TPAD14-GP TP2001TPAD14-GP

1

RN2004

RN2004

1
2 3

UMA

UMA

SRN0J-6-GP

SRN0J-6-GP

PCH_LVDSA_TXC#55
PCH_LVDSA_TXC55

PCH_LVDSA_TX0#55
PCH_LVDSA_TX1#55
PCH_LVDSA_TX2#55

PCH_LVDSA_TX055
PCH_LVDSA_TX155
PCH_LVDSA_TX255

PCH_LVDSB_TXC#55
PCH_LVDSB_TXC55

PCH_LVDSB_TX0#55
PCH_LVDSB_TX1#55
PCH_LVDSB_TX2#55

PCH_LVDSB_TX055
PCH_LVDSB_TX155
PCH_LVDSB_TX255

Need Level Shift

PCH_CRT_DDCCLK77
PCH_CRT_DDCDATA77

PCH_CRT_HSYNC77
PCH_CRT_VSYNC77

2.5V Tolerance

1KR2J-1-GP

1KR2J-1-GP

LDDC_CLK_PCH
LDDC_DATA_PCH

LCTRL_CLK
LCTRL_DATA

LIBG

LVD_VREFH

4

LVD_VREFL

CRT_IREF

12

R2007

R2007

U2001D

U2001D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CLK

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

3

4 OF 10

4 OF 10

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ46
BG46

BJ48
BG48

BF45
BH45

T51
T53

BG44
BJ44
AU38

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

Y49
AB49

BE44
BD44
AV40

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

CRT

CRT

2

+3.3V_RUN

4

RN2006

RN2006
SRN2K2J-1-GP

SRN2K2J-1-GP

UMA

UMA

1

2 3

PCH_HDMI_CLK 57
PCH_HDMI_DATA 57

HDMI_DATA2#_C
HDMI_DATA2_C
HDMI_DATA1#_C
HDMI_DATA1_C
HDMI_DATA0#_C
HDMI_DATA0_C
HDMI_CLK#_C
HDMI_CLK_C

UMA

UMA
UMA

UMA
UMA

UMA
UMA

UMA
UMA

UMA
UMA

UMA
UMA

UMA
UMA

UMA

C2001 SCD1U10V2KX-5GP

C2001 SCD1U10V2KX-5GP

1 2

C2002 SCD1U10V2KX-5GP

C2002 SCD1U10V2KX-5GP

1 2

C2003 SCD1U10V2KX-5GP

C2003 SCD1U10V2KX-5GP

1 2

C2004 SCD1U10V2KX-5GP

C2004 SCD1U10V2KX-5GP

1 2

C2005 SCD1U10V2KX-5GP

C2005 SCD1U10V2KX-5GP

1 2

C2006 SCD1U10V2KX-5GP

C2006 SCD1U10V2KX-5GP

1 2

C2007 SCD1U10V2KX-5GP

C2007 SCD1U10V2KX-5GP

1 2

C2008 SCD1U10V2KX-5GP

C2008 SCD1U10V2KX-5GP

1 2

HDMI_PCH_DET 57

HDMI_PCH_DATA2# 57,82
HDMI_PCH_DATA2 57,82
HDMI_PCH_DATA1# 57,82
HDMI_PCH_DATA1 57,82
HDMI_PCH_DATA0# 57,82
HDMI_PCH_DATA0 57,82
HDMI_PCH_CLK# 57,82
HDMI_PCH_CLK 57,82

Close to VGA

Impedance:85 ohm Impedance:100 ohm

1

<Core Design>

<Core Design>

A A

5

4

3

2

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

PCH (LVDS/CRT/DDI)

PCH (LVDS/CRT/DDI)

PCH (LVDS/CRT/DDI)

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

of

20 92Monday, March 29, 2010

of

20 92Monday, March 29, 2010

of

20 92Monday, March 29, 2010

1

A00

A00

A00

5

RN2101

PCI_TRDY#
PCI_DEVSEL#
INT_PIRQA#

+3.3V_RUN

D D

+3.3V_RUN

PCI_ IRDY#

INT_PIRQH#
INT_PIRQB#
INT_PIRQF#
PCI_REQ3#

+3.3V_RUN

RN2101

1
2
3
4
5 6

SRN8K2J-2-GP-U

SRN8K2J-2-GP-U

RN2103

RN2103

1
2
3
4
5 6

SRN8K2J-2-GP-U

SRN8K2J-2-GP-U

RN2102

RN2102

1
2
3
4 5

SRN8K2J-4-GP

SRN8K2J-4-GP

PCI_STOP#

8

INT_PIRQE#

7

INT_PIRQC#

6

INT_PIRQG#

10
9
8
7

10
9
8
7

PCI_FRAME#
PCI_REQ2#
INT_PIRQD#
PCI_SERR#

PCI_REQ1#
PCI_PLOCK#
PCI_PERR#
PCI_REQ0#

+3.3V_RUN

+3.3V_RUN

PLT_RST#9,37,70,76,78,80

BOOT BIOS Strap

PCI_GNT#1 BOOT BIOS LocationPCI_GNT#0

0 0 LPC

C C

+3.3V_ALW

B B

A16 swap override Strap/Top-Block
Swap Override jumper

PCI_GNT#3 Low = A16 swap

0 1 Reserved

01

11

RN2104

USB_OC#2_3

SMC_WAKE_SCI#_R

PCI_GNT3#

RN2104

1
2
3
4
5 6

SRN8K2J-2-GP-U

SRN8K2J-2-GP-U

R2105

R2105

1 2

DY

DY

4K7R2J-2-GP

4K7R2J-2-GP

override/Top-Block
Swap Override enabled
High = Default

PCI

SPI(Default)

10

USB_OC#12_13

9

USB_OC#8_9USB_OC#6_7

8

USB_OC#10_11USB_OC#0_1

7

USB_OC#4_5

+3.3V_ALW

PCLK_FWH70
CLK_PCI_FB23
PCLK_KBC37

4

SSID = PCH

+3.3V_RUN

5

VCC

DY

DY

4

Y

NL17SZ08DFT2G-GP

NL17SZ08DFT2G-GP

1 2

R2101 0R0402-PADR2101 0R0402-PAD

12

C2101

C2101

DY

DY

SC220P50V2KX-3GP

SC220P50V2KX-3GP

1 2

R2107 22R2J-2-GPR2107 22R2J-2-GP

1 2

R2108 22R2J-2-GPR2108 22R2J-2-GP

1 2

R2109 22R2J-2-GPR2109 22R2J-2-GP

1 2

DY

DY

U2101

U2101

1

A

PCI_PLTRST#

2

B

3

GND

EC2101

EC2101
SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

3

5 OF 10

U2001E

U2001E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

TP2102TPAD14-GP TP2102TPAD14-GP
TP2103TPAD14-GP TP2103TPAD14-GP
TP2104TPAD14-GP TP2104TPAD14-GP

TP2110TPAD14-GP TP2110TPAD14-GP

TP2115TPAD14-GP TP2115TPAD14-GP

PCI_GNT0#

1

PCI_GNT1#

1

PCI_GNT2#

1

PCI_GNT3#

INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#

PCIRST#

1

PCI_SERR#
PCI_PERR#

PCI_ IRDY#

PCI_DEVSEL#
PCI_FRAME#

PCI_PLOCK#

PCI_STOP#
PCI_TRDY#

PCH_PME#

1

PCI_PLTRST#

PCLK_FWH_R
CLK_PCI_FB_R
PCLK_KBC_R

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1#/GPIO50

B45

REQ2#/GPIO52

M53

REQ3#/GPIO54

F48

GNT0#

K45

GNT1#/GPIO51

F36

GNT2#/GPIO53

H53

GNT3#/GPIO55

B41

PIRQE#/GPIO2

K53

PIRQF#/GPIO3

A36

PIRQG#/GPIO4

A48

PIRQH#/GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

PCI

PCI

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_DQ0/NV_IO0
NV_DQ1/NV_IO1
NV_DQ2/NV_IO2
NV_DQ3/NV_IO3
NV_DQ4/NV_IO4
NV_DQ5/NV_IO5
NV_DQ6/NV_IO6
NV_DQ7/NV_IO7
NV_DQ8/NV_IO8

NV_DQ9/NV_IO9
NV_DQ10/NV_IO10
NV_DQ11/NV_IO11

NVRAM

NVRAM

NV_DQ12/NV_IO12
NV_DQ13/NV_IO13
NV_DQ14/NV_IO14
NV_DQ15/NV_IO15

NV_RCOMP

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

USBP0N

USBP1N

USBP2N

USBP3N

USBP4N

USBP5N

USBP6N

USBP7N

USBP8N

USBP9N

USB

USB

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43

OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

5 OF 10

NV_ALE
NV_CLE

NV_RB#

USBP0P

USBP1P

USBP2P

USBP3P

USBP4P

USBP5P

USBP6P

USBP7P

USBP8P

USBP9P

AY9
BD1
AP15
BD8

AV9
BG8

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

BD3
AY6

AU2

AV7

AY8
AY5

AV11
BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

B25

D25

N16
J16
F16
L16
E14
G16
F12
T15

2

NV_ALE
NV_CLE

NV_RCOMP

1

USB_RBIAS_PN

USB_OC#0_1
USB_OC#2_3
USB_OC#4_5
USB_OC#6_7
USB_OC#8_9
USB_OC#10_11
USB_OC#12_13
SMC_WAKE_SCI#_R

DMI Termination Voltage

NV_CLE Set to Vss when low.

TP2105 TPAD14-GPTP2105 TPAD14-GP

Set to Vcc when high.

Danbury Technology:
Disabled when Low.
Enable when High.

Pair

USB_PN0 77
USB_PP0 77
USB_PN1 77
USB_PP1 77
USB_PN2 76
USB_PP2 76

USB_PN4 78
USB_PP4 78
USB_PN5 73
USB_PP5 73

0

1

2

3

4

5

6

7

USB_PN8 76
USB_PP8 76
USB_PN9 76
USB_PP9 76

USB_PN11 76
USB_PP11 76

USB_PN13 54
USB_PP13 54

1 2

R2106

R2106
22D6R2F-L1-GP

22D6R2F-L1-GP

8

9

10

11

12

13

USB_OC#0_1 63

USB_OC#8_9 63

1

+V_NVRAM_VCCQ

12

R2102

R2102
1KR2J-1-GP

1KR2J-1-GP

DY

DY

NV_CLE

+V_NVRAM_VCCQ

12

R2103

R2103
1KR2J-1-GP

1KR2J-1-GP

DY

DY

NV_ALE

USB

Device

USB2 (CRT Board)

USB3 (CRT Board)

WLAN (I/O Board)

X

CARD READER

BLUETOOTH

X

X

USB1 (I/O Board)

ESATA (I/O Board COMBO)

X

W-WAN (I/O Board)

X

CAMERA

KBC CLK EMI

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

PCH (PCI/USB/NVRAM)

PCH (PCI/USB/NVRAM)

PCH (PCI/USB/NVRAM)

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

of

21 92Monday, March 29, 2010

of

21 92Monday, March 29, 2010

of

21 92Monday, March 29, 2010

1

A00

A00

A00

5

4

3

2

1

SSID = PCH

RN2201

FDI_PCH_TXP3
FDI_PCH_TXN3

3 OF 10

U2001C

U2001C

DMI_CTX_PRXN08
DMI_CTX_PRXN18
DMI_CTX_PRXN28

R2202

R2202

1 2

49D9R2F-GP

49D9R2F-GP

DMI_CTX_PRXN38

DMI_CTX_PRXP08
DMI_CTX_PRXP18
DMI_CTX_PRXP28
DMI_CTX_PRXP38

DMI_PTX_CRXN08
DMI_PTX_CRXN18
DMI_PTX_CRXN28
DMI_PTX_CRXN38

DMI_PTX_CRXP08
DMI_PTX_CRXP18
DMI_PTX_CRXP28
DMI_PTX_CRXP38

DMI_IRCOMP_R

D D

+1.05V_VTT

C C

XDP_DBRESET#9,23

X02-20091222

R2204

R2204

PM_PWROK37

PM_DRAM_PWRGD9

PCH_RSMRST#37 PM_SLP_S4# 37,50

SUS_PWR_DN_ACK37

PM_PWRBTN#_R9

PM_PWRBTN#37

B B

AC_PRESENT_EC37

1 2

0R0402-PAD

0R0402-PAD

RN2207

RN2207

4

SRN10KJ-5-GP

SRN10KJ-5-GP

X02-20091222

R2218

R2218

1 2

0R0402-PAD

0R0402-PAD

PM_BATLOW#_R

PM_RI#

PM_PWRGD

23
1

X02-20091224

TP2206TPAD14-GP TP2206TPAD14-GP

R2213

R2213

1 2

0R0402-PAD

0R0402-PAD

R2215

R2215

1 2

0R0402-PAD

0R0402-PAD

R2219

R2219

1 2

0R0402-PAD

0R0402-PAD

X02-20091222

R2206

R2206

1 2

0R0402-PAD

0R0402-PAD

LAN_RST#1

1

PM_RSMRST#_R

PM_PWRBTN#_R

AC_PRESENT

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK/GPI O30

P5

PWRBTN#

P7

ACPRESENT/GPIO31

A6

BATLOW#/GPIO 72

F14

RI#

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

DMI

DMI

System Power Management

System Power Management

3 OF 10

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI

FDI

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

WAKE#

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

SLP_LAN#/GPIO29

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14

BF13

BH13

BJ12

BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

FDI_PCH_TXN0
FDI_PCH_TXN1
FDI_PCH_TXN2
FDI_PCH_TXN3
FDI_PCH_TXN4
FDI_PCH_TXN5
FDI_PCH_TXN6
FDI_PCH_TXN7

FDI_PCH_TXP0
FDI_PCH_TXP1
FDI_PCH_TXP2
FDI_PCH_TXP3
FDI_PCH_TXP4
FDI_PCH_TXP5
FDI_PCH_TXP6
FDI_PCH_TXP7

FDI_INT_C

FDI_FSYNC0_C

FDI_FSYNC1_C

FDI_LSYNC0_C

FDI_LSYNC1_C

PM_SUS_STAT#MEPWROK

PCH_SUSCLK

PCH_SLP_S5#

PM_SLP_S4#_R

PM_SLP_S3#_R

SIO_SLP_M#_R

PM_SLP_DSW#

H_PM_SYNC

PM_SLP_LAN#

R2201

R2201

1 2

UMA

UMA

0R2J-2-GP

0R2J-2-GP

PCIE_WAKE# 76

PM_CLKRUN# 37

TP2201

TP2201
TPAD14-GP

TPAD14-GP

1

1

1

TP2203TPAD14-GPTP2203TPAD14-GP

1

TP2204TPAD14-GPTP2204TPAD14-GP

1

TP2205TPAD14-GPTP2205TPAD14-GP

TP2202

TP2202
TPAD14-GP

TPAD14-GP

FDI_INT 8

A00-20100204

1 2

R2209 0R0402-PADR2209 0R0402-PAD

1 2

R2211 10R2J-2-GPR2211 10R2J-2-GP

1 2

R2214 0R0402-PADR2214 0R0402-PAD

1 2

R2216 0R0402-PADR2216 0R0402-PAD

X02-20091222

Option to " Disable " clkrun.
Pulling it down will keep the clks running.

FDI_PCH_TXN1
FDI_PCH_TXP1

FDI_PCH_TXN4
FDI_PCH_TXP4
FDI_PCH_TXP0
FDI_PCH_TXN0

FDI_PCH_TXP6
FDI_PCH_TXN6
FDI_PCH_TXN2
FDI_PCH_TXP2

FDI_PCH_TXN7
FDI_PCH_TXP7
FDI_PCH_TXP5
FDI_PCH_TXN5

FDI_LSYNC1_C
FDI_FSYNC1_C
FDI_LSYNC0_C
FDI_FSYNC0_C

PM_SLP_S3# 37,42,47,50,51,89

H_PM_SYNC 9

RN2201

1
2
3

UMA

UMA

4 5

SRN0J-7-GP

SRN0J-7-GP

RN2202

RN2202

1
2
3

UMA

UMA

4 5

SRN0J-7-GP

SRN0J-7-GP

RN2203

RN2203

1
2

UMA

UMA

3
4 5

SRN0J-7-GP

SRN0J-7-GP

RN2204

RN2204

1
2

UMA

UMA

3
4 5

SRN0J-7-GP

SRN0J-7-GP

RN2205

RN2205

1
2

UMA

UMA

3
4 5

SRN0J-7-GP

SRN0J-7-GP

PCH_SUSCLK_2102 39

PCH_SUSCLK_KBC 37

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

FDI_TXP3 8
FDI_TXN3 8
FDI_TXN1 8
FDI_TXP1 8

FDI_TXN4 8
FDI_TXP4 8
FDI_TXP0 8
FDI_TXN0 8

FDI_TXP6 8
FDI_TXN6 8
FDI_TXN2 8
FDI_TXP2 8

FDI_TXN7 8
FDI_TXP7 8
FDI_TXP5 8
FDI_TXN5 8

FDI_LSYNC1 8
FDI_FSYNC1 8
FDI_LSYNC0 8
FDI_FSYNC0 8

PM_BATLOW#_R
PM_RI#
AC_PRESENT_EC
SUS_PWR_ACK

PCIE_WAKE#

PCH_RSMRST#SUS_PWR_ACK

RN2206

RN2206

1
2
3
4 5

SRN10KJ-6-GP

SRN10KJ-6-GP

1 2

R2210 1KR2J-1-GPR2210 1KR2J-1-GP

R2217

R2217

1 2

10KR2J-3-GP

10KR2J-3-GP

PM_CLKRUN#

12

R2221

R2221

DY

10KR2J-3-GP

10KR2J-3-GP

DY

8
7
6

+3.3V_ALW

1 2

R2220

R2220
10KR2J-3-GP

10KR2J-3-GP

+3.3V_RUN

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

PCH (DM I/FDI/PM)

PCH (DM I/FDI/PM)

PCH (DM I/FDI/PM)

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

of

22 92Monday, March 29, 2010

of

22 92Monday, March 29, 2010

of

22 92Monday, March 29, 2010

1

A00

A00

A00

5

4

3

2

1

SSID = PCH

12

12

RN2303

RN2303

2 3
1

SRN2K2J-1-GP

SRN2K2J-1-GP

Q2301

Q2301

6

5

2N7002EDW-GP

2N7002EDW-GP

UMA

UMA

+3.3V_ALW

PEG_CLKREQ#_C

4

1

2

34

DIS uses 0ohm 63.R0034.1DL
UMA uses 12pF 78.12034.1FL

X2301

X2301
XTAL-25MHZ-96GP

XTAL-25MHZ-96GP

1 2

C2307

C2307

UMA

UMA

SC12P50V2JN-3GP

SC12P50V2JN-3GP

X01 2009/11/05

2 OF 10

U2001B

U2001B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

D D

PCIE_RXN276

PCIE_RXP276
PCIE_TXN276
PCIE_TXP276

PCIE_RXN376

PCIE_RXP376
PCIE_TXN376
PCIE_TXP376

PCIE_RXN476

PCIE_RXP476
PCIE_TXN476
PCIE_TXP476

C2301 SCD1U10V2KX-5GPC2301 SCD1U10V2KX-5GP
C2302 SCD1U10V2KX-5GPC2302 SCD1U10V2KX-5GP

C2303 SCD1U10V2KX-5GPC2303 SCD1U10V2KX-5GP
C2306 SCD1U10V2KX-5GPC2306 SCD1U10V2KX-5GP

C2304 SCD1U10V2KX-5GPC2304 SCD1U10V2KX-5GP
C2305 SCD1U10V2KX-5GPC2305 SCD1U10V2KX-5GP

1 2
1 2

1 2
1 2

1 2
1 2

PCIE_C_TXN2
PCIE_C_TXP2

PCIE_C_TXN3
PCIE_C_TXP3

PCIE_C_TXN4
PCIE_C_TXP4

x01 change tolerant 20091117

C C

PCIECLKRQ{0,3,4,5,6,7}# should have a 10 K pull-up to +3.3V_ALW.
PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN

PCIE_CLK_RQ1#

CLK_PCIE_WLAN#76
CLK_PCIE_WLAN76

WLAN_CLKREQ#76

CLK_PCIE_LAN#76
CLK_PCIE_LAN76

B B

+3.3V_ALW

RN2307

RN2307

1

8

2

7

3

6

4 5

SRN10KJ-6-GP

SRN10KJ-6-GP

R2304 10KR2J-3-GPR2304 10KR2J-3-GP

CLK_PCIE_WWAN#76
CLK_PCIE_WWAN76

WW AN_CLKREQ#76

WW AN_CLKREQ#
PCIE_CLK_RQ0#
PEG_B_CLKRQ#
PCIE_CLK_RQ5#

12

PCIE_CLK_RQ3#

PCIE_CLK_RQ5#

PEG_B_CLKRQ#

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0#/GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1#/GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2#/GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4#/GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5#/GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ#/GPIO56

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

WLAN

LAN

W-WAN

SMBus

SMBus

PCI-E*

PCI-E*

Link

Link

Controller

Controller

PEG_A_CLKRQ#/GPIO47

PEG

PEG

CLKOUT_DP_N/CLKOUT_BCLK1_N
CLKOUT_DP_P/CLKOUT_BCLK1_P

From CLK BUFFER

From CLK BUFFER

CLKIN_SATA_N/CKSSCD_N
CLKIN_SATA_P/CKSSCD_P

Clock Flex

Clock Flex

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

2 OF 10

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1ALERT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

B9

PCH_SMB_CLK

H14

PCH_SMB_DATA

C8

TPM_ID1

J14

SML0_CLK

C6

SML0_DATA

G8

LPD_SPI_INTR#

M14

KBC_SCL1

E10

KBC_SDA1

G12

CL_CLK

T13

CL_DATA

T11

CL_RST#

T9

PEG_CLKREQ#_C

H1

CLK_PCIE_VGA#

AD43

CLK_PCIE_VGA

AD45

CLK_EXP_N

AN4

CLK_EXP_P

AN2

AT1
AT3

CLKIN_DMI#

AW24

CLKIN_DMIPCIE_CLK_RQ0#

BA24

CLK_CPU_BCLK#

AP3

CLK_CPU_BCLK

AP1

F18
E18

AH13
AH12

CLK_PCH_14M

P41

CLK_PCI_FB

J42

XTAL25_IN

AH51

XTAL25_OUT

AH53

XCLK_RCOMP

AF38

CLK_PCH_GPIO64

T45

P43

T42

N50

1

1

1

X01 20091118

CLK48_GPIO

PCH_GPIO11 25

SML0_CLK 9

SML0_DATA 9

KBC_SCL1 37

KBC_SDA1 37

TP2302 TPAD14-GPTP2302 TPAD14-GP

TP2303 TPAD14-GPTP2303 TPAD14-GP

TP2304 TPAD14-GPTP2304 TPAD14-GP

DY

DY

1 2

R2310 0R2J-2-GP

R2310 0R2J-2-GP

CLK_PCIE_VGA# 80
CLK_PCIE_VGA 80

CLK_EXP_N 9
CLK_EXP_P 9

CLKIN_DMI# 7
CLKIN_DMI 7

CLK_CPU_BCLK# 7
CLK_CPU_BCLK 7

CLK_DREF# 7
CLK_DREF 7

CLK_PCIE_SATA# 7
CLK_PCIE_SATA 7

CLK_PCH_14M 7

CLK_PCI_FB 21

R2306 90D9R2F-1-GPR2306 90D9R2F-1-GP

1 2

TP2301

TP2301

TPAD14-GP

TP2307

TP2307

TPAD14-GP

TPAD14-GP

TPAD14-GP

1

1

PEG_CLKREQ# 82

+3.3V_ALW

RN2309

RN2309

SRN2K2J-1-GP

SRN2K2J-1-GP

SML0_DATA

SML0_CLK

+1.05V_VTT

TPM_ID1

R2305 10KR2J-3-GPR2305 10KR2J-3-GP

LPD_SPI_INTR#

R2311 10KR2J-3-GPR2311 10KR2J-3-GP

4

1

2 3

PCH_SMB_DATA

PCH_SMB_CLK

XTAL25_IN

UMA

UMA

XTAL25_OUT

4

RN2301

RN2301
SRN2K2J-1-GP

SRN2K2J-1-GP

1

2 3

KBC_SCL1

KBC_SDA1

+3.3V_RUN

1 2

84.27002.F3F

84.27002.F3F

R2303

R2303
1M1R2J-GP

1M1R2J-GP

+3.3V_ALW

PCH_SMB_CLK

PCH_SMB_DATA

+3.3V_ALW

UMA

UMA

DIS

DIS

PCH_SMBDATA 7,18,19,76

PCH_SMBCLK 7,18,19,76

X01 2009/11/06

C2308

C2308

12

COLAY

COLAY

SC12P50V2JN-3GP

SC12P50V2JN-3GP

12

1

4

12

R2308

R2308
10KR2J-3-GP

10KR2J-3-GP

12

R2309

R2309
10KR2J-3-GP

10KR2J-3-GP

23

RN2302

RN2302
SRN2K2J-1-GP

SRN2K2J-1-GP

A A

5

+3.3V_RUN

4

RN2308

RN2308

4 5
3
2
1

SRN10KJ-6-GP

SRN10KJ-6-GP

6
7

PCIE_CLK_RQ1#

8

XDP_DBRESET#
WLAN_CLKREQ#
INT_SERIRQ

XDP_DBRESET# 9,22

INT_SERIRQ 24,37

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

PCH (PCI-E/SMBUS/CLOCK/CL)

PCH (PCI-E/SMBUS/CLOCK/CL)

PCH (PCI-E/SMBUS/CLOCK/CL)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

of

23 92Monday, March 29, 2010

of

23 92Monday, March 29, 2010

of

23 92Monday, March 29, 2010

1

A00

A00

A00

5

4

3

2

1

PCH_RTCX1

1 2

R2402 10MR2J-L-GPR2402 10MR2J-L-GP

X2401

X2401

D D

12

C2403

C2403

SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

2 3

X-32D768KHZ-65-GP

X-32D768KHZ-65-GP

82.30001.A41

82.30001.A41

PCH_RTCX2

41

12

C2401

C2401
SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

X01 X01

PCH_AZ_CODEC_SYNC30

PCH_SDOUT_CODEC30

C C

+3.3V_RUN

NO REBOOT STRAP

1 2

DY

DY

R2410 1KR2J-1-GP

R2410 1KR2J-1-GP

PCH_AZ_CODEC_BITCLK30

ACZ_SPKR

PCH_AZ_CODEC_RST#30

No Reboot Strap R23

HDA_SPKR

Low = Default
High = No Reboot

For EMI

B B

PCH_AZ_CODEC_BITCLK
PCH_AZ_CODEC_RST#

EC2402

EC2402

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

DY

1 2

DY

DY

1 2

EC2401

EC2401
SC22P50V2JN-4GP

SC22P50V2JN-4GP

+RTC_CELL

R2401

R2401

1 2

20KR2J-L2-GP

+RTC_CELL

20KR2J-L2-GP

R2403

R2403

1 2

20KR2J-L2-GP

20KR2J-L2-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2404

C2404

12

C2402

C2402
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

X01 20091118 layout swap

RN2403

RN2403

1
2 3

SRN33J-5-GP-U

SRN33J-5-GP-U

RN2402

RN2402

SRN33J-5-GP-U

SRN33J-5-GP-U

1
2 3

ACZ_SYNC_R

4

ACZ_SDATAOUT_R

4

PCH_SPI_CLK62

PCH_SPI_CS0#62

PCH_SPI_DO62

PCH_SPI_DI62

ACZ_RST#_R
ACZ_BIT_CLK

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_DO

PCH_SPI_DI

21

G2401

G2401
GAP-OPEN

GAP-OPEN

+RTC_CELL

TP2404TPAD14-GP TP2404TPAD14-GP

TP2405TPAD14-GP TP2405TPAD14-GP

TP2406TPAD14-GP TP2406TPAD14-GP

TP2407TPAD14-GP TP2407TPAD14-GP

TP2408TPAD14-GP TP2408TPAD14-GP

R2413 15R2J-GPR2413 15R2J-GP

1 2

R2414 15R2J-GPR2414 15R2J-GP

1 2

1 2

R2415 0R2J-2-GP

R2415 0R2J-2-GP

R2416 15R2J-GPR2416 15R2J-GP

1 2

INTVRMEN- Integrated SUS

1.1V VRM Enable
High - Enable internal VRs

R2407

R2407

1M1R2J-GP

1M1R2J-GP

R2404 330KR2F-L-GPR2404 330KR2F-L-GP

ACZ_SPKR30

PCH_SDIN_CODEC30

ME_UNLOCK#37

DY

DY

12

1 2

ACZ_RST#_R

ACZ_SDATAOUT_R

1

1

1

1

1

PCH_RTCX1
PCH_RTCX2

PCH_RTCRST#

SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

ACZ_BIT_CLK

ACZ_SYNC_R

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_RST#

SPI_CLK_R

SPI_CS#0_R

SPI_CS1#

SPI_MOSI_R

SSID = PCH

U2001A

U2001A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN#/GPIO33

J30

HDA_DOCK_RST#/GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

RTCIHDA

RTCIHDA

SPI JTAG

SPI JTAG

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ1#/GPIO23

LPC

LPC

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

1 OF 10

1 OF 10

LDRQ0#

SERIRQ

LPC_LAD[0..3]

LPC_LAD0

D33

LPC_LAD1

B33

LPC_LAD2

C32

LPC_LAD3

A32

C34

A34
F34

AB9

LPC_LFRAME# 37,70

INT_SERIRQ 23,37

x01 Change tolerant 20091117

AK7
AK6
AK11
AK9

AH6
AH5
AH9
AH8

AF11
AF9
AF7
AF6

AH3
AH1
AF3
AF1

AD9
AD8
AD6
AD5

AD3
AD1
AB3
AB1

AF16

AF15

T3

Y9

V1

SATA_TXN0_C
SATA_TXP0_C

SATA_TXN1_C
SATA_TXP1_C

SATA_TXN4_C
SATA_TXP4_C

C2409 SCD01U16V2KX-3GPC2409 SCD01U16V2KX-3GP

1 2

C2410 SCD01U16V2KX-3GPC2410 SCD01U16V2KX-3GP

1 2

C2405 SCD01U16V2KX-3GPC2405 SCD01U16V2KX-3GP

1 2

C2406 SCD01U16V2KX-3GPC2406 SCD01U16V2KX-3GP

1 2

C2407 SCD01U16V2KX-3GPC2407 SCD01U16V2KX-3GP

1 2

C2408 SCD01U16V2KX-3GPC2408 SCD01U16V2KX-3GP

1 2

R2412

SATAICOMP

SATA_DET#0_R

SATA_DET#1_R

R2412

1 2

37D4R2F-GP

37D4R2F-GP

SATA_LED# 66

+1.05V_VTT

LPC_LAD[0..3] 37,70

+3.3V_RUN

4

RN2401

RN2401
SRN10KJ-5-GP

SRN10KJ-5-GP

1

2 3

SATA_RXN0_C 59
SATA_RXP0_C 59
SATA_TXN0 59
SATA_TXP0 59

SATA_RXN1_C 59
SATA_RXP1_C 59
SATA_TXN1 59
SATA_TXP1 59

SATA_RXN4_C 76
SATA_RXP4_C 76
SATA_TXN4 76
SATA_TXP4 76

HDD

ODD

ESATA

x01 Change tolerant 20091117

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

PCH (SPI/RTC/LPC/SATA/IHDA)

PCH (SPI/RTC/LPC/SATA/IHDA)

PCH (SPI/RTC/LPC/SATA/IHDA)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

of

24 92Monday, March 29, 2010

of

24 92Monday, March 29, 2010

of

24 92Monday, March 29, 2010

1

A00

A00

A00

5

4

3

2

1

SSID = PCH

6 OF 10

U2001F

U2001F

S_GPIO

SIO_EXT_SCI#37

D D

RN2502

PCH_GPIO22
PCH_GPIO37
PCH_GPIO36
PCH_GPIO48

C C

B B

+3.3V_RUN

PCH_GPIO39
STP_PCI#

SRN100KJ-6-GP

SRN100KJ-6-GP

PCH_GPIO17
PCH_GPIO6

SIO_EXT_SCI#

SIO_EXT_WAKE#

PCH_GPIO24

PCH_GPIO12
SIO_EXT_SMI#
PCH_GPIO28
HOST_ALTERT#1

+3.3V_ALW

RN2502

1
2
3
4
5 6

SRN10KJ-L3-GP

SRN10KJ-L3-GP

RN2503

RN2503

4

RN2504

RN2504

1
2
3
4 5

SRN10KJ-6-GP

SRN10KJ-6-GP

R2515 100KR2J-1-GP

R2515 100KR2J-1-GP

RN2501

RN2501

1
2
3
4
5 6

SRN10KJ-L3-GP

SRN10KJ-L3-GP

DY

DY

1
23

8
7
6

+3.3V_RUN

SIO_EXT_WAKE#37

SC47P50V2JN-3GP

SC47P50V2JN-3GP

+3.3V_RUN

10

PCH_GPIO38

9

DGPU_HOLD_RST#

8
7

12

10
9
8
7

S_GPIO

PCH_TEMP_ALERT#_C

S3_RST_GATE#9

+3.3V_ALW

S3_RST_GATE#

PCH_GPIO45

PCH_GPIO57

C2501

C2501

DY

DY

SC47P50V2JN-3GP

SC47P50V2JN-3GP

PCH_TEMP_ALERT#37

12

SIO_EXT_SMI#37

PCH_GPIO22

C2502

C2502

12

DY

DY

1 2

1 2

C2503 SCD047U16V2KX-1-GPC2503 SCD047U16V2KX-1-GP

PCH_GPIO11 23

R2508

R2508
10KR2J-3-GP

10KR2J-3-GP

TP2502TPAD14-GP TP2502TPAD14-GP

R2510

R2510

1 2

0R0402-PAD

0R0402-PAD

X02-20091222

TP2503TPAD14-GP TP2503TPAD14-GP

TP2504TPAD14-GP TP2504TPAD14-GP

TP2505TPAD14-GP TP2505TPAD14-GP

TP2507TPAD14-GP TP2507TPAD14-GP

SIO_EXT_SCI#

PCH_GPIO6

SIO_EXT_WAKE#

SIO_EXT_SMI#

PCH_GPIO12

HOST_ALTERT#1

DGPU_HOLD_RST#

PCH_GPIO17

PCH_GPIO24

PCH_GPIO27

1

PCH_GPIO28

STP_PCI#

CLK_SATA_OE#

PCH_GPIO36

PCH_GPIO37

PCH_GPIO38

PCH_GPIO39

PCH_GPIO45

PCH_GPIO48

PCH_TEMP_ALERT#_C

PCH_GPIO57

PCH_NCTF_1

1

PCH_NCTF_2

1

PCH_NCTF_3

1

PCH_NCTF_4

1

Y3

BMBUSY#/GPIO0

C38

TACH1/GPIO1

D37

TACH2/GPIO6

J32

TACH3/GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL/GPI O12

T7

GPIO15

AA2

SATA4GP/GPIO16

F38

TACH0/GPIO17

Y7

SCLOCK/GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI#/GPIO34

V6

SATACLKREQ#/GPIO35

AB7

SATA2GP/GPIO36

AB13

SATA3GP/GPIO37

V3

SLOAD/GPIO38

P3

SDATAOUT0/GPIO39

H3

PCIECLKRQ6#/GPIO45

F1

PCIECLKRQ7#/GPIO46

AB6

SDATAOUT1/GPIO48

AA4

SATA5GP/GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

MISC

MISC

CLKOUT_BCLK0_N/CLKOUT_PCIE8N

CLKOUT_BCLK0_P/CLKOUT_PCIE8P

GPIO

GPIO

CPU

CPU

NCTF

NCTF

RSVD

RSVD

6 OF 10

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

NC_1

NC_2

NC_3

NC_4

NC_5

INIT3_3V#

TP24

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

AH45
AH46

AF48
AF47

U2

AM3

AM1

BG10

T1

BE10

BD10

BA22

AW22

BB22

AY45

AY46

AV43

AV45

AF13

M18

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AB45

AB38

AB42

AB41

T39

P6

C10

INIT3_3V#

BCLK_CPU_N 9

BCLK_CPU_P 9

H_PECI 9

SIO_RCIN# 37

1

H_PWRGD 9,42

TP2506TPAD14-GPTP2506TPAD14-GP

PCH_THERMTRIP_R

SIO_A20GATE 37

+1.05V_VTT

1 2

R2506 54D9R2F-L1-GPR2506 54D9R2F-L1-GP

1 2

Placed Within 2" from PCH

R2504

R2504
56R2J-4-GP

56R2J-4-GP

H_THERMTRIP# 9,37,42,82

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet

Date: Sheet

PCH (GPIO/CPU)

PCH (GPIO/CPU)

PCH (GPIO/CPU)

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

25 92Monday, March 29, 2010

of

25 92Monday, March 29, 2010

of

25 92Monday, March 29, 2010

1

A00

A00

A00

5

4

3

2

1

SSID = PCH

DIS

DIS

1 2

R2601 0R2J-2-GP

+1.05V_VTT

1.524A

SC10U6D3V5KX-1GP

D D

SC10U6D3V5KX-1GP

C2602

C2602

12

12

C2601

C2601
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

DY

DY

x01 change tolerant 20091117

+1.05V_VTT

TP2602 TPAD14-GPTP2602 TPAD14-GP

1

C C

+1.05V_VTT

3.208A

x01 change tolerant 20091117

12

C2614

C2614

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

UMA

UMA

12

C2615

C2615

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2616

C2616

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

UMA

UMA

12

C2617

C2617

x01 change tolerant 20091117

C2621

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

B B

+1.05V_VTT

C2621

TP2601

TP2601

VCCAPLLEXP

12

C2618

C2618

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+3.3V_RUN

12

357mA

VCCAFDI_VRM

VCCFDIPLL

1

TPAD14-GP

TPAD14-GP

U2001G

U2001G

AB24

VCCCORE

AB26

VCCCORE

AB28

VCCCORE

AD26

VCCCORE

AD28

VCCCORE

AF26

VCCCORE

AF28

VCCCORE

AF30

VCCCORE

AF31

VCCCORE

AH26

VCCCORE

AH28

VCCCORE

AH30

VCCCORE

AH31

VCCCORE

AJ30

VCCCORE

AJ31

VCCCORE

AK24

VCCIO

BJ24

VCCAPLLEXP

AN20

VCCIO

AN22

VCCIO

AN23

VCCIO

AN24

VCCIO

AN26

VCCIO

AN28

VCCIO

BJ26

VCCIO

BJ28

VCCIO

AT26

VCCIO

AT28

VCCIO

AU26

VCCIO

AU28

VCCIO

AV26

VCCIO

AV28

VCCIO

AW26

VCCIO

AW28

VCCIO

BA26

VCCIO

BA28

VCCIO

BB26

VCCIO

BB28

VCCIO

BC26

VCCIO

BC28

VCCIO

BD26

VCCIO

BD28

VCCIO

BE26

VCCIO

BE28

VCCIO

BG26

VCCIO

BG28

VCCIO

BH27

VCCIO

AN30

VCCIO

AN31

VCCIO

AN35

VCC3_3

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

POWER

POWER

VCC CORE

VCC CORE

DMI

DMI

PCI E*

PCI E*

NAND / SPI

NAND / SPI

FDI

FDI

CRTLVDS

CRTLVDS

HVCMOS

HVCMOS

7 OF 10

7 OF 10

VCCADAC

VCCADAC

VSSA_DAC

VSSA_DAC

VCCALVDS

VSSA_LVDS

VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS

VCC3_3

VCC3_3

VCC3_3

VCCVRM

VCCDMI

VCCDMI

VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND

VCCME3_3
VCCME3_3
VCCME3_3
VCCME3_3

AE50

AE52

AF53

AF51

AH38

AH39

AP43
AP45
AT46
AT45

AB34

AB35

AD35

AT24

AT16

AU16

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

AM8
AM9
AP11
AP9

+VCCA_DAC_1_2

+VCCA_DAC_1_2

12

C2603

C2603

UMA

UMA

DIS

DIS

1 2

R2604 0R2J-2-GP

R2604 0R2J-2-GP

+1.8VS_VCCTX_LVDS

R2605

R2605

DIS

DIS

1 2

0R2J-2-GP

0R2J-2-GP

12

C2611

C2611
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

35mA

+1.05VS_VCC_DMI

12

C2619

C2619

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2620

C2620
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

PCH_VCCME3_3

12

C2623

C2623
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

69mA

12

C2604

C2604

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+3VS_VCCA_LVD

SCD01U16V2KX-3GP

12

C2607

C2607

UMA

UMA

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

357mA

156mA

85mA

12

C2605

C2605

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

UMA

UMA

C2606

C2606

1 2

DY

DY

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2608

C2608

UMA

UMA

+3.3V_RUN

+1.8V_RUN

DY

DY

12

X02-20091222

R2606

R2606

1 2

0R0402-PAD

0R0402-PAD

+V_NVRAM_VCCQ

+3.3V_RUN

X02-20091222

12

R2609

R2609
0R0402-PAD

0R0402-PAD

1 2

L2602 HCB1608KF-181-GP

L2602 HCB1608KF-181-GP

R2603 0R3J-0-U-GP

R2603 0R3J-0-U-GP

UMA

UMA

1 2

R2611 0R5J-5-GP

R2611 0R5J-5-GP

C2609

C2609

X01 Change location-20091116

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

61mA

R2601 0R2J-2-GP

+3.3V_CRT_LDO

UMA

UMA

UMA

UMA

300mA

12

59mA

+1.05V_VTT

A00-20100204

UMA

UMA

1 2

R2602 0R2J-2-GP

R2602 0R2J-2-GP

+3.3V_RUN

+1.8V_RUN

+5V_RUN +3.3V_CRT_LDO

C2612

C2612

SC1U10V2KX-1GP

SC1U10V2KX-1GP

+1.8V_RUN

12

R2607

R2607
0R0402-PAD

0R0402-PAD

+3.3V_RUN

3.3V CRT LDO

U2601

U2601

12

DY

DY

VIN3VOUT

2

GND

1

EN

RT9198-33PBG-GP

RT9198-33PBG-GP

DY

DY

NC#5

4

5

DY

DY

Second 74.09091.H3F

x01 change tolerant 20091117

+3.3V_RUN

12

R2608

R2608

DY

DY

0R2J-2-GP

0R2J-2-GP

12

C2613

C2613
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

X02-20091222

R2610

4

R2610

1 2

0R0402-PAD

0R0402-PAD

VCCAFDI_VRM

A A

5

+1.8V_RUN

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

3

2

Date: Sheet

PCH (POWER1)

PCH (POWER1)

PCH (POWER1)

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

of

26 92Wednesday, February 10, 2010

of

26 92Wednesday, February 10, 2010

of

26 92Wednesday, February 10, 2010

1

A00

A00

A00

5

4

3

2

1

10 OF 10

HDA

HDA

10 OF 10

VCCIO
VCCIO
VCCIO
VCCIO

VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

VCCSUS3_3

VCCIO

V5REF_SUS

V5REF

VCC3_3

VCC3_3

VCC3_3

VCC3_3

VCC3_3

VCC3_3

VCC3_3

VCCSATAPLL
VCCSATAPLL

VCCIO

VCCVRM

VCCIO

VCCIO

VCCIO

VCCIO
VCCIO
VCCIO
VCCIO

VCCIO
VCCIO
VCCIO
VCCIO

VCCME
VCCME
VCCME
VCCME

VCCSUSHDA

V24
V26
Y24
Y26

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

U23

V23

F24

K49

J38

L38

M36

N36

P36

U35

AD13

AK3
AK1

AH22

AT20

AH19

AD20

AF22

AD19
AF20
AF19
AH20

AB19
AB20
AB22
AD22

AA34
Y34
Y35
AA35

L30

+VCCSUSHDA

12

C2705

C2705
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

DY

DY

x01 change tolerant 20091117

12

C2706

C2706
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+3.3V_ALW

x01 change tolerant 20091117

+5VALW_PCH_VCC5REFSUS

+5VS_PCH_VCC5REF

12

C2718

C2718
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

x01 change tolerant 20091117

VCCSATAPLL

1

TPAD14-GP

TPAD14-GP

+1.8V_RUN

X02-20091222

R2703

R2703

1 2

0R0402-PAD

0R0402-PAD

12

C2733

C2733

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

POWER

U2001J

U2001J

TP2701

TP2701

D D

x01 change tolerant 20091117

+1.05V_VTT

C2707

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

+1.05V_VTT

C C

X01 20091121

L2702

L2702

1 2

IND-10UH-218-GP

IND-10UH-218-GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

L2703

L2703

1 2

IND-10UH-218-GP

IND-10UH-218-GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+1.05VS_VCCA_A_DPL

12

C2711

C2711

DY

DY

+1.05VS_VCCA_B_DPL

12

C2716

C2716

DY

DY

12

C2707

C2712

C2712
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2717

C2717
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1.998A

12

12

DY

DY

x01 change tolerant
20091118

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

72mA
73mA

+1.05V_VTT

x01 change tolerant 20091117

12

C2720

C2720

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

B B

x01 change tolerant 20091117

C2725

C2725

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+3.3V_ALW

+1.05V_VTT

163mA

12

C2728

C2728
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

x01 change tolerant 20091117

1mA

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

A A

+RTC_CELL

C2721

C2721

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

+3.3V_RUN

12

C2730

C2730

2mA

VCCACLK

1

TPAD14-GP

TPAD14-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2704

C2704

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C2710

C2710

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2714

C2714

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

12

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+VCCSST

+1.05VALW_INT_VCCSUS

12

C2726

C2726
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2729

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2729

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2731

C2731

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2734

C2734

DCPSUSBYP

12

C2703

C2703

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2708

C2708

12

DY

DY

+VCCRTCEXT

+1.8V_RUN

C2722

C2722

12

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2732

C2732

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2735

C2735

AP51

VCCACLK

AP53

VCCACLK

AF23

VCCLAN

AF24

VCCLAN

Y20

DCPSUSBYP

AD38

VCCME

AD39

VCCME

AD41

VCCME

AF43

VCCME

AF41

VCCME

AF42

VCCME

V39

VCCME

V41

VCCME

V42

VCCME

Y39

VCCME

Y41

VCCME

Y42

VCCME

V9

DCPRTC

AU24

VCCVRM

BB51

VCCADPLLA

BB53

VCCADPLLA

BD51

VCCADPLLB

BD53

VCCADPLLB

AH23

VCCIO

AJ35

VCCIO

AH35

12

VCCIO

AF34

VCCIO

AH34

VCCIO

AF32

VCCIO

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3

U19

VCCSUS3_3

U20

VCCSUS3_3

U22

VCCSUS3_3

V15

VCC3_3

V16

VCC3_3

Y16

VCC3_3

AT18

V_CPU_IO

AU18

V_CPU_IO

A12

VCCRTC

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

POWER

USB

USB

Clock and Miscellaneous

Clock and Miscellaneous

PCI/GPIO/LPC

PCI/GPIO/LPC

SATA

SATA

PCI/GPIO/LPC

PCI/GPIO/LPC

CPU

CPU

RTC

RTC

x01 change tolerant 20091117

5

4

3

+1.05V_VTT

+3.3V_ALW

+3.3V_ALW

12

C2709

C2709
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

TP2702

TP2702

+1.05V_VTT

+3.3V_RUN

12

21

D2701

D2701
CH751H-40PT-GP

CH751H-40PT-GP

R2702 10R2J-2-GPR2702 10R2J-2-GP

12

C2713

C2713
SC1U10V2KX-1GP

SC1U10V2KX-1GP

C2719

C2719
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

x01 change tolerant 20091117

12

C2727

C2727
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+1.05V_VTT

<Core Design>

<Core Design>

6mA

+3.3V_ALW

2

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

+5V_ALW

12

C2715

C2715
SC1U10V2KX-1GP

SC1U10V2KX-1GP

+3.3V_RUN

+1.05V_VTT

PCH (POWER2)

PCH (POWER2)

PCH (POWER2)

Berry

Berry

Berry

SSID = PCH

+3.3V_RUN

21

D2702

D2702
CH751H-40PT-GP

CH751H-40PT-GP

1 2

R2701 10R2J-2-GPR2701 10R2J-2-GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

27 92Wednesday, February 10, 2010

27 92Wednesday, February 10, 2010

27 92Wednesday, February 10, 2010

1

of

of

of

+5V_RUN

A00

A00

A00

5

4

3

2

1

SSID = PCH

D D

C C

B B

A A

5

U2001H

U2001H

AB16

VSS

AA19

VSS

AA20

VSS

AA22

VSS

AM19

VSS

AA24

VSS

AA26

VSS

AA28

VSS

AA30

VSS

AA31

VSS

AA32

VSS

AB11

VSS

AB15

VSS

AB23

VSS

AB30

VSS

AB31

VSS

AB32

VSS

AB39

VSS

AB43

VSS

AB47

VSS

AB5

VSS

AB8

VSS

AC2

VSS

AC52

VSS

AD11

VSS

AD12

VSS

AD16

VSS

AD23

VSS

AD30

VSS

AD31

VSS

AD32

VSS

AD34

VSS

AU22

VSS

AD42

VSS

AD46

VSS

AD49

VSS

AD7

VSS

AE2

VSS

AE4

VSS

AF12

VSS

Y13

VSS

AH49

VSS

AU4

VSS

AF35

VSS

AP13

VSS

AN34

VSS

AF45

VSS

AF46

VSS

AF49

VSS

AF5

VSS

AF8

VSS

AG2

VSS

AG52

VSS

AH11

VSS

AH15

VSS

AH16

VSS

AH24

VSS

AH32

VSS

AV18

VSS

AH43

VSS

AH47

VSS

AH7

VSS

AJ19

VSS

AJ2

VSS

AJ20

VSS

AJ22

VSS

AJ23

VSS

AJ26

VSS

AJ28

VSS

AJ32

VSS

AJ34

VSS

AT5

VSS

AJ4

VSS

AK12

VSS

AM41

VSS

AN19

VSS

AK26

VSS

AK22

VSS

AK23

VSS

AK28

VSS

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

8 OF 10

8 OF 10

4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

U2001I

U2001I

AY7

VSS

B11

VSS

B15

VSS

B19

VSS

B23

VSS

B31

VSS

B35

VSS

B39

VSS

B43

VSS

B47

VSS

B7

VSS

BG12

VSS

BB12

VSS

BB16

VSS

BB20

VSS

BB24

VSS

BB30

VSS

BB34

VSS

BB38

VSS

BB42

VSS

BB49

VSS

BB5

VSS

BC10

VSS

BC14

VSS

BC18

VSS

BC2

VSS

BC22

VSS

BC32

VSS

BC36

VSS

BC40

VSS

BC44

VSS

BC52

VSS

BH9

VSS

BD48

VSS

BD49

VSS

BD5

VSS

BE12

VSS

BE16

VSS

BE20

VSS

BE24

VSS

BE30

VSS

BE34

VSS

BE38

VSS

BE42

VSS

BE46

VSS

BE48

VSS

BE50

VSS

BE6

VSS

BE8

VSS

BF3

VSS

BF49

VSS

BF51

VSS

BG18

VSS

BG24

VSS

BG4

VSS

BG50

VSS

BH11

VSS

BH15

VSS

BH19

VSS

BH23

VSS

BH31

VSS

BH35

VSS

BH39

VSS

BH43

VSS

BH47

VSS

BH7

VSS

C12

VSS

C50

VSS

D51

VSS

E12

VSS

E16

VSS

E20

VSS

E24

VSS

E30

VSS

E34

VSS

E38

VSS

E42

VSS

E46

VSS

E48

VSS

E6

VSS

E8

VSS

F49

VSS

F5

VSS

G10

VSS

G14

VSS

G18

VSS

G2

VSS

G22

VSS

G32

VSS

G36

VSS

G40

VSS

G44

VSS

G52

VSS

AF39

VSS

H16

VSS

H20

VSS

H30

VSS

H34

VSS

H38

VSS

H42

VSS

IBEXPEAK-M-GP-NF

IBEXPEAK-M-GP-NF

3

9 OF 10

9 OF 10

VSS
VSS
VSS
VSS
VSS
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Berry

Berry

Berry

Taipei Hsien 221, Taiwan, R.O.C.

PCH (VSS)

PCH (VSS)

PCH (VSS)

1

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A00

of

28 92Wednesday, February 10, 2010

of

28 92Wednesday, February 10, 2010

of

28 92Wednesday, February 10, 2010

A00