Page 1
A
B
C
D
AG1(Alviso) Block Diagram 2005/11/01
E
CLK GEN.
4 4
DDR II
IDT CV125
34 , 5
400MHz
400 MHz
11,12
DDR II
400MHz
400 MHz
11,12
3 3
Line In
Int.
MIC In
Line Out
27
Codec
ALC655
27
OP AMP
27
G1421B
ACLINK
26
27
Mobile CPU
Dothan
HOST BUS
400MHz
Intel 910GML
6,7,8,9,10
DMI I/F
100MHz
ICH6-M
G792
PCI BUS
19
RGB
LVDS
ENE
CB1410
10/100
CRT
CONN
LCD
XGA
24,25
LAN
RTL8110CL
2 2
INT.SPKR
27
MODEM
MDC Card
21
22, 23
LPC BUS
15,16,17,18
PATA
PCB Layer Stackup
L1: Signal 1
1 1
L2:VCC
L3: Signal 2
HDD
20
CD ROM
20
L4: Signal 3
L5: GND
USB
4 PORT
21
MINI USB
Blue-tooth
21
L6: Signal 4
A
B
C
Project Code:91.4G301.001
PCB:05223-01
14
13
Mini-PCI
802.11A/B/G
KBC
ENE KB3910
Pad
30 30
PWR SW
CP2211
25
28
TXFM
23
Xbus
INT_KB Touch
PCMCIA
ONE SLOT
RJ45
23
BIOS ROM
4M BITS
PM39LV040-70JCE
31 29
25
<Core Design>
Title
Size Document Number Rev
Custom
Date: Sheet
D
INPUTS
DCBATOUT
INPUTS
APL5912-LAC
APL5308-25AC
INPUTS OUTPUTS
5V_S5
3D3V_S0 2D5V_S0
INPUTS OUTPUTS
DCBATOUT
5V_S5
DCBATOUT
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
BLOCK DIAGRAM
AG1(Alviso)
CPU DC/DC
ISL6218CV-T
OUTPUTS
VCC_CORE
0.844~1.3V
27A
SYSTEM DC/DC
TPS51120
DCBATOUT
SYSTEM DC/DC
ISL6227
TPS51100DGQ
CHARGER
ISL6255
14 0 Tuesday, Novem ber 01, 2005
E
35
OUTPUTS
3D3V_S5
5V_S5
1D5V_S0
5V_S5
3D3V_S3
DDR_VREF
DDR_VREF_S3
OUTPUTS INPUTS
BT+
16.8V 3A
of
34
36
37
37
38
01
Page 2
A
B
C
D
E
Alviso Strapping Signals
and Configuration
Pin Name
CFG[2:0]
4 4
CFG[3:4]
CFG5
CFG6
CFG7
CFG[8:11]
CFG[12:13]
CFG[14:15]
CFG16
CFG17
CFG18
3 3
CFG19
CFG20
SDVOCRTL
_DATA
All strap signals are sampled with respect to the leading
NOTE:
edge of the Alviso GMCH PWORK In signal.
Strap Description
FSB Frequency Select
Reversed
DMI x2 Select
DDR I / DDR II
CPU Strap
Reversed
XOR/ALL Z test
straps
Reversed
FSB Dynamic ODT 0 = Dynamic ODT Disabled
Reversed
CPU core VCC
Select
CPU VTT Select
Reversed
SDVO Present
Configuration
000 = Reserved
001 = FSB533
010 = FSB800
011-111 = Reversed
0 = DMI x2
1 = DMI x4
0 = DDR II
1 = DDR I
0 = Prescott
1 = Dothan
00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation
(Default)
1 = Dynamic ODT Enabled
(Default)
0 = 1.05V
1 = 1.5V
0 = 1.05V
1 = 1.2V
0 = No SDVO device present
(Default)
1= SDVO device present
(Default)
(Default)
(Default)
(Default)
page 7
PCI Routing
1410
MiniPCI
LAN
25
21
23
IRQ
B.F.G
F
E
REQ/GNT IDSEL
0
1
2
ICH6-M Integrated Pull-up
and Pull-down Resistors
ACZ_BIT_CLK,
EE_DOUT,
GNT[6]#/GPO[16],
LAD[3:0]#/FB[3:0]#, LDRQ[0],
PME#, PWRBTN#,
LAN_RXD[2:0]
ACZ_RST#, ACZ_SDIN[2:0],ACZ_SYNC,
ACZ_SDOUT,ACZ_BITCLK,
SPKR,
USB[7:0][P,N]
DD[7],
LAN_CLK
DPRSLP#, EE_DIN,
GNT[5]#/GPO[17],
TP[3]
EE_CS,
SDDREQ
LDRQ[1]/GPI[41],
DPRSLPVR,
ICH6 internal 20K pull-ups
ICH6 internal 10K pull-ups
ICH6 internal 20K pull-downs
ICH6 internal 15K pull-downs
ICH6 internal 11.5K pull-downs
ICH6 internal 100K pull-downs
ICH6-M EDS 14308 0.8V1
ICH6-M IDE Integrated Series
Termination Resistors
DD[15:0],
DDACK#,
DCS3#,
IORDY,
IDEIRQ
DIOR#, DREQ, DIOW#,
DA[2:0],
DCS1#,
approximately 33 ohm
2 2
1 1
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
Memo
AG1(Alviso)
24 0 Tuesday, November 01, 2005
of
01
Page 3
3D3V_S0 3D3V_S0 3D3V_S0
3D3V_APWR_S0 3D3V_CLKGEN_S0 3D3V_48MPWR_S0
R122
1 2
0R0603-PAD
1 2
C124
1 2
C295
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
R105
1 2
2R3J-2-GP
R110
1 2
1 2
C104
1 2
C103
SC4D7U6D3V3KX-GP
SCD1U16V2ZY-2GP
0R0603-PAD
1 2
C108
1 2
SC10U10V5ZY-1GP
C109
1 2
1 2
C122
C105
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
IN
(3D3V_S0)
H
X
EN
(6218_PGOOD)
L
OUT
(VTT_PWRGD#)
H
Hi - Z H
AG1-910-01
3D3V_CLKGEN_S0
R98
1KR2J-1-GP
R102
1KR2J-1-GP
1 2
1 2
R369
1KR2J-1-GP
FS_A
1 2
FS_B
FS_C
0
0
0
0
1
1
0
0
1
1 100M
0
1
1
1
1
AG1-A-SA
6218_PGOOD 32,34
AG1-910-01
CPU_SEL1 7
CPU_SEL0 4,7
FS_A
0
01200M
1
00333M
1
0
1 Reserved
PCLK_MINI 28
PCLK_LAN 22
PCLK_PCM 24
PCLK_KBC 29
CLK_ICHPCI 16
AG1-910-SB AG1-910-01
SC22P50V2JN-4GP
C116
1 2
3D3V_S0
123
1 2
C120
SC27P50V2JN-2-GP
678
4 5
CPU
266M
133M
166M
400M
VTT_PWRGD#
D
Q23
1
G
2 3
S
2N7002PT-U
R251 33R2J-2-GP
AG1-A-SA
X1
X-14D31818M-31GP
1 2
CLK_ICH14 & CLK14_SIO
need equal length
RN64
SRN10KJ-4-GP
1 2
DY
R106
10KR2J-2-GP
1 2
8
7
6
RN7
SRN33J-4-GP
PM_STPPCI# 16
SMBC_ICH 11,18
SMBD_ICH 11,18
DREFCLK 7
DREFCLK# 7
1
2
3
4 5
CLK_Audio 26
CLK_ICH14 16
ITP_EN
SS_SEL
1 2
DY
R104
10KR2J-2-GP
PCLK_MINI_1
PCLK_LAN_1
PCLK_PCM_1
PCLK_KBC_1
H/L: 100/96MHz
ITP_EN
H/L : CPU_ITP/SRC7
RN63 SRN33J-5-GP-U
4
4
RN13 SRN33J-5-GP-U
1 2
R252 475R2F-L1-GP
VTT_PWRGD#
2 3
1
2 3
1
SS_SEL
DREFCLK_1
DREFCLK#_1
XTAL_IN
XTAL_OUT
AG1-910-01
AG1-A-SA
56
3
4
5
9
8
55
46
47
14
15
50
49
52
39
10
2
6
51
45
38
13
29
IDTCV125PAG-GP
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_ICH
CLK_PCIE_ICH#
DREFSSCLK#
DREFSSCLK
DREFCLK#
DREFCLK
PCI0
PCI1
PCI2
PCI3
PCIF1/SEL100/96#
PCIF0/ITP_EN
PCI_STOP#
SCL
SDA
DOT96
DOT96#
XTAL_IN
XTAL_OUT
REF
IREF
VTT_PWRGD#/PD
VSS_PCI
VSS_PCI
VSS_REF
VSS_CPU
VSSA
VSS48
VSS_SRC
RN20 SRN49D9F-GP
1
2 3
RN19 SRN49D9F-GP
1
2 3
RN14 SRN49D9F-GP
1
2 3
RN9 SRN49D9F-GP
1
2 3
AG1-910-01
2 3
1
RN60 SRN49D9F-GP
2 3
1
RN61
CPU2_ITP/SRC7
CPU2_ITP#/SRC7#
CPU_STOP#
FSC/TEST_SEL
FSB/TEST_MODE
U28
LVDS
LVDS#
SRC1
SRC1#
SRC2
SRC2#
SRC3
SRC3#
SRC4
SRC4#
SRC5
SRC5#
SRC6
SRC6#
CPU0
CPU0#
CPU1
CPU1#
USB48/FSA
VDD_SRC
VDD_SRC
VDD_PCI
VDD_PCI
VDD_REF
VDD_CPU
VDDA
VDD48
VDD_SRC
4
4
4
4
4
4
SRN49D9F-GP
2nd
17
18
19
20
22
23
24
25
26
27
CLK_PCIE_ICH1
31
CLK_PCIE_ICH#1
30
CLK_MCH_3GPLL1
33
CLK_MCH_3GPLL#1
32
36
35
CLK_CPU_BCLK1
44
CLK_CPU_BCLK#1
43
CLK_MCH_BCLK1
41
CLK_MCH_BCLK#1
40
54
CPU_SEL0
53
CPU_SEL1
16
12
34
21
7
1
48
42
37
11
28
DREFSSCLK1
DREFSSCLK#1
FS_A
3D3V_CLKGEN_S0
3D3V_APWR_S0
3D3V_48MPWR_S0
RN10 SRN33J-5-GP-U
R103 22R2J-2-GP
2 3
1
4
RN62
SRN33J-5-GP-U
1
4
2 3
RN18 SRN47J-7-GP
1
4
2 3
RN12 SRN33J-5-GP-U
1
4
2 3
RN11 SRN33J-5-GP-U
1
4
2 3
1 2
CLK48_ICH 16
AG1-910-01
EMI capacitor
CLK_ICH14 CLK_MCH_BCLK
PCLK_PCM
PCLK_MINI
PCLK_KBC
CLK_ICHPCI
CLK48_ICH
<Core Design>
Title
Size Document Number Rev
A3
Date: Sheet of
EC45 SC10P50V2JN-4GP
1 2
DY
EC41 SC10P50V2JN-4GP
1 2
DY
EC70 SC10P50V2JN-4GP
1 2
DY
EC42 SC10P50V2JN-4GP
1 2
DY
EC43 SC10P50V2JN-4GP
1 2
DY
EC39 SC10P50V2JN-4GP
1 2
DY
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Clock Gener ator - IDT125
AG1(Alviso)
34 0 Friday, October 28, 2005
DREFSSCLK 7
DREFSSCLK# 7
CLK_PCIE_ICH 16
CLK_PCIE_ICH# 16
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
PM_STPCPU# 16, 34
01
Page 4
A
B
C
D
E
U41A
TUALA-SKT-1
H_A#3
4 4
3 3
H_A#[31..3] 6
AG1-A-SA
H_ADSTB#0 6
H_REQ#[4..0] 6
H_ADSTB#1 6
H_A20M# 15
H_FERR# 15
H_IGNNE# 15
H_STPCLK# 15
H_INTR 15
H_NMI 15
H_SMI# 15
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
P4
A3#
U4
A4#
V3
A5#
R3
A6#
V2
A7#
W1
A8#
T4
A9#
W2
A10#
Y4
A11#
Y1
A12#
U1
A13#
AA3
A14#
Y3
A15#
AA2
A16#
U3
ADSTB#0
R2
REQ0#
P3
REQ1#
T2
REQ2#
P1
REQ3#
T1
REQ4#
AF4
A17#
AC4
A18#
AC7
A19#
AC3
A20#
AD3
A21#
AE4
A22#
AD2
A23#
AB4
A24#
AC6
A25#
AD5
A26#
AE2
A27#
AD6
A28#
AF3
A29#
AE1
A30#
AF1
A31#
AE5
ADSTB#1
C2
A20M#
D3
FERR#
A3
IGNNE#
C6
STPCLK#
D1
LINT0
D4
LINT1
B4
SMI#
62.10053.061
CONNECTOR Y
ADDR GROUP 0
ADDR GROUP 1
PROCHOT#
THERMTRIP#
HCLK THERM XTP/ITP SIGNALS CONTROL
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
THERMDA
THERMDC
ITP_CLK1
ITP_CLK0
BCLK1
BCLK0
N2
L1
J3
L4
H2
M2
N4
A4
B5
J2
B11
H1
K1
L2
M3
K3
K4
C8
B8
A9
C9
A10
B10
A13
C12
TDI
A12
C11
B13
A7
B17
B18
A18
C17
A15
A16
B14
B15
AG1_A-SA : 62.10079.001
2 2
CPU_PROCHOT#
XDP_TDI
XDP_TMS
XDP_TDO
H_CPURST#
XDP_DBRESET#
1 1
XDP_TCK
XDP_TRST#
All place within 2" to CPU
R262 56R2F-1-GP
R256 150R2F-1-GP
R259 39D2R3F-GP
R257 54D9R2F-L1-GP
R258 54D9R2F-L1-GP
R263 150R2F-1-GP
R255 27D4R2F-L1-GP
R260 680R3F-GP
AG1-910-01
A
B
TP53
TPAD28
H_RS#0
H_RS#1
H_RS#2
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
CPU_PROCHOT#
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
H_IERR#
TP78 TPAD28
TP87 TPAD28
TP86 TPAD28
TP77 TPAD28
TP85 TPAD28
TP76 TPAD28
TP81 TPAD28
TP82 TPAD28
TP83 TPAD28
TP84 TPAD28
TP91 TPAD28
TP88 TPAD28
TP89 TPAD28
1D05V_S0
H_RS#[2..0] 6
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BREQ#0 6
H_INIT# 15
H_LOCK# 6
H_CPURST# 6
H_TRDY# 6
H_HIT# 6
H_HITM# 6
H_THERMDA 19
H_THERMDC 19
PM_THRMTRIP-I# 7,15,19
CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3
1D05V_S0
3D3V_S0
1 2
AG1-910-01
R261
56R2J-4-GP
Place testpoint on
H_IERR# with a GND
0.1" away
PM_THRMTRIP#
should connect to
ICH6 and Alviso
without T-ing
( No stub)
CPU_SEL0 3,7
AG1-910-01
AG1-A-SA
TP90 TPAD28
R283
1KR2F-3-GP
R282
2KR3F-L-GP
C
1D05V_S0
1 2
1 2
To V-CORE SWITCH
R264
1 2
DY
TP80 TPAD28
TP94 TPAD28
TP93 TPAD28
TP49 TPAD28
Layout Note:
0.5" max length.
BSEL[1:0] Freq.(MHz)
(A Stepping)
L L 100
L H 133
BSEL[1:0] Freq.(MHz)
(B Stepping)
L H 100
L L 133
TP92
TPAD28
0R3-0-U-GP
GTLREF0
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
C23
C22
D25
H23
G25
M26
H24
G24
M23
N24
M25
H26
N25
K25
K24
C16
C14
AF7
AC1
E26
AD26
L23
F25
J23
J25
L26
L24
J26
E1
C3
U41B
TUALA-SKT-1
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
DATA GRP 0 DATA GRP 1
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
PSI#
BSEL0
BSEL1
MISC
RSVD2
RSVD3
RSVD4
RSVD5
GTLREF0
62.10053.061
CONNECTOR
Y
D
Y26
D32#
AA24
D33#
T25
D34#
U23
D35#
V23
D36#
R24
D37#
R26
D38#
R23
D39#
AA23
D40#
U26
D41#
V24
D42#
U25
D43#
V26
D44#
DATA GRP 2
Y23
D45#
AA26
D46#
Y25
D47#
W25
DSTBN2#
W24
DSTBP2#
T24
DINV2#
AB25
D48#
AC23
D49#
AB24
D50#
AC20
D51#
AC22
D52#
AC25
D53#
AD23
D54#
AE22
D55#
AF23
D56#
AD24
D57#
AF20
D58#
AE21
D59#
AD21
D60#
DATA GRP 3
AF25
D61#
AF22
D62#
AF26
D63#
AE24
DSTBN3#
AE25
DSTBP3#
AD20
DINV3#
P25
COMP0
P26
COMP1
AB2
COMP2
AB1
COMP3
G1
DPRSTP#
B7
DPSLP#
C19
DPWR#
SLP#
TEST1
TEST2
E4
A6
C5
F23
PWRGOOD
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
TEST1
TEST2
H_DSTBN#3
H_DSTBP#3
H_DINV#3
AG1-910-01
R281 27D4R2F-L1-GP
1 2
R279 54D9R2F-L1-GP
1 2
R287 27D4R2F-L1-GP
1 2
R284 54D9R2F-L1-GP
1 2
H_DPRSLP# 15
H_DPSLP# 15
H_DPWR# 6
H_CPUSLP# 6,15
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
TP79 TPAD28
TP51 TPAD28
H_D#[63..0] 6
H_DINV#[3..0] 6
H_DSTBN#[3..0] 6
H_DSTBP#[3..0] 6
1D05V_S0
1 2
R154
200R2F-L-GP
AG1-910-01
H_PW R GD 15,19
AG1-A-SA
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
CPU (1 of 2)
AG1(Alviso) 01
44 0 Monday, October 31, 2005
E
of
Page 5
A
VCC_CORE_S0
U41C
TUALA-SKT-1
AA11
VCC0
AA13
VCC1
AA15
VCC2
AA17
VCC3
AA19
VCC4
AA21
VCC5
AA5
VCC6
4 4
3 3
2 2
1 1
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
D6
D8
E17
E19
E21
E5
E7
E9
F18
F20
F22
F6
F8
G21
Layout Note:
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
62.10053.061
CONNECTOR
Y
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCCA0
VCCA1
VCCA2
VCCA3
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCQ0
VCCQ1
VID0
VID1
VID2
VID3
VID4
VID5
VCCSENSE
VSSSENSE
VCCSENSE and VSSSENSE lines
should be of equal length.
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6
F26
B1
N1
AC26
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21
P23
W4
E2
F2
F3
G3
G4
H4
AE7
AF6
VCC_CORE_S0
1D05V_S0
TP_VCCSENSE
TP_VSSSENSE
AG1-A-SA
SCD01U16V2KX-3GP
C311
H_VID0 34
H_VID1 34
H_VID2 34
H_VID3 34
H_VID4 34
H_VID5 34
1D5V_S0
1 2
TP58 TPAD28
TP59 TPAD28
VCC_CORE_S0
A
1 2
C161
SC10U10V5ZY-1GP
1D05V_S0
1 2
VCC_CORE_S0
1 2
1 2
DY
AG1-910-SB
VCC_CORE_S0
1 2
B
1 2
C178
C168
C167
C202
C187
DY
SCD1U16V2ZY-2GP
1 2
1 2
C169
SC10U6D3V5KX-1GP
1 2
1 2
C166
SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
SC10U6D3V5KX-1GP
SCD1U16V2ZY-2GP
SC10U6D3V5KX-1GP
B
1 2
1 2
C196
SC10U6D3V5KX-1GP
C209
SCD1U16V2ZY-2GP
C163
DY
C177
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C194
SC10U6D3V5KX-1GP
1 2
1 2
C213
SCD1U16V2ZY-2GP
DY
1 2
1 2
C180
SCD1U16V2ZY-2GP
1 2
C211
C200
SCD1U16V2ZY-2GP
C
1 2
C164
TC8
DY
SCD1U16V2ZY-2GP
ST100U6D3VBM-9GP
AG1-A-SA
1 2
1 2
C201
C203
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C
D
U41D TUALA-SKT-1
A2
VSS0
A5
VSS1
A8
VSS2
A11
VSS3
A14
VSS4
A17
VSS5
A20
VSS6
A23
VSS7
A26
VSS8
AA1
VSS9
AA4
VSS10
AA6
VSS11
AA8
VSS12
AA10
VSS13
AA12
VSS14
AA14
VSS15
AA16
VSS16
AA18
VSS17
AA20
VSS18
AA22
VSS19
AA25
VSS20
AB3
VSS21
AB5
VSS22
AB7
VSS23
AB9
VSS24
AB11
VSS25
AB13
VSS26
AB15
VSS27
AB17
VSS28
AB19
VSS29
AB21
VSS30
AB23
VSS31
AB26
VSS32
AC2
VSS33
AC5
VSS34
AC8
VSS35
AC10
VSS36
AC12
VSS37
AC14
VSS38
AC16
VSS39
AC18
VSS40
AC21
VSS41
AC24
VSS42
AD1
VSS43
AD4
VSS44
AD7
VSS45
AD9
VSS46
AD11
VSS47
AD13
VSS48
AD15
VSS49
AD17
VSS50
AD19
VSS51
AD22
VSS52
AD25
VSS53
AE3
VSS54
AE6
VSS55
AE8
VSS56
AE10
VSS57
AE12
VSS58
AE14
VSS59
AE16
VSS60
AE18
VSS61
AE20
VSS62
AE23
VSS63
AE26
VSS64
AF2
VSS65
AF5
VSS66
AF9
VSS67
AF11
VSS68
AF13
VSS69
AF15
VSS70
AF17
VSS71
AF19
VSS72
AF21
VSS73
AF24
VSS74
B3
VSS75
B6
VSS76
B9
VSS77
B12
VSS78
B16
VSS79
B19
VSS80
B22
VSS81
B25
VSS82
C1
VSS83
C4
VSS84
C7
VSS85
C10
VSS86
C13
VSS87
C15
VSS88
C18
VSS89
C21
VSS90
C24
VSS91
D2
VSS92
D5
VSS93
D7
VSS94
D9
VSS95
D11
<Core Design>
Title
Size Document Number Rev
A3
D
Date: Sheet
VSS96
CPU (2 of 2)
AG1(Alviso) 01
E
D13
VSS97
D15
VSS98
D17
VSS99
D19
VSS100
D21
VSS101
D23
VSS102
D26
VSS103
E3
VSS104
E6
VSS105
E8
VSS106
E10
VSS107
E12
VSS108
E14
VSS109
E16
VSS110
E18
VSS111
E20
VSS112
E22
VSS113
E25
VSS114
F1
VSS115
F4
VSS116
F5
VSS117
F7
VSS118
F9
VSS119
F11
VSS120
F13
VSS121
F15
VSS122
F17
VSS123
F19
VSS124
F21
VSS125
F24
VSS126
G2
VSS127
G6
VSS128
G22
VSS129
G23
VSS130
G26
VSS131
H3
VSS132
H5
VSS133
H21
VSS134
H25
VSS135
J1
VSS136
J4
VSS137
J6
VSS138
J22
VSS139
J24
VSS140
K2
VSS141
K5
VSS142
K21
VSS143
K23
VSS144
K26
VSS145
L3
VSS146
L6
VSS147
L22
VSS148
L25
VSS149
M1
VSS150
M4
VSS151
M5
VSS152
M21
VSS153
M24
VSS154
N3
VSS155
N6
VSS156
N22
VSS157
N23
VSS158
N26
VSS159
P2
VSS160
P5
VSS161
P21
VSS162
P24
VSS163
R1
VSS164
R4
VSS165
R6
VSS166
R22
VSS167
R25
VSS168
T3
VSS169
T5
VSS170
T21
VSS171
T23
VSS172
T26
VSS173
U2
VSS174
U6
VSS175
U22
VSS176
U24
VSS177
V1
VSS178
V4
VSS179
V5
VSS180
V21
VSS181
V25
VSS182
W3
VSS183
W6
VSS184
W22
VSS185
W23
VSS186
W26
VSS187
Y2
VSS188
Y5
VSS189
Y21
VSS190
Y24
VSS191
CONNECTOR Y
62.10053.061
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
54 0 Monday, October 17, 2005
E
of
Page 6
A
H_XRCOMP
1 2
R290
24D9R2F-L-GP
AG1-910-01
4 4
1D05V_S0
54D9R2F-L1-GP
R291
AG1-910-01
1 2
H_XSCOMP
1D05V_S0
1 2
R288
221R2F-2-GP
H_XSWING
3 3
100R2F-L1-GP-U
AG1-910-01
R289
1 2
1 2
H_YRCOMP
R292
24D9R2F-L-GP
1 2
C331
SCD1U16V2ZY-2GP
AG1-910-01
1D05V_S0
2 2
1D05V_S0
R293
100R2F-L1-GP-U
AG1-910-01
54D9R2F-L1-GP
R295
1 2
H_YSCOMP
1 2
R294
221R2F-2-GP
1 2
AG1-910-01
H_YSWING
1 2
C335
SCD1U16V2ZY-2GP
B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
C
U38A
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
C1
C2
D1
T1
L1
P1
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HOST
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
71.0GMCH.08U
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB#0
HADSTB#1
HVREF
HBNR#
HBPRI#
HBREQ0#
HCPURST#
HCLKINN
HCLKINP
HDBSY#
HDEFER#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS0#
HRS1#
HRS2#
HCPUSLP#
HTRDY#
G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
F8
B9
E13
J11
A5
D5
E7
H10
AB1
AB2
C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_VREF
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
TP_H_EDRDY#
TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
D
H_A#[31..3] 4 H_D#[63..0] 4
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_CPURST# 4
CLK_MCH_BCLK# 3
CLK_MCH_BCLK 3
H_DBSY# 4
H_DEFER# 4
H_DPWR# 4
H_DRDY# 4
TP57 TPAD28
H_HIT# 4
H_HITM# 4
H_LOCK# 4
TP55 TPAD28
H_CPUSLP# 4,15
H_TRDY# 4
1 2
C186
SCD1U16V2ZY-2GP
1D05V_S0
1 2
1 2
H_DINV#[3..0] 4
H_DSTBN#[3..0] 4
H_DSTBP#[3..0] 4
H_REQ#[4..0] 4
H_RS#[2..0] 4
E
R172
100R2F-L1-GP-U
R175
200R2F-L-GP
AG1-910-01
1 1
Place them near to the chip
A
B
C
D
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
GMCH (1 of 5)
AG1(Alviso) 01
64 0 Tuesday, October 25, 2005
E
of
Page 7
A
U38B
DMI_TXN0
DMI_TXN0 16
M_CLK_DDR0 11
M_CLK_DDR1 11
M_CLK_DDR3 11
M_CLK_DDR4 11
M_CLK_DDR#0 11
M_CLK_DDR#1 11
M_CLK_DDR#3 11
M_CLK_DDR#4 11
1 2
DDR_VREF_S3
1 2
C304 SC2D2U6D3V3MX-1-GP
DMI_TXN1 16
DMI_TXN2 16
DMI_TXN3 16
DMI_TXP0 16
DMI_TXP1 16
DMI_TXP2 16
DMI_TXP3 16
DMI_RXN0 16
DMI_RXN1 16
DMI_RXN2 16
DMI_RXN3 16
DMI_RXP0 16
DMI_RXP1 16
DMI_RXP2 16
DMI_RXP3 16
M_CKE0 11,12
M_CKE1 11,12
M_CKE2 11,12
M_CKE3 11,12
M_CS#0 11,12
M_CS#1 11,12
M_CS#2 11,12
M_CS#3 11,12
M_OCDCOMP0
M_OCDCOMP1
M_ODT0 11,12
M_ODT1 11,12
M_ODT2 11,12
M_ODT3 11,12
1 2
1 2
BC4 SCD1U16V2ZY-2GP
C219 SC2D2U6D3V3MX-1-GP
M_RCOMPN
M_RCOMPP
SMXSLEW
SMYSLEW
1 2
BC2 SCD1U16V2ZY-2GP
4 4
3 3
Layout Note:
Route as short
as possible
1 2
R168
R155
40D2R2F-GP
40D2R2F-GP
2 2
1 1
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
2D5V_S0
1D8V_S3
1 2
1 2
AA31
DMIRXN0
AB35
DMIRXN1
AC31
DMIRXN2
AD35
DMIRXN3
Y31
DMIRXP0
AA35
DMIRXP1
AB31
DMIRXP2
AC35
DMIRXP3
AA33
DMITXN0
AB37
DMITXN1
AC33
DMITXN2
AD37
DMITXN3
Y33
DMITXP0
AA37
DMITXP1
AB33
DMITXP2
AC37
DMITXP3
AM33
SM_CK0
AL1
SM_CK1
AE11
SM_CK2
AJ34
SM_CK3
AF6
SM_CK4
AC10
SM_CK5
AN33
SM_CK0#
AK1
SM_CK1#
AE10
SM_CK2#
AJ33
SM_CK3#
AF5
SM_CK4#
AD10
SM_CK5#
AP21
SM_CKE0
AM21
SM_CKE1
AH21
SM_CKE2
AK21
SM_CKE3
AN16
SM_CS0#
AM14
SM_CS1#
AH15
SM_CS2#
AG16
SM_CS3#
AF22
SM_OCDCOMP0
AF16
SM_OCDCOMP1
AP14
SM_ODT0
AL15
SM_ODT1
AM11
SM_ODT2
AN10
SM_ODT3
AK10
SMRCOMPN
AK11
SMRCOMPP
AF37
SMVREF0
AD1
SMVREF1
AE27
SMXSLEWIN
AE28
SMXSLEWOUT
AF9
SMYSLEWIN
AF10
SMYSLEWOUT
AG1-A-SA
2 3
1
R171
80D6R2F-L-GP
R173
80D6R2F-L-GP
71.0GMCH.08U
SRN10KJ-5-GP
4
RN24
M_RCOMPN
M_RCOMPP
DMI
DDR MUXING
PM_EXTTS#0
PM_EXTTS#1
A
CFG/RSVD
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PM
PWROK
RSTIN#
DREF_CLKN
DREF_CLKP
DREF_SSCLKN
CLK
DREF_SSCLKP
NC
B
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
B
1D05V_S0
R166
10KR2J-3-GP
CFG0
G16
H13
G14
F16
F15
G15
CFG6
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
VGATE_PWRGD
J23
PM_EXTTS#0
J21
PM_EXTTS#1
H22
F5
AD30
AE29
1 2
R152 100R2J-2-GP
A24
A23
C37
D37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
1 2
AG1-910-01
AG1-910-01
10KR2J-2-GP
DY
2K2R2J-2-GP
R254
CFG[2:0] Freq.(MHz)
101 400
001 533
CPU_SEL1 3
CPU_SEL0 3,4
R165
1 2
AG1-910-01
GMCH_VSYNC 14
GMCH_HSYNC 14
1 2
AG1-910-01
PM_BMBUSY# 16
PM_THRMTRIP-I# 4,15,19
VGATE_PWRGD 16,32
PLT_RST1# 16,18,29
DREFCLK# 3
DREFCLK 3
DREFSSCLK# 3
DREFSSCLK 3
AG1-910-01
C
Alviso will provide SDVO_CTRLCLK
and CTRLDATA pulldowns on-die
GMCH_DDCCLK 14
GMCH_DDCDATA 14
GMCH_BLUE 14
R158 150R2F-1-GP
1 2
GMCH_GREEN 14
R157 150R2F-1-GP
1 2
GMCH_RED 14
R162 150R2F-1-GP
1 2
R159 39R2J-L-GP
R156 39R2J-L-GP
AG1-910-SB
C
TP50 TPAD28
TP48 TPAD28
CLK_MCH_3GPLL# 3
CLK_MCH_3GPLL 3
1 2
1 2
1 2
R161
261R2F-GP
BL_ON 29
CLK_DDC_EDID 13
DAT_DDC_EDID 13
GMCH_LCDVDD_ON 13
TP42 TPAD28
TP44 TPAD28
TP46 TPAD28
GMCH_TXACLK- 13
GMCH_TXACLK+ 13
GMCH_TXBCLK- 13
GMCH_TXBCLK+ 13
GMCH_TXAOUT0- 13
GMCH_TXAOUT1- 13
GMCH_TXAOUT2- 13
GMCH_TXAOUT0+ 13
GMCH_TXAOUT1+ 13
GMCH_TXAOUT2+ 13
GMCH_TXBOUT0- 13
GMCH_TXBOUT1- 13
GMCH_TXBOUT2- 13
GMCH_TXBOUT0+ 13
GMCH_TXBOUT1+ 13
GMCH_TXBOUT2+ 13
LCTLA_CLK
LCTLB_DATA
CLK_DDC_EDID
DAT_DDC_EDID
BL_ON
LBKLT_CRTL
LIBG
SDVOC_CTRLDATA
SDVOC_CTRLCLK
AG1-A-SA
DY
RN21
1
2 3
SRN2K2J-1-GP
RN23
1
2 3
SRN2K2J-1-GP
1
2 3
SRN100KJ-6-GP
R271 1K5R2F-2-GP
1 2
AG1-910-01
HSYNC
CRTIREF
VSYNC
LBKLT_CRTL
LCTLA_CLK
LCTLB_DATA
CLK_DDC_EDID
DAT_DDC_EDID
LIBG
L_LVBG
L_VREFH
L_VREFL
2D5V_S0
4
4
RN22
4
AB29
AC29
H24
H25
A15
C16
A17
J18
B15
B16
B17
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
J20
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
B30
B29
C25
C24
B34
B33
B32
A34
A33
B31
C29
D28
C27
C28
D27
C26
U38G
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
LBKLT_CRTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LADATAN0
LADATAN1
LADATAN2
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
71.0GMCH.08U
D
MISC TV VGA LVDS
D
EXP_COMPI
EXP_ICOMPO
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
PCI-EXPRESS GRAPHICS
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
E
1D5V_PCIE_S0
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
R366
1 2
24D9R2F-L-GP
AG1-910-01
<Core Design>
Wistron Corporation
21F, 88, Sec .1, Hs in Ta i W u R d., Hs ichih,
Title
Size Document Number Re v
Custom
Date: Sheet
Taipei Hsi en 221, Taiwan, R.O.C .
GMCH (2 of 5)
AG1(Alviso) 01
74 0 Tuesday, October 25, 2005
E
of
Page 8
A
4 4
B
C
D
E
M_A_DQ[63..0] 11 M_B_DQ[63..0] 11
3 3
2 2
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
U38C
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
AK15
SA_BS0#
AK16
SA_BS1#
AL21
SA_BS2#
AJ37
SA_DM0
AP35
SA_DM1
AL29
SA_DM2
AP24
SA_DM3
AP9
SA_DM4
AP4
SA_DM5
AJ2
SA_DM6
AD3
SA_DM7
AK36
SA_DQS0
AP33
SA_DQS1
AN29
SA_DQS2
AP23
SA_DQS3
AM8
SA_DQS4
AM4
SA_DQS5
AJ1
SA_DQS6
AE5
SA_DQS7
AK35
SA_DQS0#
AP34
SA_DQS1#
AN30
SA_DQS2#
AN23
SA_DQS3#
AN8
SA_DQS4#
AM5
SA_DQS5#
AH1
SA_DQS6#
AE4
SA_DQS7#
AL17
SA_MA0
AP17
SA_MA1
AP18
SA_MA2
AM17
SA_MA3
AN18
SA_MA4
AM18
SA_MA5
AL19
SA_MA6
DDR SYSTEM MEMORY A
SA_RCVENIN#
SA_RCVENOUT#
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_WE#
AP20
AM19
AL20
AM16
AN20
AM20
AM15
AN15
AP16
AF29
AF28
AP15
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
SA_RCVENIN#
SA_RCVENOUT#
Place Test PAD Near to Chip
as could as possible
M_A_BS#0 11,12
M_A_BS#1 11,12
M_A_BS#2 11,12
M_A_DM[7..0] 11
M_A_DQS[7..0] 11
M_A_DQS#[7..0] 11
M_A_A[13..0] 11,12
M_A_CAS# 11,12
M_A_RAS# 11,12
TP43 TPAD28
TP47 TPAD28 TP52 TPAD28
M_A_WE# 11,12
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AK9
AK6
AH5
AK8
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
U38D
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
AJ9
SBDQ38
SBDQ39
AJ7
SBDQ40
SBDQ41
AJ4
SBDQ42
SBDQ43
SBDQ44
AJ8
SBDQ45
AJ5
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
DDR SYSTEM MEMORY B
SB_RCVENIN#
SB_RCVENOUT#
SB_BS0#
SB_BS1#
SB_BS2#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_WE#
AJ15
AG17
AG21
M_B_DM0
AF32
M_B_DM1
AK34
M_B_DM2
AK27
M_B_DM3
AK24
M_B_DM4
AJ10
M_B_DM5
AK5
M_B_DM6
AE7
M_B_DM7
AB7
M_B_DQS0
AF34
M_B_DQS1
AK32
M_B_DQS2
AJ28
M_B_DQS3
AK23
M_B_DQS4
AM10
M_B_DQS5
AH6
M_B_DQS6
AF8
M_B_DQS7
AB4
M_B_DQS#0
AF35
M_B_DQS#1
AK33
M_B_DQS#2
AK28
M_B_DQS#3
AJ23
M_B_DQS#4
AL10
M_B_DQS#5
AH7
M_B_DQS#6
AF7
M_B_DQS#7
AB5
M_B_A0
AH17
M_B_A1
AK17
M_B_A2
AH18
M_B_A3
AJ18
M_B_A4
AK18
M_B_A5
AJ19
M_B_A6
AK19
M_B_A7
AH19
M_B_A8
AJ20
M_B_A9
AH20
M_B_A10
AJ16
M_B_A11
AG18
M_B_A12
AG20
M_B_A13
AG15
AH14
AK14
SB_RCVENIN#
AF15
SB_RCVENOUT#
AF14
AH16
Place Test PAD Near to Chip
ascould as possible
M_B_BS#0 11,12
M_B_BS#1 11,12
M_B_BS#2 11,12
M_B_DM[7..0] 11
M_B_DQS[7..0] 11
M_B_DQS#[7..0] 11
M_B_A[13..0] 11,12
M_B_CAS# 11,12
M_B_RAS# 11,12
TP54 TPAD28
M_B_WE# 11,12
71.0GMCH.08U
1 1
A
B
C
71.0GMCH.08U
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
D
Date: Sheet
GMCH (3 of 5)
AG1(Alviso) 01
84 0 Monday, October 17, 2005
E
of
Page 9
A
4 4
B
2D5V_TVDAC_S0
SCD1U16V2ZY-2GP
C313
C
1D5V_S0
R274
1 2
0R0603-PAD
2D5V_S0 2D5V_ALVDS_S0
R272
1 2
0R0603-PAD
2D5V_S0
R275
1 2
C312
1 2
0R0603-PAD
1 2
2D5V_S0 2D5V_TXLVDS_S0
R273
1 2
0R0603-PAD
1D5V_DLVDS_S0
1 2
C310
SC10U10V5ZY-1GP
1 2
C309
SCD01U16V2KX-3GP
1 2
C143
SC4D7U10V5ZY-3GP
D
1D5V_DDRDLL_S0
1 2
C315
ST100U6D3VBM-9GP
1D5V_PCIE_S0
1 2
C126
SC10U10V5ZY-1GP
E
1 2
1 2
R160
0R0603-PAD
R142
0R0603-PAD
1D5V_S0
1D5V_S0
1 2
AC11
VCCSM57
VCCSM58
VTT16
VTT17
R10
1 2
C216
SCD1U16V2ZY-2GP
1 2
C330
SCD1U16V2ZY-2GP
2D5V_TXLVDS_S0
V1.8_DDR_CAP4
V1.8_DDR_CAP3
V1.8_DDR_CAP6
B28
A28
AB11
AB10
VCCSM59
VCCSM60
VTT18
VTT19
P10
N10
2D5V_S0
AB9
M10
1D05V_S0
AP8
VCCSM61
VTT20
K10
AG1-910-SB
A27
AM1
AE1
VCCSM62
VCCSM63
VCCSM64
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VTT21
VTT22
VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51
J10
SCD47U10V3ZY-GP
R278
1 2
1KR2J-1-GP
DY
D
AE37
W37
U37
R37
N37
L37
VCC3G0
VCC3G1
VCC3G2
1D05V_S0
VCC3G3
VCC3G4
VCCP_GMCH_CAP1
1 2
J37
VCC3G5
VCC3G6
C325
1D05V_S0
AF20
AP19
AF19
AF18
VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3
C324
D27
2 1
SSM5818SLPT-GP
DY
SC4D7U10V5ZY-3GP
<Core Design>
Title
Size Document Number Rev
A3
Date: Sheet
C185
1D5V_3GPLL_S0
1 2
Y27
Y29
Y28
F37
VCCA_3GBG
VCCA_3GPLL2
VCCA_3GPLL0
VCCA_3GPLL1
SCD47U10V3ZY-GP
1 2
C328
1 2
C142
SC10U10V5ZY-1GP
2D5V_3GBG_S0 2D5V_S0
1 2
G37
VSSA_3GBG
G1
VCCP_GMCH_CAP3
VCCP_GMCH_CAP4
VCCP_GMCH_CAP2
1 2
1 2
SCD22U16V3ZY-GP
1 2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
R153
1 2
0R0603-PAD
1 2
0R0603-PAD
C305
SCD1U16V2ZY-2GP
U38E
71.0GMCH.08U
Route ASSA3GBG gnd from GMCH to
decoupling cap groung lead and
then connect to the gnd plane
C329
SCD22U16V3ZY-GP
1 2
C210
SC2D2U6D3V3MX-1-GP
GMCH (4 of 5)
AG1(Alviso) 01
94 0 Monday, October 17, 2005
E
1D5V_S0
R253
C184
SCD1U16V2ZY-2GP
of
SCD1U16V2ZY-2GP
C133
2D5V_ALVDS_S0
B22
B21
A21
VCCHV0
VCCHV1
VCCHV2
VCCA_LVDS
VCC17
VCC18
VCC19
VCC20
VCC21
T27
V27
U27
R27
AG1-910-SB
1 2
0R0805-PAD
1 2
0R0805-PAD
1 2
0R0805-PAD
1 2
0R0805-PAD
1 2
SCD1U16V2ZY-2GP
C131
1 2
V1.8_DDR_ CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
AM37
AH37
AP29
AD28
VCCSM0
VCCSM1
VCCSM2
VCC22
VCC23
VCC24
VCC25
L27
P27
K27
N27
M27
R178
0R0805-PAD
L5
L3
L13
L12
Note: All VCCSM
pins shorted
internally
1 2
C151
SCD1U16V2ZY-2GP
AD27
AC27
AP26
AN26
AM26
AL26
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
J27
J25
K26
K25
H27
H26
1 2
1 2
C141
SC10U10V5ZY-1GP
1 2
C136
SC10U10V5ZY-1GP
1 2
C226
SC10U10V5ZY-1GP
1 2
C225
SC10U10V5ZY-1GP
1D5V_DLVDS_S0 1D8V_S3
3 3
H17
D19
G18
F18
E18
F17
E17
D18
C18
H18
VSSA_TVBG
N29
VCCA_TVDACB0
VCC2
C195
M29
VCCA_TVDACB1
VCC3
VCCA_TVBG
VCCA_TVDACC0
VCC4
K29
SCD1U16V2ZY-2GP
VCCD_TVDAC
VCCA_TVDACC1
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
J29
T28
V28
P28
U28
R28
N28
1 2
C144
SCD1U16V2ZY-2GP
Route ASSATVBG gnd from GMCH to
decoupling cap groung lead and
then connect to the gnd plane
VCC 1D05_S0 for low speed
graphic clock.1D5V_S0 for
high speed clock.default
1 2
use 1D05V_S0
1D05V_S0
1 2
C157
SC4D7U6D3V3KX-GP
1 2
1 2
C176
SC4D7U6D3V3KX-GP
C172
C145
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
2 2
1 1
VCCA_TVDACA0
VCCA_TVDACA1
VCC0
VCC1
T29
R29
1 2
1 2
C154
SCD1U16V2ZY-2GP
VCCDQ_TVDAC
VCC11
M28
B26
VCC12
L28
1 2
B25
VCCD_LVDS0
VCCD_LVDS1
VCC13
VCC14
K28
C162
1D5V_S0
A25
VCCD_LVDS2
VCC15
J28
H28
SCD1U16V2ZY-2GP
A35
VCC16
G28
AK26
K24
AJ26
VCCSM10
VCC33
K23
AH26
VCCSM11
VCC34
K22
AG26
VCCSM12
VCC35
K21
AF26
VCCSM13
VCC36
W20
AE26
VCCSM14
VCC37
U20
SC10U10V5ZY-1GP
AP25
VCCSM15
VCC38
T20
AN25
VCCSM16
VCC39
K20
VCCSM17
VCC40
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
POWER
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
T18
V19
K19
V18
K18
U19
1 2
C150
SCD1U16V2ZY-2GP
1 2
C135
SCD1U16V2ZY-2GP
1 2
C334
SCD1U16V2ZY-2GP
1 2
C333
SCD1U16V2ZY-2GP
K17
W18
1D5V_HMPLL_S0
1D5V_DPLLA_S0
1D5V_DPLLB_S0
1D5V_HPLL_S0
1D5V_MPLL_S0
AE24
VCCSM25
VCC48
Note: All VCCSM
SCD1U16V2ZY-2GP
AM12
AL12
AK12
AJ12
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VTT7
VTT8
VTT9
VTT10
L11
P11
N11
M11
1 2
1 2
SCD1U16V2ZY-2GP
1 2
SCD1U16V2ZY-2GP
pins shorted
internally
C323
AH12
AG12
AF12
AE12
AD11
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VTT11
VTT12
VTT13
VTT14
VTT15
T10
K11
V10
U10
W10
R276
1 2
DY
0R3-0-U-GP
R277
1 2
0R0603-PAD
C314
C319
Route VSSA_CRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.
1 2
AE23
AE22
VCCSM26
VCCSM27
VCCH_MPLL1
AC2
AC1
1 2
C316
SC10U10V5ZY-1GP
AE21
AE20
AE19
AE18
AE17
AE16
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCH_MPLL0
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
F19
B23
C35
AA1
AA2
C317
SC10U10V5ZY-1GP
AE15
AE14
AP13
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
E19
G19
1 2
C321
SC10U10V5ZY-1GP
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCC_SYNC
VTT0
VTT1
VTT2
VTT3
VTT4
J13
K13
K12
H20
GMCH_VCC_SYNC
SC4D7U6D3V3KX-GP
V11
U11
W11
2D5V_CRTDAC_S0
C318
R163
1 2
0R0402-PAD
Layout Notes: VSSA_CRTDAC
Route caps within 250mil
of Alviso. Route FB
within 3" of Alviso.
AP12
VCCSM46
VTT5
T11
AN12
VCCSM47
VTT6
R11
DY
A
B
C
Page 10
A
H29
G29
F29
E29
D29
A29
AC28
AB28
AA28
W28
E28
AN27
AL27
AJ27
AG27
AF27
AB27
AA27
W27
G27
E27
B27
J26
G26
E26
A26
AN24
U38F
4 4
AL24
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
B
V31
U31
T31
R31
P31
N31
M31
L31
K31
J31
H31
G31
F31
E31
D31
AP30
AE30
AC30
AB30
AA30
Y30
C30
AM29
AJ29
AG29
AD29
AA29
W29
V29
U29
P29
L29
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
W31
C
C34
AL33
AF33
AD33
W33
V33
U33
T33
R33
P33
N33
M33
L33
K33
J33
H33
G33
F33
E33
D33
AN32
AJ32
AD32
AC32
AB32
AA32
Y32
C32
A32
AL31
AG31
AD31
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
D
AF36
AE36
AD36
AC36
AB36
AA36
C36
AE35
Y35
W35
V35
U35
T35
R35
P35
N35
M35
L35
K35
J35
H35
G35
F35
E35
D35
B35
AN34
AH34
AD34
AC34
AB34
AA34
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
E
AG37
Y37
V37
T37
P37
M37
K37
H37
E37
AN36
AL36
AJ36
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS
VSS196
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
J24
F24
B24
D24
AJ24
AG24
B36
71.0GMCH.08U
VSS259P2VSS258T2VSS257V2VSS256
VSS255
VSS254
VSS253
VSS252
VSS251A3VSS250C3VSS249
VSS248
VSS247
VSS246
AA3
AB3
AC3
VSS245C4VSS244H4VSS243L4VSS242P4VSS241U4VSS240Y4VSS239
AJ3
VSSALVDS
VSS260L2VSS268J2VSS269G2VSS270D2VSS271
Y1
AL2
AE2
AD2
AH2
AN2
AF4
VSS238
VSS237E5VSS236W5VSS235
VSS234
VSS233B6VSS232J6VSS231L6VSS230P6VSS229T6VSS228
AL5
AP5
AN4
AA6
VSS227
VSS226
VSS225
VSS224G7VSS223V7VSS222
VSS221
VSS220
VSS219
VSS218C8VSS217E8VSS216L8VSS215P8VSS214Y8VSS213
VSS212A9VSS211H9VSS210K9VSS209T9VSS208V9VSS207
AJ6
AE6
AA7
AC6
AK7
AN7
AG7
AL8
AA9
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
J12
L10
F11
Y11
Y10
D10
AE9
AC9
AH9
AN9
H11
AA11
AA10
B12
AJ11
AL11
AF11
AN11
AG11
D12
J14
F14
A14
B14
K14
K15
A16
K16
C15
D16
AJ14
AL14
AG14
H16
AN14
AL16
C17
G17
A18
AJ17
AF17
AN17
J19
U18
T19
C19
H19
W19
AL18
B18
F20
A20
E20
V20
D20
AN19
AG19
G20
C21
AK20
J22
F21
A22
E22
D22
H23
AF21
AN21
AL22
AF23
AH22
1D8V_S3
1 2
3 3
AD13
AC13
AB13
AD12
AC12
U38H
2 2
71.0GMCH.08U
AB12
VCCSM_NCTF27
VCCSM_NCTF28
VCCSM_NCTF29
VCCSM_NCTF30
VCCSM_NCTF31
1 2
C322
C181
SC10U10V5ZY-1GP
AD17
AC17
AD16
AC16
AD15
AC15
AD14
AC14
VCCSM_NCTF19
VCCSM_NCTF20
VCCSM_NCTF21
VCCSM_NCTF22
VCCSM_NCTF23
VCCSM_NCTF24
VCCSM_NCTF25
VCCSM_NCTF26
1D05V_S0
Place these Hi-Freq decoupling caps near GMCH
VCCSM_NCTF8
VTT_NCTF14
AC23
R12
VCCSM_NCTF7
VTT_NCTF13
C152
AD23
T12
SCD1U16V2ZY-2GP
VCCSM_NCTF6
VTT_NCTF12
AC24
U12
AD24
VCCSM_NCTF5
VTT_NCTF11
V12
VCCSM_NCTF4
VTT_NCTF10
AC25
W12
1 2
AD25
VCCSM_NCTF3
VTT_NCTF9
L13
1 2
SCD1U16V2ZY-2GP
AD19
AC19
AD18
AC18
VCCSM_NCTF15
VCCSM_NCTF16
VCCSM_NCTF17
VCCSM_NCTF18
1 2
C175
SCD1U16V2ZY-2GP
AD22
AC22
AD21
AC21
AD20
AC20
VCCSM_NCTF9
VCCSM_NCTF10
VCCSM_NCTF11
VCCSM_NCTF12
VCCSM_NCTF13
VCCSM_NCTF14
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
L12
P12
N12
M12
VCCSM_NCTF2
VTT_NCTF8
AC26
M13
VCCSM_NCTF1
VTT_NCTF7
1 2
C188
AD26
N13
VCCSM_NCTF0
VTT_NCTF6
C160
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
L18
W17
V17
U17
T17
P17
N17
M17
L17
VCC_NCTF71
VCC_NCTF72
VCC_NCTF73
VCC_NCTF74
VCC_NCTF75
VCC_NCTF76
VCC_NCTF77
VCC_NCTF78
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0
T13
P13
V13
R13
U13
W13
VCC_NCTF70
M18
VCC_NTTF69
N18
Y12
1D05V_S0
W26
V26
U26
T26
R26
P26
N26
M26
L26
P18
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
U21
T21
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF48
P22
N22
M22
L22
W21
V21
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
R22
M23
L23
W22
V22
U22
T22
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
V23
U23
T23
R23
P23
N23
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
W23
T24
R24
P24
N24
M24
L24
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
N25
M25
L25
W24
V24
U24
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
P21
N21
M21
L21
Y20
R20
P20
N20
M20
L20
Y19
R19
P19
N19
M19
L19
Y18
R18
W25
V25
U25
T25
R25
P25
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
NCTF
VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0
L14
M14
N14
T14
P14
R14
Y13
AA12
AA13
U14
L15
V14
Y14
W14
AA14
AB14
M15
N15
T15
P15
R15
U15
L16
V15
Y15
W15
AA15
AB15
M16
N16
T16
P16
V16
Y16
R16
U16
W16
Y17
R17
AA16
AB16
AA17
AB17
AA18
AB18
Y21
Y22
Y23
Y24
Y25
R21
AA19
AB19
AA20
AB20
AA21
AB21
AA22
AB22
AA23
AB23
Y26
AA24
AB24
AA25
AB25
AA26
AB26
1 1
A
B
C
D
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet of
GMCH (5 of 5)
AG1(Alviso)
10 40 Monday, October 17, 2005
E
01
Page 11
A
B
C
D
E
AG1-A-SA
2nd
M_B_A[13..0] 8,12
4 4
M_B_BS#2 8,12
M_B_BS#0 8,12
M_B_BS#1 8,12
M_B_DQ[63..0] 8
3 3
2 2
M_B_DQS#[7..0] 8
M_B_DQS[7..0] 8
1 1
C140
M_ODT3 7,12
1 2
DDR_VREF_S3
SC4D7U6D3V3KX-GP
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
1 2
BC1
SCD1U16V2ZY-2GP
A
DM2
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
11
29
49
68
129
146
167
186
13
31
51
70
131
148
169
188
114
119
1
2
202
CONNECTOR
High 5.2mm
2nd source:62.10017.661
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF
VSS
GND
DDR2-200P-5-GP
NC#163/TEST
108
/RAS
109
/WE
113
/CAS
110
/CS0
115
/CS1
79
CKE0
80
CKE1
30
CK0
32
/CK0
164
CK1
166
/CK1
10
DM0
26
DM1
52
DM2
67
DM3
130
DM4
147
DM5
170
DM6
185
DM7
195
SDA
197
SCL
199
VDDSPD
198
SA0
200
SA1
50
NC#50
69
NC#69
83
NC#83
120
NC#120
163
81
VDD
82
VDD
87
VDD
88
VDD
95
VDD
96
VDD
103
VDD
104
VDD
111
VDD
112
VDD
117
VDD
118
VDD
3
VSS
8
VSS
9
VSS
12
VSS
15
VSS
18
VSS
21
VSS
24
VSS
27
VSS
28
VSS
33
VSS
34
VSS
39
VSS
40
VSS
41
VSS
42
VSS
47
VSS
48
VSS
53
VSS
54
NORMAL TYPE
VSS
59
VSS
60
VSS
65
VSS
66
VSS
71
VSS
72
VSS
77
VSS
78
VSS
121
VSS
122
VSS
127
VSS
128
VSS
132
VSS
133
VSS
138
VSS
139
VSS
144
VSS
145
VSS
149
VSS
150
VSS
155
VSS
156
VSS
161
VSS
162
VSS
165
VSS
168
VSS
171
VSS
172
VSS
177
VSS
178
VSS
183
VSS
184
VSS
187
VSS
190
VSS
193
VSS
196
VSS
201
GND
62.10017.771
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
SMBD_ICH_1
SMBC_ICH_1
1 2
R183
B
10KR2J-3-GP
1
2 3
3D3V_S0
AG1-910-01
1D8V_S3
M_B_RAS# 8,12
M_B_WE# 8,12
M_B_CAS# 8,12
M_CS#2 7,12
M_CS#3 7,12
M_CKE2 7,12
M_CKE3 7,12
M_CLK_DDR3 7
M_CLK_DDR#3 7
M_CLK_DDR4 7
M_CLK_DDR#4 7
M_B_DM[7..0] 8
SRN33J-5-GP-U
RN51
4
3D3V_S0
AG1-A-SA
SMBD_ICH 3,18
SMBC_ICH 3,18
M_A_A[13..0] 8,12
M_A_BS#2 8,12
M_A_BS#0 8,12
M_A_BS#1 8,12
M_A_DQ[63..0] 8
M_A_DQS[7..0] 8
M_A_DQS#[7..0] 8
DDR_VREF_S3
SC4D7U6D3V3KX-GP
C307
M_ODT0 7,12
M_ODT1 7,12 M_ODT2 7,12
C
1 2
1 2
BC3
SCD1U16V2ZY-2GP
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
AG1-A-SA
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
DM1
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
/DQS0
29
/DQS1
49
/DQS2
68
/DQS3
129
/DQS4
146
/DQS5
167
/DQS6
186
/DQS7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
ODT0
119
ODT1
1
VREF
2
VSS
202
GND
DDR2-200P-4-GP
CONNECTOR
High 9.2mm
2nd source:62.10017.A61
2nd
108
/RAS
109
/WE
113
/CAS
110
/CS0
115
/CS1
79
CKE0
80
CKE1
30
CK0
32
/CK0
164
CK1
166
/CK1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
VDDSPD
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NORMAL TYPE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
62.10017.761
M_A_DM0
10
M_A_DM1
26
M_A_DM2
52
M_A_DM3
67
M_A_DM4
130
M_A_DM5
147
M_A_DM6
170
M_A_DM7
185
SMBD_ICH_1
195
SMBC_ICH_1
197
199
198
SA0
200
SA1
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
D
3D3V_S0
1D8V_S3
M_A_RAS# 8,12
M_A_WE# 8,12
M_A_CAS# 8,12
M_CS#0 7,12
M_CS#1 7,12
M_CKE0 7,12
M_CKE1 7,12
M_CLK_DDR0 7
M_CLK_DDR#0 7
M_CLK_DDR1 7
M_CLK_DDR#1 7
M_A_DM[7..0] 8
<Core Design>
Title
Size Document Number Rev
Custom
Date: Sheet
Wistron Corporation
21F, 88, Sec .1, Hs in Ta i W u R d., Hs ichih,
Taipei Hsi en 221, Taiwan, R.O.C .
DDR Socket
AG1(Alviso)
E
11 40 Tuesday, October 25, 2005
01
of
Page 12
A
PARALLEL TERMINATION
DDR_VREF
R177 56R2J-4-GP
1 2
R179 56R2J-4-GP
1 2
RN43
SRN56J-4-GP
RN30
SRN56J-2-GP
RN34
SRN56J-2-GP
RN42
SRN56J-2-GP
RN37
SRN56J-2-GP
RN33
SRN56J-2-GP
RN38
SRN56J-2-GP
RN39
SRN56J-2-GP
RN36
SRN56J-2-GP
RN40
SRN56J-2-GP
RN31
SRN56J-2-GP
RN32
SRN56J-2-GP
RN35
SRN56J-2-GP
1
2 3
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
4
4 4
8
7
6
8
7
6
8
7
6
8
3 3
2 2
1 1
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
Put decap near power(0.9V) and pull-up resistor
AG1-910-01
M_CKE0 7,11
M_ODT1 7,11
M_CS#3 7,11
M_ODT3 7,11
M_B_A8
M_B_A9
M_B_A12
M_B_A5
M_B_A3
M_B_A10
M_B_A13
M_B_A2
M_B_A0
M_B_A4
M_B_A6
M_B_A7
M_B_A11
M_B_A1
M_A_A13
M_A_A4
M_A_A2
M_A_A0
M_A_A12
M_A_A9
M_A_A8
M_A_A11
M_A_A7
M_A_A6
M_A_A5
M_A_A3
M_A_A1
M_A_A10
M_CKE2 7,11
M_B_BS#2 8,11
M_ODT2 7,11
M_CS#2 7,11
M_B_RAS# 8,11
M_B_BS#1 8,11
M_CKE3 7,11
M_B_BS#0 8,11
M_B_WE# 8,11
M_B_CAS# 8,11
M_A_RAS# 8,11
M_CS#0 7,11
M_ODT0 7,11
M_A_BS#1 8,11
M_A_BS#0 8,11
M_A_WE# 8,11
M_A_CAS# 8,11
M_CS#1 7,11
M_A_BS#2 8,11
M_CKE1 7,11
A
B
B
M_A_A[13..0] 8,11
M_B_A[13..0] 8,11
DDR_VREF
1D8V_S3
1D8V_S3
1 2
1 2
C245
SCD1U16V2ZY-2GP
1 2
1 2
C237
SCD1U16V2ZY-2GP
1 2
C190
SC2D2U6D3V3MX-1-GP
C
Put decap near power(0.9V)
and pull-up resistor
1 2
C227
C193
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C249
C234
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Place these Caps near DM1
1 2
C197
SC2D2U6D3V3MX-1-GP
Place these Caps near DM2
1 2
C
1 2
C214
SCD1U16V2ZY-2GP
1 2
C198
SCD1U16V2ZY-2GP
1 2
C229
SC2D2U6D3V3MX-1-GP
1 2
1 2
C212
SCD1U16V2ZY-2GP
1 2
1 2
C222
SCD1U16V2ZY-2GP
C192
SC2D2U6D3V3MX-1-GP
D
Decoupling Capacitor
1 2
C207
C238
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
1 2
1 2
C247
C251
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C235
SC2D2U6D3V3MX-1-GP
1 2
C218
SC2D2U6D3V3MX-1-GP
1 2
C204
SCD1U16V2ZY-2GP
1 2
C231
SC2D2U6D3V3MX-1-GP
C205
SCD1U16V2ZY-2GP
1 2
C228
SC2D2U6D3V3MX-1-GP
D
1 2
C199
SCD1U16V2ZY-2GP
1 2
E
C248
SCD1U16V2ZY-2GP
1 2
C224
SC2D2U6D3V3MX-1-GP
C208
SC2D2U6D3V3MX-1-GP
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DDR2 Termination Resistor
Size Document Number Rev
A3
Date: Sheet
AG1(Alviso)
E
of
12 40 Tuesday, October 25, 2005
01
Page 13
AG1-A-SA
LED
LCDVDD
Layout 40 mil
GMCH_LCDVDD_ON 7
GMCH_LCDVDD_ON
R189
1 2
1KR2J-1-GP
SC1U10V3ZY-6GP
C220
LCDVDD_ON_1
1 2
U21
1
OUT
2
GND
ON/OFF#3IN
1 2
AAT4280IGU-1-T1GP
C223
SCD1U16V2ZY-2GP
GND
6
IN
5
4
AG1-910-01
3D3V_S0
1 2
C236
SC1U10V3ZY-6GP
WLAN_LED#
BLT_LED#
LCD/INVERTER/CCD CONN
3D3V_S0 5V_S0
1 2
EC62
SCD1U16V2ZY-2GP
LED BD CONN
BAV99PT-GP-U
3
D26
BAV99PT-GP-U
3
D24
5V_S0
2
DY
1
DY
AG1-910-01 AG1-910-01
WLAN_LED# 28
FRONT_PWRLED# 29,30
STDBY_LED# 29
2
1
CHARGE_LED# 29
DC_BATFULL# 29
BLT_LED# 29
WLAN_LED#
FRONT_PWRLED#
STDBY_LED#
CHARGE_LED#
DC_BATFULL#
BLT_LED#
1 2
R205 100R2J-2-GP
SRN100J-4-GP
4 5
3
6
2
7
1
8
RN57
1 2
R200 470R2J-2-GP
LED-Y-26-U-GP 83.01608.D70
LED-G-98-GP 83.01608.J70
LED5 LED-B-27-U-GP
3D3V_S0
LED-Y-26-U-GP 83.01608.D70
LED4
1 2
LED-G-98-GP 83.01608.J70
LED6
A K
3D3V_S5
LED-Y-26-U-GP 83.01608.D70
LED3
1 2
LED2
1 2
LED1
A K
83.00190.P70
5V_S0
1 2
DY
CCD Pin
Pin
Symbol
5V
1
2
USBÂUSB+
3
4
GND
5
GND
Inverter Pin
Pin
Symbol
Vin
1
2
Vin
PWM
3
4
BLON
5
GND
GND
6
Launch BD
Pin
Symbol
5V_S0
1
PWRBTN#
2
PROGRAM#
3
EBUTTON#
4
5
INTERNET#
6
MAIL#
7
KCOL19
MAIL_LED#
8
9
STDBY_LED#
10
PWRLED#
GND
11
GND
12
LCD1
MH1
45
46
MH2
44 42
IPEX-CON40-2-GP
AG1-A-SA
20.F0763.040
CONNECTOR
LEDB1
41 43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
EDID_CLK
EDID_DAT
BRIGHTNESS
FPBACK
Layout 60 mil
SC10U35V0ZY-GP
GMCH_TXACLK- 7
GMCH_TXACLK+ 7
GMCH_TXAOUT2- 7
GMCH_TXAOUT2+ 7
GMCH_TXAOUT1- 7
GMCH_TXAOUT1+ 7
GMCH_TXAOUT0- 7
GMCH_TXAOUT0+ 7
GMCH_TXBOUT0- 7
GMCH_TXBOUT0+ 7
GMCH_TXBOUT1- 7
GMCH_TXBOUT1+ 7
GMCH_TXBOUT2- 7
GMCH_TXBOUT2+ 7
GMCH_TXBCLK- 7
GMCH_TXBCLK+ 7
1 2
C233
SC10U10V5ZY-1GP
DY
SC1000P50V3JN-GP
C173
DY
1 2
C32
LCDVDD
1 2
1 2
EVEN CHANNEL
ODD CHANNEL
DCBATOUT
C155
1 2
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C33
SCD1U50V3ZY-GP
EC63
SCD1U16V2ZY-2GP
DY
1 2
EC65
DY
BRIGHTNESS 29
FPBACK 29
1 2
EC64
SCD1U16V2ZY-2GP
DY
MLX-CON8-7-GP-U
CONNECTOR
20.K0185.008
10
1
2
CAP_LED#
3
NUM_LED#
4
IDE_LED#
5
6
7
8
9
CLK_DDC_EDID 7
DAT_DDC_EDID 7
Q26
FDN337N-1-GP
TOP VIEW
AG1-910-01
CAP_LED# 29
3D3V_S0
1 2
EC50
SCD1U16V2ZY-2GP
2D5V_S0
G
S D
Q22
FDN337N-1-GP
NUM_LED# 29
IDE_LED# 20
G
S D
SCD1U16V2ZY-2GP
EC67
DY
3D3V_S0
1 2
<Core Design>
1
2 3
4
SRN2K2J-1-GP
RN3
EDID_CLK
EDID_DAT
1 2
EC66
SCD1U16V2ZY-2GP
DY
LCD
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
LCD CONN & LED
AG1(Alviso)
of
13 40 Friday, October 28, 2005
01
Page 14
CRT CONNECTOR
GMCH_RED 7
GMCH_GREEN 7
GMCH_BLUE 7
GMCH_RED
GMCH_GREEN
GMCH_BLUE
1 2
R53
50 Ohm Impedance 75 Ohm Impedance
1 2
1 2
R79
R46
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
1 2
1 2
EC28
SC3P50V2CN-1-GP
DY
EC27
SC3P50V2CN-1-GP
DY
Ferrite bead impedance: 75ohm@100MHz
1 2
EC29
SC3P50V2CN-1-GP
DY
L6
1 2
BLM18BA100SN1DGP
L7
1 2
BLM18BA100SN1DGP
L8
1 2
BLM18BA100SN1DGP
CRT_R
CRT_G
1 2
EC22
SC6D8P50V2DN-GP
CRT_B
1 2
EC23
SC6D8P50V2DN-GP
1 2
EC26
SC6D8P50V2DN-GP
AG1-910-01
Hsync & Vsync level shift
5V_S0
1 2
C14
SCD1U16V2ZY-2GP
14
13
GMCH_HSYNC 7
GMCH_VSYNC 7
GMCH_HSYNC
GMCH_VSYNC
C15
SC33P50V2JN-3GP
2 3
1 2
DY
12 11
14
7
7
1
U3A TSAHCT125PW-GP
1 2
C11
SC33P50V2JN-3GP
DY
AG1-910-SB
DDC_CLK & DATA level shift
5V_CRT_S0 2D5V_S0
678
RN2
SRN2K2J-2-GP
123
4 5
2D5V_S0
G
GMCH_DDCDATA 7
GMCH_DDCCLK 7
S D
FDN337N-1-GP
FDN337N-1-GP
Q6
S D
G
CLK_DDC1_5
Q7
CRT_HSYNC1
TSAHCT125PW-GP
U3D
CRT_VSYNC1
DAT_DDC1_5
CRT_HSYNC1
CRT_VSYNC1
AG1-A-SA
CRT_R
CRT_G
CRT_B
5V_CRT_S0
EC1
SC100P50V2JN-3GP
5V_S0
6
1
7
2
8
3
9
4
10
5
DAT_DDC1_5
CLK_DDC1_5
1 2
1 2
EC4
SC100P50V2JN-3GP
1 2
EC5
SCD01U16V2KX-3GP
DY
CRT1
17
11
12
13
14
15
16
VIDEO-15-42-GP-U
CONNECTOR
20.20378.015
1 2
EC2
SC10P50V2JN-4GP
D4
5V_CRT_S0
2 1
CH521S-30-GP-U
DAT_DDC1_5
CRT_HSYNC1
CRT_VSYNC1
CLK_DDC1_5
1 2
EC3
SC10P50V2JN-4GP
AG1-910-01
ESD Protection Diode ESD Protection Diode
BAV99PT-GP-U
CRT_R
3
DY
BAV99PT-GP-U
CRT_G
3
DY
BAV99PT-GP-U
CRT_B
3
AG1-910-SB
DY
5V_S0
2
D1
1
2
D2
1
2
D3
1
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
CRT Connector
Size Docum e nt N u m b e r Re v
Custom
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
AG1(Alviso)
14 40 Friday, October 28, 2005
01
of
Page 15
A
3D3V_AUX_S5
D22
BAT_D
1 2
1
3
2
BAT54C-1-GP
AG1-A-SA
4 4
AG1-910-01
R202
1KR2J-1-GP
AG1-910-01
BAT
12345
2nd
3 3
ACES-CON3-1-GP
20.F0735.003
RTC1
CONNECTOR
RTC_AUX_S5
1 2
C259
SC1U10V3ZY-6GP
R215 20KR2F-L-GP
1 2
R222 1MR2J-1-GP
1 2
SCD1U16V2ZY-2GP
C53
1 2
2nd source: 20.F0736.003
BAT
EC69 SCD01U16V2KX-3GP
1 2
DY
RTC_AUX_S5
2 2
1 2
R56
100KR2J-1-GP
1 2
R60
0R2J-GP
AG1-910-01
P.H. for internal VCCSUS1_5
INTVRMEN
AG1-910-SB
AG1-910-SB
INTRUDER# 19
ACZ_BITCLK 26
ACZ_SYNC 21,26
ACZ_RST# 21,26
AG1-910-01
ACZ_SDATAOUT 21,26
B
SC22P50V2JN-4GP
C277
1 2
X-32D768KHZ-38GPU
1 2
C272
SC22P50V2JN-4GP
AG1-910-01
X2
4
1
2 3
AG1-910-01
R90 0R0603-PAD
1 2
1 2
1 2
ACZ_SDATAIN0 26
ACZ_SDATAIN1 21
1 2
R94 39R2J-L-GP
IDE_PDIORDY 20
INT_IRQ14 20
IDE_PDDACK# 20
IDE_PDIOW# 20
IDE_PDIOR# 20
R99 39R2J-L-GP
R100 39R2J-L-GP
TP36 TPAD28
1 2
R227
10MR3J-L1-GP
RCT_X1
RCT_X2
RCT_RST#
INTRUDER#
INTVRMEN
R101
1 2
10KR2J-3-GP
ACZ_SYNC_R
ACZ_RST#_R
ACZ_SDATAOUT_R
AA2
AA3
AA5
D12
B12
D11
B11
E12
E11
C13
C12
C11
E13
C10
A10
B10
AC19
AE3
AD3
AG2
AF2
AD7
AC7
AF6
AG6
AC2
AC1
AG11
AF11
AF16
AB16
AB15
AC14
AE16
Y1
Y2
F13
F12
B9
F11
F10
C9
C
AG1-910-01
RTCX1
RTCX2
RTCRST#
INTRUDER#
INTVRMEN
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
LAN_CLK
LAN_RSTSYNC
LANRXD[0]
LANRXD[1]
LANRXD[2]
LANTXD[0]
LANTXD[1]
LANTXD[2]
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN[0]
ACZ_SDIN[1]
ACZ_SDIN[2]
ACZ_SDO
SATALED#
SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP
SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#
U26A
LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]
LPC
RTC LAN
LDRQ[0]#
LDRQ[1]#/GPI[41]
LFRAME#/FWH[4]
A20GATE
CPUSLP#
DPRSLP#
CPU
CPUPWRGD/GPO[49]
INIT3_3V#
STPCLK#
THRMTRIP#
SATA AC-97/AZALIA
IDE
A20M#
DPSLP#
FERR#
IGNNE#
INIT#
INTR
RCIN#
SMI#
DA[0]
DA[1]
DA[2]
DCS1#
DCS3#
DD[0]
DD[1]
DD[2]
DD[3]
DD[4]
DD[5]
DD[6]
DD[7]
DD[8]
DD[9]
DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]
DDREQ
NMI
P2
N3
N5
N4
N6
P4
P3
AF22
AF23
AE27
AE24
AD27
AF24
AG25
AG26
AE22
AF27
AG24
AD23
AF25
AG27
AE26
AE23
AC16
AB17
AC17
AD16
AE17
AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13
AB14
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LDRQ#0
LPC_LDRQ1
H_DPSLP#
KA20GATE_1 29
H_A20M# 4
H_CPUSLP# 4,6
H_DPRSLP# 4
H_FERR_R
FWH_INIT#
H_THERMTRIP_R
D
1D05V_S0
1 2
R219
56R2J-4-GP
DY
LPC_LAD[0..3] 29
TP27 TPAD28
TP25 TPAD28
LPC_LFRAME# 29
H_DPSLP# 4
R216 56R2J-4-GP
1 2
H_PWRGD 4,19
H_IGNNE# 4
H_INTR 4
KBRCIN#_1 29
H_NMI 4
H_SMI# 4
H_STPCLK# 4
R210
1 2
56R2J-4-GP
IDE_PDA0 20
IDE_PDA1 20
IDE_PDA2 20
IDE_PDCS1# 20
IDE_PDCS3# 20
IDE_PDD0 20
IDE_PDD1 20
IDE_PDD2 20
IDE_PDD3 20
IDE_PDD4 20
IDE_PDD5 20
IDE_PDD6 20
IDE_PDD7 20
IDE_PDD8 20
IDE_PDD9 20
IDE_PDD10 20
IDE_PDD11 20
IDE_PDD12 20
IDE_PDD13 20
IDE_PDD14 20
IDE_PDD15 20
IDE_PDDREQ 20
TP2
1 2
C260
SC4700P50V2KX-1GP
DY
AG1-910-01
AG1-A-SA
LPC_LDRQ1
KBRCIN#_1
KA20GATE_1
AG1-910-01
H_INIT# 4
Layout Note: R632 needs to placed
within 2" of ICH6, R634 must be placed
within 2" of R632 w/o stub.
1D05V_S0
1 2
1D05V_S0
AG1-910-01
10KR2J-3-GP
R77
1 2
1
2 3
RN16
SRN10KJ-5-GP
R214
56R2J-4-GP
1 2
R211
75R2F-2-GP
4
E
3D3V_S0
H_FERR# 4
PM_THRMTRIP-I# 4,7,19
DY
1 1
A
B
C
D
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
ICH6-M (1 of 4)
AG1(Alviso)
15 40 Thursday, October 27, 2005
E
of
01
Page 16
A
PCI_AD[31..0]
,24,28
4 4
PCI_FRAME#
,24,28
INT_PIRQB# 24
3 3
TP17 TPAD28
TP3 TPAD28
TP10 TPAD28
TP11 TPAD28
TP18 TPAD28
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
AC5
AD5
AG4
AC9
AF4
E2
E5
C2
F5
F3
E9
F2
D6
E6
D3
A2
D2
D5
H3
B4
J5
K2
K5
D4
L6
G3
H4
H2
H5
B3
M6
B2
K6
K3
A5
L1
K4
J3
N2
L2
M1
L3
U26B
AD[0]
PCI
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
GNT[4]#/GPO[48]
AD[9]
AD[10]
GNT[5]#/GPO[17]
AD[11]
AD[12]
GNT[6]#/GPO[16]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]
FRAME#
Interrupt I/F
PIRQ[A]#
PIRQ[B]#
PIRQ[C]#
PIRQ[D]#
RESERVED
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
REQ[0]#
GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#
REQ[4]#/GPI[40]
REQ[5]#/GPI[1]
REQ[6]#/GPI[0]
C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
PLTRST#
PCICLK
PME#
PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]
PIRQ[G]#/GPI[4]
PIRQ[H]#/GPI[5]
RSVD[6]
RSVD[7]
RSVD[8]
TP[3]
PCI_REQ#0
L5
PCI_GNT#0
C1
PCI_REQ#1
B5
B6
PCI_REQ#2
M5
F1
PCI_REQ#3
B8
C8
BOOT_BLOCK#
F7
E7
PCI_REQ#5
E8
PCI_GNT#5
F6
PCI_REQ#6
B7
PCI_GNT#6
D8
J6
H6
G4
G2
A3
E1
R76 10R2J-2-GP
R2
C3
E3
PCI_LOCK#
C5
G5
J1
J2
PLT_RST1#_1
R5
G6
P6
D9
C7
C6
M3
AD9
AF8
AG8
U3
ICH6 Pullups
INT_PIRQD#
PCI_REQ#5
PCI_SERR# PCI_STOP#
INT_PIRQF#
3D3V_S0
PCI_LOCK#
INT_PIRQG#
PCI_DEVSEL#
PCI_IRDY#
3D3V_S0
2 2
PCI_REQ#0
INT_PIRQA#
INT_PIRQC#
INT_PIRQH#
3D3V_S0
SMB_LINK_ALERT#
SMLINK0
SMB_ALERT#
SMLINK1
3D3V_S5
1 1
RN47
1
2
3
4
5 6
SRN10KJ-L3-GP
RN59
1
2
3
4
5 6
SRN10KJ-L3-GP
RN45
1
2
3
4
5 6
SRN10KJ-L3-GP
RN5
1
2
3
4
5 6
SRN10KJ-L3-GP
10
PCI_FRAME#
9
8
PCI_TRDY#
7
PCI_PERR#
10
PCI_REQ#3
9
INT_PIRQE#
8
PM_CLKRUN#
7
PCI_REQ#2
10
INT_SERIRQ
9
THRM#
8
MCH_SYNC#
7
INT_PIRQB#
10
9
8
7
3D3V_S0
3D3V_S0
3D3V_S0
CHK_PW#
PM_RI#
DBRESET#
ICH6_WAKE#
PM_BATLOW#_R
ECSMI#
ECSWI#
PM_SLP_S3#_ICH
PM_DPRSLPVR_R
3D3V_S5
1 2
R70 1KR2J-1-GP
1 2
R238 8K2R2J-3-GP
1 2
R69 100KR2J-1-GP
1 2
R84 100KR2J-1-GP
1 2
0R0402-PAD
DY
1 2
TP35 TPAD28
TP34 TPAD28
1 2
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
AG1-910-01
DY
DY
R78
R207
100KR2J-1-GP
B
PCI_REQ#0 24
PCI_GNT#0 24
PCI_REQ#1 28
PCI_GNT#1 28
PCI_REQ#2 22
PCI_GNT#2 22
PCI_C/BE#0 22,24,28
PCI_C/BE#1 22,24,28
PCI_C/BE#2 22,24,28
PCI_C/BE#3 22,24,28
PCI_DEVSEL# 22,24,28
PCI_PERR# 22,24,28
PCI_SERR# 22,24,28
PCI_STOP# 22,24,28
PCI_T R D Y # 2 2 ,24,28
R67 47R2J-2-GP
1 2
CLK_ICHPCI 3
ICH_PME# 22,29
INT_PIRQE# 22
INT_PIRQF# 28
INT_PIRQG# 24
TP16 TPAD28
TP15 TPAD28
TP14 TPAD28
TP22 TPAD28
3D3V_S5
PCI_REQ#6
PCI_REQ#1
BOOT_BLOCK#
ECSCI#_1
R80
100KR2J-1-GP
DY
1 2
3D3V_S0
TP37 TPAD28
AG1-910-01
PCI_IRDY# 22,24,28
PCI_PAR 22 ,24,28
1 2
PLT_RST1# 7,18,29
Int. PH
PCIRST1# 22,24,28
C67
SC22P50V2JN-4GP
AG1-910-01
PM_CLKRUN# 22,24,28,29
RN6
1
2
3
4 5
SRN10KJ-4-GP
1 2
3D3V_S0
8
7
6
AG1-910-01
Need to check what power we will use
PM_DPRSLPVR 34
PM_SLP_S3# 18,29,32,35,37
AG1-910-01
C
RN15
SRN10KJ-4-GP
1
2
3
4 5
SMB_CLK 18
SMB_DATA 18
ACZ_SPKR 26
PM_SUS_STAT# 29
PM_BMBUSY# 7
ECSCI#_1 29
ECSMI# 29
TP60 TPAD28
ECSWI# 29
PM_STPPCI# 3
TP21 TPAD28
PM_STPCPU# 3,34
TP6 TPAD28
KBC_SLP_WAKE 29
PCB_VER1 31
PCB_VER0 31
CHK_PW# 31
TP4 TPAD28
TP20 TPAD28
INT_SERIRQ 24,28,29
THRM# 19
VGATE_PWRGD 7,32
CLK_ICH14 3
CLK48_ICH 3
PM_SUS_CLK 18
PM_SLP_S4# 29,37
TP23 TPAD28
PWROK 19
1 2
PM_PWRBTN# 29
RSMRST#_KBC 29,32
SATA0_R0
8
SATA0_R1
7
SATA0_R3
6
SATA0_R2
R204
100R2J-2-GP
LAN_RST#
100KR2J-1-GP
AG1-910-01
PM_RI#
SMB_LINK_ALERT#
SMLINK0
SMLINK1
MCH_SYNC#
DBRESET#
SMB_ALERT#
ICH_GPI12
ICH_GPO19
ICH_GPO21
KBC_SLP_WAKE
1 2
CHK_PW#
ICH_GPIO33
ICH_GPIO34
ICH6_WAKE#
THRM#
PM_SLP_S3#_ICH
PM_SLP_S5#
PM_DPRSLPVR_R
PM_BATLOW#_R
PM_PWRBTN#
1 2
R336
SATA0_R0
SATA0_R1
SATA0_R2
SATA0_R3
R83 10KR2J-3-GP
1 2
R337
10KR2J-3-GP
T2
RI#
AF17
SATA[0]GP/GPI[26]
AE18
SATA[1]GP/GPI[29]
AF18
SATA[2]GP/GPI[30]
AG18
SATA[3]GP/GPI[31]
Y4
SMBCLK
W5
SMBDATA
Y5
LINKALERT#
W4
SMLINK[0]
U6
SMLINK[1]
AG21
MCH_SYNC#
F8
SPKR
W3
SUS_STAT#/LPCPD#
U2
SYS_RESET#
AD19
BMBUSY#
AE19
GPI[7]
R1
GPI[8]
W6
SMBALERT#/GPI[11]
M2
GPI[12]
R6
GPI[13]
AC21
STP_PCI#
AB21
GPO[19]
AD22
STP_CPU#
AD20
GPO[21]
AD21
GPO[23]
V3
GPIO[24]
P5
GPIO[25]
R3
GPIO[27]
T3
GPIO[28]
AF19
CLKRUN#
AF20
GPIO[33]
AC18
GPIO[34]
U5
WAKE#
AB20
SERIRQ
AC20
THRM#
AF21
VRMPWRGD
E10
CLK14
A27
CLK48
V6
SUSCLK
T4
SLP_S3#
T5
SLP_S4#
T6
SLP_S5#
AA1
PWROK
AE20
DPRSLPVR
V2
BATLOW#
U1
PWRBTN#
V5
LAN_RST#
Y3
RSMRST#
D
U26C
GPIO
PCI-EXPRESS Direct Media Interface
DMI_ZCOMP
DMI_IRCOMP
OC[4]#/GPI[9]
OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]
USB
POWER MGT CLOCKS
H25
PERn[1]
H24
PERp[1]
G27
PETn[1]
G26
PETp[1]
K25
PERn[2]
K24
PERp[2]
J27
PETn[2]
J26
PETp[2]
M25
PERn[3]
M24
PERp[3]
L27
PETn[3]
L26
PETp[3]
P24
PERn[4]
P23
PERp[4]
N27
PETn[4]
N26
PETp[4]
T25
DMI[0]RXN
T24
DMI[0]RXP
R27
DMI[0]TXN
R26
DMI[0]TXP
V25
DMI[1]RXN
V24
DMI[1]RXP
U27
DMI[1]TXN
U26
DMI[1]TXP
Y25
DMI[2]RXN
Y24
DMI[2]RXP
W27
DMI[2]TXN
W26
DMI[2]TXP
AB24
DMI[3]RXN
AB23
DMI[3]RXP
AA27
DMI[3]TXN
AA26
DMI[3]TXP
AD25
DMI_CLKN
AC25
DMI_CLKP
F24
F23
C23
D23
C25
C24
C27
OC[0]#
B27
OC[1]#
B26
OC[2]#
C26
OC[3]#
C21
USBP[0]N
D21
USBP[0]P
A20
USBP[1]N
B20
USBP[1]P
D19
USBP[2]N
C19
USBP[2]P
A18
USBP[3]N
B18
USBP[3]P
E17
USBP[4]N
D17
USBP[4]P
B16
USBP[5]N
A16
USBP[5]P
C15
USBP[6]N
D15
USBP[6]P
A14
USBP[7]N
B14
USBP[7]P
USBRBIAS#
A22
B22
USBRBIAS
Place within 500 mils of ICH
DMI_RXN0 7
DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7
DMI_RXN1 7
DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7
DMI_RXN2 7
DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7
DMI_RXN3 7
DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7
CLK_PCIE_ICH# 3
CLK_PCIE_ICH 3
DMI_IRCOMP_R
USB_OC#6
USB_OC#0
USBPN1
USBPP1
USBPN2
USBPP2
USBPN3
USBPP3
USBPN5
USBPP5
USBPN6
USBPP6
USBPN7
USBPP7
USB_OC#1
USB_RBIAS_PN
USB_OC#6 21
USB_OC#0 21
USBPN0 21
USBPP0 21
USBPN4 21
USBPP4 21
USBPN6 21
USBPP6 21
USBPN7 21
USBPP7 21
1 2
22D6R2F-L1-GP
AG1-910-01
ICH6-M Strapping Options
REF
FUNCTION
R7F9
No Reboot
A16 Swap
R7F8
Override
R7F7
<Core Design>
Boot BIOS
Layout Note:
PCIE AC coupling caps
need to be within 250 mils of the driver.
Layout Note:
PCIE AC coupling caps
need to be within 250 mils of the driver.
TP71 TPAD28 R203 100KR2J-1-GP
TP72 TPAD28
TP75 TPAD28
TP70 TPAD28
TP69 TPAD28
TP74 TPAD28
TP73 TPAD28
TP68 TPAD28
R250
E
1D5V_S0
Place within 500 mils of ICH
1 2
R86
24D9R2F-L-GP
AG1-910-01
RN72
1
USB_OC#1
2
USB_OC#6
3
USB_OC#0
4 5
SRN10KJ-4-GP
3D3V_S0
1 2
DY
R85 1KR2J-1-GP
1KR2J-1-GP
R97
1 2
DY
1KR2J-1-GP
R87
1 2
DY
100KR2J-1-GP
R223
1 2
DY
AG1-910-SB
3D3V_S5
8
7
6
AG1-910-SB
R7F9
ACZ_SPKR
R7F8
PCI_GNT#6
R7F7
PCI_GNT#5
PWROK
DEFAULT OPTIONAL OVERRIDE
NO_STUFF
NO_STUFF
NO_STUFF
STUFF
STUFF
STUFF
A
B
C
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
D
Date: Sheet
ICH6-M (2 of 4)
AG1(Alviso)
16 40 Monday, October 31, 2005
E
of
01
Page 17
A
Layout Note:
Place above caps within
100 mils of ICH near F27, P27, AB27
1D5V_S0
B
U26E
C
1 2
C82
D
1D5V_S0
1 2
C91
Layout Note:
Place near pin AA19
E
AA22
C80
1 2
4 4
ST220U2D5VBM-2GP
TC5
1 2
DY
SCD1U16V2ZY-2GP
Layout Note:
C257
IDE decoupling
1D5V_S0
SCD1U16V2ZY-2GP
EC37
1 2
3D3V_S0
1 2
DY
SCD1U16V2ZY-2GP
Layout Note:
3 3
Place within 100
mils of ICH
near pin AG5
1D5V_S0
2 2
R224
1 2
0R0603-PAD
Place within 100
mils of ICH
Place within 100
mils of ICH
near E26, E27
SCD1U16V2ZY-2GP
Place within 100
mils of ICH
pin AG10
1 1
1 2
EC36
SCD1U16V2ZY-2GP
PCI decoupling
Place within 100
mils of ICH
near pin AG9
1D5V_GPLL_ICH_S0
1 2
C266
SC10U10V5ZY-1GP
3D3V_S0
1 2
C90
3D3V_S0
1 2
C45
SCD1U16V2ZY-2GP
1D5V_S0
1 2
C69
DY
SC10U10V5ZY-1GP
A
1D5V_S0
Place within 100
mils of ICH
pin AE1
Place within 100
mils of ICH
pin A13
1D5V_S0
C43
1 2
0R0603-PAD
1D5V_S0
1 2
SCD1U16V2ZY-2GP
1 2
C262
SCD01U16V2KX-3GP
R212
3D3V_S5
3D3V_S5
1 2
C44
1D5V_ICH_S0
1 2
C246
SCD1U16V2ZY-2GP
1 2
C56
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C96
SCD1U16V2ZY-2GP
B
VCC1_5_B
AA23
VCC1_5_B
AA24
VCC1_5_B
AA25
VCC1_5_B
AB25
VCC1_5_B
AB26
VCC1_5_B
AB27
VCC1_5_B
F25
VCC1_5_B
F26
VCC1_5_B
F27
VCC1_5_B
G22
VCC1_5_B
G23
VCC1_5_B
G24
VCC1_5_B
G25
VCC1_5_B
H21
VCC1_5_B
H22
VCC1_5_B
J21
VCC1_5_B
J22
VCC1_5_B
K21
VCC1_5_B
K22
VCC1_5_B
L21
VCC1_5_B
L22
VCC1_5_B
M21
VCC1_5_B
M22
VCC1_5_B
N21
N22
N23
N24
N25
P21
P25
P26
P27
R21
R22
T21
T22
U21
U22
V21
V22
W21
W22
Y21
Y22
AA6
AB4
AB5
AB6
AC4
AD4
AE4
AE5
AF5
AG5
AA7
AA8
AA9
AB8
AC8
AD8
AE8
AE9
AF9
AG9
AC27
E26
AE1
AG10
A13
F14
G13
G14
A11
U4
V1
V7
W2
Y7
A17
B17
C17
F18
G17
G18
Place within 100
mils of ICH
pin V7 mils of ICH
PCIE
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
SATA
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCCDMIPLL
VCC3_3
VCCSATAPLL
VCC3_3
VCCLAN3_3/VCCSUS3_3
VCCLAN3_3/VCCSUS3_3
VCCLAN3_3/VCCSUS3_3
VCCLAN3_3/VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
CORE IDE PCI
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
USB CORE USB
PCI/IDE
REF
V5REF_SUS
VCCUSBPLL
VCCSUS3_3
VCCLAN1_5/VCCSUS1_5
VCCLAN1_5/VCCSUS1_5
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC2_5
VCC2_5
V5REF
V5REF
VCCRTC
V_CPU_IO
V_CPU_IO
V_CPU_IO
F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19
AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12
P1
M7
L7
L4
J7
H7
H1
E4
B1
A6
U7
R7
G19
G20
F20
E24
SCD1U16V2ZY-2GP
E23
E22
E21
E20
D27
D26
D25
D24
V2D5S_PCI_IDE
G8
AB18
P7
SCD1U16V2ZY-2GP
AA18
A8
F21
A25
A24
AB3
G11
G10
AG23
AD26
AB22
G16
G15
F16
SCD1U16V2ZY-2GP
F15
E16
D16
C16
C
SCD1U16V2ZY-2GP
Place within 100
mils of ICH pin
AG13, AG16
Layout Note:
Distribute in PCI section
near pin A2-A6 near D1-H1
1 2
C97
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C75
1 2
3D3V_S0
1 2
1D5V_S0
AG1-910-SB
R81
DY
1 2
1 2
C74
V5REF_S0
V5REF_S5
C79
1 2
0R3J-3-GP
Layout Note:
Place near AB18
1D5V_INT_S5
1 2
Place within 100
mils of ICH
pin G10
SCD1U16V2ZY-2GP
1 2
C49
C84
SCD1U16V2ZY-2GP
1 2
EC31
SCD1U16V2ZY-2GP
C256
SCD1U16V2ZY-2GP
1 2
C62
1D5V_INT_S5
Place both
within 100 mils
of ICH near D27
2D5V_S0
1D05V_S0
Layout Note:
Place near AG23
1 2
C88
SCD1U16V2ZY-2GP
DY
1 2
EC24
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
EC32
SCD1U16V2ZY-2GP
ALL NO_STUFF Caps do
not have layout
requirements but if
layout allows then place
next to ICH6
1D5V_INT_S5
1 2
C68
SCD1U16V2ZY-2GP
1 2
C81
SCD1U16V2ZY-2GP
3D3V_S5
Place within 100
1 2
mils of ICH
C94
SCD1U16V2ZY-2GP
C50
Place within 100
pin A17
SCD1U16V2ZY-2GP
1 2
EC33
1D5V_ICH_S0
RTC_AUX_S5
1 2
3D3V_S5
D
SCD1U16V2ZY-2GP
3D3V_S0
Layout Note:
Place near ICH6
Place within 100
1 2
mils of ICH
C95
SCD01U16V2KX-3GP
Layout Note:
Place near AB3
1 2
C51
SCD1U16V2ZY-2GP
*Within a given well, 5VR EF needs to be up before the
corresponding 3.3V rail
V5REF_S0
V5REF_S5
3D3V_S0
RB751V-40-1-GP
D16
2 1
1 2
C55
SCD1U16V2ZY-2GP
RB751V-40-1-GP
D25
2 1
1 2
C89
SCD1U16V2ZY-2GP
5V_S0
10R2J-2-GP
R109
1 2
1 2
C107
SC1U10V3ZY-6GP
5V_S5 3D3V_S5
10R2J-2-GP
R248
1 2
1 2
C78
SC1U10V3ZY-6GP
AG1-910-SB
3D3V_S5
1 2
DY
C281
<Core Design>
Title
Size Document Number Rev
A3
Date: Sheet
DY
U35
2
VOUT
3
VIN
1
GND
APL5308-15AC-GP
SC1U10V3ZY-6GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
ICH6-M (3 of 4)
AG1(Alviso) 01
E
1D5V_INT_S5
C287
1 2
DY
of
17 40 Monday, October 31, 2005
AG1-910-01
SC2D2U6D3V3MX-1-GP
Page 18
A
4 4
AG1-910-SB
3 3
2 2
PLT_RST1# 7,16,29
SC100P50V2JN-3GP
SMBUS
SMB_CLK 16
1 1
SMB_DATA 16
Q94 & Q95 connect SMLINK and
SMBUS in S) for SMBus 2.0
compliance
A
B
32K suspend clock output
U30
PM_SLP_S3# 16,29,32,35,37
PM_SUS_CLK 16
1
OE
2
A
GND3Y
NC7SZ126P5X-GP
VCC
AG1-910-01
5V_S0
33R2J-2-GP
R367
1 2
C447
9 8
1 2
14
10
7
TSAHCT125PW-GP
U3C
1 2
PCIRST# 3V to 5V level shift for HDD & CDROM
AG1-A-SA
3D3V_S5
3D3V_S0
678
RN17
SRN10KJ-4-GP
123
4 5
5V_S0
G
1
D
B
2 3
Q27
2N7002PT-U
D
S
2N7002PT-U
1
Q14
3D3V_S5
5
4
AG1-910-01
R201
1 2
0R0402-PAD
R190
10KR2J-3-GP
AG1-910-01
G
2 3
S
32KHZ
AG1-910-01
1 2
10R2J-2-GP
1 2
R239
100KR2J-1-GP
C
R237
RSTDRV#_5 20
SMBC_ICH 3,11
SMBD_ICH 3,11
C
G791_32K 19
D
E27
VSS
Y6
VSS
Y27
VSS
Y26
VSS
Y23
VSS
W7
VSS
W25
VSS
W24
VSS
W23
VSS
W1
VSS
V4
VSS
V27
VSS
V26
VSS
V23
VSS
U25
VSS
U24
VSS
U23
VSS
U15
VSS
U13
VSS
T7
VSS
T27
VSS
T26
VSS
T23
VSS
T16
VSS
T15
VSS
T14
VSS
T13
VSS
T12
VSS
T1
VSS
R4
VSS
R25
VSS
R24
VSS
R23
VSS
R17
VSS
R16
VSS
R15
VSS
R14
VSS
R13
VSS
R12
VSS
R11
VSS
P22
VSS
P16
VSS
P15
VSS
P14
VSS
P13
VSS
P12
VSS
N7
VSS
N17
VSS
N16
VSS
N15
VSS
N14
VSS
N13
VSS
N12
VSS
N11
VSS
N1
VSS
M4
VSS
M27
VSS
M26
VSS
M23
VSS
M16
VSS
M15
VSS
M14
VSS
M13
VSS
M12
VSS
L25
VSS
L24
VSS
L23
VSS
L15
VSS
L13
VSS
K7
VSS
K27
VSS
K26
VSS
K23
VSS
K1
VSS
J4
VSS
J25
VSS
J24
VSS
J23
VSS
H27
VSS
H26
VSS
H23
VSS
G9
VSS
G7
VSS
G21
VSS
G12
VSS
G1
VSS
<Core Design>
Title
Size Document Number Rev
A3
D
Date: Sheet
ICH6-M (4 of 4)
AG1(Alviso) 01
E
U26D
F4
VSS
F22
VSS
F19
VSS
F17
VSS
E25
VSS
E19
VSS
E18
VSS
E15
VSS
E14
VSS
D7
VSS
D22
VSS
D20
VSS
D18
VSS
D14
VSS
D13
VSS
D10
VSS
D1
VSS
C4
VSS
C22
VSS
C20
VSS
C18
VSS
C14
VSS
B25
VSS
B24
VSS
B23
VSS
B21
VSS
B19
VSS
B15
VSS
B13
VSS
AG7
VSS
AG3
VSS
AG22
VSS
AG20
VSS
AG17
VSS
AG14
VSS
AG12
VSS
AG1
VSS
AF7
VSS
AF3
VSS
AF26
VSS
AF12
VSS
AF10
VSS
AF1
VSS
VSS
AE7
VSS
AE6
VSS
AE25
VSS
AE21
VSS
AE2
VSS
AE12
VSS
AE11
VSS
AE10
VSS
AD6
VSS
AD24
VSS
AD2
VSS
AD18
VSS
AD15
VSS
AD10
VSS
AD1
VSS
AC6
VSS
AC3
VSS
AC26
VSS
AC24
VSS
AC23
VSS
AC22
VSS
AC12
VSS
AC10
VSS
AB9
VSS
AB7
VSS
AB2
VSS
AB19
VSS
AB10
VSS
AB1
VSS
AA4
VSS
AA16
VSS
AA13
VSS
AA11
VSS
A9
VSS
A7
VSS
A4
VSS
A26
VSS
A23
VSS
A21
VSS
A19
VSS
A15
VSS
A12
VSS
A1
VSS
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
18 40 Tuesday, October 25, 2005
E
of
Page 19
*Layout* 15 mil
SCD1U16V2ZY-2GP
1 2
1 2
C70
C77
SC10U10V5ZY-1GP
DY
AG1-910-SB
3D3V_S0
AG1-910-01
1 2
R244
10KR2J-3-GP
FAN1_VCC
D13
BAT54-4-GP
2
1 2
C73
SC2200P50V2KX-2GP
DY
AG1-910-SB
3
1
AG1-910-01
5V_S0
R246
1 2
200R2F-L-GP
SCD1U16V2ZY-2GP
C286
Setting T8 as
100 Degree
V_DEGREE
=(((Degree-72)*0.02)+0.34)*VCC
THRM# 16
AG1-910-01
1 2
PWROK 16
SC2200P50V2KX-2GP
*Layout* 30 mil
1 2
R242
4K99R2F-L-GP
1 2
R241
49K9R2F-L-GP
AG1-910-SB
1 2
C65
DY
AG1-910-01
5V_S0
1 2
C66
SC4D7U10V5ZY-3GP
R236
10KR2J-3-GP
T8_HW_SHUT# LOW3_OFF
3D3V_AUX_S5
R247
10KR2J-3-GP
1 2
SCD1U16V2ZY-2GP
1 2
1 2
1 2
C72
C71
SCD1U16V2ZY-2GP
1 2
4K7R2J-2-GP
R235
AG1-910-01
SCD1U16V2ZY-2GP
3
D14
BAT54-4-GP
1
2
THRM#
T8_HW_SHUT#
V_DEGREE
G792_RESET#
BAW56-2-GP
5V_G791_S0
C92
D15
5V_S0
AG1-910-01
1 2
R82
10KR2J-3-GP
FAN1_VCC
1 2
C76
SC100P50V2JN-3GP
U19
DY
FAN1
FG1
CLK
SDA
SCL
NC#19
DGND
DGND
SGND1
SGND2
SGND3
G680LT1F-GP
U27
1
4
14
16
18
19
5
17
8
10
12
HTH
GND
LTH
G792_DXN2
G792_DXN3
R88
1MR2J-1-GP
HTH
1
2
3
R93
110KR2F-GP
G791_32K 18
SMBD_G792 29
SMBC_G792 29
H_THERMDA
G792_DXP3
G792_DXP2
H_THERMDC
G30
1 2
GAP-CLOSE
Place near chip as close
as possible
DCBATOUT
1 2
DY
1 2
DY
15KR2F-GP
R92
1 2
DY
G29
1 2
GAP-CLOSE
6
VCC
20
DVCC
7
DXP1
9
DXP2
11
DXP3
15
ALERT#
13
THERM#
3
THERM_SET
2
RESET#
G792SFUF-GP
DXP1:108 Degree
DXP2:H/W Setting
DXP3:88 Degree
5V_S5_G913
1 2
DY
5
VCC
4
RESET#/RESET
1
2
3
Output type:
Open-Drain RESET#
*Layout* 15 mil
SC470P50V2KX-3GP
1 2
1 2
C83
C290
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
System ,V
接第二組
1 2
C308
SC2200P50V2KX-2GP
R249
0R2J-GP
1 2
C171
PMBS3904-1-GP
1 2
DY
RSMRST# 29
2nd
FAN1
5
3
2
1
4
ACES-CON3-1-GP
20.F0735.003
CONNECTOR
2nd source: 20.F0736.003
SC470P50V2KX-3GP
3
Q25
1
2
1 2
C139
PMBS3904-1-GP
System Sensor
GA
接第三組
INTRUDER# 15
3
Q24
1
2
H_THERMDA 4
H_THERMDC 4
(dummy, KBC already delay)
1 2
C85
SCD1U16V2ZY-2GP
DY
AG1-910-01
R95
H_PWRGD 4,15
AG1-910-SB
1 2
1KR2J-1-GP
SCD1U16V2ZY-2GP
C412
C
Q15
B
1 2
PMBT2222A-1GP
E
PM_THRMTRIP-I# 4,7,15
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
Custom
Date: Sheet
Thermal/Fan Controllor
AG1(Alviso)
19 40 Thursday, October 27, 2005
of
01
Page 20
CD-ROM Connector HDD Connector
Check
5V_S0
C346
3D3V_S0
5V_S0
AG1-910-SB
1 2
AG1-910-01
1 2
R218
10KR2J-3-GP
5V_S0
5V_S0
SC10U10V5ZY-1GP
AG1-910-01
R217
1 2
10KR2J-3-GP
1 2
C263
C268
Y
ODD1
51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
52
STC-CONN50-4R
20.80251.050
CONNECTOR
RSTDRV#_5
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0
IDE_PDIOW#
IDE_PDIORDY IDE _PDDACK#
INT_IRQ14
IDE_PDA1
IDE_PDA0
IDE_PDCS1#
IDE_LED#
CSEL
R226
0R2J-GP
1 2
DY
R225
1 2
10KR2J-2-GP
AG1-910-SB
5V_S0
1 2
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
IDE_PDDREQ
IDE_PDIOR#
PDIAG
IDE_PDA2
IDE_PDCS3#
1 2
C270
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
PIN 49,50 DON'T USE
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
678
123
HDDCSEL
PDIAG
INT_IRQ14
RN68
SRN4K7J-6-GP
4 5
AG1-910-01
470R2J-2-GP
IDE_LED#
R305
RSTDRV#_5 18
IDE_LED# 13
INT_IRQ14 15
IDE_PDIORDY15
IDE_PDIOR# 15
IDE_PDIOW#15
IDE_PDDREQ15
IDE_PDDACK# 15
C347
SC10U10V5ZY-1GP
K A
DY
IDE_PDD15
IDE_PDD14
IDE_PDD13
IDE_PDD12
IDE_PDD11
IDE_PDD10
IDE_PDD9
IDE_PDD8
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0
IDE_PDCS3#
IDE_PDCS1#
IDE_PDA2
IDE_PDA1
IDE_PDA0
TC16
D23
SSM22LLPT-GP
1 2
ST100U6D3VDM-5
HDD1
42
+5V_MOTOR
41
+5V_LOGIC
18
DD15
16
DD14
14
DD13
12
DD12
10
DD11
8
DD10
6
DD9
4
DD8
3
DD7
5
DD6
7
DD5
9
DD4
11
DD3
13
DD2
15
DD1
17
DD0
38
CS1#
37
CS0#
36
DA2
33
DA1
35
DA0
SYN-CON44-1-GP 20.F0793.044
CONNECTOR
AG1-910-01
RESERVED#44
RESERVED#32
KEY
CSEL
PDIAG#
RESET#
DASP#
INTRQ
IORDY
DIOR#
DIOW#
DMARQ
DMACK#
NP2
NP1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IDE_PDIORDY
IDE_PDDACK#
INT_IRQ14
20
28
34
1
39
31
27
25
23
21
29
44
32
NP2
NP1
40
30
26
24
22
43
19
45
46
2
RSTDRV#_5
IDE_PDIORDY
IDE_PDIOR#
IDE_PDIOW#
IDE_PDDREQ
IDE_PDDACK#
1 2
1 2
1 2
C345
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
IDE_PDD15 15
IDE_PDD14 15
IDE_PDD13 15
IDE_PDD12 15
IDE_PDD11 15
IDE_PDD10 15
IDE_PDD9 15
IDE_PDD8 15
IDE_PDD7 15
IDE_PDD6 15
IDE_PDD5 15
IDE_PDD4 15
IDE_PDD3 15
IDE_PDD2 15
IDE_PDD1 15
IDE_PDD0 15
IDE_PDCS3# 15
IDE_PDCS1# 15
IDE_PDA2 15
IDE_PDA1 15
IDE_PDA0 15
AG1-910-SB
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
HDD and CDROM
AG1(Alviso)
20 40 Monday, October 31, 2005
of
01
Page 21
5V_USB0_S0
5V_USB0_S0
CONNECTOR
22.10218.J11
SKT-USB-105-GP
4
3
2
1
USB2
CONNECTOR
22.10218.J11
SKT-USB-105-GP
4
3
2
1
USB3
8
6
5
7
8
6
5
7
100 mil
5V_USB1_S0
TC13
SE100U10VM-4GP
1 2
EC52
1 2
EC53
SCD1U16V2ZY-2GP
SC1000P50V3JN-GP
1 2
DY
5V_S5
1
2
USB_PWR_EN# 29
3
G546A2P1UF-GP
U45
GND
OC1#
IN
OUT1
EN1/EN1#
OUT2
EN2/EN2#4OC2#
5V_USB0_S0
8
7
6
5
5V_USB1_S0
2 3
1
SRN0J-6-GP
RN66
4
EC73
SCD1U16V2ZY-2GP
DY
AG1-910-SB
USB PORT
USB_OC#0 16
USB_OC#6 16
1 2
1 2
EC74
SCD1U16V2ZY-2GP
DY
AG1-910-01
USBPN6 16
USBPP6 16
AG1-910-SB
100 mil
5V_USB0_S0
TC17
SE100U10VM-4GP
1 2
TC20
SE100U10VM-4GP
1 2
1 2
EC55
DY
1 2
EC54
SCD1U16V2ZY-2GP
SC1000P50V3JN-GP
USBPN7 16
USBPP7 16
BLUETOOTH MODULE
3D3V_BT_S0
1 2
DY
3D3V_BT_S0
EC56
SCD1U16V2ZY-2GP
U42
1
OUT
2
GND
NC#33ON/OFF#
AAT4250IGV-T1-GP
74.04250.A3F
IN
3D3V_S0
5
4
BLUETOOTH_EN 29
AG1-A-SA
2nd
BLUE1
6
4
3
2
1
5
ETY-CON4-16-GP
20.F0760.004
CONNECTOR
1st source: 20.D0197.104
USBPN4 16
USBPP4 16
3D3V_BT_S0
MDC 1.5 CONNECTOR
2nd
MDC1
13
MH1
1
3
5
7
9
11
MH2 17
16
AMP-CONN12A-GP
2nd source: 20.F0604.012
ACZ_SDATAOUT 15,26
ACZ_SDATAIN1 15
ACZ_SYNC 15,26
SCD47U10V3ZY-GP
ACZ_SDATAOUT
DY
1 2
1 2
0R0402-PAD
1 2
C41
SC22P50V2JN-4GP
C40
0R0402-PAD
R44
ACZ_SYNC
R49
DY
R47
10R2J-2-GP
ACZ_RST#
1 2
1 2
ACSDATAIN1_A
CONNECTOR
20.F0582.012
15
14
2
4
6
8
10
12
18
1 2
C243
TP5 TPAD28
TP7 TPAD28
3D3V_S5
1 2
R213
SC4D7U10V5ZY-3GP
C258
DUMMY-C2
ACZ_BTCLK_MDC 26 ACZ_RST# 15,26
AG1-910-01
1 2
100KR2J-1-GP
5V_USB1_S0
USBPN0 16
USBPP0 16
CONNECTOR
22.10218.J11
SKT-USB-105-GP
4
3
2
1
USB4
8
6
5
7
AG1-A-SA
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
USB / MDC / BLUETOOTH
AG1(Alviso)
of
21 40 Friday, October 28, 2005
01
Page 22
A
TGP0
TGN0 TGN1
2 3
4 4
LAN_X1
LAN_X2
R304
1 2
3 3
TGP0 23
TGN0 23
TGP1 23
TGN1 23
3D3V_S0
D30
BAT54-4-GP
1
2 2
2
1 1
AG1-910-01
R308
3
1 2
1KR2J-1-GP
1 2
R307 15KR2F-GP
INT_PIRQE# 16
3D3V_LAN_S5
PCIRST1# 16,24,28
PCLK_LAN 3
PCI_GNT#2 16
PCI_REQ#2 16
ICH_PME# 16,29
TGP0
TGN0
LAVDDL
TGP1
TGN1
LAVDDL
CTRL25
LDVDD
LAVDDL
LAVDDL
ISOLATE#
LDVDD
PCI_GNT#2
PCI_REQ#2
LDVDD
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
AG1-910-01
R311
1 2
100R2F-L1-GP-U
LAN_IDSEL PCI_AD23
RSET
U39
1
MDI0+
2
MDI0-
3
AVDDL
4
VSS
5
MDI1+
6
MDI1-
7
AVDDL
8
CTRL25
9
VSS
10
AVDDH
11
HSDAC+
12
HSDAC-
13
VSS
14
MDI2+
15
MDI2-
16
AVDDL
17
VSS
18
MDI3+
19
MDI3-
20
AVDDL
21
VSSPST
22
GND
23
ISOLATE#
24
VDD18
25
INTA#
26
VDD33
27
PCIRST#
28
PCICLK
29
GNT#
30
REQ#
31
PME#
32
VDD18
33
PCIAD31
34
PCIAD30
35
GND
36
PCIAD29
37
PCIAD28
38
VSSPST
RTL8100CL-U
Y
3D3V_LAN_S5
5K6R3F-GP
128
127
VSS
RSET
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_C/BE#3
LDVDD
LAN_IDSEL
PCI_AD23
PCI_AD22
PCI_AD21
126
AVDD18
A
B
TGP1
1
RN67
SRN49D9F-GP
MID0X
4
1 2
C352
SCD01U50V3KX-4GP
124
123
VSS
122
VSS
XTAL2
B
125
CTRL18
PCIAD2739PCIAD2640VDD3341PCIAD2542PCIAD2443CBEB344VDD1845IDSEL46PCIAD2347GND48PCIAD2249PCIAD2150VSSPST51GND52PCIAD2053VDD1854PCIAD1955VDD3356PCIAD1857PCIAD1758PCIAD1659CBEB260FRAME#61GND62IRDY#63VDD18
1
2 3
RN69
SRN49D9F-GP
MID1X
4
1 2
C355
SCD01U50V3KX-4GP
120
119
121
XTAL1
AVDDH
VSSPST
CLOSE TO
LAN CHIP
AG1-A-SA
117
115
114
116
118
GND
LED0
LED1
LED2
VDD18
111
113
110
109
112
GND
EEDI
LED3
EESK
VDD18
64
ACT_LED#
LDVDD
RTL_LED1#
LAN_EESK
LDVDD
LAN_EEDI
LAN_EEDO
3D3V_LAN_S5
LAN_EECS_3
108
106
105
107
EECS
EEDO
VDD33
LDVDD
PCI_IRDY#
PCI_FRAME#
PCI_C/BE#2
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
LDVDD
PCI_AD20
LANWAKE
PCI_AD0
PCI_AD1
104
103
PCIAD0
PCIAD1
PCIAD2
VSSPST
PCIAD3
PCIAD4
PCIAD5
PCIAD6
PCIAD7
VSSPST
PCIAD8
PCIAD9
PCIAD10
PCIAD11
PCIAD12
PCIAD13
PCIAD14
VSSPST
PCIAD15
DEVSEL#
VSSPST
CLKRUN#
GND
VDD18
VDD33
CBEB0
M66EN
VDD33
GND
VDD18
CBEB1
PAR
SERR#
GND
VDD33
PERR#
STOP#
TRDY#
C
ACT_LED# 23
RTL_LED1# 23
PCI_AD2
102
101
100
LDVDD
99
PCI_AD3
98
PCI_AD4
97
PCI_AD5
96
PCI_AD6
95
94
PCI_AD7
93
PCI_C/BE#0
92
91
PCI_AD8
90
PCI_AD9
89
88
PCI_AD10
87
PCI_AD11
86
PCI_AD12
85
84
PCI_AD13
83
PCI_AD14
82
81
80
PCI_AD15
79
LDVDD
78
PCI_C/BE#1
77
PCI_PAR
76
PCI_SERR#
75
74
NC
73
72
NC
71
PCI_PERR#
70
PCI_STOP#
69
PCI_DEVSEL#
68
PCI_TRDY#
67
66
PM_CLKRUN#
65
GIGALAN: RTL8110SBL
10/100 LAN:RTL8100C
PCI_IRDY# 16,24,28
PCI_FRAME# 16,24,28
3D3V_LAN_S5
C
EEPROM LED OPTION USE '01'
(DEFINED IN SPEC)
=> LED0 : ACT
=> LED1 : LINK
(BOTH 10/100 AND GIGA CHIP)
3D3V_LAN_S5
CTRL25
PCI_PAR 16 ,24,28
PCI_SERR# 16,24,28
PCI_PERR# 16,24,28
PCI_STOP# 16,24,28
PCI_DEVSEL# 16,24,28
PCI_T R D Y # 1 6 ,24,28
PM_CLKRUN# 16,24,28,29
G42
3D3V_S5
1 2
GAP-CLOSE-PWR
3D3V_LAN_S5
3D3V_LAN_S5
3D3V_LAN_S5
3
BCP69T1-1-GP
1
Q33
2
1 2
C351
D
PCI_C/BE#[3..0] 16,24,28
PCI_AD[31..0] 16,24,28
1 2
C354
SC10U10V5ZY-1GP
3D3V_LAN_S5
D
DY
R302 10KR2J-2-GP
1 2
1 2
R303 3K6R3-GP
1 2
1 2
C369
C353
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
XTAL-25MHZ-70GP
1 2
C364
SCD1U16V2ZY-2GP
A3
LAN_X2
LAN_X1
LAN_EECS_3
LAN_EESK
LAN_EEDI
LAN_EEDO
3D3V_LAN_S5
1 2
C365
LDVDD
SCD1U16V2ZY-2GP
3D3V_LAN_S5
RTL8100CL
SC15P50V3JN-GP
X3
1 2
SC15P50V3JN-GP
1
2
3
SCD1U16V2ZY-2GP
1 2
R306
0R0603-PAD
1 2
C356
SC1U10V3ZY-6GP
AG1(Alviso)
E
AG1-910-SB
1 2
C254
1 2
C255
VCC
ORG
8
7
DC
6
5
1 2
C357
22 40 Tuesday, October 25, 2005
3D3V_LAN_S5
1 2
C350
LAVDDL
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
01
U48
CS
SK
DI
DO4GND
AT93C46-10SU-1GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
E
Page 23
A
B
C
D
E
4 4
TGP0 22
TGN0 22
XRF_RDC
XRF_TDC
1 2
DY
3 3
1 2
C174
C215
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
123
4 5
678
10/100M Lan Transformer
U14
7
TD+
8
TD-
6
CT
14
CT
11
CT
3
CT
RJ45_45
RJ45_78
RN1
SRN75J-1-GP
LAN_TERMINAL
LAN_TERMINAL
SC1KP2KV8KX-LGP
C445
1 2
SCD01U50V3KX-4GP
DY
AG1-910-SB
2nd
C31
1 2
TX+
RD+
RX+
TX-
RD-
RX-
10
9
1
2
16
15
TDP_RJ45-1
TDN_RJ45-2
RDP_RJ45-3
RDN_RJ45-6
TGP1 22
TGN1 22
1.route on bottom as differential pairs.
2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace w id th ,1 2mi l separation.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except
RJ-45 moat.
LAN Connector
AG1-910-01
NP1
RJ45_1
RJ45_2
RJ45_3
RJ45_4
RJ45_5
RJ45_6
RJ45_7
RJ45_8
RJ11_1
RJ11_2
NP2
9
B1
B2
A1
A2
A3
10
LAN1
RJ45-107-GP
connector
22.10245.J01
2 2
2nd
MDCW1
3
1
2
4
ACES-CON2-GP-U
20.F0714.002
CONNECTOR
L2 0R0603-PAD
1 2
L1 0R0603-PAD
1 2
AG1-910-01
TIP TIP_MDC
RING RING_MDC
2nd source: 20.D0196.102
3D3V_S5
3D3V_S5
RTL_LED1# 22
ACT_LED# 22
B2:YELLOW
A1:ORANGE
A3:GREEN
R20
470R2J-2-GP
TDP_RJ45-1
TDN_RJ45-2
RDP_RJ45-3
RJ45_45
RDN_RJ45-6
RJ45_78
R33
1 2
470R2J-2-GP
RING
TIP
CONN_PWR_B2
1 2
ACT_LED#
CONN_PWR
RTL_LED1#
1 1
A
B
C
D
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
LAN CONN
AG1(Alviso)
23 40 Saturday, October 29, 2005
E
of
01
Page 24
A
B
C
D
E
3D3V_S0
1 2
1 2
1 2
C280
SCD1U16V2ZY-2GP
1 2
C274
SCD1U16V2ZY-2GP
SC1000P50V3JN-GP
4 4
SC1000P50V3JN-GP
3 3
C289
3D3V_S0
C264
AG1-910-01
2 2
PCLK_PCM 3
PCI_AD25 CARD_IDESL
1 2
R187
10R2J-2-GP
R188
1 2
100R2F-L1-GP-U
DY
CLK33_PCM1
1 2
DY
C267
SC10P50V2JN-4GP
1 1
TP95
1 2
1 2
PCI_AD[31..0] 16,22,28
PCI_C/BE#[3..0] 16,22,28
PCI_FRAME# 16,22,28
PCI_IRDY# 16,22,28
PCI_TRDY# 16,22,28
PCI_STOP# 16, 2 2,28
PCI_DEVSEL# 16,22,28
PCI_PERR# 16,22,28
PCI_SERR# 16,22,28
PCI_PAR 16,22,28
C276
SCD1U16V2ZY-2GP
C265
SCD1U16V2ZY-2GP
PCIRST1# 16,22,28
PCI_GNT#0 16
PCI_REQ#0 16
SC22P50V2JN-4GP
C271
1 2
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0
3
AD31
4
AD30
5
AD29
7
AD28
8
AD27
9
AD26
10
AD25
11
AD24
15
AD23
16
AD22
17
AD21
19
AD20
23
AD19
24
AD18
25
AD17
26
AD16
38
AD15
39
AD14
40
AD13
41
AD12
43
AD11
45
AD10
46
AD9
47
AD8
49
AD7
51
AD6
52
AD5
53
AD4
54
AD3
55
AD2
56
AD1
57
AD0
12
C_BE3#
27
C_BE2#
37
C_BE1#
48
C_BE0#
28
FRAME#
29
IRDY#
31
TRDY#
33
STOP#
13
IDSEL
32
DEVSEL#
34
PERR#
35
SERR#
36
PAR
21
PCI_CLK
20
RST#
59
RI_OUT#/PME#
2
GNT#
1
REQ#
VCCD1# 25
VCCD0# 25
VPPD1 25
VPPD0 25
3D3V_S0
3D3V_S0
50
6
PCI_VCC18PCI_VCC30PCI_VCC44PCI_VCC
VCCD1#/SMBCLK/SCLK74VCCD0#/SMBDATA/SDATA73VPPD172VPPD0/SLATCH71SUSPEND70O2MF669O2MF568O2MF467O2MF365O2MF264O2MF161O2MF060SPKR_OUT#
1 2
R184 10KR2J-3-GP
CBUS_SUSPEND
GND94GND78GND58GND42GND22GND
114
GND
130
GND
CB1410_GBRST#
102
122
CORE_VCC14CORE_VCC66CORE_VCC86CORE_VCC
CORE_VCC
GRST#
62
CB_MFUNC2
CB_MFUNC4
CB_MFUNC5
126
138
63
AUX_VCC
CORE_VCC
SOCKET_VCC90SOCKET_VCC
BVD1/STSCHG/RI/CSTSCHG
AG1-910-01
RC1 43KR3-GP
1 2
AG1-910-01
A
B
C
3D3V_S0
AG1-910-01
1 2
R182
4K7R2J-2-GP
1 2
SC1000P50V3JN-GP
REG#/CCBE3#
A25/CAD19
A24/CAD17
A23/CFRAME#
A22/CTRDY#
A21/CDEVSEL#
A20/CSTOP#
A19/CBLOCK#
A18/RFU
A17/CAD16
A16/CCLK#
A15/CIRDY#
A14/CPERR#
A13/CPAR
A12/CCBE2#
A11/CAD12
A10/CAD9
A9/CAD14
A8/CCBE1#
A7/CAD18
A6/CAD20
A5/CAD21
A4/CAD22
A3/CAD23
A2/CAD24
A1/CAD25
A0/CAD26
D15/CAD8
D14/RFU
D13/CAD6
D12/CAD4
D11/CAD2
D10/CAD31
D9/CAD30
D8/CAD28
D7/CAD7
D6/CAD5
D5/CAD3
D4/CAD1
D3/CAD0
D2/RFU
D1/CAD29
D0/CAD27
OE#/CAD11
WE#/CGNT#
IORD#/CAD13
IOW#/CAD15
WP/IOIS16/CCLKRUN#
INPACK#/CREQ#
RDY_IREQ#/CINT#
WAIT#/CSERR#
CD2/CCD2#
CD1/CCD1#
CE2/CAD10
CE1#/CCBE0#
RESET/CRST#
BVD2/SPKR/LED/AUDIO
VS2/CVS2
VS1/CVS1
DY
C261
SCD1U16V2ZY-2GP
1 2
C269
U40
CBB_REG#
125
CBB_A25
116
CBB_A24
113
CBB_A23
111
CBB_A22
109
CBB_A21
107
CBB_A20
105
CBB_A19
103
CBB_A18
100
CBB_A17
98
A_CCLKXX
108
CBB_A15
110
CBB_A14
104
CBB_A13
101
CBB_A12
112
CBB_A11
95
CBB_A10
89
CBB_A9
97
CBB_A8
99
CBB_A7
115
CBB_A6
118
CBB_A5
120
CBB_A4
121
CBB_A3
124
CBB_A2
127
CBB_A1
128
CBB_A0
129
CBB_D15
87
CBB_D14
84
CBB_D13
82
CBB_D12
80
CBB_D11
77
CBB_D10
144
CBB_D9
142
CBB_D8
140
CBB_D7
85
CBB_D6
83
CBB_D5
81
CBB_D4
79
CBB_D3
76
143
CBB_D1
141
CBB_D0
139
CBB_OE#
92
106
CBB_IORD#
93
CBB_IOWR#
96
136
123
132
133
137
75
CBB_CE2#
91
CBB_CE1#
88
119
134
135
117
131
CB-1410-U Y
Reduce start up noise
INT_PIRQG# 16
INT_PIRQB# 16
INT_SERIRQ 16,28,29
PM_CLKRUN# 16,22,28,29
VCC_ASKT_S0
1 2
C288
SCD1U16V2ZY-2GP
CBB_REG# 25
CBB_A25 25
CBB_A24 25
CBB_A23 25
CBB_A22 25
CBB_A21 25
CBB_A20 25
CBB_A19 25
CBB_A18 25
CBB_A17 25
R191 33R2J-2-GP
CBB_A15 25
CBB_A14 25
CBB_A13 25
CBB_A12 25
CBB_A11 25
CBB_A10 25
CBB_A9 25
CBB_A8 25
CBB_A7 25
CBB_A6 25
CBB_A5 25
CBB_A4 25
CBB_A3 25
CBB_A2 25
CBB_A1 25
CBB_A0 25
CBB_D15 25
CBB_D14 25
CBB_D13 25
CBB_D12 25
CBB_D11 25
CBB_D10 25
CBB_D9 25
CBB_D8 25
CBB_D7 25
CBB_D6 25
CBB_D5 25
CBB_D4 25
CBB_D3 25
CBB_D2 25
CBB_D1 25
CBB_D0 25
CBB_OE# 25
CBB_WE# 25
CBB_IORD# 25
CBB_IOWR# 25
CBB_INPACK# 25
CBB_RDY 25
CBB_WAIT# 25
CBB_CD2# 25
CBB_CD1# 25
CBB_CE2# 25
CBB_CE1# 25
CBB_RESET 25
CBB_BVD2# 25
CBB_BVD1# 25
CBB_VS2# 25
CBB_VS1# 25
1 2
1 2
CB_SPKR 26
AG1-910-01
R185
47KR2J-2-GP
D
VCC_ASKT_S0
1 2
R192
10KR2J-3-GP
CB_MFUNC5
CB_MFUNC4
INT_SERIRQ
CB_MFUNC2
SRN47KJ-L1-GP
RN52
CBB_RESET
CBB_OE#
CBB_CE2#
CBB_CE1#
AG1-910-01
CBB_WP 25
<Core Design>
Title
Size Document Number Rev
A3
Date: Sheet
CBB_D[0..15] 25
CBB_A[0..25] 25
3D3V_S0
RN50
1
8
2
7
3
6
4 5
SRN10KJ-4-GP
3D3V_S0
123
4 5
678
AG1-910-01
CBB_A16 25
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
CardBus_ENE CB1410
AG1(Alviso)
24 40 Tuesday, November 01, 2005
E
of
01
Page 25
A
B
C
D
E
PCMCIA Socket
4 4
VCC_ASKT_S0
1 2
C379
1 2
DY
SC10U10V5ZY-1GP
3 3
1 2
CBB_A16
1 2
2 2
C374
SC1000P50V3JN-GP
VPP_ASKT_S0
C372
SCD1U16V2ZY-2GP
Place close to pin 19.
C371
DUMMY-C2
Clock AC termination
33MHz clock for 32-bit
CBB_D3
CBB_CD1# 24
CBB_D4
CBB_D11
CBB_D5
CBB_D12
CBB_D6
CBB_D13
CBB_D7
CBB_D14
CBB_D15
1 2
C375
SCD1U16V2ZY-2GP
CBB_D0
CBB_D8
CBB_D1
CBB_D9
CBB_D2
CBB_D10
CBB_CD2# 24
Cardbus card I/F
CBB_A10
CBB_A11
CBB_A9
CBB_A8
CBB_A17
CBB_A13
CBB_A18
CBB_A14
CBB_A19
CBB_A20
CBB_A21
CBB_A16
CBB_A22
CBB_A15
CBB_A23
CBB_A12
CBB_A24
CBB_A7
CBB_A25
CBB_A6
CBB_A5
CBB_A4
CBB_A3
CBB_A2
CBB_A1
CBB_A0
VCC_ASKT_S0
47K
CBB_CD1#
CBB_CE1#
CBB_CE2#
CBB_OE#
CBB_VS1#
CBB_IORD#
CBB_IOWR#
CBB_WE#
CBB_RDY
CBB_VS2#
CBB_RESET
CBB_WAIT#
CBB_INPACK#
CBB_REG#
CBB_BVD2#
CBB_BVD1#
CBB_WP
CBB_CD2#
1 2
R309
DUMMY-R2
PCH1
NP1 NP2
69
1
35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9
43
10
44
11
45
12
46
13
47
14
48
15
49
16
50
17
51
18
52
19
53
20
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
66
33
67
34
68
70
CARDBUS68P-15-GP
62.10024.671
CONNECTOR
Cardbus I/F
CBB_D[0..15] 24
CBB_A[0..25] 24
CBB_IORD# 24
CBB_IOWR# 24
CBB_OE# 24
CBB_WE# 24
CBB_REG# 24
CBB_RDY 24
CBB_WP 24
CBB_RESET 24
CBB_WAIT# 24
CBB_INPACK# 24
CBB_CE1# 24
CBB_CE2# 24
CBB_BVD1# 24
CBB_BVD2# 24
CBB_VS1# 24
CBB_VS2# 24
PC1
1
CARDBUS-SKT43-GP
21.H0057.011
CONNECTOR
Power switch
2211_SHDN#
3D3V_S0
1 2
4K7R2J-2-GP
R318
AG1-910-01
VCC_ASKT_S0
VPP_ASKT_S0
3D3V_S0
1 2
5V_S0
SC1U10V3ZY-6GP
1 2
SCD1U16V2ZY-2GP
4
3 2
C363
1 2
C358
SC1U10V3ZY-6GP
TP96 TPAD28
VCCD0# 24
VCCD1# 24
VPPD0 24
VPPD1 24
C361
1 2
C362
SCD1U16V2ZY-2GP
3
4
5
6
9
1
2
15
14
U50
3.3V
3.3V
5V
5V
12V
VCCD0#
VCCD1#
VPPD0
VPPD1
SHDN#
TPS2211AIDBR-1GP
AVCC
AVCC
AVCC
AVPP
OC#
GND
16
13
12
11
10
8
7
1 2
C359
SCD01U16V2KX-3GP
1 1
A
B
C
D
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
Date: Sheet
PCMCA
A3
AG1(Alviso)
E
25 40 Tuesday, October 25, 2005
of
01
Page 26
A
B
C
D
E
C368
CB_SPKR 24
ACZ_SPKR 16
4 4
KBC_BEEP 29
ACZ_RST# 15,21
EPSON
3 3
FA-365 20PF
50PPM
2 2
1 2
SCD47U10V3ZY-GP
C366
1 2
SCD47U10V3ZY-GP
C367
1 2
SCD47U10V3ZY-GP
SCD47U10V3ZY-GP
ACZ_SYNC 15,21
AG1-910-01
ACZ_SDATAOUT 15,21
ACZ_SDATAIN0 15
C370
DY
CLK_Audio 3
CB_SPKR1
ACZ_SPKR1
KBC_BEEP1
1 2
R321
R315
R316 47R2J-2-GP
3D3V_S0_AU
1 2
C279
SCD1U16V2ZY-2GP
1
2
3
4 5
R314
DY
10R2J-2-GP
0R0402-PAD
1 2
0R0402-PAD
1 2
1 2
1 2
C376
SCD1U16V2ZY-2GP
RN70
SRN47KJ-L1-GP
1 2
AC97_SDIN
AG1-910-SB
R319
1 2
0R0402-PAD
AG1-910-01
ALC655 AC97 AUDIO CODEC
SCD1U16V2ZY-2GP
1 2
C373
SC3900P50V3KX-GP
RESET#
SYNC
BITCLK
XTLSEL
JD0/GPIO0
SDOUT
SDIN
SPDIFI/EAPD
SPDIFO
XTL-OUT
XTL-IN
1 2
C377
1 2
7
42
GND4GND
AGND26AGND
VDD1VDD9AVDD25AVDD
38
C393
SCD1U16V2ZY-2GP
SC1U10V3ZY-6GP
13
NC#40
40
C404
12
PHONE
PC-BEEP
NC#3333FRONT-MIC
34
8
AUDIO_BEEP AUDIP_PC_BEEP
7
6
1 2
R317
22KR2J-GP
11
AC97_BTCLK
CODEC_XTLSEL
5VA_S0
10
46
45
47
48
1 2
C382
SCD1U16V2ZY-2GP
6
5
8
3
2
44
43
LFE-OUT
CEN-OUT
VREF27VREFOUT
28
VREFOUT
1 2
37
MONO-OUT-R
VRDA31VRAD
32
20
19
18
CD-L
CD-R
CD-GND
FRONT-OUT-R
FRONT-OUT-L
LINE-R
LINE-L
SURR-OUT-R
SURR-OUT-L
JD1/GPIO1
AUX-R
AUX-L
AFILT129AFILT2
30
AFLT1
AFLT2
VRDA
1 2
SC1U10V3ZY-6GP
C391
SCD1U16V2ZY-2GP
U52
ALC655-U-GP
22
MIC2
21
MIC1
36
35
24
23
41
39
17
16
JD2
15
14
VREFOUT 27
Y
MIC MIC_IN
SOUNDR
SOUNDL
LINEIN_R LINE_IN_R
LINEIN_L LINE_IN_L
C390 SC3300P50V2KX-1GP
C399 SC1000P50V3JN-GP
C398 SC1U10V3ZY-6GP
ALC655_VREF
1 2
C400
1 2
C381 SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
C387
1 2
1 2
C383
SC1U10V3ZY-6GP
1 2
1 2
1 2
1 2
ALC655_VREF
C392
SCD1U16V2ZY-2GP
MIC_IN 27
LINE_IN_R 27
LINE_IN_L 27
AC97_BTCLK
ACZ_RST#
1 2
C397
SC1000P50V3JN-GP
1 2
1
2
R313
0R0402-PAD
1 2
C396
SC1000P50V3JN-GP
DY
U51
A
B
GND3Y
NC7SZ08M5X-NL-GP
5
VCC
4
AC97_BTCLK1
SOUNDR 27
SOUNDL 27
AG1-910-01
3D3V_S0_AU
R312 33R2J-2-GP
1 2
R310 33R2J-2-GP
1 2
AG1-910-01
ACZ_BITCLK 15
ACZ_BTCLK_MDC 21
AG1-910-01
POWER GENERATE
1 2
5V_S0
1 2
C409
SC1U10V3ZY-6GP
1 1
U53
1
SHDN#
SET
2
GND
IN3OUT
G923-330T1UF-1GP
SC1U10V3ZY-6GP
5
4
C384
C407
SC22P50V2JN-4GP
5VA_SETPIN
1 2
1 2
A
*Layout*
5VA_S0
20 mil
1 2
R332
28K7R3F-GP
1 2
R333
10KR3F-L-GP
C389
SC2D2U16V5ZY-2GP
AG1-910-01
B
C449
SC1U10V3ZY-6GP
5V_S0
1 2
AG1-910-01
U63
1
SHDN#
SET
2
GND
IN3OUT
G923-330T1UF-1GP
C
3D3V_S0
5
4
1 2
R370
1 2
DY
0R3-0-U-GP
C450
SC1U10V3ZY-6GP
3D3V_S0_AU
1 2
1 2
C416
C451
<Core Design>
SC22P50V2JN-4GP
SC2D2U16V5ZY-2GP
Title
Size Document Number Rev
A3
D
Date: Sheet of
AC'97 CODEC - ALC655
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
AG1(Alviso)
26 40 Tuesday, November 01, 2005
E
01
Page 27
A
B
C
D
E
AUDIO OP AMPLIFIER
AG1-910-SB
4 4
3 3
I/P signal level
need +5V level
R335
1 2
0R0603-PAD
SC1U10V3ZY-6GP
SOUNDL 26 SOUNDR 26
SOUND_L_OP1
AG1-910-01
OP+5V 5V_S0
1 2
1 2
C405
SC10U10V5ZY-1GP
10KR2J-3-GP
C299
SOUND_L2 SOUND_L_OP1
1 2
KBC_MUTE 29
R196
1 2
1 2
R195
10KR2J-3-GP
1 2
C298
SC1U10V3ZY-6GP
SYS_LOUT_IN
C410
DY
SCD1U16V2ZY-2GP
1
2
1 2
C406
SCD1U16V2ZY-2GP
SPKR_L+
SPKR_L-
D31
BAT54C-1-GP
IN1#/IN2
RIN1
RIN2
ROUT+
ROUT-
LBYPASS
GND
GND
25
G1432Q5U-GP
AMP_SHUTDOWN 29
AG1-910-01
10KR2J-3-GP
SOUND_R_OP1 SOUND_R2
18
17
SPKR_R+
19
SPKR_R-
12
3
16
1 2
C386
R327
10KR2J-3-GP
SC1U10V3ZY-6GP
1 2
C395
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
R326
C401
SC1U10V3ZY-6GP
C394
1 2
1 2
1 2
DY
1 2
SOUND_R_OP1
AG1-910-SB
1 2
3
C441
DY
SC10U10V5ZY-1GP
24
23
TP28
TPAD28
U61
1
2
7
6
8
MUTE_5
LIN1
LIN2
LOUT+
LOUT-
NC#6
NC#8
NC#23
1 2
15
20
4
VOL
LVDD
RVDD
MUTE
11
R365
100KR2J-1-GP
1 2
R320
10KR2J-3-GP
5
13
SHUTDOWN
RBYPBASS
GND/HS9GND/HS10GND/HS21GND/HS
14
22
SC1U10V3ZY-6GP
SOUNDL
SOUNDR
SC1U10V3ZY-6GP
KBC_MUTE 29
C293
1 2
1 2
C385
Q34
CHDTC124EU-1GP
SOUND_L1
SOUND_R1
R1
1
IN
AG1-910-01
10KR2J-3-GP
R193
1 2
1 2
R322
10KR2J-3-GP
SYS_LOUT_IN
OUT
3
R2
2
GND
AG1-910-SB
C446
SC2D2U16V5ZY-2GP
HP_L
HP_R
G1410Q4U-GP
SC2D2U16V5ZY-2GP
AG1-910-01
3D3V_S0_AU
1 2
U62
15
3
9
11
NC#9
PVDD
SVDD
SVSS
6
1 2
PVSS
10
NC#11
12
C1N
14
C1P
5
OUTL
7
OUTR
SGND
PGND
GND
2
13
17
4
INL
8
INR
1
SHDNR#
16
SHDNL#
C443
SPKR_L+1
SPKR_R+1
AG1-910-01
1 2
C442
SC2D2U16V5ZY-2GP
R194
10KR2J-3-GP
C294
SC470P50V2KX-3GP
R323
10KR2J-3-GP
C388
SC470P50V2KX-3GP
HP_L
1 2
1 2
HP_R
1 2
1 2
AG1-910-01
LINE OUT
AG1-A-SA AG1-A-SB
EXT\Internal MIC IN
2 2
VREFOUT 26
AG1-910-01
MIC_IN 26
SC3300P50V2KX-1GP
R199
2K2R2J-2-GP
C301
1 2
1 2
1 2
C300
SC4D7U10V5ZY-3GP
INT_MIC 30
R206 300R3-GP
SCD1U16V2ZY-2GP
1 2
EXT_MIC_IN_1
C302
INT_MIC
1 2
MIC2
NP2
NP1
8
7
5
4
3
6
2
1
PHONE-JK221-GP
22.10138.101
Y
AG1-910-01
SPKR_R+1
SPKR_L+1
AG1-910-01
AG1-A-SA
1 1
A
B
RN56
SRN1KJ-7-GP
LINE_IN_R 26
LINE_IN_L 26
AG1-910-01
3D3V_S0_AU
4
1 2
1
2 3
R364
1 2
2K2R2J-2-GP
100KR2J-1-GP
R368
1 2
1 2
C403
SC680P50V2KX-2GP
4
RN55
SRN10KJ-5-GP
1
2 3
C
1 2
EC59
C402
SC680P50V2KX-2GP
SRN1KJ-7-GP
2 3
1
RN54
SYS_LOUT_IN=High af ter PLUG-IN
PHONE-JK222-GP-U
NP2
NP1
8
7
SYS_LOUT_IN
DY
SC330P50V2KX-1GP
5
4
3
6
2
1
LOUT1
CONNECTOR
22.10138.091
Y
LINE IN
AUD_LINE_R
4
C411
AUD_LINE_L
C408
SC100P50V2JN-3GP
SC100P50V2JN-3GP
1 2
1 2
PHONE-JK222-GP-U
NP2
NP1
8
7
5
4
3
6
2
1
CONNECTOR
LIN1
22.10138.091 Y
D
Internal Speaker
SPKR_LÂSPKR_L+
SPKR_R-
SPKR_R+
123
4 5
SRC100P50V-2-GP
ERC8
678
<Core Design>
Title
Size Document Number Rev
Date: Sheet
Audio AMP and Jack
20.F0760.004
ETY-CON4-16-GP
6
4
3
2
1
5
SPKR1
CONNECTOR
2nd
1st source: 20 .D0197.104
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
AG1(Alviso)
E
AG1-A-SA
01
of
27 40 Monday, October 31, 2005
Page 28
A
B
C
D
3D3V_S0
E
1 2
C110
4 4
PCI_AD[31..0] 16,22,24
MINI1
125
1
2
3
4
5
6
7
8
9
CONNECTOR
62.10032.061
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
PIN 3-16 : LAN RESERVE
PME#_MINI
BT_COEX1
PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24
PCI_AD22
PCI_AD20
PCI_AD18
PCI_AD16
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
PCI_C/BE#0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
5V_S0
3D3V_S0
1 2
R123
100R2J-2-GP
PCI_GNT#1 16
TPAD28
TP39
TP38 TPAD28
AG1-910-01
PCI_AD21MOD_IDSEL
PCI_PAR 16 ,22,24
PCI_FRAME# 16,22,24
PCI_T R D Y # 1 6 ,22,24
PCI_STOP# 16,22,24
PCI_DEVSEL# 16,22,24
PCI_C/BE#0 16,22,24
INT_SERIRQ 16,24,29
1 2
C106
SC22P50V2JN-4GP
PCIRST1# 16,22,24
80211_ACTIVE
WLAN_TEST_LED 29
BT_COEX2
80211_ACTIVE
INT_PIRQF#
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
PCI_C/BE#3
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
PCI_C/BE#2
PCI_C/BE#1
PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
WIRELESS_EN 29
3D3V_S0
PCLK_MINI 3
3 3
TPAD28
TP40
PCI_C/BE#3 16 ,22,24
PCI_C/BE#2 16 ,22,24
PCI_IRDY# 16,22,24
PCI_SERR# 16,22,24
PCI_C/BE#1 16 ,22,24
2 2
TP41 TPAD28
PCI_REQ#1 16
PM_CLKRUN# 16,22,24,29
PCI_PERR# 16,22,24
5V_S0
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
PCISLT124-4-GP
SCD1U16V2ZY-2GP
1 2
C125
3D3V_S0
WIRELE SS_EN
SCD1U16V2ZY-2GP
AG1-910-01
1 2
R129
100KR2J-1-GP
AG1-A-SA
CHDTC124EU-1GP
1 2
C93
SCD1U16V2ZY-2GP
WLAN_LED# 13 INT_PIRQF# 16
D
2N7002PT-U
1
G
G
Q16
Q17
2 3
S
D
2N7002PT-U
1
Q20
2 3
S
OUT
3
R1
R2
2
1
GND
IN
1 1
A
B
C
D
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
MINI-PCI
AG1(Alviso)
E
28 40 Tuesday, October 25, 2005
of
01
Page 29
A
B
C
D
E
U44
155
149
148
119
118
109
108
107
106
105
86
85
75
70
69
63
62
55
54
48
22
21
20
12
11
8
6
5
4
3
41
28
27
25
24
23
98
97
94
93
92
91
168
175
171
165
162
156
3D3V_AUX_S5
E51TXD
E51CS#
KBRCIN#
KA20GATE
ECSMI#
VCC3VSB
KBC_PCIRST#
BL_ON
0R0402-PAD
AG1-910-01
KBC_SCL2
KBC_SDA2
R297
1 2
AG1-910-SB
1 2
KBC_XO
158
XCLKO
KBC_XI
XCLKI
122
1 2
137
SC22P50V2JN-4GP
X4
3
SC22P50V2JN-4GP
GND
GND
167
C326
Y
1 2
C327
GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO09
GPIO08
GPIO07
GPIO06
GPIO05
GPIO04
GPIO03
GPIO02
GPIO01
GPIO00
GPIO0F
GPIO0E
GPIO0D
GPIO0C
GPIO0B
GPIO0A
GPIO1F
GPIO1E
GPIO1D
GPIO1C
GPIO1B
GPIO1A
GPIOI2D
GPIO2F
GPIO2E
GPIO2C
GPIO2B
GPIO2A
CHANGE TO 71.03910.B0G
3D3V_AUX_S5
1 2
4 4
3 3
2 2
C206
SCD1U16V2ZY-2GP
KA20GATE_1 15
KBRCIN#_1 15
ECSCI#_1 16
1 2
1 2
C191
SCD1U16V2ZY-2GP
5V_S0
C217
SCD1U16V2ZY-2GP
D20
6
5
CH731UPT-GP
1
2 3
KA20GATE
1
KBRCIN#
2
ECSCI#
3 4
5V_S0
RN26
4
SRN10KJ-5-GP
LPC_LAD[0..3] 15
KBCBIOS_RD# 31
KBCBIOS_WE# 31
KBCBIOS_CS# 31
KBC_D[0..7] 31
RN25
8
7
6
SRN10KJ-4-GP
TDATA_5
TCLK_5
LPC_LFRAME# 15
PCLK_KBC 3
INT_SERIRQ 16,24,28
1
2
3
4 5
KBCBIOS_RD#
KBCBIOS_WE#
KBCBIOS_CS#
A0 31
A1 31
A2 31
A3 31
A4 31
A5 31
A6 31
A7 31
A8 31
A9 31
A10 31
A11 31
A12 31
A13 31
A14 31
A15 31
A16 31
A17 31
A18 31
TDATA_5 30
TCLK_5 30
3D3V_AUX_S5
1 2
C179
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
KBC_D0
KBC_D1
KBC_D2
KBC_D3
KBC_D4
KBC_D5
KBC_D6
KBC_D7
L10
1 2
0R0603-PAD
15
14
13
10
9
18
7
150
151
173
152
138
139
140
141
144
145
146
147
124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103
117
116
115
114
111
110
C182
LAD0
LAD1
LAD2
LAD3
LFRAME#
LCLK
SERIRQ
RD#
WR#
MEMCS#
IOCS#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
PSDAT3
PSCLK3
PSDAT2
PSCLK2
PSDAT1
PSCLK1
AG1-910-SB
3D3V_KBC_AUX_S5
1 2
123
VCC16VCC34VCC45VCC
LPC
X-bus
ROM
PS/2
PWM743PWM640PWM539PWM438PWM337PWM236PWM133PWM0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
53
KSO251KSO352KSO4
60
KSO556KSO657KSO758KSO859KSO9
136
157
166
VCC
VCC
VCC
50
161
95
KSO049KSO1
VCCA
VCCBAT
KB Matrix
KB3910
DA099DA1
GPWU02GPWU126GPWU229GPWU330GPWU444GPWU576GPWU6
32
DA2
GPWU7
100
101
102
172
176
KCOL[1..16] 30
KROW[ 1..8] 30
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
153
154
KSO1061KSO1164KSO1265KSO1366KSO1467KSO1568KSO16
KSO17
AD081AD182AD283AD384AD487AD588AD689AD7
DA3
DA41DA542DA647DA7
174
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KSI071KSI172KSI273KSI374KSI477KSI578KSI679KSI7
KROW7
KROW8
KBC_SCL2
KBC_SDA2
BAT_SCL
BAT_SDA
80
ECRST#19ECSCI#
90
160
163
169
164
170
SCL1
SCL2
SDA1
SDA2
AGND96BATGND
GND17GND35GND46GND
31
159
5V_S0
678
RN41
SRN10KJ-4-GP
123
4 5
MATRIXID2# 31
MATRIXID1# 31
PRE_CHG 38
BLT_BTN# 30
CHG_ON# 38
AD_OFF 39
STDBY_LED# 13
INTERNET# 30
MAIL# 30
PM_SLP_S4# 16,37
3S1P_I 38
PM_SUS_STAT# 16
CAP_LED# 13
FRONT_PWRLED# 13,30
KBC_MUTE 27
KEY5# 30
WIRELESS_BTN# 30
KEY4# 30
ECSMI# 16
WIRELESS_EN 28
PM_CLKRUN# 16,22,24,28
FPBACK 13
NUM_LED# 13
BLUETOOTH_EN 21
DC_BATFULL# 13
BLT_LED# 13
WLAN_TEST_LED 28
MAIL_LED# 30
CHARGE_LED# 13
AMP_SHUTDOWN 27
BL_ON 7
TP56
1 2
C336
SC150P50V2JN-3GP
D
AG1-A-SA
3D3V_S5
3D3V_S0
G
1
2 3
S
Q30
2N7002PT-U
BAT_IN#
KBC_BB_ENABLE#
BAT_IN# 39
PLT_RST1# 7,16,18
1 2
R296
100KR2J-1-GP
1 2
C332
SC1U10V3ZY-6GP
D
2N7002PT-U
3D3V_AUX_S5
1 2
R174
AG1-910-01
AG1-910-01
G
1
2 3
Q31
R176
100KR2J-1-GP
BAT_SCL 39
BAT_SDA 39
S
1 2
1 2
R170
100KR2J-1-GP
PM_PWRBTN#
SMBC_G792
SMBD_G792
100KR2J-1-GP
3D3V_S5
1 2
2 3
1
KBC_SLP_WAKE
R285 10KR2J-2-GP
PRE_CHG
R286 10KR2J-2-GP
AG1-910-01
R240
10KR2J-3-GP
RN29
SRN8K2J-3-GP
SMBC_G792 19
SMBD_G792 19
3D3V_AUX_S5
4
1 2
DY
1 2
DY
KBC_BEEP 26
A1
AG1-910-01
1 2
R186
10KR2J-3-GP
A1 for the internal pull-up resistors on XIOCS[F:0] pins==>Hig h=enable,Low=Disable
A4 for DMRP==>High=Disable,Low=Enable
1 1
A5 for EMWB==>High=Enable,Low=Disable
GPIO05 for Clock test mode==>High=test Mode,Low=32KHz clock in normal running(Recommended)
GPIO06 for DPLL test mode==> High=Test Mode,Low=Normal op

ECSWI# 16
PM_PWRBTN# 16
RSMRST#_KBC 16,32
S5_ENABLE 35
BRIGHTNESS 13
PM_SLP_S3# 16,18,32,35,37
KBC_PWRBTN# 30
AC_IN# 38
KBC_LID# 30
KBC_SLP_WAKE 16
eration(Recommended)
RSMRST#_KBC
BRIGHTNESS
KBC_SLP_WAKE
Place near K/B Connector (TOP side)
USB_PWR_EN# 21
3S2P_I
38
AG1-A-SA
A
B
KBC_BB_ENABLE#
C
EC_RST#
ECSCI#
GAP-OPEN
G11
AG1-910-SB
2 1
C413
3D3V_AUX_S5
B
CH3906PT-GP
Q28
SRN10KJ-5-GP
2 3
1
RN49
4
D
RSMRST# 19
S5_ENABLE 35
AG1-910-01
100KR2F-L1-GP
<Core Design>
Title
Size Doc ument N umber Re v
Custom
Date: Sheet
KBC ENE
AG1(Alviso)
1 2
R34
Wistron Corporation
21F, 88, Se c .1, Hsin T ai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
E
1 2
E
C
SCD1U16V2ZY-2GP
01
of
29 40 Thursday, October 27, 2005
Page 30
A
LAUNCH BD CONN
3D3V_S0
1 2
EC20
MAIL_LED#
MAIL#_1
INTERNET#_1
KEY4#_1
KEY5#_1
PWRBTN#
SCD1U16V2ZY-2GP
EC58
SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
MAIL_LED# 29
123
4 5
SRC100P50V-2-GP
ERC1
678
INT_MIC 27
AG1-A-SB
WIRELESS_BTN# 29
1
2
3
4 5
SRN470J-3-GP
RN28
WLBTN1
4
Y
5
SW-SLIDE34
62.40018.191
CONNECTOR
8
7
6
1
2
3
4 4
LAUNCH1
AG1-910-SB
ACES-CON12-GP
20.K0174.012
CONNECTOR
14
12
11
10
9
8
7
6
5
4
3
2
1
13
1 2
EC21
2nd
2nd source: 20.K0185.012
3 3
WIRELESS_BTN#
BLT_BTN#
SCD1U16V2ZY-2GP
EC57
1 2
1 2
DY
B
MAIL#_1
INTERNET#_1
KEY4#_1
KEY5#_1
SRN10KJ-4-GP
MAIL# 29
INTERNET# 29
KEY4# 29
KEY5# 29
3D3V_S0
4
RN58
SRN10KJ-5-GP
1
2 3
C
3D3V_S5
RN44
1
8
2
7
3
6
4 5
3D3V_AUX_S5
AG1-910-01
1 2
R58
10KR2J-3-GP
470R2J-2-GP
MAIL_LED#
1 2
R61
EC30 SC100P50V2JN-3GP
1 2
1 2
C58
SCD1U16V2ZY-2GP
AG1-A-SA
KBC_PWRBTN# 29
13
BTBTN1
SW-SLIDE34
62.40018.191
CONNECTOR
1
2
3
BLT_BTN# 29
Level Trigger
4
Y
5
Cover Up Switch
AG1-A-SA
4
3
PUSH-SW81-GP
62.40014.141
CONNECTOR
TOUCH PAD
TDATA_5 29
TP_SCROLL_LEFT
SCRL2
1 2
5
62.40009.431
CONNECTOR
2nd
4 3
SW-TACT-59-GP-U1
2nd source: 62.40009.341
LID1
TCLK_5 29
SW-TACT-59-GP-U1
D
2
1
TP_SCROLL_UP
SCRL1
1 2
62.40009.431
CONNECTOR
2nd
TP_SCROLL_DOWN
SCRL4
1 2
SW-TACT-59-GP-U1
62.40009.431
CONNECTOR
5
4 3
5
4 3
2nd
AG1-910-01
R169
1 2
100R2F-L1-GP-U
SCD1U16V2ZY-2GP
RN27
1
2 3
SRN100J-3-GP
TP_SCROLL_RIGHT
SCRL3
1 2
SW-TACT-59-GP-U1
62.40009.431
CONNECTOR
2nd
3D3V_AUX_S5
1 2
R167
10KR2J-3-GP
1 2
C183
SCD22U16V3ZY-GP
EC51
DY
4
5
4 3
SW-TACT-59-GP-U1
AG1-910-01
1 2
TP_LEFT
LEFT1
1 2
62.40009.431
CONNECTOR
E
KBC_LID# COVER_SW#
5V_S0
1 2
C189
SC1U10V3ZY-6GP
TP_DATA
TP_CLK
TP_SCROLL_RIGHT
TP_SCROLL_UP
TP_SCROLL_DOWN
TP_LEFT
TP_RIGHT
TP_SCROLL_LEFT
2nd source: 20.K0185.012
5
4 3
2nd
SW-TACT-59-GP-U1
KBC_LID# 29
14
12
11
10
9
8
7
6
5
4
3
2
1
13
ACES-CON12-GP
CONNECTOR
20.K0174.012
TP_RIGHT
RIGHT1
1 2
62.40009.431
CONNECTOR
TPAD1
2nd
5
4 3
2nd
EMI Bypass cap.
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KROW[1..8] 29
KCOL[1..16] 29
Pin1 ==>*R01
Pin2 ==>*R02
Pin3 ==>*R03
Pin4 ==> C01
Pin5 ==> C02
Pin6 ==> C03
Pin7 ==>*R04
Pin8 ==> C04
Pin9 ==> C05
Pin10 ==> C06
Pin11 ==> C07
Pin12 ==> C08
Pin13 ==> C09
Pin14 ==>*R05
Pin15 ==> C10
Pin16 ==>*R06
Pin17 ==>*R07
Pin18 ==> C11
Pin19 ==> C12
Pin20 ==>*R08
Pin21 ==> C13
Pin22 ==> C14
Pin23 ==> C15
Pin24 ==> C16
Pin25 ==> NC
C
KROW7
KCOL11
KCOL12
KROW8
KCOL5
KCOL6
KCOL7
KCOL8
KCOL2
KCOL3
KROW4
KCOL4
KCOL9
KROW5
KCOL10
KROW6
KROW1
KROW2
KROW3
KCOL1
KCOL13
KCOL14
KCOL15
KCOL16
ERC6
1
2
3
4 5
SRC100P50V-2-GP
ERC4
1
2
3
4 5
SRC100P50V-2-GP
ERC3
1
2
3
4 5
SRC100P50V-2-GP
ERC5
1
2
3
4 5
SRC100P50V-2-GP
ERC2
1
2
3
4 5
SRC100P50V-2-GP
ERC7
1
2
3
4 5
SRC100P50V-2-GP
ERC10
DY
8
7
6
DY
8
7
6
DY
8
7
6
DY
8
7
6
DY
8
7
6
DY
8
7
6
D
TP_DATA
TP_CLK
TP_RIGHT
TP_SCROLL_RIGHT
TP_SCROLL_UP
TP_SCROLL_LEFT
TP_SCROLL_DOWN
TP_LEFT
<Core Design>
Title
Size Document Number Rev
A3
Date: Sheet
1
2
3
4 5
1
2
3
4 5
BUTTONs / KB / TOUCHPAD
AG1-910
DY
8
7
6
SRC100P50V-2-GP
ERC9
DY
8
7
6
SRC100P50V-2-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
30 40 Tuesday, November 01, 2005
E
of
01
Internal KeyBoard CONN
2 2
KB1
12 5
........
1 1
ACES-CON25-GP
2nd source: 20.K0198.025
NC#26
C01
C02
C03
R01
R02
R03
C04
R04
R05
R06
R07
R08
R09
C05
R10
C06
C07
R11
R12
C08
R13
R14
R15
R16
NC#25
NC#27
20.K0197.025
CONNECTOR
26
KROW1
1
KROW2
2
KROW3
3
4
5
6
KROW4
7
8
9
10
11
12
13
KROW5
14
15
KROW6
16
KROW7
17
18
19
KROW8
20
21
22
23
24
25
27
2nd
A
B
Page 31
5
D D
C C
3D3V_S0
KBC_D[0..7] 29
KBCBIOS_WE# 29
KBCBIOS_RD# 29
KBCBIOS_CS# 29
KBC_D0 29
KBC_D1 29
KBC_D2 29
KBC_D3 29
KBC_D4 29
KBC_D5 29
KBC_D6 29
KBC_D7 29
4
3D3V_AUX_S5
1 2
A0 29
A1 29
A2 29
A3 29
A4 29
A5 29
A6 29
A7 29
SCD1U16V2ZY-2GP
C360
U49
13
DQ0
14
DQ1
15
DQ2
17
DQ3
18
DQ4
19
DQ5
20
DQ6
21
DQ7
32
22
VDD
VSS
16
3
24
1
31
CE#
OE#
WE#
A012A111A210A39A48A57A66A7
A162A1730A18
3
A15
29
A14
28
A13
4
A12
25
A11
23
A10
26
A9
27
A8
5
(SOCKET) 62.10002.032 - (IC)72.39040.H03 IN DIP,SMT
ROM SIZE MAX. 512KBYTE
2
A18 29
A17 29
A16 29
A15 29
A14 29
A13 29
A12 29
A11 29
A10 29
A9 29
A8 29
1
PLCC32 Socket P/N:
SSKT3262.10002.032
1
2 3
SRN10KJ-5-GP
RN8
B B
4
PH at ICH6M
CHK_PW# 16
MATRIXID1# 29
MATRIXID2# 29
1 2
EC44
SC1000P50V3JN-GP
AG1-910-01
Plz put G12 close SW1
GAP-OPEN
G12
SW1
1
2
3
4
SW-DIP-4-2-U2-GP
CONNECTOR
DY
2 1
5
6
7
8
DY
A A
Keyboard matrix ( from vendor )
Low Bit
High Bit
MATRIXID1#
MATRIXID2#
1
Jap US
10 0
0 1
Other Eur
10
5
4
SSKT32 62.10005.032
Board ID
PCB_VER0 16
PCB_VER1 16
PCB_VER0
PCB_VER1
3
3D3V_S0
1 2
1 2
R243
10KR2J-3-GP
DY
R245
10KR2J-3-GP
DY
1 2
R221
10KR2J-3-GP
DY
1 2
R220
10KR2J-3-GP
DY
Planar ID(2,1,0)
SA:
SB:
-1 :
2
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
BIOS ROM
AG1-910
of
31 40 Tuesday, November 01, 2005
1
01
Page 32
Run Power
DCBATOUT
AG1-910-01
R48
1 2
10KR2J-3-GP
R50
1 2
330KR2J-L1-GP
AG1-910-01
RUN_POWER1
RUN_POWER2
TP0610K-T1-GP
S
2 3
1
G
1 2
Q11
R51
1KR2J-1-GP
5V_S0 5V_S5
C42
1 2
SCD1U16V2ZY-2GP
K A
D8
MMGZ5242BPT-GP
3D3V_S0
1 2
C46
SCD1U50V3ZY-GP
RUN_POWER_ON
1 2
AG1-910-01
R52
330KR2J-L1-GP
D
U13
S
1
2
3
4 5
1
2
3
4 5
D
U11
D
D
D
D
D
8
7
6
3D3V_S5
8
7
6
S
S
GD
AO4422-1-GP
S
S
S
GD
AO4422-1-GP
AG1-910-01
PWRGD to Turn on CPU_Core_Power
PM_SLP_S3
OUT
AG1-A-SA
Q13
CHDTC124EU-1GP
PM_SLP_S3# 16,18,29,35,37
5V_S5
1 2
E
CH3906PT-GP
R301
10KR2J-3-GP
5V_AUX_2951
1 2
B
Q32
C
1 2
C344
SC1U10V3ZY-6GP
RSMRST#_KBC 16,29
SCD1U16V2ZY-2GP
AG1-910-01
1 2
C349
R1
1
IN
AG1-910-01
R300
10KR2J-3-GP
1
2
3
4
LP2951CDR2G-GP
3
R2
2
GND
U47
SCD1U16V2ZY-2GP
OUTPUT
SENSE
SHUTDOWN
100mA
GND
DY
C348
1 2
INPUT
FEEDBACK
VO TAP
ERROR# OUTPUT
5V_S5
D29
2 1
CH521S-30-GP-U
D28
2 1
CH521S-30-GP-U
DCBATOUT
8
7
6
C282
5
DUMMY-C5
1 2
1 2
C283
SC1U50V5ZY-1-GP
1 2
C340
DUMMY-C3
1 2
C337
SC10U10V5ZY-1GP
5V_S5_G913
1 2
C342
SC1U10V3ZY-6GP
PWRGD for NB and SB
3D3V_S0
AG1-910-01
1 2
R209
1KR2J-1-GP
R208
1 2
0R0402-PAD
Aux Power
3D3V_AUX_S5
3D3V_AUX_S5
1 2
C339
SC22P50V2JN-4GP
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
1 2
C343
DY
RUN POWER and 3D3V_AUX_S5
1
2
3
U46
SHDN#
GND
IN
G913CF-GP
5
SET
4
OUT
SC10U10V5ZY-1GP
C338
3D3V_AUX_S5
3D3V_G913_SET
1 2
1 2
C341
<Core Design>
Title
Size Document Number Rev
A3
Date: Sheet
VGATE_PWRGD 7,16 6218_PGOOD 3,34
Rx
1 2
R298
16K5R2F-1-GP
O utput = 3.3V
output=1.25(1+(Rx/Ry))
1 2
R299
10KR2F-2-GP
AG1-910-01
Ry
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
AG1-910
32 40 Tuesday, October 25, 2005
01
of
Page 33
A
B
C
D
E
CPU_CORE ISL6218CV
H_VID0
H_VID1
4 4
3 3
H_VID2
H_VID3
H_VID4
H_VID5
CPUCORE_ON
PM_DPRSLPVR
VCC_CORE_S0
DCBATOUT
VID Setting
VID0(I / 1.05V)
VID1(I / 1.05V)
VID2(I / 1.05V)
VID3(I / 1.05V)
VID4(I / 1.05V)
VID5(I / 1.05V)
Input Signal
EN(I / 3.3V)
DRSEN(I / 3.3V)
DSEN# (I / 3.3V) PM_STPCPU#
Voltage Sense
VSEN(I / 1.55V / 1.35V)
Input Power
VCC(I)
Output Signal
PGOOD(OD / 3.3V)
Output Power
VCC_CORE(O)
6218_PGOOD
VCC_CORE (27A)
SHUTDOWN_S5
SHUTDOWN_S5
PM_SLP_S3#
PM_SLP_S3#
DCBATOUT_5130
DCBATOUT_5130
DCBATOUT
5V_S5
5V_AUX_S5
5V_S0
Input Signal
SS_STBY1(I / 5V)
SS_STBY2(I / 5V)
SS_STBY3(I / 5V)
STBY_LDO(I / 5V)
STBY_VREF5(I / 28V)
STBY_VREF3.3(I / 28V)
Input Power 1D05V (5.2A)
VIN (I / 28V)
REG5V_IN(I / 5V)
5V_AUX_S5
For PGOUT
TPS5130
3D3V/5V/1D05V/2D5V
Output Signal
FOR
5V
FOR
3.3V
FOR
1.05V
FOR
1.8V
PGOUT(OD / 5V)
Output Power
ISL6227
3D3(O)
5V(O)
1D05V(O)
2D5V (O)
TPS5130_PWRGD
3D3V (6A)
5V (6A)
2D5V (3.5A)
1D8V/1D5V
5V_S0
VCC(I)
Input Signal
Output Signal
EN1 (I)
2 2
CHG_ON#/OFF
BAT_IN#
KBC_SCL0
KBC_SDA0
CHG_I_PRE_SEL
1 1
Charger_ISL6255
Input Signal Output Signal
EN (I / 3.3V)
THM (I / 3.3V)
SCL (IO / 5V)
SDA (IO / 5V)
CHLIM (IO / 5V)
PB0/MOSI/AIN0
Input Power
DCIN (I)
A
ACPRN (O / 3.3V)
XTAL2/PB4 (O/5V)
Output Power
VCC (O)
VCC (O)
AC_IN
CHARGE_LED#
DCBATOUT
BT+
B
PM_SLP_S3#_ICH
5V_S5
EN2 (I)
Input Power
VCC (I)
Adapter
AD_OFF DC_IN+
AD_JK
5V_AUX_S5
Input Signal
(I)
Input Power Output Power
VCC(I)
VCC(I)
C
Output Signal
(O)
VCC(O)
AD+
D
Output Power
<Core Design>
Title
Size Document Number Rev
A3
Date: Sheet
PG1
PG2/REF
1D8V (O)
1D5V (O)
CPUCORE_ON PM_SLP_S4#
CPUCORE_ON
1D8V_S3 (6A)
1D5V_S0 (6A)
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Power Diagram
AG1(Alviso) 01
33 40 Monday, October 17, 2005
E
of
Page 34
A
B
C
DCBATOUT_6218
D
E
DCBATOUT DCBATOUT_6218
L4
4 4
SCD027U50V3KX-GP
CORE_AGND
CPUCORE_ON 37
PM_DPRSLPVR 16
PM_STPCPU# 3,16
H_VID0 5
H_VID1 5
1K8R3F
H_VID2 5
H_VID3 5
H_VID4 5
H_VID5 5
C112
DY
SC470P50V2KX-3GP
PH 10K P.45
1 2
R111
6K04R3F-GP
1 2
DY
1 2
R121
3 3
IMVP IV
Load Line Slope :3mR
2 2
25A*3mV/A=> 75mV
C111
1 2
R108
1 2
100KR2F-L1-GP
6218_PGOOD 3,32
1 2
C115
DUMMY-C3
Idroop = 75mV / 6.04K = 12.4uA
VCC_CORE_S0
SC1U10V3ZY-6GP
1 2
1 2
1 2
R117 0R0603-PAD
1 2
R116 0R0603-PAD
1 2
1 2
1 2
1 2
1 2
1K21R2F-2-GP
R112
1 2
R127
15KR3F-GP
C119
SC2200P50V2KX-2GP
R125
4K7R3F-GP
R113 243KR3F-GP
R115 0R0402-PAD
R114 1KR2J-1-GP
C118
SC1000P50V3JN-GP
5V_S0
C114
CORE_AGND
6217_DAC
6217_DSV
6217_FSET
6217_PWRCH
6217_EN#
6217_DRSEN
6217_DSEN#
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
6217_EA+
6217_COMP
6217_SOFT
1 2
R126
10R3J-3-GP
6217_VDD
1 2
6217_FB
1 2
CORE_AGND
1 2
R124
3K57R3F-L-GP
AG1-910-01
1 2
BLM41PG600-GP
AG1-910-01
SCD1U50V3ZY-GP
U29
1
VDD
2
DACOUT
3
DSV
4
FSET
5
NC#5
6
EN
7
DRSEN
8
DSEN#
9
VID0
10
VID1
11
VID2
12
VID3
13
VID4
14
VID5
15
PGOOD
16
EA+
17
COMP
18
FB
19
SOFT
ISL6218CVZ-TGP
C113
SCD022U16V2KX-3GP
AG1-910-01
VCC_CORE_S0
C127
CORE_AGND
VBAT
ISEN1
PHASE1
UG1
BOOT1
VSSP1
LG1
VDDP
NC#31
NC#29
NC#28
NC#27
NC#26
NC#25
VSEN
DRSV
STV
OCSET
VSS
G41
1 2
GAP-CLOSE
1 2
CORE_AGND
1 2
R138
4D7R3J-L1-GP
6217_VBAT
1 2
CORE_AGND
C128
SC1U10V3ZY-6GP
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
5V_S0
6217_ISEN1
6217_PHASE1
6217_UG1
6217_BOOT1
6217_LG1
6217_DRSV
6217_STV
6217_OCSET
1 2
C129
SC4D7U10V5ZY-3GP
CORE_AGND
4K7R3F-GP
1 2
AG1-910-SB
R131
1 2
54K9R3F-GP
1 2
R130
174KR3F-GP
DY
1
BAT54-4-GP
3
R137
46K4R3F-1-GP
1 2
2
D17
R133
1 2
C130
SC1800P50V3KX-GP
1 2
0R0402-PAD
R132
AG1-910-01 AG1-910-01
1 2
C134
SCD33U16V3ZY-GP
R140
1 2
75KR3F-GP
1 2
C132
SC680P50V2KX-2GP
CORE_AGND
AG1-910-SB
1 2
C148
U31
2nd
1 2
1 2
R148
R146
1 2
C138
SC10U25V0KX-3GP
678
DDD
G D
AO4422-1-GP
4 5
U33
2nd
AO4430-1-GP
4 5
12.4uA/0.87/0.5 = 28.54uA
Rds(on) *Io = Isen * Rsen
(5m/2)*25A=28.54uA*Rsen
R33 = 2.18K ~ 2.15K
1 2
R147
G D
SSS
123
678
DDD
1 2
R150
1 2
C159
SC10U25V0KX-3GP
U32
2nd
U34
2nd
SSS
123
1 2
R149
SC10U25V0KX-3GP
678
G D
AO4422-1-GP
4 5
AO4430-1-GP
4 5
1D05V_S0
1 2
DDD
678
G D
R151
123
DDD
1 2
C170
SSS
123
SC10U25V0KX-3GP
SSS
1 2
EC48
SCD1U50V3ZY-GP
1 2
R280
0R2J-GP
DY
1 2
DY
C320
SC1000P50V3JN-GP
SE330U2VDM-4-GP
TC15
2nd
L22
1 2
L-D56UH-2-GP
K A
D19
SSM34APT-GP
DY
1 2
1 2
DY
TC12
ST330U3VDM-1-GP
2nd
1 2
TC7
SE470U2D5VDM-LGP
2nd
VCC_CORE_S0
1 2
TC14
SE470U2D5VDM-LGP
2nd
VCC_CORE_S0
1 2
TC6
SE330U2VDM-4-GP
2nd
H_VID0
1. U12,U14:AO4422 84.04422.037
U13,U15:AO4430 84.04430.B37
1 1
R100:3K83R2F
2. U12,U14:IRF7413 84.07413.037
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
U13,U15:IRF7832-U 84.07832.037
R100:2K43R2F
A
B
C
DUMMY-R2
DUMMY-R2
1 2
R265
DUMMY-R2
DUMMY-R2
DUMMY-R2
1 2
1 2
R266
1 2
R269
DUMMY-R2
DUMMY-R2
R267
DUMMY-R2
DUMMY-R2
DUMMY-R2
1 2
1 2
R270
R268
DUMMY-R2
DUMMY-R2
D
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
VCC_CORE
AG1(Alviso)
34 40 Thursday, October 27, 2005
E
of
01
Page 35
5
4
3
2
1
AG1-SB-910
DCBATOUT_51120
G43
1 2
GAP-CLOSE-PWR
G45
1 2
GAP-CLOSE-PWR
D D
DCBATOUT
C C
AG1-SB-910
B B
GND
SKIPSEL
COMP
TONSEL
A A
VFB1
VFB2
EN1,EN2
EN3,EN5 not use
AUTOSKIP
N/A
380k/CH1
590k/CH2
N/A
N/A
Switcher OFF
LDO OFF
1 2
GAP-CLOSE-PWR
1 2
GAP-CLOSE-PWR
1 2
GAP-CLOSE-PWR
S5_ENABLE 32
TP24 TPAD28
TP26 TPAD28
51120_V5FILT
5
G46
G49
G51
VREF2
AUTOSKIP
/FAULTS
OFF
N/A
290k/CH1
440k/CH2
not use
not use
not use
DCBATOUT_51120
1 2
1 2
R346 0R0603-PAD
1 2
R349 0R0603-PAD
1 2
R352 0R0603-PAD
AG1-910-01
CURRENT
MODE
220k/CH1
330k/CH2
Swithchr ON
LDO ON
51120_VREG5
AG1-910-01
51120_LL2
R340 0R0603-PAD
51120_LL1 51120_LL1_1
R341 0R0603-PAD
0R0603-PAD
R347
51120_GND
51120_V5FILT
FLOAT
PWM
ADJ.
ADJ.
51120_LL2_1 51120_VBST2
1 2
1 2
SC10U10V5KX-2GP
51120_GND 51120_GND
TPS51120_EN3
TPS51120_EN5
1 2
R353
R354
1 2
C422
51120_EN1
51120_EN2
51120_VFB2
51120_VFB1
5V_PWR
3D3V_PWR
51120_VREF2
C424
SC1000P50V3JN-GP
TPS51120RHBR-GPU1
11KR3F-GP
1 2
1 2
11KR3F-GP
SC10U10V5KX-2GP
V5FILT
PWM
D-Cap
MODE
180k/CH1
280k/CH2
5V
Fixed Output
3.3V
Fixed Output
Switcher ON
VREG3 on
R339
1 2
5D1R3F-GP
SC1U10V3ZY-6GP
C418
1 2
SCD1U50V3ZY-GP
C419
51120_VBST1
1 2
SCD1U50V3ZY-GP
51120_VREG5
51120_VREG3
1 2
C423
29
EN1
12
EN2
10
EN3
9
EN5
6
VFB2
3
VFB1
1
VO1
8
VO2
4
VREF2
U12
51120_CS1
51120_CS2
DY
C428
SC390P50V3JN-GP
51120_V5FILT
C417
51120_GND
19
21
28
VBST1
VREG3
VREG5
GND
PGND2
PGND1
GND
5
17
24
33
51120_GND
51120_COMP1
DY
1 2
51120_GND
4
1 2
DCBATOUT_51120
20
22
13
VBST2
V5FILT
CS1
18
23
1 2
R358
30KR3F-2-GP
51120_COMP1_PL
1 2
DY
C430
AG1-910-SB
1 2
C420
SCD1U50V3ZY-GP
51120_COMP2
51120_COMP1
2
7
VIN
COMP1
COMP2
CS2
TONSEL31SKIPSEL
32
51120_SKIPSEL
1 2
R355
0R0603-PAD
51120_GND
DY
C429
SC1000P50V3JN-GP
R343 0R0603-PAD
R344 0R0603-PAD
LL2
LL1
PGOOD1
PGOOD2
DRVL1
DRVL2
DRVH1
DRVH2
1 2
R363
0R0603-PAD
AG1-910-01
51120_COMP2
1 2
SC390P50V3JN-GP
1 2
1 2
AG1-910-01 AG1-910-01
15
26
51120_PGD1
30
51120_PGD2
11
25
16
27
14
1 2
DY
51120_COMP2_ PL
1 2
51120_GND
51120_V5FILT
51120_LL2
51120_LL1
51120_DRVL1
51120_DRVL2
51120_DRVH1
51120_DRVH2
AG1-910-01
51120_VREF2
R359
22KR3F-GP
SC680P50V3JN-GP
DY
C431
1 2
AO4422-1-GP
51120_DRVH1
51120_LL1
AO4702-1-GP
51120_DRVL1
678
DDD
U10
2nd
G D
4 5
678
U9
DDD
2nd
GD
4 5
SSS
123
SSS
123
1 2
SC10U35V0ZY-1GP
C117
SC10U35V0ZY-1GP
L17
1 2
IND-4D7UH-85-GP
51120_VFB1
2nd
DY
C421
1 2
C87
SC33P50V3JN-GP
1 2
DY
1 2
1 2
DY
3D3V_S0
51120_GND
1 2
R348
100KR2J-1-GP
DY
1 2
R350 0R 2J-GP
1 2
R351
DY
For TPS51120,
Vout=5V
1. If you use a 6.8uH inductor, the minimum ESR is 70m ohm.
2. If you use a 4.7uH inductor, the minimum ESR is 48m ohm.
3. If you use a 3.3uH inductor, the minimum ESR is 34m ohm.
Vout=3.3V
1. If you use a 4.7uH inductor, the minimum ESR is 51m ohm.
2. If you use a 3.3uH inductor, the minimum ESR is 36m ohm.
3. If you use a 2.5uH inductor, the minimum ESR is 27m ohm.
0R2J-GP
3
DY
AO4422-1-GP
51120_DRVH2
51120_LL2 51120_LL2 51120_LL2 51120_LL2
AO4702-1-GP
U7
2nd
U8
2nd
51120_DRVL2
678
DDD
G D
4 5
678
DDD
GD
4 5
SSS
123
SSS
123
1 2
SC10U35V0ZY-1GP
AG1-910-SB
1 2
IND-2D5UH-7-GP
C427
DY
51120_VFB2
C34
SC10U35V0ZY-1GP
L14
DCBATOUT_51120
1 2
C30
SC33P50V3JN-GP
1 2
1 2
DY
R356
1 2
DY
51120_GND
3D3V_PWR
1 2
30K9R3F-GP
R357
13KR3F-GP
2
EC7
SCD1U50V3ZY-GP
5V_PWR
5V Iomax=5A
OCP>10A
1 2
R342
30KR3F-2-GP
TC3
ST220U6D3VDM-13GP
2nd
SANYO 220uF ESR=25mohm
Iripple=2.4A
R345
7K5R3F-L1-GP
3D3V Iomax=5A
OCP>10A
TC2
ST220U6D3VDM-13GP
2nd
SANYO 220uF ESR=25mohm
Iripple=2.4A
<Core Design>
Title
Size Document Number Rev
A3
Date: Sheet of
3D3V_PWR 3D3V_S5
AG1-SB-910
Vout=1V*(R1+R2)/R2
TPS51120_3D3V_5V
AG1(Alviso)
G44
1 2
GAP-CLOSE-PWR
G47
1 2
GAP-CLOSE-PWR
G48
1 2
GAP-CLOSE-PWR
G50
1 2
GAP-CLOSE-PWR
G52
1 2
GAP-CLOSE-PWR
G53
1 2
GAP-CLOSE-PWR
G54
1 2
GAP-CLOSE-PWR
G55
1 2
GAP-CLOSE-PWR
G56
1 2
GAP-CLOSE-PWR
G57
1 2
GAP-CLOSE-PWR
G58
1 2
GAP-CLOSE-PWR
G59
1 2
GAP-CLOSE-PWR
G60
1 2
GAP-CLOSE-PWR
G61
1 2
GAP-CLOSE-PWR
G62
1 2
GAP-CLOSE-PWR
G63
1 2
GAP-CLOSE-PWR
G64
1 2
GAP-CLOSE-PWR
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
35 40 Friday, October 28, 2005
1
5V_S5 5V_PWR
51120_GND
01
Page 36
5
4
3
2
1
AG1-910-SB
D D
3D3V_S0
5V_S5 1D8V_S3
SC1U10V3ZY-6GP
1 2
C432
SC10U10V5ZY-1GP
1 2
C434
1 2
C433
AG1-910-01
10KR2J-3-GP
R96
1 2
1D05V_EN 16,18,29,32,35
PM_SLP_S3# 16,18,29,32,35
1 2
R360 0R0603-PAD
1D05V_EN
5912_EN_8
AG1-910-01
APL5912-KAC-GP
C C
B B
6
U59
1
VCNTL
GND
VOUT
VOUT
5
VIN
9
VIN
3
4
2
FB
7
POK
8
EN
Vo=0.8*(1+(R1/R2))
3D3V_S0 2D5V_S0
1 2
1 2
C306
C296
SC10U10V5ZY-1GP
1K78R3F-GP
2KR3F-L-GP
DY
1 2
5912_FB_2 5912_FB_2 5912_FB_2 5912_FB_2
5912_FB_2 5912_FB_2 5912_FB_2 5912_FB_2
1 2
R361
R362
AG1-910-01
3
SC10U10V5ZY-1GP
1 2
U37
VIN
APL5308-25AC-1GPU
1 2
C435
VOUT
GND
TC23
SCD01U16V3KX-LGP
ST220U2D5VBM-2GP
KEMET
100uF, 4V, B2 Size
Iripple=1.1A, ESR=70mohm
2
1
DY
1 2
C297
G65
1 2
GAP-CLOSE-PWR
G66
1 2
GAP-CLOSE-PWR
G68
1 2
GAP-CLOSE-PWR
G67
1 2
GAP-CLOSE-PWR
G69
1 2
GAP-CLOSE-PWR
Trace Length=3cm
Trace Width=5mils
Trace Resistance>80mohm
1 2
C303
SC2D2U16V5ZY-2GP
1D5V_S0 1D5V_LDO
SC1U10V3ZY-6GP
AG1-910-SA
A A
5
4
3
SC10U10V5ZY-1GP
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
2
Date: Sheet
1D5V/2D5V(LDO)
AG1(Alviso) 01
36 40 Monday, October 31, 2005
1
of
Page 37
A
DCBATOUT_6227 DCBATOUT
B
C
DCBATOUT_6227
D
E
G70
1 2
GAP-CLOSE-PWR
G71
1 2
R54
1D8V_S3_PG
R74
GAP-CLOSE-PWR
G72
1 2
GAP-CLOSE-PWR
G73
1 2
GAP-CLOSE-PWR
6227_VCC
1 2
R62 0R0402-PAD
1 2
R72 0R0402-PAD
1 2
R65 0R0402-PAD
1 2
R73 0R0402-PAD
SCD01U16V2KX-3GP
DCBATOUT_6227
1 2
R75
10R3J-3-GP
SC4D7U10V5ZY-3GP
1 2
C48
6227_EN1
6227_PG2
1 2
C57
DY
SCD1U50V3ZY-GP
C61
1 2
1 2
1 2
R66
78K7R3F-GP
AG1-910-01
6227_SS1
6227_PG1
6227_EN2
6227_SS2
C64
SCD01U16V2KX-3GP
28
VCC
11
OCSET1
8
EN1
12
SOFT1
15
PG1
13
DDR
21
EN2
17
SOFT2
16
PG2/REF
1
GND
20
VOUT2
U16
ISL6227CAZ-1-GP
14
ISL6227
4 4
AG1-SB-910
5V_S5
1 2
10R3J-3-GP
AG1-910-01
CPUCORE_ON 34
3D3V_S0
PM_SLP_S4# 16,29
DY
R71
1 2
10KR2J-2-GP
1D05V_EN 16,18,29,32,35
1 2
10KR2J-3-GP
3 3
5V_S5
AG1-910-SB
AG1-910-01
2 2
VIN
BOOT1
UGATE1
PHASE1
LGATE1
PGND1
VOUT1
VSEN1
BOOT2
UGATE2
PHASE2
LGATE2
PGND2
VSEN2
OCSET2
5V_S5
BAW56PT-U
1 2
C63
SCD1U50V3ZY-GP
6
5
4
2
3
7
ISEN1
9
10
23
24
25
27
26
22
ISEN2
19
18
D9
3
6227_BOOT1
6227_HDRV1
6227_SW1 6227_ILIM1
6227_LDRV1
6227_ISNS1
6227_VSEN1
6227_BOOT2
6227_HDRV2
6227_SW2
6227_LDRV2
6227_ISNS2
6227_VSEN2
6227_ILIM2
6227_BOOT_2
2
6227_BOOT_1
1
1 2
SCD1U50V3ZY-GP
R55
1 2
2R3J-2-GP
1 2
C54
R68
78K7R3F-GP
C52
1 2
SCD1U50V3ZY-GP
1 2
2R3J-2-GP
R59
R57
1 2
2KR3F-L-GP
AG1-910-01
R63 2KR3F-L-GP
1 2
678
DDD
G D
123
4 5
678
DDD
SSS
GD
123
4 5
OCP
7.8A=>R169=151K
0D9V
C252
1 2
R181 0R0402-PAD
1 2
R180 0R0402-PAD
1 2
PM_SLP_S4# 16,29
PM_SLP_S3# 16,18,29,32,35
1 1
DDR_VREF_S3
SCD1U16V2ZY-2GP
9.0A=>R169=133K
5V_S5
1 2
C250
SC10U10V5ZY-1GP
10
9
8
7
6
TPS51100DGQ-1-GP
SC10U10V5ZY-1GP
VDDQSNS
VIN
VLDOIN
S5
GND
PGND
S3
VTTSNS
VTTREF
GND
11
1 2
C244
U36
1
2
3
VTT
4
5
SC10U10V5ZY-1GP
1D8V_S3
C232
DDR_VREF
1 2
1 2
C230
SC10U10V5ZY-1GP
U22
2nd
SSS
AO4422-1-GP
2nd
AO4702-1-GP
U20
AG1-A-SA
1 2
C285
SC10U25V6KX-1GP
L21
1 2
IND-4D7UH-85-GP
1 2
DY
R230
0R2J-GP
1 2
R231
678
DDD
U23
2nd
SSS
G D
AO4422-1-GP
123
4 5
678
DDD
2nd
AO4702-1-GP
U25
SSS
GD
123
4 5
AG1-910-01
A
B
C
1 2
1D8V / 6A ,OCP>7.8A
2nd
SCD01U16V2KX-3GP
1 2
C273
0R0402-PAD
AG1-910-01
DCBATOUT_6227
1 2
C278
SC10U25V6KX-1GP
L20
1 2
IND-4D7UH-85-GP
2nd
R232
0R0402-PAD
D
EC34
SCD1U50V3ZY-GP
AG1-910-SB
1D8V_S3
R234
10KR3F-L-GP
1 2
1 2
1 2
1 2
R64
10KR3F-L-GP
1 2
R233
0R2J-GP
DY
C284
1 2
SC10U25V6KX-1GP
C275
DY
TC9
ST330U3VDM-1-GP
1 2
EC35
SCD1U50V3ZY-GP
SCD01U16V2KX-3GP
1 2
1 2
C291
R229
1 2
1 2
R228
1 2
SCD1U16V2ZY-2GP
1K74R3F-GP
10KR3F-L-GP
TC11
SE220U2D5VDM-4GP
2nd
1 2
C292
DY
AG1-910-01
<Core Design>
Title
Size Document Number Rev
A3
Date: Sheet
1D8V/1D05V/0D9V
AG1-910-SB
1D05V_S0
1 2
TC10
SE220U2D5VDM-4GP
2nd
79.2271V.20L
ESR=15mohm
SCD1U16V2ZY-2GP
Iripple=2.7A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
AG1(Alviso)
E
AG1-910-SB
1D05V/6A
OCP>7.8A
AG1-910-SB
37 40 Thursday, October 27, 2005
of
01
Page 38
DY
D11
2 1
AD+
1 2
EC61
DY
SCD1U50V3ZY-GP
AG1-910-SB
5V_S5_G913
R89
AC_IN#
AC_IN# 29
1 2
0R0402-PAD
AD+
ACSET Threshold 1.27V typ.
ACSET > 1.29V Max. --> AC
DETECT
ISL6255_VDD
AG1-910-01
1 2
R91
100KR2J-1-GP
ISL6255_ACPRN#
AG1-910-01
1 2
R8
200KR3F-GP
ISL6255_VDD
ISL6255_ACSET
1 2
ISL6255_VDD
AG1-910-01
10KR2J-3-GP
CHG_ON# 29
D S
G
R10
15K4R3-GP
C16
Near ISL6255
Pin 26
100KR2J-1-GP
1 2
1 2
R1
G
AG1-A-SA
BSS84LT1G-GP
Q2
SC1U50V5ZY-1-GP
SCD1U50V3ZY-GP
C19
1 2
1 2
SC1U10V3ZY-6GP
SC680P50V2KX-2GP
R5
D
Q3
1
2 3
S
CELLS Operate Mode
VDD
GND
Float
4S
3S
2S
2R3J-2-GP
1 2
C21
22
23
24
25
26
27
28
29
C7
1 2
ISL6255_EN
ISL6255_VDD
AG1-A-SA
0R3-0-U-GP
2N7002PT-U
AG1-910-01
R13
CSON
ACPRN
DCPRN
DCIN
VDD
ACSET
DCSET
GND
1 2
DY
ISL6255_CELLS
1 2
R22
SSM34PT
U6
S
D
8
D
7
D
6
AO4411-1-GP
1
S
2
S
3
G D
4 5
AG1-910-SB
1 2
18R3-GP
R14
ISL6255_SGATE
SCD1U50V3ZY-GP
C22
1 2
1 2
ISL6255_CSIP
ISL6255_CSIN
21
20
CSIN
CSOP
EN1CELLS2ICOMP3VCOMP4ICM5VREF6CHLIM
R2
R24
SC6800P25V2KX-1GP
0R0603-PAD
19
CSIP
1 2
1 2
SC 100P50V2JN-3GP
18
SGATE
ISL6255_VCOMP
0R0603-PAD
C1
C5
1 2
17
BGATE
ISL6255_ICM
1 2
R4
C3
1 2
3S1P_I 29
AG1-A-SA
AD+_TO_SYS
1 2
AG1-A-01
16
PHASE
10KR2J-3-GP
1 2
R3
100R2F-L1-GP-U
SCD01U16V2KX-3GP
1 2
C2
C448
SCD015U50V3KX-GP
AG1-910-01
ISL6255_UGATE
U2
ISL6255HRZ
15
0R0402-PAD
UGATE
14
BOOT
13
VDDP
12
LGATE
11
PGND
10
GND
9
VADJ
8
ACLIM
7
AG1-A-SA
ISL6255_CHLIM
DY
DY
SCD1U16V2ZY-2GP
1
G
1 2
C23
AG1-A-SA
SC1U50V5ZY-1-GP
ISL6255_CSIN_1
1 2
C20
SCD1U50V3ZY-GP
D5
BAT54-4-GP
2
ISL6255_VDDP
ISL6255_VREF
1 2
R6
80K6R3F-1-GP
1 2
3
SC1U10V3ZY-6GP
1 2
R12
ISL6255_LGATE
Near ISL6255 Pin 13
R9
15K8R3F-GP
ISL6255_VREF
AG1-A-SA
R19
1 2
21K5R3F-GP
D
DY
Q1
2 3
S
2N7002PT-U
AG1-910-SB
1 2
D02R3720F-2-GP
G3
GAP-CLOSE
1 2
1
R11
1 2
2R3J-2-GP
1 2
20KR3F-GP
DY
20KR3F-GP
DY
1 2
R35
24K3R3F-GP
1 2
R7
100KR3F-GP
R30
ISL6255_VDD
C17
1 2
R39
1 2
R40
R27
1 2
1K74R3F-GP
DCBATOUT
1 2
24K3R3F-GP
DCBATOUT
1 2
G2
GAP-CLOSE
1 2
678
DDD
G D
4 5
U5
2nd
SSS
AO4422-1-GP
123
CHG_PWR-2
1 2
AG1-A-SA
678
DDD
U1
2nd
SSS
G D
AO4422-1-GP
123
4 5
1 2
C4
SC2700P50V3KX-1GP
ICHG : 3S2P = 3.0A/
3S1P = 1.4A
IPRE_CHG = 400mA
R36
DY
D
Q4
2N7002PT-U
2 3
DY
S
D
AG1-910-01
Q9
1
G
2 3
S
2N7002PT-U
(Power Team)
U24
S
1
S
2
S
3
GD
EC9
SCD1U50V3ZY-GP
For EMI
4 5
AO4407-1-GP
ID = 10A @
VGS = 10V
ISL6255_BGATE
1 2
1 2
C24
SC10U35V0ZY-GP
GAP-CLOSE
CHG_PWR-3
C25
G1
SC10U35V0ZY-GP
1 2
D03R3720F-1-GP
G6
GAP-CLOSE
R118
1 2
C239
1 2
1 2
1 2
1 2
C102
C101
C18
DY
SCD1U50V3ZY-GP
L9
1 2
IND-15UH-41-GP
2nd
12*12*4 Imax= 6A
DY
DY
SCD1U50V3ZY-GP
VADJ
VREF
Float
GND
ISOURCE_MAX = (((ACLIM/VREF)*0.05+0.05)/Rsense)
Adaptor is 65W/19V : I_LIMIT = 2.9A ( 85% )
1
G
PRE_CHG 29
3S2P_I 38
AG1-A-SA
<Core Design>
Title
Size Document Number Rev
A3
Date: Sheet
CHARGER ISL6225
AG1(Alviso)
SC10U25V0KX-3GP
Cell voltage
4.41V/cell
4.20V/cell
3.99V/cell
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
D
8
D
7
D
6
BT+
1 2
EC68
DY
SCD1U50V3ZY-GP
BT+
1 2
C241
SC10U25V0KX-3GP
AG1-A-SA
of
1 2
C242
DY
SC10U25V0KX-3GP
SC10U25V0KX-3GP
01
1 2
C240
DY
SC10U25V0KX-3GP
38 40 Tuesday, November 01, 2005
Page 39
A
B
C
D
E
3
1
2
3
4 5
1
3
1 2
EC15
SCD1U50V3ZY-GP
DY
D10
PZM24NB1
2
1
U4
S
D
S
S
GD
AO4411-1-GP
8
D
7
D
6
ID = -10A/70deg
Rds(ON) = 24mohm
SO-8
AG1-910-SB
3D3V_AUX_S5
2
DY
R41 27R3F-GP
1 2
1
3
1 2
DY
EC16
SC1000P50V3JN-GP
2
D7
BAV99PT-GP-U
DY
1 2
R43 27R3F-GP
EC17
SC1000P50V3JN-GP
EC12
1 2
SC10P50V2JN-4GP
AD+
1 2
BATA_SCL_1
BATA_SDA_1
1 2
C10
SCD1U50V3ZY-GP
EC13
SC10P50V2JN-4GP
1 2
BAT1
8
1
2
3
4
5
6
7
9
SYN-CON7-11-UGP
20.80577.007
CONNECTOR
Adaptor in to generate DCBATOUT
AG1-A-01
DC1
4 4
DC-JACK115-GP
22.10037.C51
connector
4
1
2
3
5
6
MH1
AG1-A-SA
CHDTC124EU-1GP
3 3
AD_OFF 29
1 2
1KR2J-1-GP
AD_JK
Q5
1
IN
AG1-910-01
R42
1 2
C6
SCD1U50V3ZY-GP
1 2
R37
R2
B
OUT
3
R1
R2
2
GND
PDTA124EU-1-GP
Q10
E
R1
C
100KR2J-1-GP
AG1-910-01
AD+_2
1 2
C13
SC1U50V5ZY-1-GP
1 2
R38
56KR3F-GP
BATTERY CONNECTOR
D6
BAV99PT-GP-U
BAT_SCL 29
BAT_SDA 29
BAT_IN# 29
BT+
2 2
SCD1U50V3ZY-GP
EC14
1 2
DY
1 1
A
B
C
D
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
Date: Sheet of
AD/BATT CONN
A3
AG1(Alviso)
E
39 40 Tuesday, November 01, 2005
01
Page 40
H1
HOLE
H2
HOLE
H3
HOLE
5
H5
H4
HOLE
HOLE
H8
HOLE
4
H9
HOLE
H10
HOLE
H11
HOLE
H12
HOLE
H13
HOLE
H14
HOLE
3
H15
HOLE
H16
HOLE
H17
HOLE
H18
HOLE
H19
HOLE
2
H20
HOLE
H21
HOLE
H22
HOLE
H23
HOLE
H24
HOLE
H25
HOLE
1
H26
HOLE
H27
HOLE
Y
1
34.4A902.001 34.4A902.001
D D
H28
HOLE
1
DCBATOUT
1 2
EC71
Y
1
1
Y
1
Y
1
1
Y
1
Y
1
Y
1
Y
1
1
1
1
34.4A908.001
HOLE
H30
HOLE
1
1
SCD1U50V3ZY-GP
1 2
EC18
1 2
H29
SCD1U50V3ZY-GP
EC38
HOLE
SCD1U50V3ZY-GP
1
EC75
H32
HOLE
1 2
H31
H33
H34
HOLE
HOLE
1
1
SCD1U50V3ZY-GP
1 2
EC76
1
SCD1U50V3ZY-GP
EC77
SCD1U50V3ZY-GP
1 2
EC78
34.4A908.001
SCD1U50V3ZY-GP
1 2
EC10
34.4A903.001
BT+
EC6
SCD1U50V3ZY-GP
1 2
SCD1U50V3ZY-GP
1 2
EC11
SCD1U50V3ZY-GP
1 2
EC19
SCD1U50V3ZY-GP
1 2
EC80
3D3V_S0
1 2
1
34.4A905.001
SCD1U16V2ZY-2GP
EC81
Y
1
1
Y
1
1
1
1
34.4A906.001
5V_S0
INT_MIC 30
EC82
SCD1U16V2ZY-2GP
1 2
SCD1U16V2ZY-2GP
1 2
EC83
SCD1U16V2ZY-2GP
1 2
EC84
SCD1U16V2ZY-2GP
1 2
Y
1
34.4A905.001
1
1
1
Y
1
34.4A904.001
DY
K7
SPRING-14
AG1-910-SB AG1-910-SB
1
K8
SPRING-14
K9
1
SPRING-28
1
K10
SPRING-28
AG1-910-SB AG1-910-01
K11
1
SPRING-28
C C
K1
1
SPRING-23-GP
K2
1
SPRING-23-GP
K3
1
SPRING-23-GP
K4
1
SPRING-29-GP
K5
1
SPRING-29-GP
K6
1
SPRING-14
1
B B
AG1-910-SB
A A
5V_S0
14
4
5 6
TSAHCT125PW-GP
7
U3B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet
EMI
AG1(Alviso)
40 40 Wednesday, November 02, 2005
of
01
Page 41