Wistron 2012 S-Series Richie, ProBook 4340s, ProBook 4540s Schematic

5

4

3

2

1

2012 S-Series Richie 13.3"

D D

UMA/DIS Muxless Schematic

In

C C

tel Chief River Platform

Ivy Bridge (rPGA989)

Panther Point PCH

B B

REV:-1

2012-03-15

Wistron Corporation

A A

Title

DY:No stuff DIS_PX:Only DIS install

5

4

3

Title

Cover Page

Size Document Number Rev

A4

Date: Sheet of

2

Cover Page

2012 S-Series Richie 13.3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-1

1 103Wednesday, March 14, 2012

1

5

S-Series Richie Block Diagram

D D

1600/1333

DDR III 1600/1333

C C

SIM Card

54

SD/MMC/MS

B B

RJ45 CONN

INT MIC

EXT MIC

Headphone

A A

31

Pre-AMP TLV2462

31

Speaker

5

USB3.0 x 3

FingerPrinter

USB2.0 x 1

CAMERA

Mini-Card

X3401 25MHz

30

31

Slot 0DDR III

Slot 1

WWAN

DDRIII 1600/1333 Channel A

14

DDRIII 1600/1333 Channel B

15

62

64

61

49

54

JMicron

JMB709

LAN Realtek 8151FH

10/100/1000

AUDIO CODEC

IDT92HD87

3233

3435

29

4

USB3.0

USB 2.0

X1701

32.768KHz

X1801 25MHz

PCIE

XDP

26

HD Audio

4

(Muxless)

Intel CPU

Ivy Bridge-M Dual Core SV 35W

FDI*2

2.7GT/s

INTEL

PCH Panther Point-M

USB 3.0/2.0/1.1 ports (14)

ETHERNET

High Definition Audio

Serial Peripheral I/F(dual output)

ACPI 1.1

LPC I/F SATA ports (6) PCIE ports (8)

17,18,19,20,21,22,23,24,25 27

USB2.0

Mini-Card WLAN

802.11abg/n Blue Tooth

4,5,6,7,8,9,10

(10/100/1000Mb)

PCIe

53

DMI2.0*4 5GT/s

SMBus

Accelerometer

HP3DC2

3

PCIe x 16

RGB CRT

HDMI

LVDS

SMBus

SATA II 6Gb/s

LPC Bus

SPI/PECI

SPI

SPI Flash 8MB

65

3

VRAM

128MBx16 128MBx16

4

88 89

GDDR5

Thames Pro

18W

S3 Package

83,84,85,86,87

RGB CRT

60

25

CRT

HDMI 1.4

LCD

Battery

50

51

49

Thermal Sensor

GMT G781

HDD

ODD

KBC

SMSC KBC1126

Touch Pad

6939

28

56

VRAM

GDDR5

X8501 27MHz

Int. KB

69

2

SYSTEM DC/DC

TPS51461RGER

INPUTS

DCBATOUT

4

Project code:91.4RS01.001 P

CB P/N:11241

PCB 8 LAYER

Top

L1:

GND

L2:

Signal

L3:

Signal

L4:

VCC

L5:

Signal

L6:

GND

L7:

Bottom

L8:

Title

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

1

CPU DC/DC

ISL95832HRTZ

INPUTS

DCBATOUT

OUTPUTS

+VCCSA

48

SYSTEM DC/DC

TPS51211DSCR

INPUTS

DCBATOUT

SYSTEM DC/DC

TPS51123RGER

INPUTS

DCBATOUT 5V_S5

SYSTEM DC/DC

TPS51216RUKR

INPUTS

DCBATOUT

GFX DC/DC

ISL95832HRTZ

INPUTS

DCBATOUT

INPUTS

DCBATOUT

CHARGER

BQ24736RGRR

INPUTS

AD+ BT+

26

SYSTEM DC/DC

RT8068AZQWID

INPUTS

3D3V_S5

SYSTEM DC/DC

INPUTS OUTPUTS

26

1D5V_S3 1V_VGA_S0

INPUTS OUTPUTS

1D5V_S3 5V_S5

PCB LAYER

L1:Top L2:GND L3:Signal L4:Signal

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

2012 S-Series Richie 13.3

1

OUTPUTS

VCC_CORE

OUTPUTS

1D05V_S0

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

OUTPUTS

VCC_GFXCORE

VGA

UP1527QQDD

OUTPUTS

VGA_CORE

OUTPUTS

DCBATOUT

OUTPUTS

1D8V_S0

FDMC7696

Switches

1D5V_S0 5V_S0 3D3V_S03D3V_S5

L5:Vcc L6:Signal L7:GND L8:Bottom

2 103Wednesday, March 14, 2012

42~44

45

41

46

42~44

92

4

47

93

-1

0

5

PCH Strapping

Chief River Schematic Checklist Rev0.72

Name Schematics Notes

SPKR

INIT3_3V#

D D

INTVRMEN

GNT3#/GPIO55 GNT2#/GPIO53 GNT1#/GPIO51

DF_TVS

SATA1GP/ G

PIO19

C C

SATA2GP/

PIO36

G

SATA3GP/

PIO37

G

HDA_DOCK_EN# /GPIO33

HDA_SDO

B B

HDA_SYNC

GPIO15

L_DDC_DATA

SDVO_CTRLDATA

DDPC_CTRLDATA

DDPD_CTRLDATA

DSWVRMEN

A A

GPIO28

GPIO29/

LP_LAN#

S

The signal has a weak internal pull-down. N

ote: the internal pull-down is disabled after PLTRST# deasserts. If the signal is sampled high, this indicates that the system is strapped to the "No Reboot" mode (Cougar Point will disable the TCO Timer system reboot feature). This signal has a weak internal pull-up. N

ote: The internal pull-up is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled low. Leave as "No Connect". Integrated 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when high N

OTE: This signal should always be pulled high External 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when Low. NOTE: This signal should be pulled down to GND through 330 kOhms resistor

GNT[3:0]# functionality is not available on Mobile. Used as GPIO only. Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail.

This signal is a strap for selecting DMI and FDI termination voltage. For Ivy Bridge processor only implementation: DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms ±5% resistor. For future processor compatibility: It needs to be connected to PROC_SELECT through a

1.0 kOhms ±5% series resistor. The PROC_SELECT signal would need a 2.2 kOhms ±5% pull-up resistor to PCH VccDFTERM. This Signal has a weak internal pull-up.

Note: the internal pull-up is disabled after PLTRST# deasserts. This field determines the destination of accesses to the BIOS memory range. Also controllable via Boot BIOS Destination bit (Chipset Config Registers: Offset 3410h:Bit 10). This strap is used in conjunction with Boot BIOS Destination Selection 1 strap. Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI 0 0 LPC NOTE: If option 00 LPC is selected BIOS may still be placed on LPC, but all platforms with Cougar Point require SPI flash connected directly to the Cougar Point's SPI bus with a valid descriptor in order to boot. NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or via Boot BIOS Destination Bit will not affect SPI accesses initiated by Management Engine or Integrated GbE LAN. NOTE: PCI Boot BIOS destination is not supported on mobile.

Reserved. This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.

Reserved This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.

High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking isolation logic. This is an

ctive-low-signal. When deasserted the external docking switch is in isolate mode. When asserted the external docking switch

a electrically connects the Intel? HD Audio dock signals to the corresponding Cougar Point signals. This signal can instead be used as GPIO33.

Signal has a weak internal pull-down. If strap is sampled low, the security measures defined in the Flash Descriptor will be in effect (default). If sampled high, the Flash Descriptor Security will be overridden. This strap should only be asserted high via external pull-up in manufacturing/debug environments ONLY. Note: The weak internal pull-down is disabled after PLTRST# deasserts. Asserting the HDA_SDO high on the rising edge of RSMRST# will also halt Intel Management Engine after chipset bring up and disable runtime Intel Management Engine features. This is a debug mode and must not be asserted after manufacturing/ debug.

This signal has a weak internal pull-down. On Die PLL VR is supplied by 1.5 V from VCCVRM when sampled high, 1.8 V from VCCVRM when sampled low. Needs to be pulled High for Chief River platform. TLS Confidentiality Low (0) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality This signal has a weak internal pull-down. NOTE: The weak internal pull-down is disabled after RSMRST# deasserts. NOTE: A strong pull-up may be needed for GPIO functionality

LVDS Detected.

hen '1'- LVDS is detected; When '0'- LVDS is not detected. This signal has a weak internal pull-down.

W NOTE: The internal pull-down is disabled after PLTRST# deasserts. Port B Detected When '1'- Port B is detected; When '0'- Port B is not detected. This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts. Port C Detected. When '1'- Port C is detected; When '0'- Port C is not detected This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts Port D Detected.

hen '1'- Port D is detected; When '0'- Port D is not detected This signal has a weak internal pull-down.

W NOTE: The internal pull-down is disabled after PLTRST# deasserts. Deep S4/S5 Well On-Die Voltage Regulator Enable If strap is sampled high, the Integrated Deep S4/S5 Well (DSW) On-Die VR mode is enabled.

The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled. If not used, 8.2-kΩ to 10-kΩ pull-up to +V3.3A power-rail. Note: This signal has a weak internal pull-up. The internal pull-up is disabled after RSMRST# deasserts. GPIO29 is multiplexed with SLP_LAN#. If Intel LAN is implemented on the platform, SLP_LAN# must be used to control the power to the PHY LAN (no other implementation is supported). If integrated Intel LAN is not supported on the platform, GPIO29 can be used as a normal GPIO. A soft strap determines the functionality of GPIO29, either as SLP_LAN# or GPIO. By default, the soft strap enables SLP_LAN# functionality on the pin. If the soft trap is changed to enable GPIO functionality, then SLP_LAN# functionality is no longer available, and the signal can be used as a normal GPIO (default to GPI).

5

4

3

PCIe Routing

LANE1 LANE2 LANE3 Card Reader LANE4 LANE5 LANE6 LANE7 LANE8

X X

Mini Card1(WLAN) X LAN X X

USB 2.0 Table

Pair

0 1 2 3 4 5 6 7 8 9 10 11 12 13

3

Device

FREE

USB 3.0 I/O CONN. 1 USB 3.0 I/O CONN. 2 USB 3.0 I/O CONN. 3

FREE BT WLAN combo FREE FREE Fingerprint

USB 2.0 I/O CONN. 1

Camera FREE WWAN FREE

2

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[0]

CFG[2] CFG2 is for the 16x

CFG[4]

CFG[6:5]

CFG[17:7]

PCIe Static x16 Lane Numbering Reversal.

Display Port Presence strap

PCIE Port Bifurcation Straps

Reserved configuration lands. A test point may be placed on the board for these lands.

POWER PLANE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_S0 VCCSA 0D75V_S0 VCC_CORE VCC_GFXCORE VGA_CORE 1D8V_VGA_S0 3D3V_VGA_S0 1D5V_VGA_S0 1V_VGA_S0

1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

3D3V_AUX_KBC 3.3V

3D3V_AUX_S5

1 unless specified otherwise)

Connect a series 1K ohm resistor on the critical CFG[0] trace in a manner which does not introduce any stubs to CFG[0] trace. Route as needed from the opposite side of this series isolation resistor to the debug port. ITP will drive the net to GND.

1: Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed

1:Disabled - No Physical Display Port attached to Embedded DisplayPort 0:Enabled - An external Display Port device is connected to the Embedded Display Port Pull down to GND through a 1KΩ ± 5% resistor to enable port

00 = 1 x 8, 2 x 4 PCI Express 01 = reserved 10 = 2 x 8 PCI Express 11 = 1 x 16 PCI Express

VOLTAGE DESCRIPTION

5V

3.3V

1.8V

1.5V

1.05V

1.0V

0.9 - 0.675V

0.75V

0.35V to 1.5V

0.4 to 1.25V

1.8V

3.3V 1V

5V

1.5V

9V-14.1V 9V-19.5V 5V 5V

3.3V

Chief River Schematic Checklist Rev0.72

Voltage Rails

ACTIVE IN

S0

S3

All S states

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

CPU Core Rail Graphics Core Rail

AC Brick Mode only

Powered by Li Coin Cell in G3 and 3D3V_S5 in Sx

USB3.0 Table

Pair Device

1 2 3 4

USB

FREE

I/O CONN. 1 I/O CONN. 2 I/O CONN. 3

SATA Table

Pair

0 1 2 3 4 5

SATA Device

HDD ODD

N/A N/A N/A N/A

SMBus ADDRESSES

I C / SMBus Addresses

Device

DIMM1 DIMM2

KBC G781_Thermal IC GPU_Thames PRO G-Sensor

2

Title

Size Document Number Rev

Date: Sheet of

Custom

Ref Des

Table of Content

Chief River CRV

Address Hex Bus

1001100 0X41 0X52 PCH_SML1CLK/PCH_SML1DATA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

2012 S-Series Richie 13.3

1

PCH_SMB_CLK/PCH_SMB_DATA PCH_SMB_CLK/PCH_SMB_DATA PCH_SMB_CLK/PCH_SMB_DATATouch-Pad

PCH_SML0_CLK/PCH_SML0_DATAN/A

PCH_SML1CLK/PCH_SML1DATA PCH_SML1CLK/PCH_SML1DATA PCH_SML1CLK/PCH_SML1DATA

3 103Wednesday, March 14, 2012

1

Default Value

1

11

-1

5

4

3

2

1

CPU(1/7)

IVY BRIDGE PROCESSOR (DMI,DP,PEG,FDI)

EG Compensation

1 2

P

1D05V_S0

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9

PEG_TXN7

PEG_TXP15PEG_C_TXP15 PEG_TXP13PEG_C_TXP13 PEG_TXP11PEG_C_TXP11 PEG_TXP9 PEG_TXP7PEG_C_TXP7 PEG_TXP5

PEG_TXP4PEG_C_TXP4 PEG_TXP3PEG_C_TXP3 PEG_TXP2PEG_C_TXP2 PEG_TXP1PEG_C_TXP1

PEG_TXN[0..15] 83

PEG_TXP[0..15] 83

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(1/7): DMI/PEG/FDI

Size Document Number Rev

A3

Date: Sheet of

CPU(1/7): DMI/PEG/FDI

Taipei Hsien 221, Taiwan, R.O.C.

2012 S-Series Richie 13.3

4 103Wednesday, March 14, 2012

-1

D D

1 OF 9

CPU1A

1 2

DMI_TXN[3:0]19

DMI_TXP[3:0]19

DMI_RXN[3:0]19

DMI_RXP[3:0]19

FDI_TX_N[7:0]19

FDI_TX_P[7:0]19

FDI_FSYNC019 FDI_FSYNC119

FDI_INT19 FDI_LSYNC019

FDI_LSYNC119

Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

C C

Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Lane reversal does not apply to FDI sideband signals.

DP Compensation, within 500mil

B B

NOTE: EDP_HPD Select a Fast FET similar to 2N7002E whose rise/ fall time is less than 6 ns. If HPD on eDP interface is disabled, connect it to CPU VCCIO via a 10-kΩ pull-Up

sistor on the motherboard.

re This signal can be left as no connect if entire eDP interface is disabled.

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

A A

NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

1D05V_S0

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

4mil

12mil

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TX_N0 FDI_TX_N1 FDI_TX_N2 FDI_TX_N3 FDI_TX_N4 FDI_TX_N5 FDI_TX_N6 FDI_TX_N7

FDI_TX_P0 FDI_TX_P1 FDI_TX_P2 FDI_TX_P3 FDI_TX_P4 FDI_TX_P5 FDI_TX_P6 FDI_TX_P7

DP_COMP

G21

D21 G22

D22 C21

H19

C20 D18

G19 G18 C19

D19

H20

H17

C15 D15

C17 C16

G15 C18 D16

B27 B25 A25 B24

B28 B26 A24 B23

E22 F21

F20

A21 E19

F18 B21

E17

A22 E20 B20

F17

A18 A17 B16

F16

E16 F15

J18 J17

J19

IVY-BRIDGE

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI0_FSYNC FDI1_FSYNC

FDI_INT FDI0_LSYNC

FDI1_LSYNC

EDP_COMPIO EDP_ICOMPO EDP_HPD

EDP_AUX EDP_AUX#

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3

DMI

Intel(R) FDI

eDP

62.10040.821

1ST = 62.10055.551

1ST = 62.10055.551 2nd = 62.10055.321

2nd = 62.10055.321 3rd = 62.10055.731

3rd = 62.10055.731

BOM Note:1st/2nd/3rd Add in BOM

1 OF 9

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_TX#10 PEG_TX#11

PCI EXPRESS* - GRAPHICS

PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_COMP

PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0

PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0

PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_TXN6 PEG_C_TXN5 PEG_TXN5 PEG_C_TXN4 PEG_TXN4 PEG_C_TXN3 PEG_TXN3 PEG_C_TXN2 PEG_TXN2 PEG_C_TXN1 PEG_TXN1 PEG_C_TXN0 PEG_TXN0

PEG_C_TXP14 PEG_TXP14 PEG_C_TXP12 PEG_TXP12 PEG_C_TXP10 PEG_TXP10

PEG_C_TXP9 PEG_C_TXP8 PEG_TXP8

PEG_C_TXP6 PEG_TXP6 PEG_C_TXP5

PEG_C_TXP0 PEG_TXP0

DIX_PX

DIX_PX DIX_PX

DIX_PX

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

PEG_RXN[0..15] 83

PEG_RXP[0..15] 83

C401 SCD22U16V2KX-GP

1 2

C402 SCD22U16V2KX-GP

1 2

C403 SCD22U16V2KX-GP

1 2

C404 SCD22U16V2KX-GP

1 2

C405 SCD22U16V2KX-GP

1 2

C406 SCD22U16V2KX-GP

1 2

C407 SCD22U16V2KX-GP

1 2

C408 SCD22U16V2KX-GP

1 2

C409 SCD22U16V2KX-GP

1 2

C410 SCD22U16V2KX-GP

1 2

C411 SCD22U16V2KX-GP

1 2

C412 SCD22U16V2KX-GP

1 2

C413 SCD22U16V2KX-GP

1 2

C414 SCD22U16V2KX-GP

1 2

C415 SCD22U16V2KX-GP

1 2

C416 SCD22U16V2KX-GP

1 2

C417 SCD22U16V2KX-GP

1 2

C418 SCD22U16V2KX-GP

1 2

C419 SCD22U16V2KX-GP

1 2

C420 SCD22U16V2KX-GP

1 2

C421 SCD22U16V2KX-GP

1 2

C422 SCD22U16V2KX-GP

1 2

C423 SCD22U16V2KX-GP

1 2

C424 SCD22U16V2KX-GP

1 2

C425 SCD22U16V2KX-GP

1 2

C426 SCD22U16V2KX-GP

1 2

C427 SCD22U16V2KX-GP

1 2

C428 SCD22U16V2KX-GP

1 2

C429 SCD22U16V2KX-GP

1 2

C430 SCD22U16V2KX-GP

1 2

C431 SCD22U16V2KX-GP

1 2

C432 SCD22U16V2KX-GP

1 2

5

4

3

2

1

CPU(2/7)

IVY BRIDGE PROCESSOR (CLK,MISC,JTAG)

2 OF 9

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

MISC

2 OF 9

A28

BCLK

A27

BCLK#

A16 A15

CPUDRAMRST#

R8

AK1 A5 A4

AP29

PRDY#

AP27

PREQ#

AR26

TCK

AR27

TMS

AP30

TRST#

AR28

TDI

AP26

TDO

AL35

DBR#

AT28

BPM#0

AR29

BPM#1

AR30

BPM#2

AT30

BPM#3

AP32

BPM#4

AR31

BPM#5

AT31

BPM#6

AR32

BPM#7

DDR3 Compensation Signals

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

PU/PD for JTAG signals

XDP_TMS XDP_TDI XDP_PREQ#

XDP_TCK

XDP_TRST#

Title

Size Document Number Rev

Custom

Date: Sheet of

20120116PV-R

CPU_BCLK_P CPU_BCLK_N

CLK_DP_P_R CLK_DP_N_R

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

XDP_PRDY# XDP_PREQ#

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_BPM0_R XDP_BPM1_R XDP_BPM2_R XDP_BPM3_R XDP_BPM4_R XDP_BPM5_R XDP_BPM6_R XDP_BPM7_R

2 3 1

RN

1 2 3

1

1 1 1 1 1 1 1 1

0R4P2R-PADRN501RN0R4P2R-PADRN501

4

RN504

4

SRN1KJ-7-GP

TP503 TPAD14-OP-GPTP503 TPAD14-OP-GP

TP510 TPAD14-OP-GPTP510 TPAD14-OP-GP TP511 TPAD14-OP-GPTP511 TPAD14-OP-GP TP512 TPAD14-OP-GPTP512 TPAD14-OP-GP TP513 TPAD14-OP-GPTP513 TPAD14-OP-GP TP514 TPAD14-OP-GPTP514 TPAD14-OP-GP TP515 TPAD14-OP-GPTP515 TPAD14-OP-GP TP516 TPAD14-OP-GPTP516 TPAD14-OP-GP TP517 TPAD14-OP-GPTP517 TPAD14-OP-GP

PUT CLOSE CPU

12

CPU(2/7) : CLK/MISC/JTAG

12

R510

200R2F-L-GP

R506 51R2J-2-GPR506 51R2J-2-GP

1 2

R509 51R2J-2-GPR509 51R2J-2-GP

1 2

R505 51R2J-2-GP

1 2

DY

R507 51R2J-2-GPR507 51R2J-2-GP

1 2

R511 51R2J-2-GPR511 51R2J-2-GP

1 2

2012 S-Series Richie 13.3

12

R503

R504

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

R503

25D5R2F-GP

1D05V_S0

5 103Wednesday, March 14, 2012

1

CLKOUT_DMI_P 18 CLKOUT_DMI_N 18

1D05V_S0

XDP_DBRESET# 19

140R2F-GP

-1

CPU1B

1D05V_S0

D D

Q501

KBC_PROCHOT27

12

R525

100KR2J-1-GP

G

S

2N7002K-2-GP

84.2N702.J31

84.2N702.J31 2nd = 84.07002.I31

2nd = 84.07002.I31 3rd = 84.2N702.W31

3rd = 84.2N702.W31

D

PM_DRAM_PWRGD Traces impedance= 50 ohm

3D3V_S0

R523

200R2F-L-GP

C C

PM_DRAM_PWRGD19

B B

200R2F-L-GP

PWR_GOOD27,37,42,50,96

PLT_RST#17,21,32,34,53,54,56,71,83,96,97

DEEP S3

A A

12

74VHC1G09DFT2G-GP

2nd = 73.01G09.0AB

2nd = 73.01G09.0AB 3rd = 73.01G09.BAH

3rd = 73.01G09.BAH

PCH_DDR_RST#18

KBC_DDR_RST#27,46

5

AND GATE

U501

1

IN B

VCC

2

IN A GND3OUT Y

73.01G09.AAH

R502

1 2

0R2J-2-GP

C503

12

SCD1U10V2KX-5GP

5

PM_DRAM_PWRGD_M

75R2J-1-GP

U502

1

NC#1

VCC

2

A GND3Y

74LVC1G07GW-GP

Buffered reset to CPU

1st = 73.01G07.AHG

1st = 73.01G07.AHG 2nd = 73.01G07.AHG

2nd = 73.01G07.AHG 3rd = 73.17S07.0AG

3rd = 73.17S07.0AG

3D3V_S5

R529

20KR2J-L2-GP

G

Q503

Q503 DMN5L06K-7-GP

DMN5L06K-7-GP

DS

DY_DS3

84.05067.031

2ND = 84.07002.I31

3rd = 84.2N702.W31

DY

4

200R2F-L-GP

1D05V_S0

R526

5

4

12

DY

1D5V_S03D3V_S5

12

R524

12

BUF_CPU_RST#_R

20120116PV-R

R530

1 2

0R0402-PAD

R528

1 2

DY_DS3

20KR2J-L2-GP

12

C502

C502 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1 2

4

1 2

R512 130R2F-1-GPR512 130R2F-1-GP

3D3V_S0

12

C504

C504 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R517

R517 43R2J-GP

43R2J-GP

R527

R527 1K5R2F-2-GP

1K5R2F-2-GP

DY

12

H_PM_SYNC19

H_CPUPWRGD22

PCH_DDR_EN# 8

R501

R501 62R2F-GP

62R2F-GP

12

R521

R521 750R2F-GP

750R2F-GP

DY

TPAD14-OP-GP

H_PROCHOT# 42

H_PROCHOT#

TPAD14-OP-GP

H_PECI22,27

1 2

R508 56R2F-1-GPR508 56R2F-1-GP

1 2

R518 10KR2J-3-GPR518 10KR2J-3-GP

R519 0R0402-PAD-1-GPR519 0R0402-PAD-1-GP

1 2

R520 0R0402-PAD-1-GPR520 0R0402-PAD-1-GP

1 2

3 Power Reduction Circuit

S SM_DRAMRST#

CPUDRAMRST#

4K99R2F-L-GP

R515

3

TP501TPAD14-OP-GPTP501TPAD14-OP-GP

TP502

H_THRMTRIP#22,85

H_SNB_IVB#22

12

TP_SKTOCC#_R

1

H_CATERR#

1

H_CPUPWRGD_R

H_PM_SYNC_R

H_CPUPWRGD_R

PM_DRAM_PWRGD_R

BUF_CPU_RST#

DY

R522

1 2

0R2J-2-GP

DMN5L06K-7-GP

H_PROCHOT#_D

CPUDRAMRST#_R

Q502

DS

84.05067.031

2ND = 84.00138.F31

G

12

C501

C501 SCD047U25V2KX-GP

SCD047U25V2KX-GP

CPU1B

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

1D5V_S3

12

R513

R513 1KR2F-3-GP

1KR2F-3-GP

R514

1 2

1KR2J-1-GP

20120112 PV-R

IVY-BRIDGE

3D3V_S0 1D05V_S0

R1110

1KR2J-1-GP

DDR3_DRAMRST# 14,15,97

PCH_DDR_EN# 8

MISCTHERMALPWR MANAGEMENT

CLOCKS

DDR3

JTAG & BPM

R1111

R1111 51R2J-2-GP

51R2J-2-GP

1 2

XDP_TDO

XDP_DBRESET#

2

5

4

3

2

1

CPU(3/7)

IVY BRIDGE PROCESSOR (DDR3)

D D

CPU1C

IVY-BRIDGE

M_A_DQ[63:0]14 M_B_DQ[63:0]15

C C

B B

M_A_BS014 M_A_BS114 M_A_BS214

M_A_CAS#14 M_A_RAS#14 M_A_WE#14

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M10

AG6 AG5 AK6 AK5 AH5 AH6

AK8 AK9

AH8 AH9

AP11 AN11

AL12 AM12 AM11

AL11

AP12 AN12

AJ14 AH14

AL15

AK15

AL14

AK14

AJ15 AH15

AE10

AF10

AE8 AD9

C5

SA_DQ0

D5

SA_DQ1

D3

SA_DQ2

D2

SA_DQ3

D6

SA_DQ4

C6

SA_DQ5

C2

SA_DQ6

C3

SA_DQ7

F10

SA_DQ8

F8

SA_DQ9

G10

SA_DQ10

G9

SA_DQ11

F9

SA_DQ12

F7

SA_DQ13

G8

SA_DQ14

G7

SA_DQ15

K4

SA_DQ16

K5

SA_DQ17

K1

SA_DQ18

J1

SA_DQ19

J5

SA_DQ20

J4

SA_DQ21

J2

SA_DQ22

K2

SA_DQ23

M8

SA_DQ24

N10

SA_DQ25

N8

SA_DQ26

N7

SA_DQ27 SA_DQ28

M9

SA_DQ29

N9

SA_DQ30

M7

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37

AJ5

SA_DQ38

AJ6

SA_DQ39

AJ8

SA_DQ40 SA_DQ41

AJ9

SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45

AL9

SA_DQ46

AL8

SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1

V6

SA_BS2

SA_CAS# SA_RAS#

AF9

SA_WE#

IVY-BRIDGE

DDR SYSTEM MEMORY A

3 OF 9

SA_CK0

SA_CLK#0

SA_CKE0

SA_CK1

SA_CLK#1

SA_CKE1

SA_CK2

SA_CLK#2

SA_CKE2

SA_CK3

SA_CLK#3

SA_CKE3

SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3

SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIM0_CLK_DDR0 14 M_A_DIM0_CLK_DDR#0 14 M_A_DIM0_CKE0 14

M_A_DIM0_CLK_DDR1 14 M_A_DIM0_CLK_DDR#1 14 M_A_DIM0_CKE1 14

M_A_DIM0_CS#0 14 M_A_DIM0_CS#1 14

M_A_DIM0_ODT0 14 M_A_DIM0_ODT1 14

M_A_DQS#[7:0] 14

M_A_DQS[7:0] 14

M_A_A[15:0] 14

CPU1D

IVY-BRIDGE

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_BS015 M_B_BS115 M_B_BS215

M_B_CAS#15 M_B_RAS#15 M_B_WE#15

AJ11

AH11

AJ12

AH12

AT11 AN14 AR14

AT14

AT12 AN15 AR15

AT15

AA10

D10

AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9

AT8 AT9

AR8

AA9 AA7

AB8 AB9

C9

SB_DQ0

A7

SB_DQ1 SB_DQ2

C8

SB_DQ3

A9

SB_DQ4

A8

SB_DQ5

D9

SB_DQ6

D8

SB_DQ7

G4

SB_DQ8

F4

SB_DQ9

F1

SB_DQ10

G1

SB_DQ11

G5

SB_DQ12

F5

SB_DQ13

F2

SB_DQ14

G2

SB_DQ15

J7

SB_DQ16

J8

SB_DQ17

K10

SB_DQ18

K9

SB_DQ19

J9

SB_DQ20

J10

SB_DQ21

K8

SB_DQ22

K7

SB_DQ23

M5

SB_DQ24

N4

SB_DQ25

N2

SB_DQ26

N1

SB_DQ27

M4

SB_DQ28

N5

SB_DQ29

M2

SB_DQ30

M1

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1

R6

SB_BS2

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

4 OF 9

SB_CK0

SB_CLK#0

SB_CKE0

SB_CK1

SB_CLK#1

SB_CKE1

SB_CK2

SB_CLK#2

SB_CKE2

SB_CK3

SB_CLK#3

SB_CKE3

SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIM0_CLK_DDR0 15 M_B_DIM0_CLK_DDR#0 15 M_B_DIM0_CKE0 15

M_B_DIM0_CLK_DDR1 15 M_B_DIM0_CLK_DDR#1 15 M_B_DIM0_CKE1 15

M_B_DIM0_CS#0 15 M_B_DIM0_CS#1 15

M_B_DIM0_ODT0 15 M_B_DIM0_ODT1 15

M_B_DQS#[7:0] 15

M_B_DQS[7:0] 15

M_B_A[15:0] 15

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU(3/7) : DDR3

2012 S-Series Richie 13.3

6 103Wednesday, March 14, 2012

1

-1

5

4

3

2

1

CPU(4/7)

IVY BRIDGE PROCESSOR (POWER)

POWER

CPU1F

12

C709

12

C711

12

C714

C723

C708

VCC_CORE

SC22U6D3V5MX-2GP

SC10U6D3V3MX-GP

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

53A

4

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

D D

PROCESSOR CORE PO

WER

C727

C722

C713

SC22U6D3V5MX-2GP

12

C736

SC10U6D3V3MX-GP

12

SC22U6D3V5MX-2GP

Place Bottom

C735

C721

SC22U6D3V5MX-2GP

C738

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

12

C701

SC10U6D3V5KX-1GP

C702

SC10U6D3V5KX-1GP

12

C704

SC22U6D3V5MX-2GP

12

C C

C742

C740

12

5

C742

12

C739

SC22U6D3V5MX-2GP

12

lace Top

P

B B

A A

C726

12

C712

12

C741

C706

C728

SC22U6D3V5MX-2GP

SC10U6D3V3MX-GP

12

C703

SC22U6D3V5MX-2GP

12

SC10U6D3V5KX-1GP

C707

SC10U6D3V5KX-1GP

12

C710

SC22U6D3V5MX-2GP

12

POWER

IVY-BRIDGE

CORE SUPPLY

SENSE LINES SVID

6 OF 9

AH13

VCCIO1

AH10

VCCIO2

AG10

VCCIO3

AC10

VCCIO4

Y10

VCCIO5

U10

VCCIO6

P10

VCCIO7

L10

VCCIO8

J14

VCCIO9

J13

VCCIO10

J12

VCCIO11

J11

VCCIO12

H14

VCCIO13

H12

VCCIO14

H11

VCCIO15

G14

VCCIO16

G13

VCCIO17

G12

VCCIO18

F14

VCCIO19

F13

VCCIO20

F12

VCCIO21

F11

VCCIO22

E14

VCCIO23

E12

VCCIO24

E11

VCCIO25

D14

VCCIO26

D13

VCCIO27

D12

VCCIO28

D11

VCCIO29

C14

VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK VIDSOUT

C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

PEG AND DDR

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

12

R707

10R2F-L-GP

PUT CLOSE CPU

3

PROCESSOR UNCORE POWER

C729

C730

SC10U6D3V3MX-GP

12

Route these three net together

1 2

R703 130R2F-1-GPR703 130R2F-1-GP

reserve PAD for ESD

DY

VCCSENSE

VSSSENSE

VTT_SENSE 45 VSSP_SENSE 45

1D05V_S0

R708

10R2F-L-GP

SC10U6D3V3MX-GP

12

R705 43R2J-GPR705 43R2J-GP

DY

0R2J-2-GP

1 2

D701

1 2

0R2J-2-GP

D702

Differential Sense feedback

C731

12

1D05V_S0

SC22U6D3V5MX-2GP

VCC_CORE

C732

SC10U6D3V3MX-GP

12

PUT CLOSE CPU

R706

R706 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R704

R704 100R2F-L1-GP-U

100R2F-L1-GP-U

C716

C715

SC10U6D3V3MX-GP

12

VR_SVID_ALERT# 42

H_CPU_SVIDCLK 42

H_CPU_SVIDDAT 42

VCCSENSE 42 VSSSENSE 42

2

8.5A

1D05V_S0

C717

C718

SC22U6D3V5MX-2GP

C718

SC22U6D3V5MX-2GP

SC10U6D3V3MX-GP

12

SC10U6D3V3MX-GP

12

Title

Size Document Number Rev

Custom

Date: Sheet of

C734

C733

SC10U6D3V3MX-GP

12

C720

C719

SC22U6D3V5MX-2GP

SC10U6D3V3MX-GP

12

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU(4/7) : PWR

2012 S-Series Richie 13.3

7 103Wednesday, March 14, 2012

1

-1

5

IVY BRIDGE PROCESSOR (GRAPHICS POWER)

33A

VCC_GFXCORE

Under Socket and Closed to CPU

D D

VCC_GFXCORE

C C

1.5A

1D8V_S0

B B

C821

C820

SC22U6D3V5MX-2GP

12

Closed to CPU Socket

C827

C826

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

12

C823

C822

SC22U6D3V5MX-2GP

12

C828

C829

SC22U6D3V5MX-2GP

12

C819

SC10U6D3V5KX-1GP

12

DY

SC10U6D3V5KX-1GP

12

SC22U6D3V5MX-2GP

12

C816

SC10U6D3V5KX-1GP

12

C830

SC22U6D3V5MX-2GP

12

AM24 AM23 AM21 AM20 AM18

C831

SC22U6D3V5MX-2GP

12

C817

C818

SC1U10V2KX-1GP

12

AM17

C825

C824

SC10U6D3V5KX-1GP

AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17

AL24 AL23 AL21 AL20 AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

B6 A6 A2

CPU1G

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

VCCPLL1 VCCPLL2 VCCPLL3

4

POWER

IVY-BRIDGE

1.8V RAIL

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

SA_DIMM_VREFDQ

VREFMISC

SB_DIMM_VREFDQ

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

VCCSA_SENSE

VCCSA_VID0 VCCSA_VID1

VCCIO_SEL

H_VCCP_SEL Voltage

1

0

CPU(5/7)

7 OF 9

AK35 AK34

AL1

SM_VREF

B4:VREF_DQ CHA D1:VREF_DQ CHB

B4 D1

1KR2F-3-GP

AF7

VDDQ1

AF4

VDDQ2

AF1

VDDQ3

AC7

VDDQ4

AC4

VDDQ5

AC1

VDDQ6

Y7

VDDQ7

Y4

VDDQ8

Y1

VDDQ9

U7

VDDQ10

U4

VDDQ11

U1

VDDQ12

P7

VDDQ13

P4

VDDQ14

P1

VDDQ15

M27

VCCSA1

M26

VCCSA2

L26

VCCSA3

J26

VCCSA4

J25

VCCSA5

J24

VCCSA6

H26

VCCSA7

H25

VCCSA8

H23

C22 C24

A19

NB: No Connect

S

B: VSS

IV

1.05V

1.0V

1 2

+V_SM_VREF_CNT

12

R815

DY

H_VCCP_SEL

3

R820

R820 100R2F-L1-GP-U

100R2F-L1-GP-U

R819

R819 100R2F-L1-GP-U

100R2F-L1-GP-U

DDR_VREF_S3_B4 DDR_VREF_S3_D1

12

R816

R816 1KR2F-3-GP

1KR2F-3-GP

DY

C803

SC10U6D3V3MX-GP

12

C813

SC10U6D3V5KX-1GP

12

H_FC_C22

VCC_GFXCORE

VCCGT_SENSE 42 VSSGT_SENSE 42

CAD Note: +V_SM_VREF should

have 10 mil trace width

12

C802

C801

SCD1U16V2ZY-2GP

DY

C805

C806

12

SC10U6D3V5KX-1GP

12

R818

R818 0R2J-2-GP

0R2J-2-GP

1 2

SC10U6D3V5KX-1GP

C815

C806

12

C804

SC10U6D3V3MX-GP

12

C814

SC10U6D3V5KX-1GP

12

VCCUSA_SENSE

R817

0R2J-2-GP

DY

SC10U6D3V5KX-1GP

12

DY

VCCGT_SENSE VSSGT_SENSE

DY

D801

12

0R2J-2-GP

DY

reserve PAD for ESD

M_VREF_DQ_DIMM014 M_VREF_DQ_DIMM115

SC2D2U10V3ZY-1GP

33OU*1 10U*6

C808

C807

SC10U6D3V5KX-1GP

12

2nd = 77.22771.00L

6A

VCCSA

TC802

SE330U2D5VDM-1GP

12

DY

1st = 77.23371.13L

2ND = 79.33719.L01

VCCSA_SEL

12

R804

1KR2J-1-GP

H_SNB_IVB#_PWRCTRL 45

2

M3 - Processor Generated SO-DIMM VREF_DQ

D802

12

0R2J-2-GP

20120112 PV-R

PCH_DDR_EN#5

1st = 84.05067.031

1st = 84.05067.031 2nd = 84.00138.F31

2nd = 84.00138.F31 3rd = 84.05067.031

3rd = 84.05067.031

PCH_DDR_EN#

1st = 84.05067.031

1st = 84.05067.031 2nd = 84.00138.F31

2nd = 84.00138.F31 3rd = 84.05067.031

3rd = 84.05067.031

Q802

AP2302GN-HF-GP

Q803

AP2302GN-HF-GP

G

D S

DS

G

12~16A

1D5V_S0

12

TC803

TC803 ST330U2D5VBM-1-GP

ST330U2D5VBM-1-GP

80.3371V.A2L

20120131PVR

VCCSA

R0801 need be close to pin H23.

12

R801

DY

100R2J-2-GP

VCCUSA_SENSE 48

H_FC_C22 48 VCCSA_SEL 48

12

R806

R806 1KR2J-1-GP

1KR2J-1-GP

1

R810

R810 0R2J-2-GP

0R2J-2-GP

DY

1 2

DDR_VREF_S3_B4 DDR_VREF_S3_D1

R814

R814 0R2J-2-GP

0R2J-2-GP

DY

1 2

S3 Power Reduction Circuit Processor VREF_DQ Implementation

1D5V_S3

R821

1KR2F-3-GP

A A

5

1KR2F-3-GP

R822

1KR2F-3-GP

DDR_VREF_S3

12

DY

12

DY

PM_SLP_S3#19,27,29,34,35,36,37,45,46,47,48,92,93

20120112 PV-R

PCH_DDR_EN#5

20120112 PV-R

4

R807

1 2

0R0402-PAD

1 2

DMN5L06K-7-GP

+V_SM_VREF

1st = 84.2N702.J31

1st = 84.2N702.J31 2ND = 84.07002.I31

2ND = 84.07002.I31 3rd = 84.2N702.W31

3rd = 84.2N702.W31

R802

1 2

0R2J-2-GP

R823 0R0402-PADR823 0R0402-PAD

1 2

DMN5L06K-7-GP

84.05067.031

DY

D S

R811

R811 0R2J-2-GP

0R2J-2-GP

Q801

DY

G

1 2

+V_SM_VREF_G

+V_SM_VREF_CNT

12

R803

R803 100KR2J-1-GP

100KR2J-1-GP

DY

C832

C832 SC470P50V2KX-3GP

SC470P50V2KX-3GP

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU(5/7) : GFX/PWR

2012 S-Series Richie 13.3

8 103Wednesday, March 14, 2012

1

-1

5

4

3

2

1

CPU(6/7)

IVY BRIDGE PROCESSOR (GND)

9 OF 9

8 OF 9

CPU1H

D D

C C

B B

AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7 AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7 AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7

AM4

AM3

AM2

AM1

AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4 AJ25

CPU1H

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

IVY-BRIDGE

VSS

8 OF 9

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

M34

G35 G32 G29 G26 G23 G20 G17 G11

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26

L33 L30 L27

K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10

F34 F31 F29

CPU1I

IVY-BRIDGE

VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233

IVY-BRIDGE

VSS

9 OF 9

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

CPU(6/7) : GND

Taipei Hsien 221, Taiwan, R.O.C.

2012 S-Series Richie 13.3

9 103Wednesday, March 14, 2012

1

-1

5

4

3

2

1

CPU(7/7)

IVY BRIDGE PROCESSOR (RESERVED)

D D

5 OF 9

CPU1E

AK28

CFG0

AK29

CFG2 CFG4

CFG5 CFG6 CFG7

C C

VCC_GFXCORE

VCC_CORE

B B

DY

1 2

DY

1 2 1 2

DY

1 2

DY

R100149D9R2F-GP

R100149D9R2F-GP R100249D9R2F-GP

R100249D9R2F-GP R100349D9R2F-GP

R100349D9R2F-GP R100449D9R2F-GP

R100449D9R2F-GP

VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE

CFG1

AL26

CFG2

AL27

CFG3

AK26

CFG4

AL29

CFG5

AL30

CFG6

AM31

CFG7

AM32

CFG8

AM30

CFG9

AM28

CFG10

AM26

CFG11

AN28

CFG12

AN31

CFG13

AN26

CFG14

AM27

CFG15

AK31

CFG16

AN29

CFG17

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD#AJ26

F25

RSVD#F25

F24

RSVD#F24

F23

RSVD#F23

D24

RSVD#D24

G25

RSVD#G25

G24

RSVD#G24

E23

RSVD#E23

D23

RSVD#D23

C30

RSVD#C30

A31

RSVD#A31

B30

RSVD#B30

B29

RSVD#B29

D30

RSVD#D30

B31

RSVD#B31

A30

RSVD#A30

C29

RSVD#C29

J20

RSVD#J20

B18

RSVD#B18

J15

RSVD#J15

IVY-BRIDGE

CFG

RESERVED

5 OF 9

VCC_DIE_SENSE

VSS_DIE_SENSE

RSVD#L7

RSVD#AG7

RSVD#AE7 RSVD#AK2

RSVD#W8

RSVD#AT26

RSVD#AM33

RSVD#AJ27

RSVD#T8

RSVD#J16 RSVD#H16 RSVD#G16

RSVD_NCTF#AR35

RSVD_NCTF#AT34 RSVD_NCTF#AT33 RSVD_NCTF#AP35 RSVD_NCTF#AR34

RSVD_NCTF#B34 RSVD_NCTF#A33 RSVD_NCTF#A34 RSVD_NCTF#B35 RSVD_NCTF#C35

RSVD#AJ32

RSVD#AK32

BCLK_ITP

BCLK_ITP#

RSVD_NCTF#AT2 RSVD_NCTF#AT1 RSVD_NCTF#AR1

VCC_DIE_SENSE

AH27 AH26

L7 AG7 AE7 AK2

W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

CLK_XDP_ITP_P

AN35

CLK_XDP_ITP_N

AM35

AT2 AT1 AR1

TP1004 TPAD14-OP-GPTP1004 TPAD14-OP-GP

1

TP1024 TPAD14-OP-GPTP1024 TPAD14-OP-GP

1

TP1025 TPAD14-OP-GPTP1025 TPAD14-OP-GP

1

CFG4

CFG7

DY

12

R1006

R1006 1KR2J-1-GP

1KR2J-1-GP

12

R1009

R1009 1KR2J-1-GP

1KR2J-1-GP

Display Port Presence Strap

CFG4

1:(Default) Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB de assertion

CFG7

0: PEG Wait for BIOS for training

CFG2

CFG6

DY

12

PEG Static Lane Reversal

R1005

CFG2

1KR2J-1-GP

CFG5

R1007

R1007 1KR2J-1-GP

1KR2J-1-GP

1:(Default) Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed

12

R1008

DY

1KR2J-1-GP

PCIE Port Bifurcation Straps

CFG[6:5] 11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

0:Enable eDP

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(7/7): CFG/RSVD/DDR3_VREF

Size Document Number Rev

A3

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

2012 S-Series Richie 13.3

1

of

10 103Wednesday, March 14, 2012

-1

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_XDP

2012 S-Series Richie 13.3

11 103Wednesday, March 14, 2012

1

-1

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

RESERVED

2012 S-Series Richie 13.3

12 103Wednesday, March 14, 2012

1

-1

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

RESERVED

2012 S-Series Richie 13.3

13 103Wednesday, March 14, 2012

1

-1

5

4

3

2

1

DIMM1

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6

M_VREF_CA_DIMM0

M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

0D75V_S0

D D

M_A_BS26 M_A_BS06

M_A_BS16

M_A_DQ[63:0]6

C C

12

0D75V_S0

12

SC1U6D3V2KX-GP

1KR2F-3-GP

C1421

SC1U6D3V2KX-GP

12

1D5V_S3

R1403

R1405

1D5V_S3

R1406

R1407

C1422

SC1U6D3V2KX-GP

12

SCD1U10V2KX-4GP

12

SCD1U10V2KX-4GP

C1423

12

DY

SC1U6D3V2KX-GP

M_VREF_CA_DIMM0

12

DY

M_VREF_DQ_DIMM0

12

DY

C1404

C1404 SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

12

DY

C1406

C1406 SC2D2U10V3ZY-1GP

SC2D2U10V3ZY-1GP

M_A_DIM0_ODT06 M_A_DIM0_ODT16

M_VREF_DQ_DIMM08

DDR3_DRAMRST#5,15,97

C1403

C1405

DY

DDR_VREF_S3

R1401

0R2J-2-GP

DY

DDR_VREF_S3

B B

Place these caps close to VTT1 and VTT2.

A A

R809

0R2J-2-GP

DY

C1420

Bom Not: 1st/2nd/3rd Add in BOM

5

4

DIMM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA

1

VREF_DQ RESET#

VTT1 VTT2

DDR3-204P-168-GP

NC#125/TEST

40 42 50 52 57 59 67 69 56 58 68

70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

10

27

45

62 135 152 169 186

12

29

47

64 137 154 171 188

116 120

126

30

203 204

1st = 62.10024.I91

1st = 62.10024.I91 2nd = 62.10017.U01

2nd = 62.10017.U01 3rd = 62.10024.H81

3rd = 62.10024.H81

RAS#

WE#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#77

NC#122

NP1 NP2

CK0

CK1

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA SCL

SA0 SA1

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H=9.2mm

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199

SA0_DIM0

197

SA1_DIM0

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

M_A_DQS#[7:0] 6 M_A_DQS[7:0] 6 M_A_A[15:0] 6

M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6

M_A_DIM0_CS#0 6 M_A_DIM0_CS#1 6

M_A_DIM0_CKE0 6 M_A_DIM0_CKE1 6

M_A_DIM0_CLK_DDR0 6 M_A_DIM0_CLK_DDR#0 6

M_A_DIM0_CLK_DDR1 6 M_A_DIM0_CLK_DDR#1 6

SODIMM1_1_SMB_DATA_R SODIMM1_1_SMB_CLK_R

1D5V_S3

3

TS#_DIMM0_1 15

12

C1401

SA0_DIM0 SA1_DIM0

1

23

RN1402

RN1402 SRN10KJ-5-GP

SRN10KJ-5-GP

4

0R4P2R-PADRN1401RN0R4P2R-PADRN1401

2 3 1

4

12

C1402

SCD1U16V2ZY-2GP

3D3V_S0

SC2D2U6D3V3KX-GP

RN

Thermal EVENT

TS#_DIMM0_1

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

PCH_SMBDATA 15,18,31,65 PCH_SMBCLK 15,18,31,65

3D3V_S0

12

R1402

10KR2J-3-GP

SODIMM A DECOUPLING

1D5V_S3

C1409

Layout Note: Place these Caps near SO-DIMMA.

C1413

C1409

C1408

C1407

SC10U6D3V5KX-1GP

12

C1416

C1415

C1414

12

SCD1U10V2KX-5GP

12

SCD1U10V2KX-5GP

2

C1411

C1410

SC10U6D3V5KX-1GP

12

C1417

12

SCD1U10V2KX-5GP

C1412

SC10U6D3V5KX-1GP

SC1U10V2KX-1GP

SC10U6D3V5KX-1GP

12

C1418

12

C1419

12

SC1U10V2KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

DDR3 SO-DIMM1

2012 S-Series Richie 13.3

1

-1

14 103Wednesday, March 14, 2012

-1

5

M_B_A[15:0]6

M_B_DQS#[7:0]6

M_B_DQS[7:0]6

D D

C C

DDR_VREF_S3

R1501

0R2J-2-GP

DY

R808

0R2J-2-GP

DDR_VREF_S3

DY

5

B B

A A

1D5V_S3

12

R1506

1KR2F-3-GP

R1507

1KR2F-3-GP

1D5V_S3

12

R1508

1KR2F-3-GP

R1509

1KR2F-3-GP

Place these caps close to VTT1 and VTT2.

C1523

SC1U6D3V2KX-GP

12

SCD1U10V2KX-4GP

12

SCD1U10V2KX-4GP

C1501

SC1U6D3V2KX-GP

12

C1502

M_VREF_CA_DIMM1

12

DY

12

DY

C1507

C1507 SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

M_VREF_DQ_DIMM1

12

DY

C1515

C1515 SC2D2U10V3ZY-1GP

SC2D2U10V3ZY-1GP

M_VREF_DQ_DIMM18 DDR3_DRAMRST#5,14,97

C1506

C1514

0D75V_S0

C1503

SC1U6D3V2KX-GP

12

DY

4

DIMM2

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

M_VREF_CA_DIMM1

M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_BS26 M_B_BS06

M_B_BS16

M_B_DQ[63:0]6

M_B_DIM0_ODT06 M_B_DIM0_ODT16

4

DIMM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-85-GP-U

62.10017.U21

62.10017.U21 2nd = 62.10017.T91

2nd = 62.10017.T91 3rd = 62.10024.I61

3rd = 62.10024.I61

RAS#

WE#

CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H=5.2mm

NP1 NP2

CK0

CK1

SCL

SA0 SA1

3

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199 197

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

DIMM2

SODIMM0_1_SMB_DATA_R SODIMM0_1_SMB_CLK_R

SB0_DIM0 SB1_DIM0

1D5V_S3

3

M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6

M_B_DIM0_CS#0 6 M_B_DIM0_CS#1 6

M_B_DIM0_CKE0 6 M_B_DIM0_CKE1 6

M_B_DIM0_CLK_DDR0 6 M_B_DIM0_CLK_DDR#0 6

M_B_DIM0_CLK_DDR1 6 M_B_DIM0_CLK_DDR#1 6

RN

1

4

2 3

TS#_DIMM0_1 14

12

C1504

DY

C1505

SCD1U16V2ZY-2GP

SC2D2U10V3ZY-1GP

0R4P2R-PADRN1501RN0R4P2R-PADRN1501

1D5V_S3

Layout Note: Place these Caps near SO-DIMMB.

2

SB1_DIM0 SB0_DIM0

SRN10KJ-5-GP

PCH_SMBDATA 14,18,31,65 PCH_SMBCLK 14,18,31,65

1st = 77.23371.13L

1st = 77.23371.13L 2ND = 79.33719.L01

2ND = 79.33719.L01 3rd = 77.23371.13L

3rd = 77.23371.13L

3D3V_S0

TC1401

2

3D3V_S0

RN1502

1

4

2 3

SODIMM B DECOUPLING

C1508

C1509

C1510

SC10U6D3V5KX-1GP

12

C1517

12

C1519

C1518

12

SCD1U10V2KX-5GP

SE330U2D5VDM-1GP

C1516

12

SCD1U10V2KX-5GP

1

Note: S

O-DIMMB SPD Address is 0xA4

SO-DIMMB TS Address is 0x34

C1511

C1512

C1513

SC10U6D3V5KX-1GP

12

C1521

12

SCD1U10V2KX-5GP

C1513

SC10U6D3V5KX-1GP

12

C1522

C1520

12

SC1U10V2KX-1GP

Title

Size Document Number Rev

Custom

Date: Sheet of

12

SC1U10V2KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DDR3 SO-DIMM2

2012 S-Series Richie 13.3

15 103Wednesday, March 14, 2012

1

-1

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

RESERVED

2012 S-Series Richie 13.3

16 103Wednesday, March 14, 2012

1

-1

A

5,21,32,34,53,54,56,71,83,96,97

B

C

D

E

RTC_X1

R1706

1 2

10MR2J-L-GP

X1701

X-32D768KHZ-34GPU

C1702

SC6P50V2CN-1GP

12

X-32D768KHZ-34GPU

1

4

7pF20PPM

2 3

82.30001.661

2ND = 82.30001.B21

BAT_GRNLED#27,82

PLT_RST#

4 4

3 3

2 2

RTC_X2

12

C1703

SC6P50V2CN-1GP

20120312MV

10KR2J-3-GP

10KR2J-3-GP R1701

R1701

1 2

10KR2J-3-GP

10KR2J-3-GP R1702

R1702

1 2

RTC_AUX_S5

20KR2J-L2-GP

HDA_SDOUT_CODEC29,97 HDA_BITCLK_CODEC29,97

BAT_GRNLED#_G

PLT_RST#_G

For Flash Descriptor Security Override HW strap

NO REBOOT STRAP

No Reboot Strap R710

HDA_SPKR

3D3V_S0

1 1

1 2

R1722 10KR2J-3-GP

1 2

R1723 10KR2J-3-GPR1723 10KR2J-3-GP

Low = Default High = No Reboot

DY

A

HDA_SPKR

SIRQ

RTC_AUX_S5

R1708

1 2

C1704

SC1U10V2KX-1GP

R1705

1 2

20KR2J-L2-GP

SC1U10V2KX-1GP

21

12

G1701

GAP-OPEN

3D3V_S5

12

R1725

R1725 1KR2J-1-GP

1KR2J-1-GP

BAT_GRNLED#_S

2nd = 84.BSS84.B31

G

D S

BAT_GRNLED#_D

G

D S

HDA_SDO HDA_SDO_R

12

C1701

INTRUDER#54,97

RTC_AUX_S5

HDA_RST#_CODEC29,97 HDA_SYNC_CODEC29

HDA_SPKR29

HDA_SDIN0_CODEC29

HDD_HALTLED68

84.00084.F31

BSS84-7-F-GP

BSS84-7-F-GP Q1701

Q1701

84.00084.F31

2nd = 84.BSS84.B31

BSS84-7-F-GP

BSS84-7-F-GP Q1702

Q1702

5V_S0

4

RN1702

RN1702 SRN10KJ-5-GP

SRN10KJ-5-GP

1

2 3

U1704

1 2 3 4

2N7002KDW-GP

B

HDA_SDO_G

6 5

HDA_SDO_G

R1709 1MR2J-1-GPR1709 1MR2J-1-GP

1 2

R1710 330KR2J-L1-GPR1710 330KR2J-L1-GP

1 2

SRN33J-7-GP

R1711

0R0402-PAD

20120112 PV-R

1KR2J-1-GP

1KR2J-1-GP R1712

R1712

PCH_SPI_CLK60 PCH_SPI_CS#060

PCH_SPI_MOSI60

PCH_SPI_MISO60

3D3V_S5

R1724 1KR2J-1-GPR1724 1KR2J-1-GP R1729 10KR2J-3-GPR1729 10KR2J-3-GP

HDA_SYNCHDA_SYNC_C

84.2N702.A3F

2nd = 84.2N702.E3F

2nd = 84.2N702.E3F 3rd = 84.2N702.F3F

3rd = 84.2N702.F3F

1 2

DY

R1707 330KR2J-L1-GP

RN1701

1 2 3 4 5

1 2

SPI_CS1#27,71

1 2 1 2

8 7 6

PCH_INTVRMEN

RTC_X1 RTC_X2 RTC_RST#

SRTC_RST#

PCH_INTVRMEN

HDA_BIT_CLK HDA_SYNC PCH_HDA_SPKR PCH_HDA_RST# HDA_SYNC_C

HDA_SDO_R HDA_SDO

HDD_HALTLED_R ISO_PREP#

PCH_JTAG_TCK_BUF PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

HDA_SYNC ISO_PREP#

3D3V_S5

PCHXDP

PCHXDP PCHXDP

PCHXDP

LAYOUT NOTE: JTAG_TMS TERMINATIONS NEED TO BE PLACED NEAR PCH JTAG_TDI TERMINATIONS NEED TO BE PLACED NEAR PCH JTAG_TDO TERMINATIONS NEED TO BE PLACED NEAR XDP JTAG_TCK TERMINATIONS NEED TO BE PLACED NEAR PCH

PCH(1/9)

RMEN- Integrated

INTV SUS 1.05V VRM Enable High - Enable internal VRs

PCH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-GP-NF

R1717 210R2F-L-GP

1 2

R1718 210R2F-L-GP

1 2

R1719 210R2F-L-GP

1 2

RN1703

1

8

2

7

3

6

4 5

SRN100J-4-GP

SRN100J-4-GP R1721 51R2J-2-GP

R1721 51R2J-2-GP

1 2

R1727 1KR2J-1-GP

1 2

DY

R1728 20KR2J-L2-GPR1728 20KR2J-L2-GP

1 2

C

LPC

FWH4/LFRAME#

LDRQ1#/GPIO23

RTCIHDA

SATA 6G

SATA

JTAG

SATA3RCOMPO

SPI

SATA0GP/GPIO21 SATA1GP/GPIO19

PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI

PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_TMS

PCH_JTAG_TCK_BUF HDD_HALTLED_R HDA_SDO

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3COMPI

SATA3RBIAS

SATALED#

RTC1

BAT-060003HA002M213ZL-GP-U

62.70014.001

62.70014.001 2nd = 62.70001.061

2nd = 62.70001.061

20120314 MV 20120315 MV

LPC_AD[3:0] 27,71

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37

LPC_FRAME#_R

D36 E36

K36

PCH_GPIO23

V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

SATA_COMP

Y10

AB12

SATA3_COMP

AB13

RBIAS_SATA3

AH1

NEED TO PLACE CLOSE TO PCH

P3 V14 P1

1 2

R1726 22R2J-2-GPR1726 22R2J-2-GP

TP1701 TPAD14-OP-GPTP1701 TPAD14-OP-GP

1

R1713 37D4R2F-GPR1713 37D4R2F-GP

1 2

R1714 49D9R2F-GPR1714 49D9R2F-GP

1 2

R1715 750R2F-GPR1715 750R2F-GP

SATA_LED#

RTC Battery

+RTC_VCC

1

PWR

2

GND

NP1

NP2

D

LPC_FRAME# 27,71

SIRQ 27,71

SATA_RXN0 56 SATA_RXP0 56

SATA_TXN0 56 SATA_TXP0 56

SATA_RXN1 56 SATA_RXP1 56

SATA_TXN1 56 SATA_TXP1 56

1 2

R1720 1KR2J-1-GPR1720 1KR2J-1-GP

Title

ze Document Number Rev

Size Document Number Rev

Si

A3

Date: Sheet of

HDD

ODD

1D05V_S0

3D3V_S0

12

R1716

R1716 10KR2J-3-GP

10KR2J-3-GP

SATA_LED# 68

SATA0GP_GPIO21 22

SATA_ODD_DET# 56

3D3V_AUX_S5

U1701

2

RTC_PW R+RTC_VCC

2ND = 83.00040.E81

PCH(1/9) : HDA/JTAG/SATA

2012 S-Series Richie 13.3

3

1

SC1U10V3ZY-6GP

CH715FGP-GP-U

83.R0304.D81

SC1U10V3ZY-6GP

20120210PV-R

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

17 103Wednesday, March 14, 2012

E

C1705

RTC_AUX_S5

12

-1

A

4 4

Media

WLAN

LAN

3 3

2 2

1 1

CLKREQ_LAN# PCH_GPIO74 GPIO44 CLKRQ_W WAN#

3D3V_S5

PCIE_RXN3_MEDIA32 PCIE_RXP3_MEDIA32 PCIE_TXN3_MEDIA32 PCIE_TXP3_MEDIA32

PCIE_RXN4_WLAN53 PCIE_RXP4_WLAN53 PCIE_TXN4_WLAN53 PCIE_TXP4_WLAN53

PCIE_RXN6_LAN34

PCIE_RXP6_LAN34 PCIE_TXN6_LAN34 PCIE_TXP6_LAN34

RN1804

1 2 3 4 5 6

SRN10KJ-L3-GP

C1805 SCD1U10V2KX-5GPC1805 SCD1U10V2KX-5GP

1 2

C1806 SCD1U10V2KX-5GPC1806 SCD1U10V2KX-5GP

1 2

C1809 SCD1U10V2KX-5GPC1809 SCD1U10V2KX-5GP

1 2

C1807 SCD1U10V2KX-5GPC1807 SCD1U10V2KX-5GP

1 2

C1810 SCD1U10V2KX-5GPC1810 SCD1U10V2KX-5GP

1 2

C1811 SCD1U10V2KX-5GPC1811 SCD1U10V2KX-5GP

1 2

20120212 MV 20120112 PV-R

R1804

WWAN_DET#54

Media

WLAN

LAN

10 9 8 7

A

1 2

0R2J-2-GP

CLK_PCIE_MEDIA#32 CLK_PCIE_MEDIA32

CLKREQ_MEDIA#32

CLK_PCIE_WLAN#53 CLK_PCIE_WLAN53

CLKRQ_W LAN#53

CLK_PCIE_LAN#34

CLK_PCIE_LAN34

CLKREQ_LAN#34

TP1805TPAD14-OP-GPTP1805TPAD14-OP-GP TP1806TPAD14-OP-GPTP1806TPAD14-OP-GP

3D3V_S5

CLKRQ_W LAN# GPIO56 CLKREQ_MEDIA# GPIO73

PCIE_TXN3_C PCIE_TXP3_C

PCIE_TXN4_C PCIE_TXP4_C

PCIE_TXN6_C PCIE_TXP6_C

GPIO73

GPIO18

GPIO20

GPIO44

GPIO56

CLKRQ_W WAN# PCIE_CLK_XDP_N

1

PCIE_CLK_XDP_P

1

3D3V_S0

B

BG34

BJ34

AV32

AU32

BE34 BF34 BB32 AY32

BG36

BJ36

AV34

AU34

BF36 BE36 AY34 BB34

BG37 BH37

AY36 BB36

BJ38 BG38 AU36

AV36

BG40

BJ40

AY40 BB40

BE38

BC38

AW38

AY38

Y40 Y39

J2

AB49 AB47

M1

AA48 AA47

V10

Y37 Y36

A8

Y43 Y45

L12

V45 V46

L14

AB42 AB40

E6

V40 V42

T13 V38

V37 K12

AK14 AK13

RN1805

1 2 3

SRN10KJ-5-GP

B

PCH(2/9)

PCH1B

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6 PERP6 PETN6 PETP6

PERN7 PERP7 PETN7 PETP7

PERN8 PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

PCIECLKRQ0#/GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1#/GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2#/GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

PCIECLKRQ3#/GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4#/GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5#/GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ#/GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6#/GPIO45 CLKOUT_PCIE7N

CLKOUT_PCIE7P PCIECLKRQ7#/GPIO46 CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

PANTHER-GP-NF

GPIO18

4

GPIO20

PCI-E*

CLOCKS

SMBALERT#/GPIO11

SMBDATA

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

Link

PEG_A_CLKRQ#/GPIO47

FLEX CLOCKS

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_N

CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67

C

2 OF 10

SMBCLK

SML0CLK

CL_CLK1

C

R1806

E12

PCH_SMB_CLK

H14

PCH_SMB_DATA

C9

A12

PCH_SML0_CLK

C8

PCH_SML0_DATA

G12

PCH_GPIO74

C13

PCH_SML1CLK

E14

PCH_SML1DATA

M16

M7

T11

P10

CLKREQ_PEG_A#

M10

CLKOUT_PEG_A_N

AB37

CLKOUT_PEG_A_P

AB38

AV22 AU22

AM12

CLOCK TERMINATION FOR FCIM

AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

XCLK_RCOMP

Y47

CLK_48_USB30

K43

CLK_27_NSSC

F47

CLK_48_KBC_PCH_SIO

H47

CLK_14M_KBC_P

K49

XTAL25_IN

1MR2J-1-GP

XTAL25_OUT

R1807

PCH_DDR_RST# 5

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

CLK_BUF_REF14

All resistors need very close to PCH

XTAL25_IN XTAL25_OUT

1 2

R1803 90D9R2F-1-GPR1803 90D9R2F-1-GP

12

R1805

3D3V_S5

12

10KR2J-3-GP

FPR_OFF 64,97

3D3V_S5

1 2

1KR2J-1-GP

3D3V_S5

12

R1801

R1801 10KR2J-3-GP

10KR2J-3-GP

84.2N702.J31

84.2N702.J31 2nd = 84.07002.I31

2nd = 84.07002.I31 3rd = 84.2N702.W31

3rd = 84.2N702.W31

2N7002K-2-GP

D

Q1801

R1808

R1808 10KR2J-3-GP

RN

RN1810

1

4

2 3

0R4P2R-PAD

RN1806

1 2 3

RN1807

2 3 1

RN1808

1 2 3

RN1809

1 2 3

R1802 10KR2J-3-GPR1802 10KR2J-3-GP

1 2

1D05V_S0

2 3

10KR2J-3-GP

12

DY

20120116PV-R

CLKOUT_DMI_N 5 CLKOUT_DMI_P 5

4

SRN10KJ-5-GP

4

SRN10KJ-5-GP

4

SRN10KJ-5-GP

CLK_PCI_FB 21

X1801

X1801 XTAL-25MHZ-155-GP

XTAL-25MHZ-155-GP

82.30020.D41

82.30020.D41 2nd = 82.30020.G71

2nd = 82.30020.G71

41

3rd = 82.30020.G61

D

DIS_PX

G

S

PCH_KBC_CLK27,28,85

1 2

C1801

C1801 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

1 2

D

PCH_SMBDATA14,15,31,65

PE_PWRGD 22,86,92,93,96,97

3D3V_AUX_S5

CLK_PCIE_VGA# 83 CLK_PCIE_VGA 83

PCH_SML1DATA

1 1 1 1

C1802

C1802 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

3D3V_S0

4

RN1803

RN1803 SRN2K2J-1-GP

SRN2K2J-1-GP

1

2 3

U1801

1

PCH_SMB_CLK

45

678

TP1801 TPAD14-OP-GPTP1801 TPAD14-OP-GP TP1802 TPAD14-OP-GPTP1802 TPAD14-OP-GP TP1803TPAD14-OP-GPTP1803TPAD14-OP-GP TP1804TPAD14-OP-GPTP1804TPAD14-OP-GP

Title

ze Document Number Rev

Size Document Number Rev

Si

A3

Date: Sheet of

2 3 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.2N702.E3F

2nd = 84.2N702.E3F 3rd = 84.2N702.F3F

3rd = 84.2N702.F3F

3D3V_S5

123

RN1802

RN1802 SRN2K2J-4-GP

SRN2K2J-4-GP

PCH_SML1DATA PCH_SML1CLK

U1802

1

6

2

5

3 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.2N702.E3F

2nd = 84.2N702.E3F 3rd = 84.2N702.F3F

3rd = 84.2N702.F3F

PCH_SML0_DATA PCH_SML0_CLK PCH_SMB_CLK PCH_SMB_DATA

PCH : PCI/USB/NVRAM/RSVD

2012 S-Series Richie 13.3

E

3D3V_S0

45

678

E

123

RN1801

RN1801 SRN2K2J-4-GP

SRN2K2J-4-GP

PCH_SMB_DATA

PCH_SMBCLK 14,15,31,65

PCH_KBC_DATA 27,28,85

3D3V_S5

18 103Wednesday, March 14, 2012

6 5

3D3V_S5

PCH_SML1CLK

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-1

A

B

C

D

E

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT) (R1917 STUFFED,

PCH(3/9)

3 OF 10

PCH1C

4 4

1D05V_S0

3 3

XDP_DBRESET#5

VGATE42

PM_PWROK27,97

2 2

R1906 0R0402-PADR1906 0R0402-PAD

R1907 0R0402-PADR1907 0R0402-PAD

R1908 0R0402-PADR1908 0R0402-PAD R1909 0R0402-PADR1909 0R0402-PAD

DMI_RXN[3:0]4

DMI_RXP[3:0]4

DMI_TXN[3:0]4

DMI_TXP[3:0]4

PUT CLOSE PCH

R1902 49D9R2F-GPR1902 49D9R2F-GP

1 2

TP1903TPAD14-OP-GPTP1903TPAD14-OP-GP

1

12

12 12

PM_DRAM_PWRGD5

RSMRST#27,41,97

SUS_PW R_ACK27

PWR_BTN_OUT#27

ADP_PRES_OUT27,85

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_COMP_R

1 2

R1903 750R2F-GPR1903 750R2F-GP

RBIAS_CPY

SUSACK#_R

PM_SYSRST#_R

SYS_PWROK_R

PM_PCH_PWROK PCH_GPIO61

APWROK

PCH_GPIO72

PM_RI#

PCH1C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT/GPIO31

E10

BATLOW#/GPIO72

A10

RI#

PANTHER-GP-NF

DMI

SUS_STAT#/GPIO61

System Power Management

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

FDI

FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN#/GPIO32

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#/GPIO29

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_TX_N0

FDI_TX_N1 FDI_TX_N2 FDI_TX_N3 FDI_TX_N4 FDI_TX_N5 FDI_TX_N6 FDI_TX_N7

FDI_TX_P0

FDI_TX_P1 FDI_TX_P2 FDI_TX_P3 FDI_TX_P4 FDI_TX_P5 FDI_TX_P6 FDI_TX_P7

DSWODVREN

PCH_DPW ROK

PM_SLP_S5#

SLP_S4#_R

SLP_S3#_R

PM_SLP_A#_R

SLP_SUS#

SLP_LAN#

FDI_TX_N[7:0] 4

FDI_TX_P[7:0] 4

FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4

20120112 PV-R

R1904 0R0402-PADR1904 0R0402-PAD

1 2

R1905 10KR2J-3-GP

1 2

DY

TP1901 TPAD14-OP-GPTP1901 TPAD14-OP-GP

1

20120112 PV-R

R1911 0R0402-PADR1911 0R0402-PAD

1 2

R1912 0R0402-PADR1912 0R0402-PAD

1 2

R1910 0R2J-2-GP

1 2

DY

R1913 0R0402-PADR1913 0R0402-PAD

1 2

TP1905 TPAD14-OP-GPTP1905 TPAD14-OP-GP

1

3D3V_S0

RSMRST#

PCIE_WAKE# 34,53

PM_CLKRUN# 27

SUSCLK32_KBC 27

PM_SLP_S4# 46,62,97

PM_SLP_S3# 8,27,29,34,35,36,37,45,46,47,48,92,93

PM_SLP_A# 27

H_PM_SYNC 5

R1901 UNSTUFFED

LOW Disabled (R1901 STUFFED, R1917 UNSTUFFED

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

DSWODVREN

ADP_PRES_OUT PWR_BTN_OUT# PM_RI# PCIE_WAKE#

PM_CLKRUN#

PCH_GPIO72 SUS_PW R_ACK

1 2

R1901 330KR2J-L1-GP

1 2

DY

RN1901

1 2 3 4 5

SRN10KJ-6-GP

1 2

R1915 8K2R2J-3-GPR1915 8K2R2J-3-GP

RN1902

1 2 3

SRN10KJ-5-GP

RTC_AUX_S5

3D3V_S5

8 7 6

3D3V_S0

3D3V_S5

4

Intel ME-EC Interaction Signal List with and without M3 support

Signal Name

P (e.g., Intel AMT)

Platform Without M3 Support

latform With M3 Support

SUSPWRDNACK(GPIO30) Required Required

1 1

SLP_A# Required

A

Required RequiredACPRESENT(GPIO31)

(Tie to SLP_S3#) Note: If SLP_S3# is not routed from PCH to EC, then SLP_A# becomes required from Intel ME-EC prespecrive.

B

3D3V_S5

C

AMT/ME COMPLIANCY TEST CONN.

PM_SLP_S3# PM_SLP_S4#

PM_SLP_S5# PM_SLP_A#

ON_OFF#82,97

ON_OFF# SLP_LAN#

APS1

9 1 2

3 4 5

DY

6 7 8

10

ACES-CON8-13-GP-U1

20.F1295.008

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH(3/9) : DMI/FDI/PM

Size Document Number Rev

A3

Date: Sheet of

D

Date: Sheet of

PCH(3/9) : DMI/FDI/PM

Taipei Hsien 221, Taiwan, R.O.C.

2012 S-Series Richie 13.3

19 103Wednesday, March 14, 2012

E

-1

A

B

C

D

E

4 4

3D3V_S0

1

23

RN2002

RN2002 SRN2K2J-1-GP

SRN2K2J-1-GP

4

3 3

2 2

LCD_BL_EN49,97 LCDVDD_EN49,97

BKLT_CTL49

LCD_SMBCLK49 LCD_SMBDATA49

L_CTRL_CLK L_CTRL_DATA

TXCLKA_L-49 TXCLKA_L+49

TXOUTA_L0-49 TXOUTA_L1-49 TXOUTA_L2-49

TXOUTA_L0+49 TXOUTA_L1+49 TXOUTA_L2+49

PCH_BLUE50 PCH_GREEN50 PCH_RED50

CRT_DDC_CLK50 CRT_DDC_DATA50

CRT_HSYNC50 CRT_VSYNC50

R2003

1KR2D-1-GP

LVD_IBG

1 2

R2005 2K37R2F-GPR2005 2K37R2F-GP

DAC_IREF

12

AE48 AE47

AK39 AK40

AN48 AM47 AK47

AN47 AM49 AK49

AH45 AH47

AH43 AH49

PCH(4/9)

PCH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG LVD_VREFH

LVD_VREFL

LVDSA_CLK# LVDSA_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2

AJ48

LVDSA_DATA#3 LVDSA_DATA0

LVDSA_DATA1 LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK LVDSB_DATA#0

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3 LVDSB_DATA0

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-GP-NF

4 OF 10

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN

DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN

DDPD_AUXP

CRT

DDPD_HPD

DPD_AUXN DPD_AUXP

3D3V_S0

4

1

TP2002TPAD14-OP-GPTP2002TPAD14-OP-GP

1

TP2001TPAD14-OP-GPTP2001TPAD14-OP-GP

1

RN2001

RN2001 SRN2K2J-1-GP

SRN2K2J-1-GP

2 3

PCH_HDMI_CLK 51 PCH_HDMI_DATA 51

HDMI_PCH_DET 51,97 HDMI_DATA2_R# 51

HDMI_DATA2_R 51 HDMI_DATA1_R# 51 HDMI_DATA1_R 51 HDMI_DATA0_R# 51 HDMI_DATA0_R 51 HDMI_CLK_R# 51 HDMI_CLK_R 51

1 1

A

B

C

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH(4/9) : LVDS/CRT/DDI

Size Document Number Rev

A3

Date: Sheet of

PCH(4/9) : LVDS/CRT/DDI

Taipei Hsien 221, Taiwan, R.O.C.

2012 S-Series Richie 13.3

20 103Wednesday, March 14, 2012

E

-1

A

GPIO Table

S 2012 Chief River

Richie U&D (13 inches) Rocky U&D (14 inches)

Rocky U&D (15/17 inches)

PCH GPIO 52

1 1 0

GNT1#/GPIO51

0 0

1 1

4 4

3D3V_S0

R2113

1 2

10KR2J-3-GP

R2109

1 2

10KR2J-3-GP

DY

3D3V_S0

1 2

10KR2J-3-GP

10KR2J-3-GP R2112

INT_PIRQA# INT_PIRQD# INT_PIRQB# INT_PIRQC#

R2112

R2110

1 2

10KR2J-3-GP

RN2101

1 2 3

SRN8K2J-3-GP

1 2 3 4 5 6

3 3

3D3V_S0

2 2

PCH_GPIO51

DY

PE_GPIO0

DY

CAMERA_ON

ACCEL_INT

4

NMI_SMI_DBG#

RN2102

SRN8K2J-2-GP-U

10 9 8 7

3D3V_S0

PE_GPIO1 PCH_GPIO2 PLT_DET_R PCH_GPIO50

USB3_RXN262 USB3_RXN362 USB3_RXN462

USB3_RXP262 USB3_RXP362 USB3_RXP462

USB3_TXN262 USB3_TXN362 USB3_TXN462

USB3_TXP262 USB3_TXP362 USB3_TXP462

PLT_DET27,69

PE_GPIO192,93

CAMERA_ON49

PE_GPIO083

CLK_PCI_KBC27,97 CLK_PCI_FB18

CLK_PCI_DEBUG71,97

B

Boot BIOS Strap

SATA1GP#/GPIO19 Boot BIOS Location

0 1 01

LPC

Reserved

PCI

SPI(Default)

USB3.0 Table

Pair Device

1 2 3 4

20120112 PV-R

R2103 22R2J-2-GPR2103 22R2J-2-GP

1 2

R2105 22R2J-2-GPR2105 22R2J-2-GP

1 2

R2107 22R2J-2-GPR2107 22R2J-2-GP

1 2

3D3V_S5

USB

FREE I/O CONN. 1 I/O CONN. 2 I/O CONN. 3

R2106 0R0402-PADR2106 0R0402-PAD

1 2

PE_GPIO1

SATA_ODD_DA#56,96

TP2108TPAD14-OP-GP TP2108TPAD14-OP-GP TP2106TPAD14-OP-GP TP2106TPAD14-OP-GP

R2102

NMI_SMI_DBG#27,71 ACCEL_INT65

1 2

DY

3D3V_S5

10KR2J-3-GP

PCI_PLTRST#

CLK_PCI_SIO_R CLK_PCI_FB_R CLK_OUT_PCI2

1

CLK_OUT_PCI3

1

CLK_PCI_KBC_R

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

PCH_GPIO50 PLT_DET_R

PCH_GPIO51

PCH_GPIO2

PME#

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

AH12

AM4 AM5

Y13 K24

AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

K40 K38 H38 G38

C46 C44 E40

D47 E42

G42 G40 C42 D44

K10

H49 H43

K42 H40

H3

L24

F46

C6

J48

C

PCH(5/9)

PCH1E

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

RSVD

TP21 TP22 TP23 TP24

USB3RN1 USB3RN2 USB3RN3 USB3RN4 USB3RP1 USB3RP2 USB3RP3 USB3RP4 USB3TN1 USB3TN2 USB3TN3 USB3TN4 USB3TP1 USB3TP2 USB3TP3 USB3TP4

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PME# PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

PANTHER-GP-NF

RSVD

PCI

USB

5 OF 10

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

RSVD23 RSVD24

RSVD25 RSVD26

RSVD27 RSVD28

RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5 AV10

AT8 AY5

BA2 AT12

BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

USB_BIAS

OC0#_GPIO59 OC1#_GPIO40 OC2#_GPIO41 OC3#_GPIO42 OC4#_GPIO43 OC5#_GPIO9

OC7#_GPIO14

D

USB_PN1 62 USB_PP1 62 USB_PN2 62 USB_PP2 62 USB_PN3 62 USB_PP3 62

USB_PN5 53 USB_PP5 53

USB_PN8 64 USB_PP8 64 USB_PN9 61 USB_PP9 61 USB_PN10 49 USB_PP10 49

USB_PN12 54 USB_PP12 54

R2101 22D6R2F-L1-GPR2101 22D6R2F-L1-GP

USB 3.0 Conn. 1 USB 3.0 Conn. 2 USB 3.0 Conn. 3

BT WLAN combo

Fingerprint

USB 2.0 Conn. 1

Camera

WWAN

1 2

LANLINK_STATUS 35

3D3V_S5

E

USB2.0 Table

Pair Device

0 1 2 3 4 5 6 7 8 9 10 11 12 13

USB

FREE

USB 3.0 I/O CONN. 1 USB 3.0 I/O CONN. 2 USB 3.0 I/O CONN. 3

FREE BT WLAN combo FREE FREE Fingerprint

USB 2.0 I/O CONN. 1

Camera FREE

WAN

W FREE

RN2104

U2101

1

1 1

A

PCI_PLTRST#

A

2

B GND3Y

U74LVC1G08G-AL5-R-GP-U

73.01G08.EHG

73.01G08.EHG 2nd = 73.7SZ08.EAH

2nd = 73.7SZ08.EAH 3rd = 73.01G08.L04

3rd = 73.01G08.L04

R2104

R2104 0R2J-2-GP

0R2J-2-GP

VCC

1 2

B

AND GATE

5

PLT_RST#

4

DY

12

R2108

R2108 100KR2J-1-GP

100KR2J-1-GP

PLT_RST# 5,17,32,34,53,54,56,71,83,96,97

C

OC4#_GPIO43 OC1#_GPIO40 OC2#_GPIO41 OC3#_GPIO42

OC5#_GPIO9 LANLINK_STATUS OC7#_GPIO14 OC0#_GPIO59

RN2104

8 7 6

SRN10KJ-6-GP

RN2103

8 7 6

SRN10KJ-6-GP

1 2 3 45

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH(5/9) : PCI/USB/NVM

ze Document Number Rev

Size Document Number Rev

Si

A3

Date: Sheet of

PCH(5/9) : PCI/USB/NVM

Taipei Hsien 221, Taiwan, R.O.C.

2012 S-Series Richie 13.3

21 103Wednesday, March 14, 2012

E

-1

A

RP2201

PE_PWRGD OCP_OC# LPC_RESET#

SATA_ODD_PWR_EN

3D3V_S0

4 4

3 3

2 2

3D3V_S5

R2204 10KR2J-3-GP

1 2

R2205 10KR2J-3-GPR2205 10KR2J-3-GP

1 2

R2207 10KR2J-3-GPR2207 10KR2J-3-GP

1 2

3D3V_S0

1 2

R2212 10KR2J-3-GP

DY

VRAM ID TABLE

3D3V_S0 3D3V_S0

R2225

R2225 10KR2J-3-GP

10KR2J-3-GP

Hynix_Elpida

1 2

PCH_GPIO39 PCH_GPIO38

R2223

R2223 10KR2J-3-GP

10KR2J-3-GP

UMA_Samsung

1 2

GDDR5/DDR3 TABLE

3D3V_S5

12

R2206

R2206 10KR2J-3-GP

10KR2J-3-GP

R2218

R2218 10KR2J-3-GP

10KR2J-3-GP

1 2

1 2 3 4 5 6

DY

FPR_LOCK#

R2220

R2220 10KR2J-3-GP

10KR2J-3-GP

Samsung_Elipda

1 2

R2224

R2224 10KR2J-3-GP

10KR2J-3-GP

UMA_Hynix

1 2

20110822SI

DY

PCH_GPIO12

RP2201

SRN10KJ-L3-GP

10 9

GPIO34

8

WWAN_TRANSMIT_OFF#

7

RUNSCI_EC#

PCH_GPIO24

GPI_INV_LIDWAKE

WLAN_TRANSMIT_OFF#

R2211 10KR2J-3-GPR2211 10KR2J-3-GP

0 1 1 0

1 1 0 0

2012 Chief River

Richie U&D (13 inches) Rocky U&D (14 inches) Rocky U&D (15/17 inches)

1 2

PCH_GPIO38PCH_GPIO39

PCH_GPIO27

VENDER Samsung

Hynix Elpida

UMA

PCH GPIO 12

0 (13") GDDR5

1(14",15",17")DDR3 1(14",15",17")DDR3

3D3V_S5

B

BT_OFF#53,97

TP2214TPAD14-OP-GPTP2214TPAD14-OP-GP

TP2216TPAD14-OP-GPTP2216TPAD14-OP-GP TP2215TPAD14-OP-GPTP2215TPAD14-OP-GP

TP2218TPAD14-OP-GPTP2218TPAD14-OP-GP TP2217TPAD14-OP-GPTP2217TPAD14-OP-GP

CRD_REQ#_R_R

GPI_INV_LIDWAKE PCH_GPIO12 TLS_ENcrytion

SATA4GP_GPIO16

PE_PWRGD

PCH_GPIO24 PCH_GPIO27 PCH_GPIO28

1

GPIO34 BT_OFF# SATA2GP_GPIO36 SATA3GP_GPIO37 PCH_GPIO38 PCH_GPIO39

SATA5GP_GPIO49

NCTF_VSS#A4

1

NCTF_VSS#B3

1

NCTF_VSS#B47

1

NCTF_VSS#BF1

1

NCTF_VSS#BF49

1

R2214

CRD_REQ#_R_R32

1 2

WWAN_TRANSMIT_OFF#54,68

WLAN_TRANSMIT_OFF#53

OCP_OC#38 RUNSCI_EC#27 THERM_SCI#28

1KR2J-1-GP

PE_PWRGD18,86,92,93,96,97

TP2206TPAD14-OP-GPTP2206TPAD14-OP-GP

FPR_LOCK#64,97

C

PCH(6/9)

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49/TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1#A4

A44

VSS_NCTF_2#A44

A45

VSS_NCTF_3#A45

A46

VSS_NCTF_4#A46

A5

VSS_NCTF_5#A5

A6

VSS_NCTF_6#A6

B3

VSS_NCTF_7#B3

B47

VSS_NCTF_8#B47

BD1

VSS_NCTF_9#BD1

BD49

VSS_NCTF_10#BD49

BE1

VSS_NCTF_11#BE1

BE49

VSS_NCTF_12#BE49

BF1

VSS_NCTF_13#BF1

BF49

VSS_NCTF_14#BF49

PANTHER-GP-NF

6 OF 10

TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71

A20GATE

RCIN#

PROCPWRGD

GPIO

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

VSS_NCTF_15#BG2

VSS_NCTF_16#BG48

VSS_NCTF_17#BH3

VSS_NCTF_18#BH47

VSS_NCTF_19#BJ4 VSS_NCTF_20#BJ44 VSS_NCTF_21#BJ45

NCTF

VSS_NCTF_22#BJ46

VSS_NCTF_23#BJ5

VSS_NCTF_24#BJ6

VSS_NCTF_25#C2

VSS_NCTF_26#C48

VSS_NCTF_27#D1

VSS_NCTF_28#D49

VSS_NCTF_29#E1

VSS_NCTF_30#E49

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

VSS_NCTF_31#F1

VSS_NCTF_32#F49

PECI

NC_1

C40 B41 C41 A40

P4

H_PECI_R

AU16 P5 AY11

PCH_THRMTRIP#_R

AY10

INIT3_3V#

T14

DF_TVS

AY1

AH8 AK11 AH10 AK10

P37

NCTF_VSS#BG2

BG2

NCTF_VSS#BG48

BG48

NCTF_VSS#BH3

BH3

NCTF_VSS#BH47

BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6

NCTF_VSS#C2

C2

NCTF_VSS#C48

C48 D1

NCTF_VSS#D49

D49 E1 E49 F1 F49

D

1 2

DY

R2209 0R2J-2-GP

R2210 390R2F-2GPR2210 390R2F-2GP

TP2203TPAD14-OP-GPTP2203TPAD14-OP-GP

1

TP2207 TPAD14-OP-GPTP2207 TPAD14-OP-GP

1

TP2208 TPAD14-OP-GPTP2208 TPAD14-OP-GP

1

TP2209 TPAD14-OP-GPTP2209 TPAD14-OP-GP

1

TP2210 TPAD14-OP-GPTP2210 TPAD14-OP-GP

1

1 1

1

SATA_ODD_PWR_EN 56,97 D3E_WAKE# 32,97 LPC_RESET# 27 GPS_XMIT_OFF# 54,97

GATEA20 27

H_PECI 5,27

KBRST# 27,97

H_CPUPW RGD 5

1 2

TP2212TPAD14-OP-GPTP2212TPAD14-OP-GP TP2211TPAD14-OP-GPTP2211TPAD14-OP-GP

TP2213TPAD14-OP-GPTP2213TPAD14-OP-GP

E

RN2205

D3E_WAKE# GPS_XMIT_OFF# GATEA20 KBRST#

1D05V_S0

12

R2222

DY

56R2J-4-GP

PROC_SELECT

1 2

R2202 1KR2J-1-GPR2202 1KR2J-1-GP

RN2205

8 7 6

SRN10KJ-6-GP

H_THRMTRIP# 5,85

1D8V_S0

12

R2201

R2201 2K2R2J-2-GP

2K2R2J-2-GP

1 2 3 45

H_SNB_IVB# 5

DMI & FDI Termination Voltage

DF_TVS

SNB: "1" IVB: "0"

3D3V_S03D3V_S0

3D3V_S0

1 2

R2217 200KR2J-L1-GP

DY

1 1

DY

SATA3GP_GPIO37

FDI TERMINATION VOLTAGE OVERRIDE

GPIO37 (FDI_OVRVLTG)

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

A

3D3V_S0

1 2

R2213 200KR2J-L1-GP

DY

SATA2GP_GPIO36

DMI TERMINATION VOLTAGE OVERRIDE

GPIO36

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

B

DY

RN2203

4

C

BT_OFF#

SATA5GP_GPIO49

CRD_REQ#_R_R

1 2

R2216 10KR2J-3-GP

1 2 3

SRN10KJ-5-GP

3D3V_S0

RN2202

1 2 3

SRN10KJ-5-GP

4

SATA4GP_GPIO16

D

SATA0GP_GPIO21 17 SATA4GP_GPIO16 96

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH(6/9) : GPIO/NTCF/RSVD

A3

2012 S-Series Richie 13.3

22 103Wednesday, March 14, 2012

E

-1

5

4

3

2

1

VCC_PCH: 6A

PCH(7/9)

D D

1D05V_S0

1.3A

SC10U6D3V3MX-GP

12

C2313

SC1U10V2KX-1GP

12

C2314

SC1U10V2KX-1GP

12

C2315

1D05V_S0

SC1U10V2KX-1GP

DY

12

C2316

2.925A

L2301

1D05V_S0

C C

1D05V_S0

C2310

B B

1D05V_S0

L2301

DY

1 2

IND-1UH-100-GP

12

C2311

C2321

SC1U10V2KX-1GP

3D3V_S0

1 2

DY

R2303

0R0402-PAD

C2321

12

SC10U6D3V3MX-GP

R2302 0R3J-0-U-GP

+V1.05S_VCCAPLL_EXP

SC10U6D3V3MX-GP

12

C2317

DY

12

C2320

SC1U10V2KX-1GP

12

C2304

C2304 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+V1.05S_VCCAPLL_FDI

+V1.05S_VCCDPLL_FDI

12

C2301

SC1U10V2KX-1GP

+VCCAFDI_VRM

+V1.05S_VCC_DMI

AA23 AC23 AD21 AD23

AF21

AF23 AG21 AG23 AG24 AG26 AG27 AG29

AJ23

AJ26

AJ27

AJ29

AJ31

AN19

BJ22

AN16 AN17

AN21 AN26 AN27 AP21 AP23 AP24 AP26

AT24

AN33 AN34

BH29

AP16

BG6

AP17

AU20

PCH1G

VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE13 VCCCORE14 VCCCORE15 VCCCORE16 VCCCORE17

VCCIO28

VCCAPLLEXP

VCCIO15 VCCIO16

VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26

VCC3_3_3

VCCVRM2

VCCAFDIPLL

VCCIO27

VCCDMI2

PANTHER-GP-NF

POWER

VCC CORE

VCCIO

FDI

CRTLVDS

DMI

DFT / SPI HVCMOS

7 OF 10

VCCADAC

VSSADAC

VCCALVDS VSSALVDS

VCCTX_LVDS1 VCCTX_LVDS2 VCCTX_LVDS3 VCCTX_LVDS4

VCC3_3_6

VCC3_3_7

VCCVRM3

VCCDMI1

VCCCLKDMI

VCCDFTERM1

VCCDFTERM2

VCCDFTERM3

VCCDFTERM4

VCCSPI

U48

U47

AK36 AK37

AM37 AM38 AP36 AP37

266mA

V33

V34

+VCCAFDI_VRM

AT16

AT20

VCCCLKDMI

AB36

C2302

SC1U10V2KX-1GP

AG16

AG17

AJ16

AJ17

V1

SCD01U16V2KX-3GP

3D3V_S0

SCD1U10V2KX-4GP

12

C2322

SCD1U10V2KX-4GP

12

C2318

C2323

SCD01U16V2KX-3GP

12

C2306

SCD01U16V2KX-3GP

12

160mA

+V1.05S_VCC_DMI 1D05V_S0

12

C2319

C2319 SC1U10V2KX-1GP

SC1U10V2KX-1GP

12

20120112 PV-R

SCD1U10V2KX-4GP

12

C2303

3D3V_S5

20mA

SC1U10V2KX-1GP

12

C2305

C2307

R2301

0R0402-PAD

R2306

1 2

0R0402-PAD

3D3V_S0_LDO

C2325

SC2D2U6D3V3KX-GP

C2325

3D3V_S0

1D8V_S0

60mA

C2309

SC22U6D3V5MX-2GP

12

1D05V_S0

1D8V_S0

1mA

12

1mA

42mA

20mA

190mA

U2301

OUT5IN

GND

4

NC#4

EN

TLV70233DBVR-GP

74.70233.03F

74.70233.03F 2nd = 74.08818.B3F

2nd = 74.08818.B3F 3rd = 74.09090.D3F

3rd = 74.09090.D3F

5V_S0

1 2 3

12

C2308

SC1U10V2KX-1GP

20120116PV-R

R2304 0R0603-PAD-1-GPR2304 0R0603-PAD-1-GP

A A

5

1D5V_S0

1D8V_S0

1 2

DY

R2305 0R3J-0-U-GP

4

+VCCAFDI_VRM

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

3

2

Date: Sheet of

PCH(7/9) : PWR1

Taipei Hsien 221, Taiwan, R.O.C.

2012 S-Series Richie 13.3

23 103Wednesday, March 14, 2012

1

-1

A

B

C

D

E

1D05V_S0

1 2

DY

R2405 0R3J-0-U-GP

12

C2403

C2403 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

12

C2439

C2411

12

+V1.05S_VCCA_B_DPL

SC22U6D3V5MX-2GP

12

TC2402

DY

12

55mA

SC1U10V2KX-1GP

DY

SCD1U10V2KX-4GP

12

C2433

B

R2405 0R3J-0-U-GP

+VCCPDSW

PCH_VCCDSW

C2401

12

SCD1U10V2KX-4GP

DY

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

C2424

C2424 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D05V_S0

C2429

C2434

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

1D05V_S0

C2408

DY

SC1U10V2KX-1GP

C2412

C2413

12

C2421

12

+VCCRTCEXT

160mA

+V1.05S_VCCA_A_DPL +V1.05S_VCCA_B_DPL

95mA

12

C2430

1 2

+V1.05M_VCCSUS

C2431

12

SC1U10V2KX-1GP

DY

RTC_AUX_S5

SCD1U10V2KX-4GP

12

C2435

SC1U10V2KX-1GP

SCD1U10V2KX-4GP

+VCCACLK

+VCCSUS1

12

C2414

12

DY

+VCCAFDI_VRM

PCH_DCPSST

SCD1U10V2KX-4GP

6uA

SC1U10V2KX-1GP

DY

12

C2436

12

AD49

BH23

AA19 AA21 AA24 AA26 AA27 AA29 AA31 AC26 AC27 AC29 AC31 AD29 AD31

BD47

AG34

AG33

C2437

T16

V12

T38

AL29

AL24

W21 W23 W24 W26 W29 W31 W33

N16

Y49

BF47

AF17 AF33 AF34

V16

T17 V19

BJ8

A22

3D3V_S5

2mA

4 4

3 3

2 2

3D3V_S0

L2401

1 2

IND-10UH-238-GP

1st = 68.1001A.10B

1st = 68.1001A.10B 2nd = 68.1001D.10E

2nd = 68.1001D.10E 3rd = 68.1001A.10B

3rd = 68.1001A.10B

+V3.3S_VCC_CLKF33

SC1U10V2KX-1GP

SC10U6D3V3MX-GP

1D05V_S0

1st = 68.1001A.10B

1st = 68.1001A.10B 2nd = 68.1001D.10E

2nd = 68.1001D.10E 3rd = 68.1001A.10B

3rd = 68.1001A.10B

SC1U10V2KX-1GP

12

C2404

1D05V_S0

3rd = 68.1001A.10B

3rd = 68.1001A.10B 2nd = 68.1001D.10E

2nd = 68.1001D.10E 1st = 68.1001A.10B

1st = 68.1001A.10B

L2402

1 2

IND-10UH-238-GP

L2403

1 2

IND-10UH-238-GP

12

C2405

1D05V_S0

1 2

R2401

0R0603-PAD-1-GP

20120116PV-R

L2405

IND-10UH-193-GP

SC10U6D3V3MX-GP

1.01A

C2410

SC10U6D3V3MX-GP

12

80mA

+V1.05S_VCCA_A_DPL

80mA

SC1U10V2KX-1GP

SC22U6D3V5MX-2GP

C2420

12

TC2401

DY

SC10U6D3V3MX-GP

12

AF33, AF34 and AG34 should be VCCDIFFCLKN[3:1]

1D05V_S0

SC1U10V2KX-1GP

1D05V_S0

12

C2427

1 1

A

C2426

SC1U10V2KX-1GP

1D05V_S0

R2404 0R3J-0-U-GP

1D05V_S0

1mA

SC4D7U6D3V3KX-GP

12

C2432

1 2

SCD1U10V2KX-4GP

PCH(8/9)

POWER

PCH1J

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3_5

VCCAPLLDMI2 VCCIO14

DCPSUS3

VCCASW1 VCCASW2 VCCASW3 VCCASW4 VCCASW5 VCCASW6 VCCASW7 VCCASW8 VCCASW9 VCCASW10 VCCASW11 VCCASW12 VCCASW13 VCCASW14 VCCASW15 VCCASW16 VCCASW17 VCCASW18 VCCASW19 VCCASW20

DCPRTC

VCCVRM4

VCCADPLLA VCCADPLLB

VCCIO7 VCCDIFFCLKN1 VCCDIFFCLKN2 VCCDIFFCLKN3

VCCSSC

DCPSST

DCPSUS1 DCPSUS2

V_PROC_IO

VCCRTC

PANTHER-GP-NF

POWER

Clock and Miscellaneous

CPURTC

C

PCI/GPIO/LPCMISC

SATA USB

HDA

10 OF 10

VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33

VCCSUS3_3_7 VCCSUS3_3_8 VCCSUS3_3_9

VCCSUS3_3_10

VCCSUS3_3_6

VCCIO34

V5REF_SUS

DCPSUS4

VCCSUS3_3_1

V5REF

VCCSUS3_3_2 VCCSUS3_3_3 VCCSUS3_3_4 VCCSUS3_3_5

VCC3_3_1 VCC3_3_8 VCC3_3_4

VCC3_3_2

VCCIO5

VCCIO12 VCCIO13

VCCIO6

VCCAPLLSATA

VCCVRM1

VCCIO2 VCCIO3 VCCIO4

VCCASW22

VCCASW23

VCCASW21

VCCSUSHDA

N26 P26 P28 T27 T29

T23 T24 V23 V24 P24

T26

M26

+VCCA_USBSUS

AN23 AN24

P34

N20 N22 P20 P22

AA16 W16 T34

AJ2

AF13

AH13 AH14

AF14

+V1.05S_VCCAPLL_SATA3

AK1

+VCCAFDI_VRM

AF11

AC16 AC17 AD17

1D05V_S0

T21

V21

T19

P32

1D05V_S0

12

C2402

C2402 SC1U10V2KX-1GP

SC1U10V2KX-1GP

3D3V_S5

12

C2407

C2407 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+V5A_PCH_VCC5REFSUS

+V5S_PCH_VCC5REF

3D3V_S5

12

C2417

C2417 SC1U10V2KX-1GP

SC1U10V2KX-1GP

SCD1U10V2KX-4GP

12

C2418

12

C2423

SC1U10V2KX-1GP

1D05V_S0

12

C2428

SC1U10V2KX-1GP

12

C2438

C2438 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

2

.925A

3D3V_S5

1D05V_S0

12

DY

SCD1U10V2KX-4GP

12

3D3V_S5

12

C2415

3D3V_S0

C2419

97mA

C2406

C2406 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

3D3V_S5

AK

D2401

83.R0304.D8F

CH751H-40-1-GP

2ND = 83.R2004.C8F

2ND = 83.R2004.C8F 3RD = 83.1PS76.01F

3RD = 83.1PS76.01F

12

C2409

C2409 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC1U10V2KX-1GP

2ND = 83.R2004.C8F

2ND = 83.R2004.C8F 3RD = 83.1PS76.01F

3RD = 83.1PS76.01F

20120201PV-R

266mA

3D3V_S0

12

C2422

C2422 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D05V_S0

1 2

12

C2425

C2425 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

DY

10mA

D

5V_S5

1mA

12

R2402

R2402 10R2J-2-GP

10R2J-2-GP

20120201PV-R

3D3V_S0

5V_S0

83.R0304.D8F

DY

IND-10UH-193-GP

AK

CH751H-40-1-GP

12

L2404

Title

Size Document Number Rev

A3

Date: Sheet of

Date: Sheet

1mA

12

D2402

R2403

R2403 10R2J-2-GP

10R2J-2-GP

C2416

C2416 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1D05V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH(8/9) : PWR2

2012 S-Series Richie 13.3

E

-1

of

24 103Wednesday, March 14, 2012

-1

A

PCH1I

AY4

VSS159

AY42

VSS160

AY46

VSS161

AY8

VSS162

B11

VSS163

B15

VSS164

B19

VSS165

B23

VSS166

B27

VSS167

4 4

3 3

2 2

1 1

A

B31 B35 B39

F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38

BB4 BB46 BC14 BC18

BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46

BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28

BD3 BF30 BF38 BF40

BF8 BG17 BG21 BG33 BG44

BG8 BH11 BH15 BH17 BH19

H10 BH27 BH31 BH33 BH35 BH39 BH43

BH7

D12

D16

D18

D22

D24

D26

D30

D32

D34

D38

D42

E18

E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34

B7

D3

D8

F3

VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258

PANTHER-GP-NF

B

9 OF 10

VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS328 VSS329 VSS330 VSS331 VSS333 VSS334 VSS335 VSS337 VSS338 VSS340 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352

B

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

C

PCH(9/9)

C

AA17

AA2

AA3 AA33 AA34 AB11 AB14 AB39

AB4 AB43

AB5

AB7 AC19

AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39

AD4 AD40 AD42 AD43 AD45 AD46

AD8 AE2

AE3 AF10 AF12

AD14 AD16

AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38

AF4 AF42 AF46

AF5

AF7

AF8

AG19

AG2 AG31 AG48 AH11

AH3 AH36 AH39 AH40 AH42 AH46

AH7

AJ19 AJ21 AJ24 AJ33 AJ34

AK12

AK3

H5

PCH1H

VSS0 VSS1

VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79

PANTHER-GP-NF

D

8 OF 10

VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158

D

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

E

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

PCH(9/9) : GND

2012 S-Series Richie 13.3

25 103Wednesday, March 14, 2012

E

-1

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

PCH_XDP

2012 S-Series Richie 13.3

26 103Wednesday, March 14, 2012

1

-1

5

R2721 0R2J-2-GP

1 2

DY

SPI_CS1#17,71

3D3V_AUX_S5

RN2701

8 7 6

D D

SRN4K7J-10-GP

SRN4K7J-10-GP RN2702

RN2702

8 7 6

SRN4K7J-10-GP

R2735

1 2

10KR2J-3-GP

C C

KBC_AGND

3D3V_AUX_KBC

R2751 100KR2J-1-GPR2751 100KR2J-1-GP

PWR_BTN_OUT#19

B B

KBC_AGND

0R0402-PAD

1 2 3 45

DY

1 2

KSO1782,97

R2715

KSI1 KSI2 KSI3 KSI0

KSI7 KSI6 KSI4 KSI5

KSO5

VOLTAGE_ADC_R

C2709SC2200P50V2KX-2GP C2709SC2200P50V2KX-2GP

12

CURRENT_ADC_L

C2710SC2200P50V2KX-2GP C2710SC2200P50V2KX-2GP

12

OCP_IN_ADC_L

C2711SC2200P50V2KX-2GP C2711SC2200P50V2KX-2GP

12

ADC_VREF_L

C2712SC100P50V2JN-3GP C2712SC100P50V2JN-3GP

12

ADP_ID_ADC_L

C2713SC2200P50V2KX-2GP C2713SC2200P50V2KX-2GP

12

R2744 0R0402-PADR2744 0R0402-PAD

KBC_AGND

SCD1U16V2ZY-2GP

3D3V_AUX_S5

ADC_VREF38 ADP_A_ID38

12

KSO15

1 2

C2714

RUNSCI_EC#22 KBC_GPIO5141

SUSCLK32_KBC19

DY

ADP_EN40

OCP_A_IN38

CURRENT_ADC38

TPAD14-OP-GP

WWAN_OFF54 IMDAT31

ADP_DET40 WLAN_OFF53 SPI_CLK_FLH60

MAIN_BAT_DET#39,97

KSO[0..15]69,97

20120112 PV-R

KSI[0..7]69,82,97

1 2

R2706 10R2J-2-GPR2706 10R2J-2-GP

1 2 1 2

R2708

LPC_AD[3:0]17,71

LPC_FRAME#17,71

LPC_RESET#22 CLK_PCI_KBC21,97 PM_CLKRUN#19

SIRQ17,71

OCP_PW M_OUT38

1 2

R2717 0R0402-PADR2717 0R0402-PAD

300R2J-4-GP

SPI_CS1#_R

20120112 PV-R

R2726 0R0402-PADR2726 0R0402-PAD

1 2

R2728 300R2J-4-GPR2728 300R2J-4-GP

1 2

R2729 300R2J-4-GPR2729 300R2J-4-GP

1 2

TP2709

1 2 1 2

TP2708TPAD14-OP-GPTP2708TPAD14-OP-GP

PWR_BTN_OUT#_KBC

IMCLK31

PM_SLP_S4#_KBC

ADC_VREF_L ADP_ID_ADC_L

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

SUSCLK32_KBC_IN

20120112 PV-R

A A

PM_SLP_S3#8,19,29,34,35,36,37,45,46,47,48,92,93

PM_SLP_S4#_KBC46

5

4

1

R2730 0R0402-PADR2730 0R0402-PAD R2731 0R0402-PADR2731 0R0402-PAD

KBC_GPIO36

1

U2701

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

KSO17 KSI0

KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

108

R2732

R2732 20KR2J-L2-GP

20KR2J-L2-GP

DY_DS3

1 2

21 20 19 18 17 16 13 12 10

9 8 7 6

5 81 83

4

29 28 27 26 25 24 23 22

35 36 38 40 41 42

46 48 50 51 52 53 54 55 57 59

45 76

70 71

4

SPI_SI_FLASH60 CHG_RST40 SPI_CS0#_FLASH60

SPI_SO_FLASH60 QUICKX_LED#82,97

R2747 4K7R2J-2-GPR2747 4K7R2J-2-GP

1 2

LID_SW#49,82,97

ADP_EN_L OCP_IN_ADC_L

CURRENT_ADC_L KBC_GPIO37

SPI_CS1#_R ADP_DET_R

1

2

30

3

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12/GPIO0/KBRST KSO13/GPIO18 GPIO4/KSO14 GPIO5/KSO15 GPIO24/KSO16 GPIO26/KSO17

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

IMCLK VSS ADC4/GPIO50 AVCC ADC_VREF ADC2/GPIO40

LAD0 LAD1 LAD2 LAD3 LFRAME# LRESET# PCI_CLK CLKRUN# SER_IRQ ADC_TO_PWM_OUT/GPIO19

AVSS EC_SCI#

PWMOK_PWMDEAD#_CKT#2/GPIO51 32KHZ_INPUT

FLCLK

HSTCLK/GPIO41

ALARM_CKT#2/GPIO36

3D3V_AUX_KBC

44

31

43

34

32

62

KDAT

IMDAT

GPIO39

GPIO3833GPIO37

ADC1/GPIO46

ADC_TO_PWM_IN

AC_CKT#2/GPIO42

KBC1126-NU-GP

72

300R2J-4-GP

KCB_GPIO33

+VCC0

94

127

64

65

66

67

EMCLK

GPIO3563GPIO34

Q/GPIO33

128

96

95

97

EMDAT

FLCS0#

FLDATAIN

FLDATAOUT

HSTCS0#/GPIO44

HSTDATAIN/GPIO43

HSTDATAOUT/GPIO45

PM_PWROK DELAY 99ms

71.01126.00G

VSS

GPIO52/PWM3

TP_LED#

VSS82VSS56VSS47VCC137VSS

11

TP2707 TPAD14-OP-GPTP2707 TPAD14-OP-GP

1

117

104

3

3D3V_AUX_KBC

R2722

1 2

VOLTAGE_ADC_R

39

84

VCC068VCC158VCC1

VCC114VCC1

ADC3/GPIO23

ADP_PRES_CKT#2/GPIO27

CAP

15

KBC_CAP

SC4D7U6D3V3KX-GP

3

R2701

1 2

0R0603-PAD-1-GP

12

C2703

SC4D7U10V5ZY-3GP

1070_VCC2

12

119

106

49

VCC1

VCC2

OUT0/SCI GPIO53/AB3_DATA CFETA/OUT7/SMI#

OUT8/KBRST

OUT9/TACH2PWM_OUT

OUT10/PWM0

CHRGCTL_PWM/OUT11

GPIO1

VREF_PECI

GPIO3/PECI_DATA

RESET_OUT#/GPIO6

OUT1/RSMRST#

GPIO8/RXD

GPIO9/TXD

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK

GPIO15/FAN_TACH1

GPIO16/TACH2PWM_IN

GPIO17/A20M

KCLK GPIO20/PS2CLK GPIO21/PS2DAT

32KHZ_OUT/GPIO22

GPIO25

GPIO28 GPIO29/BC_CLK GPIO30/BC_DAT

GPIO31/BC_INT#

GPIO32/AB3_CLK

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

TEST_PIN

PWRGD

VCC1_RST#

CFETB/GPIO10

BAT_LED#

PWR_LED#/8051TX

FDD_LED#/8051RX

C2715

1 2

8051TX/S3_LED#

VOLTAGE_ADC 38

3D3V_AUX_S5

20111117PV 20111122PV 20120116PV-R

12

C2705

C2706

SCD1U16V2ZY-2GP

20120112 PV-R

R2702

1 2

0R0402-PAD

C2708

C2708 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

124 125

FET_A

123

KBRST#_L

122 121 120

PWM_LED#

118

CPPWR_EN

107

VREF_PECI

79

EC_PECI

80

PGD_IN

60

RSMRST#_R

85

GPIO8/RXD

86

PLT_DET

87

88 89 90 91

KBC_GPIO15

92

TACH_FAN_IN_R

101

GPIO17

102 61 103 105

KBC_DDR_RST#

75 73 74 93 98 99 100 126

111 112 109 110

1070_TEST

69 78

VCC1_POR#

77

FET_B

116 113 115 114

20120210PV-R

U2702

1

DY

A1

2

GND A23Y2

NC7WZ07P6X-1GP

73.7WZ07.0AJ

12

C2704

C2707

SCD1U16V2ZY-2GP

3D3V_S0

83.R0304.D8F2ND = 83.R2004.C8F 3RD = 83.1PS76.01F

D2701 CH751H-40-1-GP

R2737 0R0402-PADR2737 0R0402-PAD

1 2

R2738 43R2J-GPR2738 43R2J-GP

1 2

R2741 0R0402-PADR2741 0R0402-PAD

1 2

R2742 10KR2J-3-GPR2742 10KR2J-3-GP

1 2

PLT_DET 21,69

1 2

DY

R2704 0R2J-2-GP

R2714 1KR2J-1-GPR2714 1KR2J-1-GP

1 2

PWR_BD_LED#

6

Y1

5

VCC

KB_CAPS_LED8051RX/CAPS_LED

4

2

C2702

12

DY

3D3V_AUX_KBC

2

1

20120131PVR

1D05V_S0

H_PECI 5,22 PM_PWROK 19,97 RSMRST# 19,41,97

R2739

1 2

R2736

20120112 PV-R

R2703

1 2

0R0402-PAD

SC1U10V2KX-1GP

KBC_DDR_RST#

20120201PV-R

KBC PIN

KBRST#_L

122

8051TX/S3_LED#

15

1

8051RX/CAPS_LED

114

KBC_GPIO15

92

AMBER_BATLED#

113

KBC_PW R_ON

100

GPIO8/RXD

86

8051_RECOVER#

83

VCC1_POR#

77

ADP_EN_L

63 61

CHG_RST

127

FET_A

123

RSMRST#_R

85

PGD_IN

60

PWR_GOOD

78

KBC_DDR_RST#

75

FET_B

116

0R2J-2-GP

Keyboard Matrix: hi and low for 15"&17"

PWR_BD_LED# 82 8051TX/S3_LED# 71 8051RX/CAPS_LED 71 KB_CAPS_LED 69,97

+VCC0 RTC_AUX_S5

C2701

SCD1U10V2KX-4GP

1 2

DY

D2703

3

BAV99-5-GP-U

83.00099.T11

83.00099.T11 2nd = 83.BAV99.D11

2nd = 83.BAV99.D11 3rd = 83.BAV99.H11

3rd = 83.BAV99.H11

NMI_SMI_DBG# 21,71 CHARGER_DAT 40

KBRST# 22,97 FAN_PW M 28 BAT_GRNLED# 17,82

TP2703TPAD14-OP-GPTP2703TPAD14-OP-GP TP2704TPAD14-OP-GPTP2704TPAD14-OP-GP

AK

0R2J-2-GP

SCD1U16V2ZY-2GP

1 1

R2725

VOLTAGE_ADC

20120112 PV-R

PCH_KBC_DATA 18,28,85 PCH_KBC_CLK 18,28,85 KBC_PROCHOT 5 A_SD# 29

GATEA20 22

8051_RECOVER# 71 PM_SLP_S3# 8,19,29,34,35,36,37,45,46,47,48,92,93

KBC_DDR_RST# 5,46

ON/OFFBTN_KBC# 82 ADP_PRES 34,38 PM_SLP_A# 19 SUS_PW R_ACK 19 ADP_PRES_OUT 19,85 KBC_PW R_ON 41

CHARGER_CLK 40

AB1A_DATA 39,97 AB1A_CLK 39,97

PWR_GOOD 5,37,42,50,96 VCC1_POR# 71

AMBER_BATLED# 82

20120210PV-R

D2702

KBC_SMSC_KBC1126

12

C2716

C2716 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

2

3D3V_AUX_S5

TACH_FAN_IN28

20120201PV-R

Title

Size Document Number Rev

A3

Date: Sheet of

1

3D3V_AUX_S5

12

R2727

gh for 13"&14"

PLT_DET

R2724 10KR2J-3-GP

AK

CH751H-40-1-GP

83.R0304.D8F

83.R0304.D8F 2ND = 83.R2004.C8F

2ND = 83.R2004.C8F 3RD = 83.1PS76.01F

3RD = 83.1PS76.01F

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

2012 S-Series Richie 13.3

R2727 10KR2J-3-GP

10KR2J-3-GP

DY

1 2

DY

3D3V_AUX_S5

R2734 10KR2J-3-GP

1 2

DY

1

4

2 3

RN2703

RN2703 SRN100KJ-6-GP

SRN100KJ-6-GP

R2716 22KR2J-GPR2716 22KR2J-GP

1 2

R2748 100KR2J-1-GPR2748 100KR2J-1-GP

1 2

R2746 100KR2J-1-GPR2746 100KR2J-1-GP

1 2

R2723 10KR2J-3-GP

1 2

DY

R2720 100KR2J-1-GPR2720 100KR2J-1-GP

1 2

R2733 10KR2J-3-GPR2733 10KR2J-3-GP

1 2

R2705 10KR2J-3-GPR2705 10KR2J-3-GP

1 2

R2707 10KR2J-3-GPR2707 10KR2J-3-GP

1 2

R2709 100KR2J-1-GPR2709 100KR2J-1-GP

1 2

R2710 10KR2J-3-GPR2710 10KR2J-3-GP

1 2

R2711 10KR2J-3-GPR2711 10KR2J-3-GP

1 2

R2712 10KR2J-3-GP

1 2

DY

R2713 22KR2J-GP

1 2

DY_DS3

R2719 100KR2J-1-GPR2719 100KR2J-1-GP

1 2

3D3V_S0

12

R2718

R2718 10KR2J-3-GP

10KR2J-3-GP

TACH_FAN_IN_R

27 103Wednesday, March 14, 2012

1

3D3V_S5

-1

5

4

3

2

1

4 WIRE PWM Fan Control circuit

D D

KBC control signal is LOW , Fan ON

FAN_PW M27

C C

THERM#

NAND gate

U2802

B1VCC

2

A

3

GND

74AHCT1G00GW-GP

73.01G00.0BG

1st = 73.01G00.01G

1st = 73.01G00.01G 2nd = 73.7SET0.0BG

2nd = 73.7SET0.0BG 3rd = 73.01G00.0BG

3rd = 73.01G00.0BG

A BLY

L

H

LLH

H

L

H

FAN PWM LEVEL = 5V

5V_S0 5V_S0_FAN

5 4

Y

C2801

5V_S0_FAN FAN_PW M_Y TACH_FAN_IN_C GND

FAN_PW M_Y

TACH_FAN_IN27

12

SC47P50V2JN-3GP

DY

AFTP2801 AFTE14P-GPAFTP2801 AFTE14P-GP

1

AFTP2802 AFTE14P-GPAFTP2802 AFTE14P-GP

1

AFTP2803 AFTE14P-GPAFTP2803 AFTE14P-GP

1

AFTP2804 AFTE14P-GPAFTP2804 AFTE14P-GP

1

20mil

5V_S0

0R0402-PAD

R2802

1 2

0R0402-PAD

20120112 PV-R

R2801

12

TACH_FAN_IN_C

20110906SI

PMBS3904-3-GP

20120116PV-R

56

FAN1

1

ACES-CON4-19-GP

2

20.F1637.004

3

2nd = 20.F1808.004

4

3rd = 20.F1579.004

Cap closed to Q2801

C

Q2801

E

84.S3904.011

84.S3904.011 2nd = 84.03904.X11

2nd = 84.03904.X11

12

B

Meter_SMBDATA65 Meter_SMBCLK65

C2803

C2803 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

20120116PV-R

RN

RN2802

1

4

2 3

0R4P2R-PAD

Thermal IC Control circuit

R2803

2K2R2J-2-GP

DXP1 DXN1 THERM#

3D3V_S0 3D3V_S0

1

23

RN2801

RN2801 SRN2K2J-1-GP

SRN2K2J-1-GP

4

THERM_SDA

THERM_SCL

3D3V_S0

12

C2802

C2802 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

U2801

1

VCC

2

DXP

SMBDATA

3

DXN THERM#4GND

G781P8F-GP

U2803

1

6

2

5

3 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.2N702.E3F

2nd = 84.2N702.E3F 3rd = 84.2N702.F3F

3rd = 84.2N702.F3F

12

R2804

R2804 10KR2J-3-GP

10KR2J-3-GP

THERM_SCL

8

SMBCLK

ALERT#

THERM_SDA

7 6 5

PCH_KBC_DATA 18,27,85

PCH_KBC_CLK 18,27,85

THERM_SCI# 22

B B

T8 H/W Shutdown Control circuit

Degree Rset

95

90

85

A A

Layout: PUT U2805 Bottom side and close CPU PUT R2806 Close U2806

25.5K

22.1K

U2805

R2806

18.7K

AMB_TEMP_SD#41

5

R2806

22K1R2F-L-GP

1 2

4

U2804_SET U2804_VCC

U2805

1

SET

2

GND OUT#3HYST

G709T1UF-GP

74.00709.A7F

74.00709.A7F 2nd = 74.00709.0BF

2nd = 74.00709.0BF

VCC

5 4

12

C2806

U2804_HYST

SCD1U10V2KX-5GP

R2813

R2813 0R0402-PAD

0R0402-PAD

20120112 PV-R

1 2

3

R2811

1 2

150R2F-1-GP

3D3V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ze Document Number Rev

Size Document Number Rev

Si

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Thermal G781 / FAN

2012 S-Series Richie 13.3

28 103Wednesday, March 14, 2012

1

-1

5

D D

3D3V_S0

Close to codec

12

C2904

SCD1U10V2KX-4GP

R2922

10KR2J-3-GP

D2901

20110904SI

12

DY

3D3V_S0

12

AK

12

C2902

C2924

HDA_BITCLK_CODEC17,97

HDA_SDIN0_CODEC17

SCD1U10V2KX-4GP

HDA_SDOUT_CODEC17,97 HDA_SYNC_CODEC17 HDA_RST#_CODEC17,97

DMIC_CLK49,97 DMIC_DATA49,97

A_SD#_R

SCD1U10V2KX-4GP

R2920 100R2J-2-GPR2920 100R2J-2-GP R2921 0R2J-2-GPR2921 0R2J-2-GP

DMIC_CLK_R97 DMIC_DATA_R97

SC4D7U6D3V3KX-GP

12

C2903

SC1U10V2KX-1GP

from KBC

C C

20120201PV-R

B B

A_SD#27

2ND = 83.R2004.C8F

2ND = 83.R2004.C8F 3RD = 83.1PS76.01F

3RD = 83.1PS76.01F

3D3V_S0

R2926

R2926 4K7R2J-2-GP

4K7R2J-2-GP

1 2

HDA_RST#_CODEC

12

C2928

C2928 SC820P50V2KX-1GP

SC820P50V2KX-1GP

CH751H-40-1-GP

83.R0304.D8F

4

Close to codec

R2901

1 2

33R2J-2-GP

20120116PV-R

20120112 PV-R

1 2 1 2

C2914

1 2

AUD_DVDDCORE

12

C2901

C2901 SC10U10V5KX-2GP

SC10U10V5KX-2GP

HDA_BITCLK_CODEC HDA_CODEC_SDIN0 HDA_SDOUT_CODEC HDA_SYNC_CODEC HDA_RST#_CODEC

DMIC_CLK_RDMIC_CLK_R DMIC_DATA_R

PUMP_CAPP

PUMP_CAPN

AUD_AGND

U2901

1

DVDD_LV

7

DVDD

5

BITCLK

6

SDATA_IN

4

SDATA_OUT

8

SYNC

9

RESET#

2

DMIC_CLK/GPIO1

3

DMIC_0/GPIO2

40

EAPD

!! Notice PORTD_-R/+R

29

CAP-

30

CAP+

24

AVSS2

27

AVSS2

36

PVSS

41

GND

92HD87B2X5NDGXRAX-GP-U1

3

20120112 PV-R

AVDD1 AVDD2

PVDD PVDD

SENSE_A SENSE_B

PORTA_L PORTA_R

VREFOUT_A

PORTB_L PORTB_R

PORTC_L

PORTC_R

VREFOUT_C

PORTD_-L

PORTD_+L

PORTD_-R

PORTD_+R

PORTF_L PORTF_R

PCBEEP

CAP2

VREFFILT

V-

VREG/+2_5V

71.92H87.C03

21 32

39 33

AUD_SENSE_A

11

AUD_SENSE_B

12

22 23 19

25 26

15 16 20

35 34

37 38

13 14

10

18 17 28 31

AVDD_CODEC

AUDIO_AVDD

L2901

1 2

MCB1608S300IBP-GP

68.00909.191

12

C2906

C2905

SCD1U10V2KX-4GP

AUD_AGND

AUD_EXT_MIC_L AUD_EXT_MIC_R AUD_VREFOUT_B

AUD_SPK_LAUD_SPK_L+

AUD_SPK_RAUD_SPK_R+

AUD_PC_BEEP

AUD_CAP2 AUD_VREFFLT AUD_V_B AUD_VREG AUD_V_B

68.00909.191

2nd = 68.00217.B11

SC1U10V2KX-1GP

12

C2909

C2908

SCD1U10V2KX-4GP

AUD_AGND

C2922 SC1U10V2KX-1GPC2922 SC1U10V2KX-1GP C2921 SC1U10V2KX-1GPC2921 SC1U10V2KX-1GP

12 12

AUD_SPK_L- 31

AUD_SPK_L+ 31

AUD_SPK_R- 31

AUD_SPK_R+ 31

AUD_CAP2 AUD_VREFFLT

AUD_VREG

2

20120112 PV-R

5V_S0

10KR2J-3-GP

R2905

12

5V_S0

12

C2910

SC1U10V2KX-1GP

SC10U10V5KX-2GP

HP_OUT_L 31,97

HP_OUT_R 31,97 MICL 30

MICR 30 AUD_VREFOUT_B 30

12

AUD_AGND AUD_AGND AUD_AGND AUD_AGND

12

C2917

SC4D7U6D3V3KX-GP

DY

AVDD_CODEC_EN

12

C2907

C2907 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C2918

SC4D7U6D3V3KX-GP

12

R2906

R2906 0R0402-PAD

0R0402-PAD

12

Close to codec

PM_SLP_S3# 8,19,27,34,35,36,37,45,46,47,48,92,93

Vout = 1.25(1+R1/R2)

Q2902

4 5

OUT

SCD01U16V2KX-3GP

AUD_SENSE_B

AUD_AGND

C2915

SC10U10V5KX-2GP

EN3NR

2

GND

1

IN

HPA01085DBVR-GP

74.01085.03F

12

C2916

SCD1U10V2KX-4GP

Close to Pin14

1

Vout = 4.75 V

AVDD_CODEC

TPS793475_NR

12

C2911

AUD_AGND

AVDD_CODEC

12

R2927

R2927 100KR2J-1-GP

100KR2J-1-GP

1 2

SC2D2U6D3V3KX-GP

C2912

Digital GND & AUD_AGND

Tie Analog GND and Digital GND under codec by a single point

G2901 GAP-CLOSE-PWR-3-GPG2901 GAP-CLOSE-PWR-3-GP

1 2

G2902 GAP-CLOSE-PWR-3-GPG2902 GAP-CLOSE-PWR-3-GP

1 2

G2903 GAP-CLOSE-PWR-3-GPG2903 GAP-CLOSE-PWR-3-GP

1 2

A A

audio ground must be connect to digital ground with an 80 mil copper bridge located directly under codec

AUD_AGND

HDA_SPKR17

AVDD_CODEC

R2924

10KR2J-3-GP

PC BEEP

12

MONO_L AUD_PC_BEEPMONO_L_0

D

G

AUD_AGND

12

C2927

C2927 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

Q2901

Q2901 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

84.2N702.J31 2nd = 84.07002.I31

2nd = 84.07002.I31 3rd = 84.2N702.W31

3rd = 84.2N702.W31

S

1 2

MONO_L_1

R2923

R2923 100KR2J-1-GP

100KR2J-1-GP

R2925

10KR2J-3-GP

12

AUD_AGND

12

C2925

C2925 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

C2926

C2926 SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

AUD_SENSE_A

to prevent ESD latch up.

5

4

3

2

AVDD_CODEC

12

R2915

R2915 2K49R2F-GP

2K49R2F-GP

12

C2919

C2919 SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

AUD_AGND

Close to Pin13

R2913 20KR2F-L-GPR2913 20KR2F-L-GP

1 2

R2919 10KR2F-2-GPR2919 10KR2F-2-GP

1 2

Title

Audio Codec 92HD87B2X5

ze Document Number Rev

Size Document Number Rev

Si

Date: Sheet of

Audio Codec 92HD87B2X5

A3

2012 S-Series Richie 13.3

HP_DETECT# 31,97

MIC_DETECT# 31,97

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

29 103Wednesday, March 14, 2012

1

-1

5

4

3

2

1

Pre-AMP. for External MIC

D D

CODEC_VREF_EQ

100KR2J-1-GP

100KR2J-1-GP R3004

R3004

1 2

C3006

C3001

SC1U10V2KX-1GP

12

R3001

R3001 3K9R2F-GP

3K9R2F-GP

EXT_MICL_1

1 2

AUD_VREFOUT_B29 AUD_VREFOUT_B29

C C

L3001

MIC_IN_L31,97

SC220P50V2KX-3GP

1 2

MCB1005S601FBP-GP-U

68.00213.011

68.00213.011 2nd = 68.00217.601

2nd = 68.00217.601

12

C3002

3rd = 68.00225.121

AUD_AGND

20120112 PV-R

EXT_MICL

C3003

C3003 SCD47U10V2KX-GP

SCD47U10V2KX-GP

R3002

0R0402-PAD

SC100P50V2JN-3GP

EXT_MICL_R

12

1 2

AUD_AGND

C3005

R3003

1 2

10KR2J-3-GP

C3004

C3004 SC68P50V2JN-1GP

SC68P50V2JN-1GP

12

C3006 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

EXT_MIC_1IN-

AUD_AGND

1 2 3

MICL 29

U3001

VDD

OUTB

INB-

8 7 6 5

OUTA INAINA+ VSS4INB+

G1224P8U-1-GP

74.G1224.019

2nd = 74.02462.019

AVDD_CODEC

EXT_MIC_2IN-

100KR2J-1-GP R3005

R3005

1 2

C3008

C3008 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

CODEC_VREF_EQ

12

C3009

C3009 SC100P50V2JN-3GP

SC100P50V2JN-3GP

12

R3006

10KR2J-3-GP

AUD_AGND AUD_AGND

MICR 29

20120112 PV-R

R3007

1 2

0R0402-PAD

C3011

C3011 SC68P50V2JN-1GP

SC68P50V2JN-1GP

1 2

R3007

EXT_MICR

12

C3012

SCD47U10V2KX-GP

EXT_MICR_R EXT_MICR_1

12

R3008

R3008 3K9R2F-GP

3K9R2F-GP

L3002

1 2

MCB1005S601FBP-GP-U

68.00213.011

2nd = 68.00217.601

2nd = 68.00217.601 3rd = 68.00225.121

3rd = 68.00225.121

12

C3013

C3013 SC220P50V2KX-3GP

SC220P50V2KX-3GP

MIC_IN_R 31,97

CODEC_VREF_EQAVDD_CODEC

12

R3009

R3009 47KR2J-2-GP

B B

C3014

SCD1U10V2KX-4GP

A A

5

4

47KR2J-2-GP

12

R3010

12

47KR2J-2-GP

AUD_AGND

C3015

SC4D7U6D3V3KX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ze Document Number Rev

Size Document Number Rev

Si

A3

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

External MIC_Pre-Amp

2012 S-Series Richie 13.3

30 103Wednesday, March 14, 2012

1

-1