Winbond Electronics W24L11T-70L, W24L11T-70LL, W24L11S-70LL, W24L11S-70L, W24L11Q-70LL Datasheet
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Preliminary W24L11
1
V
CS2
DD
CS1
WE
OE
128K × 8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24L11 is a normal-speed, very low-power CMOS static RAM organized as 131072 × 8 bits that
operates on a wide voltage range from 3.0V to 3.6V power supply. This device is manufactured using
Winbond's high performance CMOS technology.
FEATURES
•
Low power consumption:
− Active: 144 mW (max.)
•
Access time: 70 nS
•
Single 3.3V power supply
•
Fully static operation
•
All inputs and outputs directly TTL compatible
PIN CONFIGURATIONS BLOCK DIAGRAM
V
32-pin
32
DD
31
A15
30
CS2
29
WE
28
A13
A8
27
A9
26
A11
25
OE
24
23
A10
22
CS1
21
I/O8
20
I/O7
I/O6
19
18
I/O5
17
I/O4
32
31
30
29
I/O8
28
27
26
25
V
24
SS
23
22
21
20
19
18
17
1
NC
A16
2
A14
3
4
A12
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O1
13
I/O2
14
I/O3
15
V
SS
16
A11
A9
A8
A13
WE
A15
NC
A16
A14
A12
A7
A6
A5
A4
•
Three-state outputs
•
Battery back-up operation capability
•
Data retention voltage: 2V (min.)
•
Packaged in 600 mil DIP, 450 mil SOP,
standard type one, TSOP (8 mm × 20 mm) ,
small type one and TSOP (8 mm × 13.4 mm)
PRECHARGE CKT.
A16
A14
A4
A3
A7
A6
A9
I/O1
:
WE
CS1
OE
A13 A1A0A10
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0−A16
I/O1−I/O8
, CS2
VDD Power Supply
VSS Ground
NC No Connection
Address Inputs
Data Inputs/Outputs
Chip Select Input
Write Enable Input
Output Enable Input
Publication Release Date: October 1999
- 1 - Revision A1
TRUTH TABLE
CS1
OE WE
WE
Preliminary W24L11
CS2
H X X X Not Selected High Z ISB, I
X L X X Not Selected High Z ISB, I
MODE
I/O1−I/O8
VDD CURRENT
SB1
SB1
L H H H Output Disable High Z IDD
L H L H Read Data Out IDD
L H X L Write Data In IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to VSS Potential -0.5 to +4.6 V
Input/Output to V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150
Operating Temperature 0 to 70
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
SS
Potential -0.5 to VDD +0.5 V
°C
°C
Operating Characteristics
(VDD = 3.0V to 3.6V; VSS = 0V; TA (°C) = 0 to 70)
PARAMETER SYM. TEST CONDITIONS MIN. MAX. UNIT
Input Low Voltage VIL - -0.5 +0.6 V
Input High Voltage V
Input Leakage Current I
Output Leakage Current I
Output Low Voltage VOL IOL = +2.1 mA - 0.4 V
Output High Voltage V
Operating Power Supply
Current
IH
VIN = VSS to VDD -1 +1
LI
VI/O = VSS to VDD,
LO
CS1 = V
CS2 = VIL (max.) or
OE
OH IOH
I
DD
CS1
CS2 = VIH (min.), I/O = 0 mA,
Cycle = min. Duty = 100%
(min.) or
IH
= VIH (min.) or
= VIL (max.)
= -1.0 mA 2.2 - V
= VIL (max.) and
- +2.0 VDD +0.5 V
-1
-
+1
40
- 2 -
A
µ
A
µ
mA
Preliminary W24L11
Operating Characteristics, continued
PARAMETER SYM. TEST CONDITIONS MIN. MAX. UNIT
Standby Power Supply
Current
I
SB
= VIH (min.) or
CS1
CS2 = VIL (max.)
Cycle = min. Duty = 100%
Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 3.3V
ISB1
CS1
VDD -0.2V or
≥
CS2 ≤ 0.2V
LL - 50 µ
L - 100
CAPACITANCE
(VDD = 3.3 V, TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF
Input/Output Capacitance C
Note: These parameters are sampled but not 100% tested.
I/O
V
OUT
= 0V 8 pF
-
1
mA
A
AC characteristics
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load See the drawing below
AC Test Loads and Waveform
OUTPUT
1 TTL
100 pF
Including
Jig and
Scope
3.0 V
0 V
5 nS
OUTPUT
5 pF
Including
Jig and
Scope
(For T T T T T T )
90%
10%
CLZ, OLZ,
90%
10%
5 nS
OHZ, WHZ, OW
CHZ,
1 TTL
Publication Release Date: October 1999
- 3 - Revision A1
Preliminary W24L11
CS1
AC Characteristics, continued
(VDD = 3.0V to 3.6 V; VSS = 0V; TA (°C) = 0 to 70)
Read Cycle
PARAMETER SYMBOL W24L11-70L/LL UNIT
MIN. MAX.
Read Cycle Time TRC 70 - nS
Address Access Time TAA - 70 nS
Chip Select Access Time T
Output Enable to Output Valid T
Chip Selection to Output in Low Z T
Output Enable to Output in Low Z T
Chip Deselection to Output in High Z T
Output Disable to Output in High Z T
Output Hold from Address Change TOH 10 - nS
These parameters are sampled but not 100% tested
∗
ACS
- 70 nS
AOE
- 35 nS
CLZ
* 10 - nS
OLZ
* 5 - nS
CHZ
* - 30 nS
OHZ
* - 30 nS
Write Cycle
PARAMETER SYMBOL W24L11-70L/LL UNIT
MIN. MAX.
Write Cycle Time TWC 70 - nS
Chip Selection to End of Write TCW 55 - nS
Address Valid to End of Write TAW 55 - nS
Address Setup Time TAS 0 - nS
Write Pulse Width TWP 50 - nS
Write Recovery Time
, CS2, WE
TWR 0 - nS
Data Valid to End of Write TDW 45 - nS
Data Hold from End of Write TDH 0 - nS
Write to Output in High Z T
Output Disable to Output in High Z T
WHZ
* - 25 nS
OHZ
* - 25 nS
Output Active from End of Write TOW 5 - nS
These parameters are sampled but not 100% tested
∗
- 4 -
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