winbond W78C51C User Manual

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W78C51C

8-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W78C51C microcontroller supplies a wider frequency range than most 8-bit microcontrollers on
the market. It is compatible with the industry standard 80C51 microcontroller series.

The W78C51C contains four 8-bit bidirectional parallel ports, two 16-bit timer/counters, and a serial
port. These peripherals are supported by a five-source, two-level interrupt capability. There are 128
bytes of RAM and an 4K byte mask ROM for application programs.

The W78C51C microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

FEATURES

• 8-bit CMOS microcontroller

• Fully static design

• Low standby current at full supply voltage

• DC-40 MHz operation

• 128 bytes of on-chip scratchpad RAM

• 4K bytes of on-chip mask ROM

• 64K bytes program memory address space

• 64K bytes data memory address space

• Four 8-bit bidirectional ports

• Two 16-bit timer/counters

• One full duplex serial port

• Boolean processor

• Five-source, two-level interrupt capability

• Built-in power management

• Code protection

• Packages:

− DIP 40: W78C51C-16/24/40

− PLCC 44: W78C51CP-16/24/40

− QFP 44: W78C51CF-16/24/40

− TQFP 44: W78C51CM-16/24/40

Publication Release Date: October 1997

- 1 - Revision A3

PIN CONFIGURATIONS

40-Pin DIP (W78C51C)

W78C51C

44-Pin PLCC (W78C51CP)

P

P

P

P

P

1

1

1

1

1

.

.

P1.5
P1.6
P1.7

RST

RXD, P3.0

TXD, P3.1
INT0, P3.2
INT1, P3.3

T0, P3.4
T1, P3.5

NC

.
4

6 5 4 3

7
8
9
10
11
12
13
14
15
16
17

P
3
.
6
,
/
W
R

3

P
3
.
7
,
/
R
D

.

2

1

X

X

T

T

A

A

L

L

1

2

.
0

2 1 44 43 42

V
S
S

P1.0
P1.1

P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

RST
RXD, P3.0
TXD, P3.1

INT0, P3.2
INT1, P3.3

T0, P3.4
T1, P3.5

WR, P3.6

RD, P3.7

XTAL2
XTAL1

VSS

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

VCC1

40
39

P0.0, AD0

P0.1, AD1

38
37

P0.2, AD2
P0.3, AD3

36
35

P0.4, AD4

34

P0.5, AD5

33

P0.6, AD6

32

P0.7, AD7

31

EA

30

ALE

29

PSEN

28

P2.7, A15

27

P2.6, A14

P2.5, A13

26
25

P2.4, A12

24

P2.3, A11
P2.2, A10

23
22

P2.1, A9
P2.0, A8

21

44-Pin QFP/TQFP (W78C51CF/W78C51CM)

A

A

A

A

A

A

A

D

D

D

D

3

2

1

0

,

,

,

,

P

P

P

P

V

N

C

C

C

N

P

C

2
.
0
,
A
8

0

0

0

0

.

.

.

.

3

1

2

0

40

41

P

P

P

2

2

2

.

.

.

3

2

1

,

,

,

A

A

A

1

1

9

1

0

P0.4, AD4

39
38

P0.5, AD5

37

P0.6, AD6

36

P0.7, AD7

35

EA

34

NC

33

ALE

32

PSEN

31

P2.7, A15

30

P2.6, A14

29

P2.5, A13

2827262524232221201918

P
2
.
4
,
A
1
2

P1.5
P1.6
P1.7

RST

RXD, P3.0

NC

TXD, P3.1
INT0, P3.2
INT1, P3.3

T0, P3.4
T1, P3.5

1
2

3

4
5
6
7
8
9
10

11

P
1
.
4

12

P
3
.
6
,
/
W
R

P

P

1

1

.

.

2

3

43 42 41

X

P

T

3

A

.

L

7

2

,
/
R
D

P
1
.
1

X
T
A
L
1

A
D
0
,

P

P

V

1

0

N

C

.

.

C

C

0

0

40 39 38 37 36

V

N

P

P

S

2

2

C

S

.

.

1

0

,

,

A

A

9

8

D

D

D

3

1

2

,

,

,

P

P

P

0

0

0

.

.

.

3

2

1

34

3544

P

P

2

2

.

.

3

2

,

,

A

A

1

1

1

0

P0.4, AD4

33
32

P0.5, AD5

31

P0.6, AD6

30

P0.7, AD7

29

EA

28

NC

27

ALE

26

PSEN

25

P2.7, A15

24

P2.6, A14

23

P2.5, A13

22212019181716151413

P
2
.
4
,
A
1
2

- 2 -

W78C51C

INT0

INT1

WR

RD

PIN DESCRIPTION

P0.0−P0.7

Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.

P1.0−P1.7

Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups.

P2.0−P2.7

Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.

P3.0−P3.7

Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:

PIN ALTERNATE FUNCTION

P3.0 RXD Serial Receive Data
P3.1 TXD Serial Transmit Data
P3.2

P3.3
P3.4 T0 Timer 0 Input

P3.5 T1 Timer 1 Input
P3.6

P3.7

External Interrupt 0

External Interrupt 1

Data Write Strobe

Data Read Strobe

EA

External Address Input, active low. This pin forces the processor to execute out of external ROM.
This pin should be kept low for all W78C31 operations.

RST

Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.

ALE

Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high impedance state during reset with
a weak pull-up.

Publication Release Date: October 1997

- 3 - Revision A3

PSEN

PSEN

PSEN

W78C51C

Program Store Enable Output, active low.
address/data bus during fetch and MOVC operations.

enables the external ROM onto the Port 0

goes to a high impedance state during

reset with a weak pull-up.

XTAL1

Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.

XTAL2

Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.

VSS, VCC

Power Supplies. These are the chip ground and positive supplies.

BLOCK DIAGRAM

RAM

128

Bytes

SFR

Port 0
Port 1

ROM

4K

Bytes

CPU

CORE

- 4 -

Data Bus

Interrupt

Serial

Port

Timer 0
Timer 1

INT 0
INT 1

Port 2

Port 3

Alternate

W78C51C

FUNCTIONAL DESCRIPTION

The W78C51C architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64 K data storage
space.

Timers 0, 1

Timers 0, 1 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1
and TH1 for Timer 1. The TCON and TMOD registers provide control functions for timers 0, 1.

Clock

The W78C51C is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78C51C relatively insensitive to duty
cycle variations in the clock.

Crystal Oscillator

The W78C51C incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.

An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C51C is used
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

Publication Release Date: October 1997

- 5 - Revision A3