winbond W78C52D, W78C052D User Manual

W78C52D/W78C052D

8-BIT MICROCONTROLLER

Publication Release Date: December 4, 2006

- 1 - Revision A5

Table of Contents-

1. GENERAL DESCRIPTION ......................................................................................................... 2

2. FEATURES ................................................................................................................................. 2

3. PIN CONFIGURATIONS ............................................................................................................ 3

4. PIN DESCRIPTION..................................................................................................................... 4

5. FUNCTIONAL DESCRIPTION ................................................................................................... 6

6. ABSOLUTE MAXIMUM RATINGS ........................................................................................... 10

7. DC CHARACTERISTICS.......................................................................................................... 11

8. AC CHARACTERISTICS .......................................................................................................... 13

9. TIMING WAVEFORMS ............................................................................................................. 15

10. APPLICATION CIRCUITS ........................................................................................................ 17

11. PACKAGE DIMENSIONS......................................................................................................... 19

12. REVISION HISTORY ................................................................................................................21

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W78C52D/W78C052D

- 2 -

1. GENERAL DESCRIPTION

The W78C052D microcontroller supplies a wider frequency and supply voltage range than most 8-bit
microcontrollers on the market. It is compatible with the industry standard 80C52 microcontroller
series. The W78C052D contains four 8-bit bidirectional parallel ports, one extra 4-bit bit-addressable

I/O port (Port 4) and two additional external interrupts (

INT2

, INT3 ), three 16-bit timer/counters, one
watchdog timer and a serial port. These peripherals are supported by a eight-source, two-level
interrupt capability. There are 256 bytes of RAM and an 8K byte mask ROM for application programs.

The W78C052D microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

2. FEATURES

y Fully static design

y

Supply voltage of 4.5V to 5.5V

y DC-40 MHz operation

y 256 bytes of on-chip scratchpad RAM

y 8K bytes of on-chip mask ROM

y 64K bytes program memory address space

y 64K bytes data memory address space

y Four 8-bit bidirectional ports

y Three 16-bit timer/counters

y One full duplex serial port

y

Eight-source, two-level interrupt capability

y One extra 4-bit bit-addressable I/O port

y

Two additional external interrupts INT2 / INT3

y Watchdog timer

y EMI reduction mode

y Built-in power management

y Code protection

y Packages:

− Lead Free (RoHS) DIP 40: W78C052D40DL

− Lead Free (RoHS) PLCC 44: W78C052D40PL

− Lead Free (RoHS) PQFP 44: W78C052D40FL

W78C52D/W78C052D

Publication Release Date: December 4, 2006

- 3 - Revision A5

3. PIN CONFIGURATIONS

VDD1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

39

40

34

35

36

37

38

30

31

32

33

26

27

28

29

21

22

23

24

25

P0.0, AD0
P0.1, AD1

P0.2, AD2

P0.3, AD3

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA
ALE

PSEN

P2.5, A13

P2.6, A14

P2.7, A15

P2.0, A8

P2.1, A9

P2.2, A10

P2.3, A11

P2.4, A12

T2, P1.0

40-Pin DIP

P1.2

P1.3

P1.4

P1.5

P1.6

RXD, P3.0
TXD, P3.1

P1.7

RST

INT0, P3.2

INT1, P3.3

T0, P3.4
T1, P3.5

WR, P3.6

RD, P3.7

XTAL1

XTAL2

VSS

T2EX, P1.1

44-Pin PLCC

44-Pin QFP

40

2 1 44 43 42

41

6543

39
38

37

36

35

34

33

32

31

30
29

2827262524232221201918

17

10

9

8

7

14

13

12

11

16

15

P1.5

P1.6

P1.7

RST

RXD, P3.0

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

A
D
3
,
P
0
.
3

T
2
,
P
1
.
0

P
1
.
2

V
D
D

A
D
2
,
P
0
.
2

A
D
1
,
P
0
.
1

A
D
0
,
P
0
.
0

T
2
E
X
,
P
1
.
1

P
1
.
3

P
1
.
4

X
T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

P
2
.
3
,
A
1
1

P
2
.
2
,
A
1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

X
T
A
L
2

P
3
.
7
,
/
R
D

P
3
.
6
,
/
W
R

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA

ALE

PSEN
P2.7, A15

P2.6, A14

P2.5, A13

P4.1

P
4
.
0

INT2, P4.3

/
I
N
T
3
,
P
4
.
2

34

403938 37 36 35

44

43 42 41

33
32

31

30

29

28

27

26

25

24
23

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA

ALE

PSEN
P2.7, A15

P2.6, A14

P2.5, A13

22212019181716151413

12

11

4

3

2

1

8

7

6

5

10

9

P1.5

P1.6

P1.7
RST

RXD, P3.0

TXD, P3.1
INT0, P3.2

INT1, P3.3

T0, P3.4
T1, P3.5

X
T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

P
2
.
3
,
A
1
1

P
2
.
2
,
A
1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

X
T
A
L
2

P
3
.
7
,
/
R
D

P
3
.
6
,
/
W
R

A
D
3
,
P
0
.
3

T
2
,
P
1
.
0

P
1
.
2

V
D
D

A
D
2
,
P
0
.
2

A
D
1
,
P
0
.
1

A
D
0
,
P
0
.
0

T
2
E
X
,
P
1
.
1

P
1
.
3

P
1
.
4

P
4
.
0

/
I
N
T
3
,
P
4
.
2

P4.1

INT2, P4.3

W78C52D/W78C052D

- 4 -

4. PIN DESCRIPTION

P0.0−P0.7

Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.

P1.0−P1.7

Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1
also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.

P2.0−P2.7

Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.

P3.0−P3.7

Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:

PIN ALTERNATE FUNCTION

P3.0 RXD Serial Receive Data
P3.1 TXD Serial Transmit Data

P3.2

INT0 External Interrupt 0

P3.3

INT1 External Interrupt 1

P3.4 T0 Timer 0 Input
P3.5 T1 Timer 1 Input

P3.6

WR Data Write Strobe

P3.7

RD Data Read Strobe

P4.0−P4.3

Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can be
used as general I/O pins or external interrupt input sources (

INT2 / INT3 ).

EA

External Address Input, active low. This pin forces the processor to execute out of external ROM. This
pin should be kept low for all W78C31 operations.

RST

Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.

ALE

Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high impedance state during reset with
a weak pull-up.

W78C52D/W78C052D

Publication Release Date: December 4, 2006

- 5 - Revision A5

PSEN

Program Store Enable Output, active low.

PSEN enables the external ROM onto the Port 0

address/data bus during fetch and MOVC operations.

PSEN goes to a high impedance state during

reset with a weak pull-up.

XTAL1

Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.

XTAL2

Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.

VSS, VDD

Power Supplies. These are the chip ground and positive supplies.

W78C52D/W78C052D

- 6 -

5. FUNCTIONAL DESCRIPTION

The W78C052D architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, one watchdog timer and a serial port. The
processor supports 111 different opcodes and references both a 64K program address space and a
64 K data storage space.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a special feature of the W78C052D: it is a 16-bit
timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2
can operate as either an external event counter or as an internal timer, depending on the setting of bit
C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator.
The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.

Clock

The W78C052D is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78C052D relatively insensitive to duty
cycle variations in the clock.

Crystal Oscillator

The W78C052D incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must
be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from
each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC
bias when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts when V

DD

= 5 volts.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78C052D is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.

W78C52D/W78C052D

Publication Release Date: December 4, 2006

- 7 - Revision A5

New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupts

INT2 , INT3 have been added to either the PLCC or QFP package. And description follows:

1.

INT2 / INT3

Two additional external interrupts,

INT2 and INT3 , whose functions are similar to those of external

interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.

***XICON - external interrupt control (C0H)

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

PX3: External interrupt 3 priority high if set

EX3: External interrupt 3 enable if set

IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced

IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software

PX2: External interrupt 2 priority high if set

EX2: External interrupt 2 enable if set

IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced

IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Eight-source interrupt informations:

INTERRUPT SOURCE

VECTOR

ADDRESS

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

ENABLE

REQUIRED

SETTINGS

INTERRUPT

TYPE

EDGE/LEVEL

External Interrupt 0 03H 0 (highest) IE.0 TCON.0

Timer/Counter 0 0BH 1 IE.1 -

External Interrupt 1 13H 2 IE.2 TCON.2

Timer/Counter 1 1BH 3 IE.3 -

Serial Port 23H 4 IE.4 -

Timer/Counter 2 2BH 5 IE.5 -

External Interrupt 2 33H 6 XICON.2 XICON.0

External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3