winbond W741L240 Technical data

W741L240

4-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W741L240 is a high-performance 4-bit microcontroller (µC) that provides an LCD driver. The
device contains a 4-bit ALU, a 8-bit timers, a divider, a 24 × 4 LCD driver, and three 4-bit I/O ports.
There are also three interrupt sources and 8-level subroutine nesting for interrupt applications. The
W741L240 operates on low voltage and very low current and has two power reduction modes, hold
mode and stop mode, which help to minimize power dissipation.

The W741L240 is suitable for caculators, simple watches and clocks, multiple I/O products, keyboard
controllers, speech synthesis LSI controllers, and other products.

FEATURES

• Operating voltage: 1.2V to 1.8V (LCD drive voltage: 3.0 or 4.5V)

• Crystal/RC oscillation circuit selectable by code option for system clock

• Crystal oscillator: 32.768 KHz only

• RC oscillator: 1 MHz (maximum)

− High-frequency (400 KHz to 1 MHz) or low-frequency (below 400 KHz) oscillation option must
be determined by the code option.

− In RC mode, attention must be paid to the high/low frequency oscillation option, because the
LCD driver frequency is related to this option.

• Memory

− 2048 × 16 bit program ROM (shared with 2K × 4 bit look-up table)

− 64 × 4 bit data RAM (shared with 16 working registers)

− 24 × 4 LCD data RAM

• 13 input/output pins

− Ports for input only: 1 port/4 pins

− Input/output ports: 2 ports/8 pins

− MFP output pin: 1 pin (MFP)

• Power-down mode

− Hold function: no operation (except for oscillator)

− Stop function: no operation (including oscillator)

• Three types of interrupts

− Two internal interrupts (Divider 0, Timer 1)

− One external interrupts (Port RC)

• LCD driver output

− 24 segment × 4 common

− Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) driving mode can be

selected

Publication Release Date: May 1999

- 1 - Revision A1

W741L240

• MFP output pin

− Output is software selectable as modulating or nonmodulating frequency

− Works as frequency output specified by Timer 1

• Built-in 14-bit clock frequency divider circuit

• One built-in 8-bit programmable countdown timers

− Timer 1: Offers auto-reload function and one of two internal clock frequencies (FOSC or FOSC/64)

can be selected (output through MFP pin)

• Built-in 18/14-bit watchdog timer selectable for system reset

• Powerful instruction set: 100 instructions

• 8-level subroutine (include interrupt) nesting

• Up to 4 µS instruction cycle (with 1 MHz operating frequency)

• Packaged in 64-pin QFP

PIN CONFIGURATION

RES
MFP
RA0

RA1
RA2
RA3
RB0
RB1
RB2
RB3
RC0
RC1

RC2

S

S

S

E

E

E

G

G

G

2 2 2 2

S

S

S

E

E

E

G

G

G

S
E
G

C

0123

S
E

C

G

V

V

X

V

D

NCN

O

D

H

U

N

D

C

1

C

T

V

C

NCNCNCNCR

S

O

S

M

3

X

I

N

51 50 49 48 47 46 45 44 43 424140 39 38 373635 34 33

52
53
54
55
56
57
58
59
60
61
62
63
64

1 2 3 4 5 6 7 8 91011 12 13 14 15 16 17 18 19

C
3

V

D

D

D

D

H

D

D

D

1

2

2

3

C

C

C

S

O

O

O

E

M

M

M

G

210 0 1 2 3 4 5

S
E

G

NCN

N

1

C

9

32
31
30
29
28
27
26
25
24
23
22
21
20

S

NCNCN

E
G

SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6

- 2 -

PIN DESCRIPTION

RES

SYMBOL I/O FUNCTION

XIN I Input pin for oscillator.

Connected to crystal or resistor to generate system clock by code option.

XOUT O Output pin for oscillator.

Connected to crystal or resistor to generate system clock by code option.

RA0−RA3

RB0−RB3

RC0−RC3

MFP

I/O Input/Output port.

Input/output mode specified by port mode 1 register (PM1).

I/O Input/Output port.

Input/output mode specified by port mode 2 register (PM2).

I 4-bit port for input only.

Each pin has an independent interrupt capability.
Output pin only.

O

This pin can output modulating or nonmodulating frequency, or Timer 1
clock output specified by mode register 1 (MR1).

I System reset pin with pull-high resistor.

W741L240

SEG0−SEG23

O LCD segment output pins.

Also can be used as DC output ports specified by code option.

COM0−COM3

O LCD common signal output pins.

COM0
COM1
COM2
COM3

Static

Used
Not Used
Not Used
Not Used

1/2 Duty

Used

Used
Not Used
Not Used

1/3 Duty

Not Used

Used
Used
Used

1/4 Duty

Used
Used
Used
Used

The LCD alternating frequency can be selected by code option.

DH1, DH2 I Connection terminals for voltage doubler (halver) capacitor.
VDD1, VDD2,

VDD3

I Positive (+) supply voltage terminal.

Refer to Functional Description.
VDD I Positive power supply (+).
VSS I Negative power supply (-).

Publication Release Date: May 1999

- 3 - Revision A1

BLOCK DIAGRAM

W741L240

(2048*16)

(look_up table

2K*4)

+1(+2)

STACK

(8 Levels)

RAM

(64*4)

ROM

PC

SEG0 to SEG23 COM0 to COM3

LCD DRIVER

ACC

ALU

Central Control

Unit

IEF

HCF

PSR0 PR

PM1

.

PEFHEF
EVF SEF
PM0

MR1

.

.
.

VDD1-3 DH1-2

PORT RA

PORT RB RB0-3

PORT RC

SEL

MUL

RA0-3

RC0-3

MFP

Timer 1

(8 Bit)

Divider 0

(14 Bit)

Modulation

Frequency

Pulse

- 4 -

VDD
VSS

Timing Generator

RES

XINXOUT

W741L240

FUNCTIONAL DESCRIPTION

Program Counter (PC)

Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses
of the 2048 × 16 on-chip ROM containing the program instruction words. When jump or subroutine
call instructions or interrupt or initial reset conditions are to be executed, the address corresponding to
the instruction will be loaded into the program counter. The format used is shown below.

ITEM ADDRESS INTERRUPT PRIORITY

Initial Reset 000H ­INT 0 (Divider 0) 004H 1st
INT 2 (Port RC) 00CH 2nd
INT 7 (Timer 1) 020H 3rd
JP Instruction XXXH ­Subroutine Call XXXH -

Stack Register (STACK)

The stack register is organized as 11 bits × 8 levels (first-in, last-out). When either a call subroutine or
an interrupt is executed, the program counter will be pushed onto the stack register automatically. At
the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed
to pop the contents of the stack register into the program counter. When the stack register is pushed
over the eighth level, the contents of the first level will be lost. In other words, the stack register is
always eight levels deep.

Program Memory (ROM)

The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 2048
× 4 bits. The first three quarters of ROM (000H to 5FFH) are used to store instruction codes only, but
the last quarter (600H to 7FFH) can store both instruction codes and the look-up table. Each look-up
table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements.
There are two registers (TABL and TABH) to be used in look-up table addressing and they are
controlled by MOV TABH, R and MOV TABL, R instructions. When the instruction MOVC R is
executed, the contents of the look-up table location address specified by TABH, TABL and ACC will
be read and transfered to the data RAM. Refer to the instruction table for more details. The
organization of the program memory is shown in Figure 1.

Publication Release Date: May 1999

- 5 - Revision A1

000H

W741L240

16 bits

ACCTABLTABH

2048

address

600H

7FFH

- x x x x x x x x x y y

0 1 1 x x x x x x x x x

ROM address = 600H + Offset/4

3 2 1 0

2048 x 16-bit

Figure 1. Program Memory Organization

This area can be used to store both instruction code
and look-up table

Each element (4 bits) of the look-up table

Offset

Data Memory (RAM)

1. Architecture

The static data memory (RAM) used to store data is arranged as 64 × 4 bits. The data memory can be
addressed directly or indirectly. The organization of the data memory is shown in Figure 2.

4 bits

00H

Working Register

:

0FH

64

address

3FH

64 x 4-bit

Figure 2. Data Memory Organization

The first sixteen addresses (00H to 0FH) in the data memory are known as the working registers
(WR). The other data memory is used as general memory and cannot operate directly with immediate
data. The relationship between data memory locations and the page register (PAGE) in indirect
addressing mode is described in the next section.

- 6 -

W741L240

2. Page Register (PAGE)

The page register is organized as a 4-bit binary register. The bit descriptions are as follows:

0123

PAGE

Note: R/W means read/write available.

_ _

Bit 3 and Bit2 are reserved.
Bit 1, Bit 0 are indirect addressing mode preselect bits:

00 = Page 0 (00H−0FH) 01 = Page 1 (10H−1FH)

10 = Page 2 (20H−2FH) 11 = Page 3 (30H−3FH)

Accumulator (ACC)

The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data
between the memory, I/O ports, and registers.

Arithmetic and Logic Unit (ALU)

This is a circuit which performs arithmetic and logic operations. The ALU provides the following
functions:

• Logic operations: ANL, XRL, ORL

• Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC

• Shift operations: SHRC, RRC, SHLC, RLC

• Binary additions/subtractions: ADC, SBC, ADD, SUB, DEC, INC

After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is
stored in the internal registers. CF can be read out by executing MOVA R, CF.

R/W R/W

Clock Generator

The W741L240 provides a crystal or RC oscillation circuit selected by option codes to generate the
system clock through external connections. If a crystal oscillator is used, a crystal must be connected
to XIN and XOUT, and the capacitor must be connected if an accurate frequency is needed. When a
crystal oscillator is used, only low-frequency clock (32 KHz) can be selected for the system clock by
means of option codes. If the RC oscillator is used, a resistor in the range of 20 KΩ to 1.6 MΩ must
be connected to XIN and XOUT, as shown in Figure 3. The system clock frequency range is from 32
KHz to 1 MHz. One machine cycle consists of a four-phase system clock sequence and can run up to
4 µS with a 1 MHz system clock.

XIN

XOUT

32 KHz

Crystal

XIN

or

XOUT

Figure 3. Oscillator Configuration

- 7 - Revision A1

Resistor

Publication Release Date: May 1999

W741L240

S

Divider 0

Divider 0 is organized as a 14-bit binary up-counter designed to generate periodic interrupts, as
shown in Figure 4. When the system starts, the divider is incremented by each system clock (FOSC).
When an overflow occurs, the divider event flag is set to 1 (EVF.0 = 1). Then, if the divider interrupt
enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag
has been set (HEF.0 = 1), the hold state is terminated. In addition, the 4 MSB of the divider can be
reset by executing the CLR DIVR0 instruction.

Watchdog Timer (WDT)

The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program

from unknown errors. The WDT is enable when the corresponding option code bit of the WDT is set
to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is
FOSC/1024. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/1024) by executing
the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the
instruction CLR WDT. In normal operation, the application program must reset WDT before it
overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset.
The WDT minimun overflow period is 468.75 mS when the system clock (FOSC) is 32 KHz and WDT
clock input is FOSC/1024. When the corresponding option code bit of the WDT is set to 0, the WDT
function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 4.

Divider0

Fosc

...

Q1 Q2 Q9 Q10 Q11 Q12

Fosc/16384
Fosc/1024

Q14

Q13

RRRR

PMF.3

Enable
/Disable

Mask Option

Figure 4. Organization of Divider 0 and Watchdog Timer

EVF.0

Q

R

WDT

Qw1 Qw2 Qw4Qw3

R R R R

HEF.0
IEF.0

1. Reset

2. CLR EVF, #01H

3. CLR DIVR0

Overflow signal

1. Reset

2. CLR WDT

Hold mode release (HCF.0)

Divider0 interrupt (INT0)

System Reset

Timer/Counter

Timer 1 (TM1)

Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 5. Timer 1 can
be used as a counter to output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can
be one of two sources: FOSC/64, or FOSC. The source can be selected by setting bit 0 of mode
register 1 (MR1). At initial reset, the Timer 1 clock input is FOSC. When the MOV TM1L, R or MOV
TM1H, R instruction is executed, the specified data are loaded into the auto-reload buffer and the
TM1 down-counting will be disabled (i.e. MR1.3 is reset to 0). If the bit 3 of MR1 is set (MR1.3 = 1),
the contents of the auto-reload buffer will be loaded into the TM1 down counter, Timer 1 starts to
down count, and the event flag 7 is reset (EVF.7 = 0). When the timer decrements to FFH, it will
generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it will

- 8 -

W741L240

continue to count down. An interrupt is executed if the interrupt enable flag 7 has been set to 1 (IEF.7
= 1), and the hold state is terminated if the hold mode release enable flag 7 is set to 1 (HEF.7 = 1).
The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit 2 of
MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting.

If the Timer 1 clock input is FT, then:
Desired Timer 1 interval = (preset value +1) / FT
Desired frequency for MFP output pin = FT ÷ (preset value + 1) ÷ 2 (Hz)
Preset value: Decimal number of Timer 1 preset value, and
FOSC: Clock oscillation frequency

MOV TM1L, R

8 bits

8-bit Binary

(Timer 1)

Reset

Underflow

signal

44

S

Q

R

1. Reset

2. INT 7 accept

3. CLR EVF, #80H

4. Set MR1.3 to 1

EVF.7

2

circuit

Reset

MR1.2

MFP signal

MFP

output pin

Fosc/64

Fosc

MR1.0

MR1.3 = 1

1. MR1.3 = 0

MOV TM1H, R

Enable

F

T

Disable

Auto-reload buffer

Down Counter

Set MR1.3 to 1

Figure 5. Organization of Timer 1

For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will
output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between
the tone frequency and the preset value of TM1 is shown in the table below.

Publication Release Date: May 1999

- 9 - Revision A1

W741L240

3 4 5

Tone

frequency

C

130.81

#

C

138.59

D

T
O
N

E

Note: Central tone is A4 (440 Hz).

146.83

#

D

155.56

E

164.81

F

174.61

#

F

185.00

G

196.00

#

G

207.65

A

220.00

#

A

233.08

B

246.94

TM1 preset value
& MFP frequency

7CH

131.07

75H

138.84

6FH

146.28

68H

156.03

62H

165.49

5DH

174.30

58H

184.09

53H

195.04

4EH

207.39

49H

221.40

45H

234.05

41H

248.24

Tone

frequency

261.63

277.18

293.66

311.13

329.63

349.23

369.99

392.00

415.30

440.00

466.16

493.88

TM1 preset value
& MFP frequency

260.06

3EH

277.69

3AH

292.57

37H

309.13

34H

327.68

31H

372.36

2EH

390.09

2BH

420.10

29H

443.81

26H

442.81

24H

22H

468.11

20H

496.48

Tone

frequency

523.25

554.37

587.33

622.25

659.26

698.46

739.99

783.99

830.61

880.00

932.23

987.77

Mode Register 1 (MR1)

Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control
the operation of Timer 1. The bit descriptions are as follows:

TM1 preset value
& MFP frequency

1EH

528.51

1CH

564.96

1BH

585.14

19H

630.15

18H

655.36

16H

712.34

15H

744.72

14H

780.19

13H

819.20

12H

862.84

11H

910.22

10H

963.76

0123

MR1

Note: W means write only.

WW W

Bit 0 = 0 The internal fundamental frequency of Timer 1 is FOSC.

= 1 The internal fundamental frequency of Timer 1 is FOSC/64.
Bit 1 Reserved
Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin.

= 1 The specified frequency of Timer 1 is delivered at the MFP output pin.
Bit 3 = 0 Timer 1 stops down-counting.

= 1 Timer 1 starts down-counting.

- 10 -

W741L240

Interrupts

The W741L240 provides two internal interrupt sources (Divider 0, Timer 1) and one external interrupt
sources (port RC). Vector addresses for each of the interrupts are located in the range of program
memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to control the
interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been
set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited
until the EN INT or MOV IEF, #I instruction is invoked. The interrupts can also be disabled by
executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold mode will be
released momentarily and the interrupt subroutine will be executed. After the RTN instruction is
executed in an interrupt subroutine, the µC will enter hold mode again. The operation flow chart is
shown in Figure 7. The control diagram is shown below.

Initial Reset

Divider 0

overflow signal

Port RC

signal change

Timer 1

underflow signal

SRQ

SRQ

SRQ

EN INT
MOV IEF,#I

EVF.0

IEF.0

EVF.2

IEF.2

EVF.7

IEF.7

Interrupt
Process

Circuit

Enable

Interrupt

Vector

Generator

004H

00CH
020H

Initial Reset
CLR EVF,#I instruction

Figure 6. Interrupt Event Control Diagram

Disable

DIS INT instruction

Stop Mode Operation

In stop mode, all operations of the µC cease (including the operation of the oscillator). The µC enters
stop mode when the STOP instruction is executed and exits stop mode when an external trigger is
activated (by a falling signal on the RC port). When the designated signal is accepted, the µC
awakens and executes the next instruction (if the corresponding bits of IEF and PEF have been set, It
will enter the interrupt service routine after stop mode released). To prevent erroneous execution, the
NOP instruction should follow the STOP command.

Publication Release Date: May 1999

- 11 - Revision A1

W741L240

Hold Mode Operation

In hold mode, all operations of the µC cease, except for the operation of the oscillator, timer, and
LCD driver. The µC enters hold mode when the HOLD instruction is executed. The hold mode can be
released in one of three ways: by the action of Timer 1, Divider 0, or the RC port. Before the device
enters the hold mode, the HEF, PEF, and IEF flags must be set to define the hold mode release
conditions. For more details, refer to the instruction-set table and the following flow chart.

Divider 0, Timer 1,

Signal Change on

Port RC

In
HOLD
Mode?

Interrupt

Enable?

Yes

IEF

Flag Set?

Yes

Reset EVF.n Flag

Execute

Interrupt Service Routine

Disable interrupt

HOLD

Note : The bit of EVF corresponding to the interrupt request signal will be reset.

No

HEF

Flag Set?

(Note) (Note)

NoYes

YesNo

Interrupt

Enable?

Yes

IEF

Flag Set?

Yes

Reset EVF.n Flag

Execute

Interrupt Service Routine

Disable interrupt

PC <- (PC+1)

NoNo

No

Figure 7. Hold Mode and Interrupt Operation Flow Chart

- 12 -