winbond W27E520 Technical data
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OE
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W27E520
64K × 8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27E520 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 65,536 × 8 bits. It includes latches for the lower 8 address lines to multiplex
with the 8 data lines. To cooperate with the MCU, this device could save the external TTL
component, also cost and space. It requires only one supply in the range of 4.5V to 5.5V in normal
read mode. The W27E520 provides an electrical chip erase function. It will be a great convenient
when you need to change/update the contents in the device.
FEATURES
• High speed access time: 70/90 nS (max.)
• Read operating current: 20 mA (max.)
• Erase/Programming operating current
30 mA (max.)
• Standby current: 100
•
Unregulated battery power supply range,
µ
A (max.)
4.5V to 5.5V
• +13V erase and programming voltage
• High Reliability CMOS Technology
−
2K V ESD Protection
−
200 mA Latchup Immunity
• Fully static operation
• All inputs and outputs directly TTL/CMOS
compatible
• Three-state outputs
• Available packages: 20-pin TSSOP and 20-pin
SOP
PIN CONFIGURATIONS
1
A10
2
A12
3
A14
4
ALE
5
V
OE/VPP
A15
A13
A11
A9
OE/VPP
A15
A13
A11
A9
AD0
AD2
AD4
AD6
GND
DD
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
TSSOP
Top View
SOP
Top View
BLOCK DIAGRAM
20
A8
AD1
19
AD3
18
AD5
17
AD7
16
GND
15
14
AD6
13
AD4
12
AD2
AD0
11
20
19
18
17
16
15
14
13
12
11
VDD
ALE
A14
A12
A10
A8
AD1
AD3
AD5
AD7
PIN DESCRIPTION
SYMBOL DESCRIPTION
AD0−AD7
A8−A15
ALE Address Latch Enable
VDD Power Supply
OE / V
AD7 - AD0
A15 - A8
/VPP
ALE
CONTROL
PP
L
A
T
C
H
E
S
DECODER
V
DD
GND
Address/Data Inputs/Outputs
Address Inputs
Output Enable, Program/Erase
Supply Voltage
GND Ground
OUTPUT
BUFFER
MEMORY
Publication Release Date: September 2000
- 1 - Revision A2
W27E520
OE
OE
FUNCTIONAL DESCRIPTION
Read Mode
Unlike conventional UVEPROMs, which has CE and OE two control functions, the W27E520
has one OE/VPP and one ALE (address_latch_enable) control functions. The ALE makes lower
address A[7:0] to be latched in the chip when it goes from high to low, so that the same bus can be
used to output data during read mode. i.e. lower address A[7:0] and data bus DQ[7:0] are multiplexed.
/VPP controls the output buffer to gate data to the output pins. When addresses are stable, the
address access time (T
the outputs TOE after the falling edge of OE/VPP, if T
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E520 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
There are two ways to enter Erase mode. One is to raise OE/VPP to VPE (13V), VDD = VDE (6.5V),
A9 = VHH (13V), A10 = high A8&A11 = low, and all other address pins include AD[7:0] keep at fixed
low or high. Pulsing ALE high starts the erase operation. The other way is somewhat like flash, by
programming two consecutive commands into the device and then enter Erase mode. The two
commands are loading Data = AA(hex) to Addr. = 5555(hex) and Data = 10(hex) to Addr. =
2AAA(hex). Be careful to note that the ALE pulse widths of these two commands are different: One is
50uS, while the other is 100mS. Please refer to the Smart Erase Algorithm 1 & 2.
ACC
) is equal to the delay from ALE to output (TCE), and data are available at
ACC
and TCE timings are met.
Erase Verify Mode
The device will enter the Erase Verify Mode automatically after Erase Mode. Only power down the
device can force the device enter Normal Read Mode again.
Program Mode
Programming is the only way to change cell data from "1" to "0." The program mode is entered when
/VPP is raised to VPP (13V), VDD = VDP (6.5V), the address pins equal the desired addresses, and
the input pins equal the desired inputs. Pulsing ALE high starts the programming operation.
Program Verify Mode
The device will enter the Program Verify Mode automatically after Program Mode. Only power down
the device can force the device enter Normal Read Mode again.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When ALE low, erasing or programming of non-target chips is inhibited, so that except for the
ALE and OE/VPP pins, the W27E520 may have common inputs.
Standby Mode
The standby mode significantly reduces VDD current. This mode is entered when ALE and OE/VPP
keep high. In standby mode, all outputs are in a high impedance state.
- 2 -
OE
W27E520
System Considerations
An EPROM's power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (ISB), active current levels (IDD), and
transient current peaks produced by the falling and rising edges of ALE Transient current magnitudes
depend on the device output's capacitive and inductive loading. Proper decoupling capacitor selection
will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected
between its VDD and GND. This high frequency, low inherent-inductance capacitor should be placed
as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor
should be placed at the array's power supply connection between VDD and GND. The bulk capacitor
will overcome voltage slumps caused by PC board trace inductances.
TABLE OF OPERATING MODES
(VPP = 13V, VPE = 13V, VHH = 12V, VDP = 6.5V, VDE = 6.5V, VDD = 5.0V, VDI = 5.0V, X = VIH or VIL)
MODE PIN
ALE
/VPP
Address Latch Enable VIH VIH AIN V
Read VIL VIL AIN V
Output Disable VIL
IH
/V
VIH X V
Standby VIH VIH X V
Program VIH VPP AIN V
Erase 1 VIH VPE A8&A11 = VIL, A9 = VPE,
Erase 2 VIH VPE First command:
Second command:
Product Identifier-
VIL VIL A8 = VIL, A9 = VHH, Others = X VDI DA(Hex)
manufacturer
Product Identifier-device VIL VIL A8 = VIH, A9 = VHH, Others = X VDI 1F(Hex)
OTHER ADDRESS VDD AD[7:0]
DD
A[7:0]
DD
DD
DD
DP
DE
V
OUT
D
High Z
A[7:0]
DIN
X
A10 = VIH, Others = X
DE
V
AA(hex)
Addr. = 5555 (hex)
DE
V
10(hex)
Addr. = 2AAA (hex)
Publication Release Date: September 2000
- 3 - Revision A2
W27E520
OE
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Ambient Temperature with Power Applied -55 to +125
Storage Temperature -65 to +150
Voltage on all Pins with Respect to Ground Except
PP,
/V
A9 and VDD Pins
Voltage on OE/VPP Pin with Respect to Ground
-2.0 to +7.0 V
-2.0 to +7.0 V
Voltage on A9 Pin with Respect to Ground -2.0 to +7.0 V
Voltage VDD Pin with Respect to Ground -2.0 to +14.0 V
Notes:
1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
2. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 nS. Maximum output pin voltage is
DD
V
+0.75V DC which may overshoot to +7.0V for pulses of less than 20 nS.
DC Erase Characteristics
(TA = 25° C ±5° C, VDD = 6.5V ±0.25V)
°
C
°
C
PARAMETER SYM.
Input Load Current ILI VIN = VIL or VIH -10 - 10
VDD Erase Current ICP
VPP Erase Current IPP
CONDITIONS LIMITS UNIT
MIN. TYP. MAX.
ALE = V
IH,
OE/VPP = V
PE
- - 30 mA
A8 & A11 = VIL, A9 = VPE,
A10 = VIH, Others = X
ALE = V
IH,
OE/VPP = V
PE
- - 30 mA
A8 & A11 = VIL, A9 = VPE,
A10 = VIH, Others = X
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.4 - VDD+0.3 V
Output Low Voltage
VOL IOL = 2.1 mA - - 0.45 V
(Verify)
Output High Voltage
OH
V
IOH = -0.4 mA 2.4 - - (Verify)
A9 SID Voltage V
HH
VDD = 5V ±10%
11.5 12 12.5 V
A9 Erase Voltage VPE - 12.75 13 13.25 V
VPP Erase Voltage VPE - 12.75 13 13.25 V
VDD Supply Voltage (Erase
VDE - 6.25 6.5 6.75 V
& Erase Verify)
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
µ
A
- 4 -
W27E520
Input
CAPACITANCE
(VDD = 4.5V to 5.5V, TA = 25° C, f = 1 MHz)
PARAMETER SYMBOL MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF
Output Capacitance C
OUT
V
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V/3V
Input Rise and Fall Times 10 nS
Input and Output Timing Reference Level 1.5V/1.5V
Output Load CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA
OUT
= 0V 12 pF
AC Test Load and Waveforms
D
OUT
3V
0V
+1.3V
(IN914)
3.3K ohm
100 pF (Including Jig and Scope)
Output
Test Points Test Points
1.5V
1.5V
Publication Release Date: September 2000
- 5 - Revision A2
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