winbond W27E010 Technical data
CE
OE
PGM
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W27E010
128K × 8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27E010 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 131072 × 8 bits that operates on a single 5 volt power supply. The W27E010
provides an electrical chip erase function.
FEATURES
•
High speed access time:
45/55/70/90/120 nS (max.)
•
Read operating current: 30 mA (typ.)
•
Erase/Programming operating current:
1 mA (typ.)
•
Standby current: 5 µA (typ.)
•
Single 5V power supply
•
+14V erase/+12V programming voltage
•
Fully static operation
•
All inputs and outputs directly TTL/CMOS
compatible
•
Three-state outputs
•
Available packages: 32-pin 600 mil DIP,
450 mil SOP and PLCC
PIN CONFIGURATIONS
Vpp
1
A16
2
A15
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
Q0
13
14
Q1
Q2
15
GND
16
A
A
1
1
5
2
4 3 2 1
5
A7
A6
6
7
A5
A4
8
9
10
11
12
13
32-pin PLCC
1
151
4
Q1Q
2
A3
A2
A1
A0
Q0
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/
A
V
V
P
1
c
p
G
6
c
p
M
323
1
18192
1
7
6
Q4Q
G
Q
5
N
3
D
BLOCK DIAGRAM
Vcc
PGM
NC
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
PGM
A16
GND
CE
OE
V
V
CONTROL
A0
.
DECODER
.
CC
PP
OUTPUT
BUFFER
CORE
ARRAY
Q0
.
.
Q7
PIN DESCRIPTION
N
C
3
0
0
Q
6
A14
29
A13
28
A8
27
A9
26
25
A11
OE
24
A10
23
22
CE
Q7
21
SYMBOL DESCRIPTION
A0−A16
Q0−Q7
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Program Enable
VPP Program/Erase Supply Voltage
VCC Power Supply
GND Ground
NC No Connection
Publication Release Date: June 2000
- 1 - Revision A6
W27E010
CE
PGM
PGM
PGM
OE
PGM
CE
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27E010 has two control functions, both of which produce data
at the outputs.
is for power control and chip select. OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (T
(TCE), and data are available at the outputs TOE after the falling edge of OE, if T
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E010 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE = VIL, (0.8V or below
but higher than GND), OE = V
other address pins equal VIL and data input pins equal VIH. Pulsing
operation.
IH
(2V or above but lower than VCC), A9 = VHH (14V), A0 = V
ACC
) is equal to the delay from CE to output
ACC
and TCE timings
IL,
low starts the erase
and all
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE = VIL, and OE =
IL,
V
= V
IH.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP
(12V), VCC = VCP (5V), CE = VIL, OE = VIH, the address pins equal the desired addresses, and the
input pins equal the desired inputs. Pulsing
low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE = V
IL,
and
= VIH.
= V
IL,
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE = VIH, erasing or programming of non-target chips is inhibited, so that except for the
, the W27E010 may have common inputs.
- 2 -
W27E010
PGM
CE OE
PGM
Standby Mode
The standby mode significantly reduces VCC current. This mode is entered when CE = VIH. In
standby mode, all outputs are in a high impedance state, independent of OE and
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27E010 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
concerned with three supply current issues: standby current levels (ISB), active current levels (ICC),
and transient current peaks produced by the falling and rising edges of CE. Transient current
magnitudes depend on the device output's capacitive and inductive loading. Two-line control and
proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have
a 0.1 µF ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection
between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
.
TABLE OF OPERATING MODES
VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X=VIH or VIL
MODE PINS
Read VIL VIL X X X VCC VCC D
Output Disable VIL VIH X X X VCC VCC High Z
Standby (TTL) VIH X X X X VCC VCC High Z
Standby (CMOS)
Program VIL VIH VIL X X VCP VPP DIN
Program Verify VIL VIL VIH X X VCP VPP D
Program Inhibit VIH X X X X VCP VPP High Z
Erase VIL VIH VIL VIL VPE VCC VPE FF (Hex)
Erase Verify VIL VIL VIH X X VCC VPE D
Erase Inhibit VIH X X X X VCP VPE High Z
Product Identifier-
Manufacturer
Product Identifier-Device VIL VIL X VIH VHH VCC VCC 01 (Hex)
CC
±
V
0.3V
VIL VIL X VIL VHH VCC VCC DA (Hex)
X X X X VCC VCC High Z
A0 A9 VCC VPP OUTPUTS
OUT
OUT
OUT
Publication Release Date: June 2000
- 3 - Revision A6
DC CHARACTERISTICS
CE
PGM
CE
PGM
Absolute Maximum Ratings
PARAMETER RATING UNIT
W27E010
Ambient Temperature with Power Applied -55 to +125
Storage Temperature -65 to +125
Voltage on all Pins with Respect to Ground Except V
CC, VPP
-0.5 to V
CC
+0.5 V
°
C
°
C
and A9 Pins
Voltage on V
CC
Pin with Respect to Ground -0.5 to +7 V
Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V
Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
DC Erase Characteristics
(TA = 25° C ±5° C, VCC = 5.0V ±10%, VHH = 14V)
PARAMETER SYM. CONDITIONS LIMITS UNIT
Input Load Current ILI V
VCC Erase Current ICP
VPP Erase Current IPP
MIN. TYP. MAX.
IN
= VIL or VIH -10 - 10
= V
IL,
OE = V
IH,
- - 30 mA
µ
= VIL, A9 = VHH
= V
IL,
OE = V
IH,
- - 30 mA
A
= VIL, A9 = VHH
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.4 - 5.5 V
Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V
A9 Erase Voltage VID - 13.75 14.0 14.25 V
VPP Erase Voltage VPE - 13.75 14.0 14.25 V
VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
- 4 -
W27E010
CAPACITANCE
(VCC = 5V, TA = 25° C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF
Output Capacitance C
OUT
V
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0 to 3.0V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V/1.5V
Output Load CL = 30 pF,
AC Test Load and Waveforms
OUT
= 0V 12 pF
IOH/IOL = -0.4 mA/2.1 mA
+1.3V
(IN914)
3.3K ohm
D
OUT
100 pF for 90/120 nS (Including Jig and Scope)
30 pF for 45/55/70 nS (Including Jig and Scope)
3.0V
0V
Inpu
Test Point Test Point
1.5V
Output
1.5V
Publication Release Date: June 2000
- 5 - Revision A6
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