Winbond ISD2532, ISD2540, ISD2548, ISD2564 User Manual

ISD2532/40/48/64

SINGLE-CHIP, MULTIPLE-MESSAGES,

VOICE RECORD/PLAYBACK DEVICE

32-, 40-, 48-, AND 64-SECOND DURATION

Publication Release Date: June 2003

- 1 - Revision 1.0

ISD2532/40/48/64

1. GENERAL DESCRIPTION

Winbond’s ISD2500 ChipCorder® Series provide high-quality, single-chip, Record/Playback solutions
for 32- to 64-second messaging applications. The CMOS devices include an on-chip oscillator,
microphone preamplifier, automatic gain control, antialiasing filter, smoothing filter, speaker amplifier,
and high density multi-level storage array. In addition, the ISD2500 is microcontroller compatible,
allowing complex messaging and addressing to be achieved. Recordings are stored into on-chip
nonvolatile memory cells, providing zero-power message storage. This unique, single-chip solution is
made possible through Winbond’s patented multilevel storage technology. Voice and audio signals
are stored directly into memory in their natural form, providing high-quality, solid-state voice
reproduction.

2. FEATURES

• Single 5 volt power supply

• Single-chip with duration of 32, 40, 48, or 64 seconds.

• Easy-to-use single-chip, voice record/playback solution

• High-quality, natural voice/audio reproduction

• Manual switch or microcontroller compatible

• Playback can be edge- or level-activated

• Directly cascadable for longer durations

• Automatic power-down (push-button mode)

- Standby current 1 µA (typical)

• Zero-power message storage

- Eliminates battery backup circuits

• Fully addressable to handle multiple messages

• 100-year message retention (typical)

• 100,000 record cycles (typical)

• On-chip clock source

• Programmer support for play-only applications

• Available in die form, PDIP, SOIC and TSOP packaging

• Temperature options: die (0°C to +50°C) and package (0°C to +70°C)

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3. BLOCK DIAGRAM

ISD2532/40/48/64

Internal Clock Timing

XCLK

ANA OU T

MIC

MIC REF

AGC

AmpANA IN

Pre-

Amp

V

CCAVSSAVSSDVCCD

5-Pole Active

Antialiasing Filter

Automatic

Gain Control

(AGC)

Sampling Clock

Analog Transceivers

256K Cell

Nonvolatile

Multilevel Storage

Decoders

Address Buffers

A0 A1 A2 A3 A4 A5 A6 A7 A8

Array

5-Pole Active

Smoothing Filter

Device ControlPower Conditioning

Amp

Mux

EOMCEP/ROVFPD

AUX IN

SP +

SP -

Publication Release Date: June 2003

- 3 - Revision 1.0

ISD2532/40/48/64

4. TABLE OF CONTENTS

1. GENERAL DESCRIPTION.................................................................................................................. 2

2. FEATURES ......................................................................................................................................... 2

3. BLOCK DIAGRAM .............................................................................................................................. 3

4. TABLE OF CONTENTS ...................................................................................................................... 4

5. PIN CONFIGURATION ....................................................................................................................... 5

6. PIN DESCRIPTION............................................................................................................................. 6

7. FUNCTIONAL DESCRIPTION.......................................................................................................... 10

7.1. Detailed Description.................................................................................................................... 10

7.2. Operational Modes ..................................................................................................................... 11

7.2.1. Operational Modes Description............................................................................................12

8. TIMING DIAGRAMS.......................................................................................................................... 16

9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 19

9.1 Operating Conditions ................................................................................................................... 20

10. ELECTRICAL CHARACTERISTICS ............................................................................................... 21

10.1. Parameters For Packaged Parts .............................................................................................. 21

10.1.1. Typical Parameter Variation with Voltage and Temperature - Packaged Parts ................ 24

10.2. Parameters For Die .................................................................................................................. 25

10.2.1. Typical Parameter Variation with Voltage and Temperature - Die .................................... 28

10.3. Parameters For Push-Button Mode.......................................................................................... 29

11. TYPICAL APPLICATION CIRCUIT.................................................................................................30

12. PACKAGE DRAWING AND DIMENSIONS .................................................................................... 35

12.1. 28-Lead 300-Mil Plastic Small Outline IC (SOIC)..................................................................... 35

12.2. 28-Lead 600-Mil Plastic Dual Inline Package (PDIP)............................................................... 36

12.3. 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1................................ 37

12.4. Die Bonding Physical Layout

14. VERSION HISTORY ....................................................................................................................... 41

[1]

................................................................................................ 38

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5. PIN CONFIGURATION

ISD2532/40/48/64

OVF

CE

PD

EOM

XCLK

P/R

V

CCD

A0/M0

A1/M1
A2/M2

A3/M3

A4M4
A5/M5

A6/M6

A0/M0

A1/M1

A2/M2

A3/M3

A4/M4

A5/M5

A6/M6

AUX IN

V

V

SP +

1

2

3

4

5

6

7

8

9

10

11

12

13

14

NC

SSD

SSA

V

1

2

3

4

5

6

7

8

9

A7

10

A8

11

12

13

14

ISD2532
ISD2540
ISD2548
ISD2564

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CCD

P/R

XCLK

EOM

PD

CE

OVF

ANA OU T

ANA IN

AGC

MIC REF

MIC

V

CCA

SP-

SOIC/PDIP

28

ANA OU T

27

ANA IN

26

AGC

25

MIC REF

24

ISD2532
ISD2340
ISD2548
ISD2564

MIC

23

V

CCA

22

SP-

21

SP+

20

V

SSA

19

V

SSD

18

AUX IN

17

A8

16

A7

15

NC

TSOP

Publication Release Date: June 2003

- 5 - Revision 1.0

6. PIN DESCRIPTION

PIN NO. FUNCTION

PIN NAME

SOIC /

PDIP

ISD2532/40/48/64

TSOP

A0, A1, A2,
A3, A4, A5,

A6, A7, A8

/ M0, M1,

M2, M3,

M4, M5, M6

1, 2, 3,
4, 5, 6,

7, 9, 10

/ 1, 2,

3, 4,

5, 6, 7

8, 9, 10,

11, 12, 13,

14, 16, 17

/ 8, 9,

10, 11,

12, 13, 14

NC 8 15

AUX IN 11 18

Address/Mode Inputs: The Address/Mode Inputs have two functions
depending on the level of the two Most Significant Bits (MSB) of the
address pins A7 and A8.

If either or both of the two MSBs are LOW, the inputs are all interpreted
as address bits and are used as the start address for the current record
or playback cycle. The address pins are inputs only and do not output
any internal address information during the operation. Address inputs

are latched by the falling edge of

CE .

If both MSBs are HIGH, the Address/Mode inputs are interpreted as
Mode bits according to the Operational Mode table on page 12. There
are six operational modes (M0…M6) available as indicated in the table.
It is possible to use multiple operational modes simultaneously.

Operational Modes are sampled on each falling edge of

CE , and thus

Operational Modes and direct addressing are mutually exclusive.

No Connect.

Auxiliary Input: The Auxiliary Input is multiplexed through to the output

amplifier and speaker output pins when

CE is HIGH, P/ R is HIGH,

and playback is currently not active or if the device is in playback
overflow. When cascading multiple ISD2500 devices, the AUX IN pin is
used to connect a playback signal from a following device to the
previous output speaker drivers. For noise considerations, it is
suggested that the auxiliary input not be driven when the storage array
is active.

V

, V

SSA

13, 12 20, 19

SSD

Ground: The ISD2500 series of devices utilizes separate analog and
digital ground busses. These pins should be connected separately
through a low-impedance path to power supply ground.

SP+, SP- 14, 15 21, 22

Speaker Outputs: All devices in the ISD2500 series include an on-chip
differential speaker driver, capable of driving 50 mW into 16 Ω from
AUX IN (12.2mW from memory).

[1]

The speaker outputs are held at V

down. It is therefore not possible to parallel speaker outputs of multiple
ISD2500 devices or the outputs of other speaker drivers.

[2]

A single-end output may be used (including a coupling capacitor
between the SP pin and the speaker). These outputs may be used
individually with the output signal taken from either pin. However, the
use of single-end output results in a 1 to 4 reduction in its output power.

[1]

Connection of speaker outputs in parallel may cause damage to the device.

[2]

Never ground or drive an unused speaker output.

- 6 -

levels during record and power

SSA

PIN NAME

V

, V

CCA

PIN NO.

SOIC/

PDIP

16, 28 23, 7

CCD

TSOP

ISD2532/40/48/64

FUNCTION

Supply Voltage: To minimize noise, the analog and digital circuits

in the ISD2500 series devices use separate power busses. These
voltage busses are brought out to separate pins and should be tied
together as close to the supply as possible. In addition, these
supplies should be decoupled as close to the package as possible.

MIC 17 24

MIC REF 18 25

AGC 19 26

ANA IN 20 27

Microphone: The microphone pin transfers input signal to the on­chip preamplifier. A built-in Automatic Gain Control (AGC) circuit
controls the gain of this preamplifier from –15 to 24dB. An external
microphone should be AC coupled to this pin via a series capacitor.
The capacitor value, together with the internal 10 KΩ resistance on
this pin, determines the low-frequency cutoff for the ISD2500 series
passband. See Winbond’s Application Information for additional
information on low-frequency cutoff calculation.

Microphone Reference: The MIC REF input is the inverting input
to the microphone preamplifier. This provides a noise-canceling or
common-mode rejection input to the device when connected to a
differential microphone.

Automatic Gain Control: The AGC dynamically adjusts the gain of
the preamplifier to compensate for the wide range of microphone
input levels. The AGC allows the full range of whispers to loud
sounds to be recorded with minimal distortion. The “attack” time is
determined by the time constant of a 5 KΩ internal resistance and
an external capacitor (C2 on the schematic of Figure 5 in section

11) connected from the AGC pin to V
“release” time is determined by the time constant of an external
resistor (R2) and an external capacitor (C2) connected in parallel
between the AGC pin and V
470 KΩ and 4.7 µF give satisfactory results in most cases.

Analog Input: The analog input transfers analog signal to the chip
for recording. For microphone inputs, the ANA OUT pin should be
connected via an external capacitor to the ANA IN pin. This
capacitor value, together with the 3.0 KΩ input impedance of ANA
IN, is selected to give additional cutoff at the low-frequency end of
the voice passband. If the desired input is derived from a source
other than a microphone, the signal can be fed, capacitively
coupled, into the ANA IN pin directly.

analog ground. Nominal values of

SSA

analog ground. The

SSA

Publication Release Date: June 2003

- 7 - Revision 1.0

PIN NAME

PIN NO.

SOIC/

PDIP

TSOP

ISD2532/40/48/64

FUNCTION

ANA OUT 21 28

OVF

CE

PD 24 3

22 1

23 2

Analog Output: This pin provides the preamplifier output to the
user. The voltage gain of the preamplifier is determined by the
voltage level at the AGC pin.

Overflow: This signal pulses LOW at the end of memory array,
indicating the device has been filled and the message has

overflowed. The
PD pulse has reset the device. This pin can be used to cascade
several ISD2500 devices together to increase record/playback
durations.

Chip Enable: The CE input pin is taken LOW to enable all
playback and record operations. The address pins and

playback/record pin (P/R ) are latched by the falling edge of CE .

CE has additional functionality in the M6 (Push-Button)

Operational Mode as described in the Operational Mode section.

Power Down: When neither record nor playback operation, the PD
pin should be pulled HIGH to place the part in standby mode (see

I

specification). When overflow ( OVF ) pulses LOW for an

SB

overflow condition, PD should be brought HIGH to reset the
address pointer back to the beginning of the memory array. The PD
pin has additional functionality in the M6 (Push-Button) Operation
Mode as described in the Operational Mode section.

OVF output then follows the CE input until a

EOM

25 4

End-Of-Message: A nonvolatile marker is automatically inserted at
the end of each recorded message. It remains there until the

message is recorded over. The
period of T

In addition, the ISD2500 series has an internal V
maintain message integrity should V

When the device is configured in Operational Mode M6 (Push­Button Mode), this pin provides an active-HIGH signal, indicating
the device is currently recording or playing. This signal can
conveniently drive an LED for visual indicator of a record or
playback operation in process.

EOM output pulses LOW for a

at the end of each message.

EOM

detect circuit to

CC

fall below 3.5V. In this case,

CC

EOM goes LOW and the device is fixed in Playback-only mode.

- 8 -

PIN NAME

PIN NO.

SOIC/

PDIP

TSOP

ISD2532/40/48/64

FUNCTION

XCLK 26 5

P/ R

27 6

External Clock: The external clock input has an internal pull-down
device. The device is configured at the factory with an internal
sampling clock frequency centered to ±1 percent of specification.
The frequency is then maintained to a variation of ±2.25 percent
over the entire commercial temperature and operating voltage
ranges. If greater precision is required, the device can be clocked
through the XCLK pin as follows:

These recommended clock rates should not be varied because the
antialiasing and smoothing filters are fixed, and aliasing problems
can occur if the sample rate differs from the one recommended.
The duty cycle on the input clock is not critical, as the clock is
immediately divided by two. If the XCLK is not used, this input

must be connected to ground.

Playback/Record: The P/R input pin is latched by the falling edge

of the
level selects a record cycle. For a record cycle, the address pins
provide the starting address and recording continues until PD or

CE is pulled HIGH or an overflow is detected (i.e. the chip is full).

When a record cycle is terminated by pulling PD or

then End-Of-Message (
address in memory. For a playback cycle, the address inputs

provide the starting address and the device will play until an

marker is encountered. The device can continue to pass an EOM

marker if CE is held LOW in address mode, or in an Operational
Mode. (See Operational Modes section)

Part Number Sample Rate Required Clock

ISD2532 8.0 kHz 1024 kHz

ISD2540 6.4 kHz 819.2 kHz

ISD2548 5.3 kHz 682.7 kHz

ISD2564 4.0 kHz 512 kHz

CE pin. A HIGH level selects a playback cycle while a LOW

CE HIGH,

EOM ) marker is stored at the current

EOM

Publication Release Date: June 2003

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ISD2532/40/48/64

7. FUNCTIONAL DESCRIPTION

7.1. DETAILED DESCRIPTION

Speech/Sound Quality

The Winbond’s ISD2500 series includes devices offered at 4.0, 5.3, 6.4, and 8.0 kHz sampling
frequencies, allowing the user a choice of speech quality options. Increasing the duration within a
product series decreases the sampling frequency and bandwidth, which affects the sound quality.
Please refer to the ISD2532/40/48/64 Product Summary table below to compare the duration,
sampling frequency and filter pass band.

The speech samples are stored directly into the on-chip nonvolatile memory without any digitization
and compression associated like other solutions. Direct analog storage provides a very true, natural
sounding reproduction of voice, music, tones, and sound effects not available with most solid state
digital solutions.

Duration

To meet various system requirements, the ISD2532/40/48/64 products offer single-chip solutions at
32, 40, 48, and 64 seconds. Parts may also be cascaded together for longer durations.

TABLE 1: ISD2532/40/48/64 PRODUCT SUMMARY

Part Number Duration

(Seconds)

ISD2532 32 8.0 3.4

ISD2540 40 6.4 2.7

ISD2548 48 5.3 2.3

ISD2564 64 4.0 1.7

* 3dB roll off point. This parameter is not checked during production testing and may vary due

to process variations and other factors. Therefore, customer should not rely on this value for
testing purposes.

EEPROM Storage

One of the benefits of Winbond’s ChipCorder
providing zero-power message storage. The message is retained for up to 100 years typically without
power. In addition, the device can be re-recorded typically over 100,000 times.

Microcontroller Interface

In addition to its simplicity and ease of use, the ISD2500 series includes all the interfaces necessary
for microcontroller-driven applications. The address and control lines can be interfaced to a
microcontroller and manipulated to perform a variety of tasks, including message assembly, message
concatenation, predefined fixed message segmentation, and message management.

Input Sample

Rate (kHz)

®

technology is the use of on-chip nonvolatile memory,

Typical Filter Pass

Band * (kHz)

- 10 -

ISD2532/40/48/64

Programming

The ISD2500 series is also ideal for playback-only applications, where single or multiple messages
are referenced through buttons, switches, or a microcontroller. Once the desired message
configuration is created, duplicates can easily be generated via a gang programmer.

7.2. OPERATIONAL MODES

The ISD2500 series is designed with several built-in Operational Modes that provide maximum
functionality with minimum external components. These modes are described in details as below. The
Operational Modes are accessed via the address pins and mapped beyond the normal message
address range. When the two Most Significant Bits (MSB), A7 and A8, are HIGH, the remaining
address signals are interpreted as mode bits and not as address bits. Therefore, Operational Modes
and direct addressing are not compatible and cannot be used simultaneously.

There are two important considerations for using Operational Modes. First, all operations begin initially
at address 0 of its memory. Later operations can begin at other address locations, depending on the
Operational Mode(s) chosen. In addition, the address pointer is reset to 0 when the device is changed
from record to playback, playback to record (except M6 mode), or when a Power-Down cycle is
executed.

Second, Operational Modes are executed when

effect until the next LOW-going

CE signal, at which point the current mode(s) are sampled and

CE goes LOW. This Operational Mode remains in

executed.

TABLE 2: OPERATIONAL MODES

[1]

Mode

Function Typical Use Jointly Compatible

M0 Message cueing Fast-forward through messages M4, M5, M6

M1

Delete

EOM markers Position EOM marker at the end of

M3, M4, M5, M6

the last message

M2 Not applicable Reserved N/A

M3 Looping Continuous playback from Address 0 M1, M5, M6

M4 Consecutive

addressing

M5

CE level-activated

Record/playback multiple

M0, M1, M5

consecutive messages

Allows message pausing M0, M1, M3, M4

M6 Push-button control Simplified device interface M0, M1, M3

[1]

Besides mode pin needed to be “1”, A7 and A8 pin are also required to be “1” in order to enter into the related operational
mode.

[2]

Indicates additional Operational Modes which can be used simultaneously with the given mode.

[2]

Publication Release Date: June 2003

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ISD2532/40/48/64

7.2.1. Operational Modes Description

The Operational Modes can be used in conjunction with a microcontroller, or they can be hardwired to
provide the desired system operation.

M0 – Message Cueing

Message Cueing allows the user to skip through messages, without knowing the actual physical

addresses of each message. Each
next message. This mode is used for playback only, and is typically used with the M4 Operational
Mode.

CE LOW pulse causes the internal address pointer to skip to the

M1 – Delete

The M1 Operational Mode allows sequentially recorded messages to be combined into a single

message with only one
Mode is configured, messages recorded sequentially are played back as one continuous message.

M2 – Unused

When Operational Modes are selected, the M2 pin should be LOW.

M3 – Message Looping

The M3 Operational Mode allows for the automatic, continuously repeated playback of the message
located at the beginning of the address space. A message can completely fill the ISD2500 device and

will loop from beginning to end without

M4 – Consecutive Addressing

During normal operation, the address pointer will reset when a message is played through an EOM

marker. The M4 Operational Mode inhibits the address pointer reset on
be played back consecutively.

EOM Markers

EOM marker set at the end of the final message. When this Operational

OVF going LOW.

EOM , allowing messages to

M5 -

CE -Level Activated

The default mode for ISD2500 devices is for

activated on record. The M5 Operational Mode causes the
activated as opposed to edge-activated during playback. This is especially useful for terminating

playback operations using the CE signal. In this mode, CE LOW begins a playback cycle, at the

beginning of the device memory. The playback cycle continues as long as

CE goes HIGH, playback will immediately end. A new CE LOW will restart the message from the

beginning unless M4 is also HIGH.

CE to be edge-activated on playback and level-

CE pin to be interpreted as level-

CE is held LOW. When

- 12 -

ISD2532/40/48/64

M6 – Push-Button Mode

The ISD2500 series contain a Push-Button Operational Mode. The Push-Button Mode is used
primarily in very low-cost applications and is designed to minimize external circuitry and components,
thereby reducing system cost. In order to configure the device in Push-Button Operational Mode, the
two most significant address bits must be HIGH, and the M6 mode pin must also be HIGH. A device in

this mode always powers down at the end of each playback or record cycle after

When this operational mode is implemented, three of the pins on the device have alternate
functionality as described in the table below.

TABLE 3: ALTERNATE FUNCTIONALITY IN PINS

Pin Name Alternate Functionality in Push-Button Mode

CE

PD Stop/Reset Push-Button (HIGH pulse-activated)

EOM

Start/Pause Push-Button (LOW pulse-activated)

Active-HIGH Run Indicator

CE goes HIGH.

CE (START/PAUSE)

In Push-Button Operational Mode,
If no operation is currently in progress, a LOW-going pulse on this signal will initiate a playback or

record cycle according to the level on the P/R pin. A subsequent pulse on the CE pin, before an

EOM is reached in playback or an overflow condition occurs, will pause the current operation, and

the address counter is not reset. Another
from the place where it is paused.

PD (STOP/RESET)

In Push-Button Operational Mode, PD acts as a HIGH-going pulse-activated STOP/RESET signal.
When a playback or record cycle is in progress and a HIGH-going pulse is observed on PD, the
current cycle is terminated and the address pointer is reset to address 0, the beginning of the
message space.

EOM (RUN)

In Push-Button Operational Mode,
drive an LED or other external device. It is HIGH whenever a record or playback operation is in
progress.

Recording in Push-Button Mode

1. The PD pin should be LOW, usually using a pull-down resistor.

CE acts as a LOW-going pulse-activated START/PAUSE signal.

CE pulse will cause the device to continue the operation

EOM becomes an active-HIGH RUN signal which can be used to

Publication Release Date: June 2003

- 13 - Revision 1.0