White Electronic Designs WS512K32N-45H1QA, WS512K32N-45H1Q, WS512K32N-45H1MA, WS512K32N-45H1IA, WS512K32N-45H1I Datasheet
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WS512K32-XXX
512Kx32 SRAM MODULE, SMD 5962-94611
FEATURES
n Access Times of 15*, 17, 20, 25, 35, 45, 55ns
n Packaging
66 pin, PGA Type, 1.075" square, Hermetic Ceramic HIP
(Package 400).
68 lead, 40mm Hermetic Low Profile CQFP, 3.5mm (0.140")
(Package 502)
1
, Package to be developed.
68 lead, Hermetic CQFP (G2T)
1
, 22.4mm (0.880") square
(Package 509) 4.57mm (0.180") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3).
68 lead, Hermetic CQFP (G1U), 23.9mm (0.940") square
(Package 519) 3.57mm (0.140") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3).
68 lead, Hermetic CQFP (G1U), 23.9mm (0.940") square
(Package 524) 4.06mm (0.160") height.
n Organized as 512Kx32, User Configurable as 1Mx16 or 2Mx8
FIG. 1 PIN CONFIGURATION FOR WS512K32N-XH1X
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-18 Address Inputs
WE1-4 Write Enables
CS1-4 Chip Selects
OE Output Enable
VCC Power Supply
GND Ground
NC Not Connected
TOP VIEW
BLOCK DIAGRAM
n Commercial, Industrial and Military Temperature Ranges
n TTL Compatible Inputs and Outputs
n 5 Volt Power Supply
n Low Power CMOS
n Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
n Weight
WS512K32-XH1X - 13 grams typical
WS512K32-XG2TX
1
- 8 grams typical
WS512K32-XG1UX - 5 grams typical
WS512K32-XG1TX - 5 grams typical
WS512K32-XG4TX
1
- 20 grams typical
* 15ns Access Time available only in Commercial and Industrial Temperature.
This speed is not fully characterized and is subject to change without notice.
Note 1: Package Not Recommended For New Design
November 2001 Rev. 9
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WS512K32-XXX
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
PIN DESCRIPTION
FIG. 2 PIN CONFIGURATION FOR WS512K32-XG4TX
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TOP VIEW
BLOCK DIAGRAM
I/O0-31 Data Inputs/Outputs
A0-18 Address Inputs
WE Write Enables
CS1-4 Chip Selects
OE Output Enable
VCC Power Supply
GND Ground
NC Not Connected
FIG. 3 PIN CONFIGURATION FOR WS512K32-XG2TX
1
, WS512K32-XG1TX
AND WS512K32-XG1UX
TOP VIEW
The White 68 lead CQFP fills
the same fit and function as the
JEDEC 68 lead CQFJ or 68
PLCC. But the CQFJ has the
TCE and lead inspection
advantage of the CQFP form.
PIN DESCRIPTION
BLOCK DIAGRAM
I/O0-31 Data Inputs/Outputs
A0-18 Address Inputs
WE1-4 Write Enables
CS1-4 Chip Selects
OE Output Enable
VCC Power Supply
GND Ground
NC Not Connected
Note 1: Package Not Recommended For New Design
Note 1: Package Not Recommended For New Design
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WS512K32-XXX
Parameter Symbol Min Ma x Unit
Operating Temperature T
A -55 +125 °C
Storage Temperature T
STG -65 +150 °C
Signal Voltage Relative to GND V
G -0.5 Vcc+0.5 V
Junction Temperature T
J 150 °C
Supply Voltage V
CC -0.5 7.0 V
TRUTH TABLE
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Unit
Supply Voltage V
CC 4.5 5.5 V
Input High Voltage V
IH 2.2 VCC + 0.3 V
Input Low Voltage V
IL -0.5 +0.8 V
Operating Temp (Mil) T
A -55 +125 °C
CAPACITANCE
(TA = +25°C)
Parameter
Symbol
Conditions Max Unit
OE capacitance COE
VIN = 0 V, f = 1.0 MHz
50 pF
WE
1-4 capacitance CWE
VIN = 0 V, f = 1.0 MHz
pF
HIP (PGA) 20
CQFP G4T 5 0
CQFP G2T/G1U/G1T 20
CS1-4 capacitance CCS
VIN = 0 V, f = 1.0 MHz
20 pF
Data I/O capacitance CI/O
V
I/O
= 0 V, f = 1.0 MHz
20 pF
Address input capacitance C
AD
V
IN
= 0 V, f = 1.0 MHz
50 pF
This parameter is guaranteed by design but not tested.
Parameter Symbol Conditions Units
Min Max
Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 µA
Output Leakage Current ILO CS = VIH , OE = VIH, VOUT = GND to VCC 10 µA
Operating Supply Current x 32 Mode ICC x 32 CS = VIL, OE = VIH, f = 5MHz, Vcc = 5.5 6 60 mA
Standby Current ISB CS = VIH, OE = VIH , f = 5MHz, Vcc = 5.5 80 mA
Output Low Voltage V
OL IOL = 8mA for 15 - 35ns, 0. 4 V
IOL = 2.1mA for 45 - 55ns, Vcc = 4.5
Output High Voltage V
OH IOH = -4.0mA for 15 - 35ns, 2. 4 V
I
OH = -1.0mA for 45 - 55ns, Vcc = 4.5
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
DC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
DATA RETENTION CHARACTERISTICS
(TA = -55°C to +125°C)
Parameter Symbol Conditions Units
Min Max
Data Retention Supply Voltage VDR CS £ V CC -0.2V 2.0 5.5 V
Data Retention Current ICCDR1 VCC = 3V 28 mA
Low Power Data Retention I
CCDR2 VCC = 3V 16 mA
C ur r en t (WS512K32L-XXX)
CS OE WE Mode Data I/O Power
H X X Standby High Z Standby
L L H Read Data Out Active
L H H Out Disable High Z Active
L X L Write Data In Active
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WS512K32-XXX
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
AC CHARACTERISTICS
(V
CC
= 5.0V, VSS = 0V, TA = -55°C to +125°C)
FIG. 4
AC TEST CIRCUIT
NOTES:
V
Z is programmable from -2V to +7V.
I
OL & IOH programmable from 0 to 16mA.
Tester Impedance Z
0 = 75 ý.
V
Z is typically the midpoint of VOH and VOL.
I
OL & IOH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
AC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
AC TEST CONDITIONS
Parameter Typ Unit
Input Pulse Levels VIL = 0, VIH = 3.0 V
Input Rise and Fall 5 ns
Input and Output Reference Level 1. 5 V
Output Timing Reference Level 1.5 V
Parameter Symbol -15* -17 -20 -25 -35 -45 -55 Units
Write Cycle Mi n Max Mi n Ma x Mi n Ma x Mi n Ma x Mi n Ma x Min Max Mi n Ma x
Write Cycle Time tWC 15 17 20 25 35 45 55 ns
Chip Select to End of Write tCW 13 15 15 17 25 35 50 ns
Address Valid to End of Write t AW 13 15 15 17 25 35 50 ns
Data Valid to End of Write tDW 10 11 12 13 20 25 25 ns
Write Pulse Width tWP 13 15 15 17 25 35 40 ns
Address Setup Time tAS 22222 22ns
Address Hold Time tAH 00000 55ns
Output Active from End of Write tOW
1
22344 55ns
Write Enable to Output in High Z tWHZ
1
8 9 11 13 15 20 20 ns
Data Hold Time t
DH 00000 00ns
* 15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice.
1. This parameter is guaranteed by design but not tested.
2. The Address Setup Time of minimum 2ns is for the G2T, G1U and H1 packages. t
AS minimum for the G4T package is 0ns.
Parameter Symbol
-15* -17 -20 -25 -35 -45 -55 Units
Read Cycle Mi n Ma x Mi n Max Min Max Min Ma x Min Max Min Max Min Ma x
Read Cycle Time tRC 15 17 20 25 35 45 55 ns
Address Access Time tAA 15 17 20 25 35 45 55 ns
Output Hold from Address Change t OH 0000000ns
Chip Select Access Time tACS 15 17 20 25 35 45 55 ns
Output Enable to Output Valid tOE 8 9 10 12 25 25 25 ns
Chip Select to Output in Low Z tCLZ
1
2222444ns
Output Enable to Output in Low Z tOLZ
1
0000000ns
Chip Disable to Output in High Z tCHZ
1
12 12 12 12 15 20 20 ns
Output Disable to Output in High Z t
OHZ
1
12 12 12 12 15 20 20 ns
* 15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice.
1. This parameter is guaranteed by design but not tested.
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