White Electronic Designs WME128K8-300CCA, WME128K8-250DEQA, WME128K8-250DEQ, WME128K8-250DEMA, WME128K8-250DEM Datasheet

1 White Electronic Designs Corporation  [phone]  www.whiteedc.com

White Electronic Designs

WME128K8-XXX

A0-16 Address Inputs

I/O0-7 Data Input/Output

CS Chip Select

OE Output Enable

WE Write Enable

Vcc +5.0V Power

V

SS Ground

February 2002 Rev. 3

FEATURES

■ Read Access Times of 120, 140, 150, 200, 250, 300ns

■ JEDEC Approved Packages

 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300)
 32 lead, Hermetic Ceramic, 0.400" SOJ (Package

101)

■ Commercial, Industrial and Military Temperature
Ranges

■ MIL-STD-883 Compliant Devices Available

■ Write Endurance 10,000 Cycles

■ Data Retention at 25°C, 10 Years

■ Low Power CMOS Operation

■ Automatic Page Write Operation

 Internal Address and Data Latches for 128 Bytes

 Internal Control Timer

■ Page Write Cycle Time 10ms Max.

■ Data Polling for End of Write Detection

■ Hardware and Software Data Protection

■ TTL Compatible Inputs and Outputs

FIG. 1

PIN CONFIGURATION

32 DIP

32 CSOJ

TOP VIEW

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

NC

A16

A15

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O0

I/O1

I/O2

V

SS

V

CC

WE

NC

A14

A13

A8

A9

A11

OE

A10

CS

I/O7

I/O6

I/O5

I/O4

I/O3

PIN DESCRIPTION

128Kx8 CMOS MONOLITHIC EEPROM, SMD 5962-96796

2

White Electronic Designs Corporation  Phoenix AZ  [phone]

White Electronic Designs

WME128K8-XXX

I

Current Source

D.U.T.

C = 50 pf

eff

I

OL

V ≈ 1.5V

(Bipolar Supply)

Z

Current Source

OH

FIG. 2

AC TEST CIRCUIT

Parameter Symbol Conditions Unit

Min Max

Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 µA
Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = GND to VCC 10 µA
Dynamic Supply Current ICC CS = VIL, OE = VIH, f = 5MHz, Vcc = 5.5 80 mA
Standby Current ISB CS = VIH, OE = VIH, f = 5MHz, Vcc = 5.5 0.625 mA
Output Low Voltage VOL IOL = 2.1mA, Vcc = 4.5V .45 V
Output High Voltage V

OH IOH = -400µA, Vcc = 4.5V 2.4 V

NOTE: DC test conditions: V

IH = VCC -0.3V, VIL = 0.3V

TRUTH TABLEABSOLUTE MAXIMUM RATINGS

CAPACITANCE

(TA = +25°C)

NOTE:

Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

DC CHARACTERISTICS

(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)

RECOMMENDED OPERATING CONDITIONS

AC TEST CONDITIONS

Notes:
V

Z is programmable from -2V to +7V.

I

OL & IOH programmable from 0 to 16mA.

Tester Impedance Z

0 = 75 W.

V

Z is typically the midpoint of VOH and VOL.

I

OL & IOH

are adjusted to simulate a typical resistive load circuit.

ATE tester includes jig capacitance.

Parameter Symbol Unit

Operating Temperature TA -55 to +125 °C
Storage Temperature TSTG -65 to +150 °C
Signal Voltage Any Pin VG -0.6 to + 6.25 V
Voltage on OE and A9 -0.6 to +13.5 V

CS OE WE Mode Data I/O

H X X Standby High Z

L L H Read Data Out

L H L Write Data In
X H X Out Disable High Z/Data Out
X X H Write
X L X Inhibit

Parameter Sym Condition Unit

Max

Input Capacitance CIN VIN = 0V, f = 1MHz 20 pF
Output Capacitance C

OUT VI/O = 0V, f = 1MHz 20 pF

This parameter is guaranteed by design but not tested.

Parameter Symbol Min Max Unit

Supply Voltage VCC 4.5 5.5 V

Input High Voltage VIH 2.0 VCC + 0. 3 V

Input Low Voltage VIL -0.3 +0.8 V

Operating Temp. (Mil.) TA -55 +125 °C

Operating Temp. (Ind.) T

A -4 0 +85 °C

Parameter Typ Unit

Input Pulse Levels VIL = 0, VIH = 3.0 V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V

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White Electronic Designs

WME128K8-XXX

Parameter Symbol -120 -140 -150 -200 -250 -300 Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Read Cycle Time tRC 120 140 150 200 250 300 ns

Address Access Time tACC 120 140 150 200 250 300 ns

Chip Select Access Time tACS 120 140 150 200 250 300 ns

Output Hold from Address Change, OE or CS tOH 00 0000ns

Output Enable to Output Valid tOE 50 55 55 55 85 85 ns

Chip Select or Output Enable to High Z Output t

DF 70 70 70 70 70 70 ns

Figure 3 shows Read cycle waveforms. A read cycle be­gins with selection address, chip select and output en­able. Chip select is accomplished by placing the CS line
low. Output enable is done by placing the OE line low.
The memory places the selected data byte on I/O

0 through

I/O

7 after the access time. The output of the memory is

placed in a high impedance state shortly after either the
OE line or CS line is returned to a high level.

READ

AC READ CHARACTERISTICS (SEE FIGURE 3)

(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)

FIG. 3 READ WAVEFORMS

t

A

DDRESS

CS

OE

OUTPUT

OH

t

DF

t

ACC

t

RC

t

OE

t

ACS

OUTPUT

VALID

ADDRESS VALID

HIGH Z

NOTE:
OE may be delayed up to t

ACS- tOE after the falling edge of CS

without impact on t

OE or by tACC- tOE after an address change without

impact on t

ACC.

4

White Electronic Designs Corporation  Phoenix AZ  [phone]

White Electronic Designs

WME128K8-XXX

WRITE CYCLE TIMING

Figures 4 and 5 show the write cycle timing relation­ships. A write cycle begins with address application,
write enable and chip select. Chip select is accom­plished by placing the CS line low. Write enable con­sists of setting the WE line low. The write cycle begins
when the last of either CS or WE goes low.

The WE line transition from high to low also initiates an
internal 150µsec delay timer to permit page mode op­eration. Each subsequent WE transition from high to
low that occurs before the completion of the 150µsec
time out will restart the timer from zero. The operation
of the timer is the same as a retriggerable one-shot.

Write operations are initiated when both CS and WE
are low and OE is high. The EEPROM devices support
both a CS and WE controlled write cycle. The address
is latched by the falling edge of either CS or WE, which­ever occurs last.

The data is latched internally by the rising edge of ei­ther CS or WE, whichever occurs first. A byte write
operation will automatically continue to completion.

WRITE

AC WRITE CHARACTERISTICS

(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)

Parameter Symbol 128Kx8 Unit

Min Max

Write Cycle Time, TYP = 6ms tWC 10 ms
Address Set-up Time tAS 10 ns
Write Pulse Width (WE or CS) tWP 150 ns
Chip Select Set-up Time tCS 0ns
Address Hold Time tAH 100 ns
Data Hold Time tDH 10 ns
Chip Select Hold Time tCH 0ns
Data Set-up Time tDS 100 ns
Output Enable Set-up Time tOES 10 ns
Output Enable Hold Time tOEH 10 ns
Write Pulse Width High t

WPH 50 ns