White Electronic Designs WE128K32P-300G4Q, WE128K32P-300G4MA, WE128K32P-300G4M, WE128K32P-300G4IA, WE128K32P-300G4I Datasheet

1

White Electronic Designs Corporation • [phone] • www.whiteedc.com

HI-RELIABILITY PRODUCT

WE128K32-XXX

128Kx32 EEPROM MODULE, SMD 5962-94585

TOP VIEW

PIN DESCRIPTION

I/O0-31 Data Inputs/Outputs

A0-16 Address Inputs

WE1-4 Write Enables

CS1-4 Chip Selects

OE Output Enable

VCC Power Supply

GND Ground

NC Not Connected

BLOCK DIAGRAM

I/O

8

I/O

9

I/O

10

A

13

A

14

A

15

A

16

NC

I/O

0

I/O

1

I/O

2

WE

2

CS

2

GND

I/O

11

A

10

A

11

A

12

V

CC

CS

1

NC

I/O

3

I/O

15

I/O

14

I/O

13

I/O

12

OE

NC

WE

1

I/O

7

I/O

6

I/O

5

I/O

4

I/O

24

I/O

25

I/O

26

A

6

A

7

NC

A

8

A

9

I/O

16

I/O

17

I/O

18

V

CC

CS

4

WE

4

I/O

27

A

3

A

4

A

5

WE

3

CS

3

GND

I/O

19

I/O

31

I/O

30

I/O

29

I/O

28

A

0

A

1

A

2

I/O

23

I/O

22

I/O

21

I/O

20

11 22 33 44 55 66

1 12 23 34 45 56

128K x 8

8

I/O

0-7

CS

1

128K x 8

8

I/O

8-15

2

128K x 8

8

I/O

16-23

3

128K x 8

8

I/O

24-31

4

A

0-16

OE

WE

CS

WE

CS

WE

CS

WE

1234

FEATURES

■ Access Times of 120*, 140, 150, 200, 250, 300ns

■ Packaging:

• 66-pin, PGA Type, 27.3mm (1.075") square, Hermetic
Ceramic HIP (Package 400)

• 68 lead, 40mm CQFP (G4), (Package 501)

• 68 lead, 22.4mm sq. CQFP (G2T), 4.57mm (0.180") high,
(Package 509)

• 68 lead, 22.4mm sq. Low Profile CQFP (G1U), 3.57mm
(0.140") high, (Package 519)

■ Organized as 128Kx32; User Configurable as 256Kx16 or 512Kx8

■ Write Endurance 10,000 Cycles

■ Data Retention Ten Years Minimum (at +25°C)

■ Commercial, Industrial and Military Temperature Ranges

■ Low Power CMOS

■ Automatic Page Write Operation

■ Page Write Cycle Time: 10ms Max

■ Data Polling for End of Write Detection

■ Hardware and Software Data Protection

■ TTL Compatible Inputs and Outputs

■ 5 Volt Power Supply

■ Built-in Decoupling Caps and Multiple Ground Pins for Low

Noise Operation

■ Weight

WE128K32-XG2TX - 8 grams typical
WE128K32-XG1UX - 5 grams typical
WE128K32-XH1X - 13 grams typical
WE128K32-XG4X - 20 grams typical

* 120ns not available for SMD product

FIG. 1 PIN CONFIGURATION FOR WE128K32N-XH1X

July 2001 Rev. 5

2

White Electronic Designs Corporation • [phone] • www.whiteedc.com

WE128K32-XXX

FIG. 2 PIN CONFIGURATION FOR WE128K32-XG4X

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

I/O

0

I/O

1

I/O

2

I/O

3

I/O

4

I/O

5

I/O

6

I/O

7

GND

I/O

8

I/O

9

I/O

10

I/O

11

I/O

12

I/O

13

I/O

14

I/O

15

V

CC

A11A12A13A14A15A

16

CS2OECS4

NC

NC

NCNCNCNCNC

I/O

16

I/O

17

I/O

18

I/O

19

I/O

20

I/O

21

I/O

22

I/O

23

GND
I/O

24

I/O

25

I/O

26

I/O

27

I/O

28

I/O

29

I/O

30

I/O

31

NC

A0A1A2A3A4A5CS1GND

CS3WE

A6A7A8A9A10V

CC

PIN DESCRIPTION

BLOCK DIAGRAM

TOP VIEW

128K x 8

8

I/O

0-7

CS

1

128K x 8

8

I/O

8-15

CS

2

128K x 8

8

I/O

16-23

CS

3

128K x 8

8

I/O

24-31

CS

A0-

16

OE

WE

4

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

I/O

0

I/O

1

I/O

2

I/O

3

I/O

4

I/O

5

I/O

6

I/O

7

GND

I/O

8

I/O

9

I/O

10

I/O

11

I/O

12

I/O

13

I/O

14

I/O

15

V

CC

A11A12A13A14A15A

16

CS

1

OE

CS

2

NC

WE

2WE3WE4

NC

NC

NC

I/O

16

I/O

17

I/O

18

I/O

19

I/O

20

I/O

21

I/O

22

I/O

23

GND
I/O

24

I/O

25

I/O

26

I/O

27

I/O

28

I/O

29

I/O

30

I/O

31

NC

A0A1A2A3A4A5CS3GND

CS4WE1A6A7A8A9A10V

CC

PIN DESCRIPTION

FIG. 3 PIN CONFIGURATION FOR WE128K32-XG2TX AND WE128K32-XG1UX

BLOCK DIAGRAM

128K x 8

8

I/O

0-7

CS

1

128K x 8

8

I/O

8-15

2

128K x 8

8

I/O

16-23

3

128K x 8

8

I/O

24-31

4

A

0-16

OE

WE

CS

WE

CS

WE

CS

WE

1234

TOP VIEW

The White 68 lead G2T/G1U
CQFP fills the same fit and
function as the JEDEC 68 lead
CQFJ or 68 PLCC. But the G2T/
G1U has the TCE and lead
inspection advantage of the
CQFP form.

I/O0-31 Data Inputs/Outputs

A0-16 Address Inputs

WE1-4 Write Enables

CS1-4 Chip Selects

OE Output Enable

VCC Power Supply

GND Ground

NC Not Connected

I/O0-31 Data Inputs/Outputs

A0-16 Address Inputs

WE Write Enables

CS1-4 Chip Selects

OE Output Enable

VCC Power Supply

GND Ground

NC Not Connected

0.940"

3

White Electronic Designs Corporation • [phone] • www.whiteedc.com

WE128K32-XXX

ABSOLUTE MAXIMUM RATINGS TRUTH TABLE

FIG. 4

AC TEST CIRCUIT

AC TEST CONDITIONS

I

Current Source

D.U.T.

C = 50 pf

eff

I

OL

V ≈ 1.5V
(Bipolar Supply)

Z

Current Source

OH

NOTES:

V

Z is programmable from -2V to +7V.

I

OL & IOH programmable from 0 to 16mA.

Tester Impedance Z

0 = 75 Ω.

V

Z is typically the midpoint of VOH and VOL.

I

OL & IOH

are adjusted to simulate a typical resistive load circuit.

ATE tester includes jig capacitance.

RECOMMENDED OPERATING CONDITIONS

DC CHARACTERISTICS

(V

CC = 5.0V, VSS = 0V, TA = -55°C to +125°C)

Parameter Typ Unit

Input Pulse Levels VIL = 0, VIH = 3.0 V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V

Parameter Symbol Unit

Operating Temperature TA -55 to +125 °C
Storage Temperature TSTG -65 to +150 °C
Signal Voltage Relative to GND VG -0.6 to +6.25 V
Voltage on OE and A9 -0.6 to +13.5 V

NOTE:

Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

CS OE WE Mode Data I/O

H X X Standby High Z

L L H Read Data Out

L H L Write Data In
X H X Out Disable High Z/Data Out
X X H Write
X L X Inhibit

Parameter Symbol Min Max Unit

Supply Voltage VCC 4.5 5.5 V
Input High Voltage VIH 2.0 VCC + 0.3 V
Input Low Voltage VIL -0.5 +0.8 V
Operating Temp. (Mil.) TA -55 +125 °C
Operating Temp. (Ind.) T

A -40 +85 °C

Parameter Symbol Conditions Min Max Unit

Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 µA
Output Leakage Current ILOx32 CS = VIH, OE = VIH, VOUT = GND to VCC 10 µA
Operating Supply Current x 32 Mode ICCx32 CS = VIL, OE = VIH, f = 5MHz 250 mA
Standby Current ISB CS = VIH, OE = VIH, f = 5MHz 2.5 mA
Output Low Voltage VOL IOL = 2.1mA, VCC = 4.5V 0.45 V
Output High Voltage V

OH IOH = -400µA, VCC = 4.5V 2.4 V

NOTE: DC test conditions: V

IH = VCC -0.3V, VIL = 0.3V

CAPACITANCE

(T

A = +25°C)

Parameter

Symbol

Conditions Max Unit

OE capacitance COE

VIN = 0 V, f = 1.0 MHz

50 pF

WE

1-4 capacitance CWEVIN

= 0 V, f = 1.0 MHz

pF
HIP (PGA) 20
CQFP G4 50
CQFP G2T/G1U 20

CS1-4 capacitance CCS

VIN = 0 V, f = 1.0 MHz

20 pF

Data I/O capacitance CI/O

V

I/O

= 0 V, f = 1.0 MHz

20 pF

Address input capacitance C

AD

V

IN

= 0 V, f = 1.0 MHz

50 pF

This parameter is guaranteed by design but not tested.

4

White Electronic Designs Corporation • [phone] • www.whiteedc.com

WE128K32-XXX

WRITE

A write cycle is initiated when OE is high and a low pulse is on WE
or CS with CS or WE low. The address is latched on the falling
edge of CS or WE whichever occurs last. The data is latched by
the rising edge of CS or WE, whichever occurs first. A byte write
operation will automatically continue to completion.

WRITE CYCLE TIMING

Figures 5 and 6 show the write cycle timing relationships. A
write cycle begins with address application, write enable and
chip select. Chip select is accomplished by placing the CS line
low. Write enable consists of setting the WE line low. The
write cycle begins when the last of either CS or WE goes low.

The WE line transition from high to low also initiates an
internal 150 µsec delay timer to permit page mode operation.
Each subsequent WE transition from high to low that occurs
before the completion of the 150 µsec time out will restart the
timer from zero. The operation of the timer is the same as a
retriggerable one-shot.

AC WRITE CHARACTERISTICS

(V

CC

= 5.0V, VSS = 0V, TA = -55°C to +125°C)

Write Cycle Parameter Symbol Min Max Unit

Write Cycle Time, TYP = 6ms tWC 10 ms
Address Set-up Time tAS 0ns
Write Pulse Width (WE or CS) tWP 150 ns
Chip Select Set-up Time tCS 0ns
Address Hold Time tAH 100 ns
Data Hold Time tDH 10 ns
Chip Select Hold Time tCSH 0ns
Data Set-up Time tDS 100 ns
Output Enable Set-up Time tOES 10 ns
Output Enable Hold Time tOEH 10 ns
Write Pulse Width High t

WPH 50 ns

5

White Electronic Designs Corporation • [phone] • www.whiteedc.com

WE128K32-XXX

FIG. 5

WRITE WAVEFORMS
WE CONTROLLED

FIG. 6

WRITE WAVEFORMS
CS CONTROLLED

t

ADDRESS

CS

1-4

WE

1-4

DATA IN

DH

t

WPH

t

WP

t

CSH

t

OEH

t

AH

t

OES

t

AS

t

CS

OE

t

WC

t

DS

t

ADDRESS

WE1 - 4

CS1 - 4

DATA IN

DH

t

WPH

t

WP

t

CSH

t

OEH

t

AH

t

OES

t

AS

t

CS

OE

t

DS

t

WC