White Electronic Designs W3EG6433S-D3, W3EG6433S-JD3 User Manual

White Electronic Designs

W3EG6433S-D3 -JD3

PRELIMINARY*

256MB – 2x16Mx64 DDR SDRAM UNBUFFERED

FEATURES

DDR266 and DDR333

Double-data-rate architecture

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input.

Auto and self refresh

Serial presence detect

Dual Rank

Power supply: 2.5V ± 0.2V

JEDEC 184 pin DIMM package

• JD3 PCB height: 30.48 (1.20")

NOTE: Consult factory for availability of:

•RoHS compliant products

•Vendor source control options

•Industrial temperature option

DESCRIPTION

The W3EG6433S is a 2x16Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM component. The module consists of sixteen 16Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

*This product is under development, is not qualified or characterized and is subject to change without notice.

OPERATING FREQUENCIES

	DDR333@CL=2.5	DDR266 @CL=2	DDR266 @CL=2	DDR266 @CL=2.5
Clock Speed	166MHz	133MHz	133MHz	133MHz
CL-tRCD-tRP	2.5-3-3	2-2-2	2-3-3	2.5-3-3

November 2005	1	White Electronic Designs Corporation • [phone] • www.wedc.com
Rev. 2

White Electronic Designs

W3EG6433S-D3 -JD3

PRELIMINARY

PIN CONFIGURATION

PIN	SYMBOL	PIN	SYMBOL	PIN	SYMBOL	PIN	SYMBOL
1	VREF	47	NC	93	VSS	139	VSS
2	DQ0	48	A0	94	DQ4	140	NC
3	VSS	49	NC	95	DQ5	141	A10
4	DQ1	50	VSS	96	VCCQ	142	NC
5	DQS0	51	NC	97	DQM0	143	VCCQ
6	DQ2	52	BA1	98	DQ6	144	NC
7	VCC	53	DQ32	99	DQ7	145	VSS
8	DQ3	54	VCCQ	100	VSS	146	DQ36
9	NC	55	DQ33	101	NC	147	DQ37
10	NC	56	DQS4	102	NC	148	VCC
11	VSS	57	DQ34	103	NC	149	DM4
12	DQ8	58	VSS	104	VCCQ	150	DQ38
13	DQ9	59	BA0	105	DQ12	151	DQ39
14	DQS1	60	DQ35	106	DQ13	152	VSS
15	VCCQ	61	DQ40	107	DQM1	153	DQ44
16	CK1	62	VCCQ	108	VCC	154	RAS#
17	CK1#	63	WE#	109	DQ14	155	DQ45
18	VSS	64	DQ41	110	DQ15	156	VCCQ
19	DQ10	65	CAS#	111	CKE1	157	CS0#
20	DQ11	66	VSS	112	VCCQ	158	CS1#
21	CKE0	67	DQS5	113	NC	159	DM5
22	VCCQ	68	DQ42	114	DQ20	160	VSS
23	DQ16	69	DQ43	115	NC	161	DQ46
24	DQ17	70	VCC	116	VSS	162	DQ47
25	DQS2	71	NC	117	DQ21	163	NC
26	VSS	72	DQ48	118	A11	164	VCCQ
27	A9	73	DQ49	119	DM2	165	DQ52
28	DQ18	74	VSS	120	VCC	166	DQ53
29	A7	75	CK2#	121	DQ22	167	NC
30	VCCQ	76	CK2	122	A8	168	VCC
31	DQ19	77	VCCQ	123	DQ23	169	DQM6
32	A5	78	DQS6	124	VSS	170	DQ54
33	DQ24	79	DQ50	125	A6	171	DQ55
34	VSS	80	DQ51	126	DQ28	172	VCCQ
35	DQ25	81	VSS	127	DQ29	173	NC
36	DQS3	82	VCCID	128	VCCQ	174	DQ60
37	A4	83	DQ56	129	DM3	175	DQ61
38	VCC	84	DQ57	130	A3	176	VSS
39	DQ26	85	VCC	131	D30	177	DM7
40	DQ27	86	DQS7	132	VSS	178	DQ62
41	A2	87	DQ58	133	DQ31	179	DQ63
42	VSS	88	DQ59	134	NC	180	VCCQ
43	A1	89	VSS	135	NC	181	SA0
44	NC	90	NC	136	VCCQ	182	SA1
45	NC	91	SDA	137	CK0	183	SA2
46	VCC	92	SCL	138	CK0#	184	VCCSPD

	PIN NAMES
A0-A11		Address input (Multiplexed)
BA0-BA1		Bank Select Address
DQ0-DQ63		Data Input/Output
DQS0-DQS8		Data Strobe Input/Output
CK0, CK1, CK2		Clock Input
CK0#CK1#, CK2#		Clock Input
CKE0, CKE1		Clock Enable input
CS0#, CS1#		Chip Select Input
RAS#		Row Address Strobe
CAS#		Column Address Strobe
WE#		Write Enable
DM0-DM7		Data-in-mask
VCC		Power Supply
VCCQ		Power Supply for DQS
VSS		Ground
VREF		Power Supply for Reference
VCCSPD		Serial EEPROM Power Supply
SDA		Serial data I/O
SCL		Serial clock
SA0-SA2		Address in EEPROM
NC		No Connect

November 2005	2	White Electronic Designs Corporation • [phone] • www.wedc.com
Rev. 2

White Electronic Designs

W3EG6433S-D3 -JD3

PRELIMINARY

FUNCTIONAL BLOCK DIAGRAM

CS1#
CS0#
DQS0				DQS4
DM0				DM4
DM#	CS# DQS	DM#	CS# DQS	DM#	CS# DQS	DM#	CS# DQS

DQ0

I/O 7

I/O 0

DQ32

I/O 7

I/O 0

DQ1

I/O 6

I/O 1

DQ33

I/O 6

I/O 1

DQ2

I/O 1

I/O 6

DQ34

I/O 1

I/O 6

DQ3

I/O 0

I/O 7

DQ35

I/O 0

I/O 7

DQ4

I/O 5

I/O 2

DQ36

I/O 5

I/O 2

DQ5

I/O 4

I/O 3

DQ37

I/O 4

I/O 3

DQ6

I/O 3

I/O 4

DQ38

I/O 3

I/O 4

DQS1

DQ7

I/O 2

I/O 5

DQS5

DQ39

I/O 2

I/O 5

DM1

DM5

DM#

CS# DQS

DM#

CS# DQS

DM#

CS# DQS

DM#

CS# DQS

DQ8

I/O 7

I/O 0

DQ40

I/O 7

I/O 0

DQ9

I/O 6

I/O 1

DQ41

I/O 6

I/O 1

DQ10

I/O 1

I/O 6

DQ42

I/O 1

I/O 6

DQ11

I/O 0

I/O 7

DQ43

I/O 0

I/O 7

DQ12

I/O 5

I/O 2

DQ44

I/O 5

I/O 2

DQ13

I/O 4

I/O 3

DQ45

I/O 4

I/O 3

DQ14

I/O 3

I/O 4

DQ46

I/O 3

I/O 4

DQS2

DQ15

I/O 2

I/O 5

DQS6

DQ47

I/O 2

I/O 5

DM2

DM6

DM#

CS# DQS

DM#

CS# DQS

DM#

CS# DQS

DM#

CS# DQS

DQ16

I/O 7

I/O 0

DQ48

I/O 7

I/O 0

DQ17

I/O 6

I/O 1

DQ49

I/O 6

I/O 1

DQ18

I/O 1

I/O 6

DQ50

I/O 1

I/O 6

DQ19

I/O 0

I/O 7

DQ51

I/O 0

I/O 7

DQ20

I/O 5

I/O 2

DQ52

I/O 5

I/O 2

DQ21

I/O 4

I/O 3

DQ53

I/O 4

I/O 3

DQ22

I/O 3

I/O 4

DQ54

I/O 3

I/O 4

DQ23

I/O 2

I/O 5

DQ55

I/O 2

I/O 5

DQS3

DM3

DM#

CS# DQS

DQ24 I/O 7

DQ25 I/O 6

DQ26 I/O 1

DQ27 I/O 0

DQ28 I/O 5

DQ29 I/O 4

DQ30 I/O 3

DQ31 I/O 2

Serial PD

SCL											SDA
WP			A0		A1		A2
			SA0		SA1		SA2

BA0 - BA1 BA0-BA1 : DDR SDRAMs

A0 - A11 A0-A11 : DDR SDRAMs

RAS# RAS#: DDR SDRAMs

CAS# CAS# : DDR SDRAMs

CKE0/1 CKE : DDR SDRAMs

WE# WE#: DDR SDRAMs

DM#

CS# DQS

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQS7

DM7

				DM#	CS# DQS		DM#	CS# DQS
DQ56				I/O 7			I/O 0
DQ57				I/O 6			I/O 1
DQ58				I/O 1			I/O 6
DQ59				I/O 0			I/O 7
DQ60				I/O 5			I/O 2
DQ61				I/O 4			I/O 3
DQ62				I/O 3			I/O 4
DQ63				I/O 2			I/O 5

DDR SDRAMs

VCCSPD											SPD
VCC/VCCQ											DDR SDRAMs
											DDR SDRAMs
VREF											DDR SDRAMs
VSS											DDR SDRAMs

* Clock Wiring

Clock

DDR SDRAMs

Input

*CK0/CK0# 4 DDR SDRAMs

*CK1/CK1# 6 DDR SDRAMs

*CK2/CK2# 6 DDR SDRAMs

DDR SDRAMs

		R=120Ω				*DDR SDRAMs
CK0/1/2
CK0/1/2#
		Card				*DDR SDRAMs
		Edge
						DDR SDRAMs
						DDR SDRAMs

Notes :

1.DQ-to-I/O wiring is shown as recommended but may be changed.

2.DQ/DQS/DM/CKE/CS# relationships must be maintained as shown.

3.DQ, DQS, DM#/DQS# resistors: 22 Ohms + 5%.

4.BAx, Ax, RAS#, CAS#, WE# resistors: 3 Ohms + 5%.

*Clock Net Wiring

November 2005	3	White Electronic Designs Corporation • [phone] • www.wedc.com
Rev. 2

White Electronic Designs

W3EG6433S-D3 -JD3

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Parameter			Symbol	Value	Units
Voltage on any pin relative to VSS			VIN, VOUT	-0.5 to 3.6	V
Voltage on VCC supply relative to VSS			VCC, VCCQ	-1.0 to 3.6	V
Storage Temperature			TSTG	-55 to +150	°C
Power Dissipation			PD	24	W
Short Circuit Current			IOS	50	mA
Note:	Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
	Functional operation should be restricted to recommended operating condition.
	Exposure to higher than recommended voltage for extended periods of time could affect device reliability

DC OPERATING CONDITIONS

Recommended perating conditions (Voltage referenced to VSS=0V, TA=0 to 70°C)

Parameter	Symbol	Min	Max	Unit	Note
Supply Voltage (for device with a nominal VCC of 2.5V)	VCC	2.3	2.7	V
I/O Supply Voltage	VCCQ	2.3	2.7	V
I/O Reference Voltage	VREF	0.49*VCCQ	0.51*VCCQ	V	1
I/OTermination Voltage	VTT	VREF-0.04	VREF+0.04	V	2
Input Logic High Voltage	VIH	VREF + 0.15	VCCQ + 0.3	V
Input Logic Low Voltage	VIL	-0.3	VREF -0.15	V
Input Voltage Level, CK and CK# Inputs	VIN(DC)	-0.3	VCCQ + 0.3	V
Input Differential Voltage, CK and CK# Inputs	VID(DC)	0.36	VCCQ + 0.6	V	3
V-I Matching: Pullup to Pulldown Current Ratio	VI(Ratio)	0.71	1.4	-	4
Input leakage current	II	-2	2	uA
Output leakage current	IOZ	-5	5	uA
Output High Current(Normal strengh driver); VOUT = VTT = 0.84V	IOH	-16.8		uA
Output High Current(Normal strengh driver); VOUT = VTT = 0.84V	IOL	16.8		uA
Output High Current(Half strengh driver); VOUT = VTT = 0.45V	VOH	-9		uA
Output High Current(Half strengh driver); VOUT = VTT = 0.45V	VOL	9		uA

NOTES:

1.VREF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value.

2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of

VREF.

3.VID is the magnitude of the difference between the input level on CK and the input level on CK#.

4.The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.

November 2005	4	White Electronic Designs Corporation • [phone] • www.wedc.com
Rev. 2