Weltrend WT751002S-N085, WT751002S-S085 Schematic [ru]

Weltrend Semiconductor, Inc.

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WT751002S

PC POWER SUPPLY SUPERVISOR

Data Sheet

REV. 1.00

November 04, 2005

The information in this document is subject to change without notice. ©Weltrend Semiconductor, Inc. All Rights Reserved.

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2F, No. 24, Industry E. 9th RD., Science-Based Industrial Park, Hsin-Chu, Taiwan TEL:[phone] FAX:[phone].5770419 Email:[e-mail]

WT751002S

Rev. 1.00

GENERAL DESCRIPTION

The WT751002S provides protection circuits, power good output (PGO), fault protection latch (FPOB), and a protection detector function (PSONB) control. It can minimize external components of switching power supply systems in personal computer.

The Over Voltage Detector (OVD) monitors V33, V5 and VCC input voltage level. The Under Voltage Detector (UVD) monitors V33 and V5 input voltage level. When OVD or UVD detect the fault voltage level, the FPOB is latched HIGH and PGO go low. When PGI detect the fault voltage level, the FPOB would be kept LOW and PGO go low. The latch can be reset by PSONB go HIGH. There is 3.5 ms delay time for PSONB turn off FPOB.

When PGI and OVD and UVD detect the right voltage level, the power good output (PGO) will be issue.

FEATURES

∙The Over Voltage Detector (OVD) monitors V33, V5 and VCC input voltage.

∙The Under Voltage Detector (UVD) monitors V33 and V5 input voltage.

∙Both of the power good output (PGO) and fault protection latch (FPOB) are Open Drain Output.

∙75 ms time delay for UVD.

∙300 ms time delay for PGO.

∙38 ms for PSONB input signal De–bounce.

∙73 us for PGI and UVD internal signal De–glitches.

∙55 us for OVD internal signal De–glitches.

∙3.5 ms time delay for PSONB turn-off FPOB.

∙The UVD would been disabled when PGI < 0.95V.

PIN ASSIGNMENT AND PACKAGE TYPE

	WT751002S
PGI		1	8		PGO
GND		2	7		VCC
FPOB		3	6		V5
PSONB		4	5		V33

ORDERING INFORMATION

	PACKAGE	8–Pin Plastic DIP	8–Pin Plastic SOP	CHIP
		WT751002S–N085	WT751002S–S085	WT751002S-HXXX
	Lead–Free Pb	WT751002S–N085 Pb	WT751002S–S085 Pb

The Top-Side Marking would be added a dot●in the right side for lead-free package.

Weltrend Semiconductor, Inc.

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WT751002S

Rev. 1.00

PIN DESCRIPTION

Pin Name	TYPE	Description
PGI	I	Power good input signal pin
GND	P	Ground
FPOB	O	Fault protection output pin, open drain output
PSONB	I	On/Off switch input
V33	I	3.3V over voltage & under voltage
V5	I	5V over voltage & under voltage
VCC	I	Power supply
PGO	O	Power good output signal pin, open drain output

FUNCTION TABLE

PGI	PDON_N	UVD	OVD	FPL_N	PGO
< 0.95V	L	No	No	L	L
< 0.95V	L	No	Yes	H	L
< 0.95V	L	Yes	No	L	L
0.95V < PGI < 1.2V	L	No	No	L	L
0.95V < PGI < 1.2V	L	No	Yes	H	L
0.95V < PGI < 1.2V	L	Yes	No	H	L
PGI > 1.2	L	No	No	L	H
PGI > 1.2	L	No	Yes	H	L
PGI > 1.2	L	Yes	No	H	L
X	H	X	X	H	L

X = don’t care

Weltrend Semiconductor, Inc.

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WT751002S

Rev. 1.00

BLOCK DIAGRAM

WT751002S080
VCC
	PWR	Power On Reset		PWR
VCCI
PSONB	38ms	clr	3.5ms
	debounce		delay
1.2V ~ 1.8V
					Bandgap	VREF = 1.2V
		clr	75ms		Reference
			delay
V33	- UN
	+				Internal
						VCCI = 3.6V
					Power
	-OV
	+
V5	- UN
	+
					PWR
	-OV
	+		clr
					OSC	CLK
			73us
VCC		debounce
	-OV
	+
1.2V			clr	R		FPOB
			55us	S	Q
		debounce
	+
	- UN
PGI 2 = 0.95V		clr				PGO
PGI	+ UN	73us		300ms
				clr
	-	debounce		delay
PGI 1 = 1.2V

Weltrend Semiconductor, Inc.

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