Weltrend WT751002S-N085, WT751002S-S085 Schematic [ru]
偉詮電子股份有限公司
Weltrend Semiconductor, Inc.
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WT751002S
PC POWER SUPPLY SUPERVISOR
Data Sheet
REV. 1.00
November 04, 2005
The information in this document is subject to change without notice.
Weltrend Semiconductor, Inc. All Rights Reserved.
新竹市科學工業園區工業東九路24號2樓
2F, No. 24, Industry E. 9th RD., Science-Based Industrial Park, Hsin-Chu, Taiwan
TEL:886-3-5780241 FAX:886-3-5794278.5770419
Email:support@weltrend.com.tw
WT751002S
ORDERING INFORMATION
2 3
WT751002S
Rev. 1.00
GENERAL DESCRIPTION
The WT751002S provides protection circuits, power good output (PGO), fault protection latch
(FPOB), and a protection detector function (PSONB) control. It can minimize external components of
switching power supply systems in personal computer.
The Over Voltage Detector (OVD) monitors V33, V5 and VCC input voltage level. The Under Voltage
Detector (UVD) monitors V33 and V5 input voltage level. When OVD or UVD detect the fault voltage
level, the FPOB is latched HIGH and PGO go low. When PGI detect the fault voltage level, the FPOB
would be kept LOW and PGO go low. The latch can be reset by PSONB go HIGH. There is 3.5 ms
delay time for PSONB turn off FPOB.
When PGI and OVD and UVD detect the right voltage level, the power good output (PGO) will be
issue.
FEATURES
• The Over Voltage Detector (OVD) monitors V33, V5 and VCC input voltage.
• The Under Voltage Detector (UVD) monitors V33 and V5 input voltage.
• Both of the power good output (PGO) and fault protection latch (FPOB) are Open Drain Output.
• 75 ms time delay for UVD.
• 300 ms time delay for PGO.
• 38 ms for PSONB input signal De–bounce.
• 73 us for PGI and UVD internal signal De–glitches.
• 55 us for OVD internal signal De–glitches.
• 3.5 ms time delay for PSONB turn-off FPOB.
• The UVD would been disabled when PGI < 0.95V.
PIN ASSIGNMENT AND PACKAGE TYPE
PGI
GND
FPOB
1
PSONB
4
※ The Top-Side Marking would be added a dot（●）in the right side for lead-free package.
PACKAGE 8–Pin Plastic DIP 8–Pin Plastic SOP CHIP
WT751002S–N085 WT751002S–S085
Lead–Free（Pb）
8
PGO
7
VCC
6
V5
5
V33
WT751002S–N085 Pb WT751002S–S085 Pb
WT751002S-HXXX
Weltrend Semiconductor, Inc.
Page 2
WT751002S
PIN DESCRIPTION
Pin Name TYPE Description
PGI I
GND P
FPOB O
PSONB I
V33 I
V5 I
VCC I
PGO O
FUNCTION TABLE
Power good input signal pin
Ground
Fault protection output pin, open drain output
On/Off switch input
3.3V over voltage & under voltage
5V over voltage & under voltage
Power supply
Power good output signal pin, open drain output
Rev. 1.00
0.95V < PGI < 1.2V L No No L L
0.95V < PGI < 1.2V L No Yes H L
0.95V < PGI < 1.2V L Yes No H L
X = don’t care
PGI PDON_N UVD OVD
< 0.95V L No No L L
< 0.95V L No Yes H L
< 0.95V L Yes No L L
PGI > 1.2 L No No L H
PGI > 1.2 L No Yes H L
PGI > 1.2 L Yes No H L
X H X X H L
FPL_N PGO
Weltrend Semiconductor, Inc.
Page 3
WT751002S
WT750202C-085 BLOCK DIAGRAM
BLOCK DIAGRAM
WT751002S- 080
VCC
Rev. 1.00
PWR
VCCI
PSONB
1.2V ~ 1.8V
V33
V5
VCC
1.2V
PGI 2 = 0.95V
PGI
PGI 1 = 1.2V
-
UN
+
-
OV
+
-
UN
+
-
OV
+
-
OV
+
+
UN
-
+
UN
-
38ms
debounce
Power On Reset
3.5ms
clr
delay
75ms
clr
delay
clr
73us
debounce
clr
55us
debounce
clr
73us
debounce delay
PWR
Bandgap
Reference
Internal
Power
PWR
OSC
R
S Q
300ms
clr
VREF = 1.2V
VCCI = 3.6V
CLK
FPOB
PGO
Weltrend Semiconductor, Inc.
Page 4
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