IBM and IBM products are registered trademarks of International Business Machines
Corporation.
Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc.
VINC and VINC products are registered trademarks of V, Inc.
VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards
Association (VESA).
Energy Star is a registered trademark of the US Environmental Protection Agency (EPA).
No part of this document may be copied, reproduced or transmitted by any means for any
purpose without prior written permission from VINC.
FCC INFORMATION
This equipment has been tested and found to comply with the limits of a Class B digital device,
pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses and can radiate radio frequency energy, and if not installed and used in accordance with
the instructions, may cause harmful interference to radio communications. However, there is
no guarantee that the interference will not occur in a particular installation. If this equipment
does cause unacceptable interference to radio or television reception, which can be
determined by turning the equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures -- reorient or relocate the receiving
antenna; increase the separation between equipment and receiver; or connect the into an
outlet on a circuit different from that to which the receiver is connected.
FCC WARNING
To assure continued FCC compliance, the user must use a grounded power supply cord and
the provided shielded video interface cable with bonded ferrite cores. Also, any unauthorized
changes or modifications to Amtrak products will void the user’s authority to operate this
device. Thus VINC Will not be held responsible for the product and its safety.
CE CERTIFICATION
This device complies with the requirements of the EEC directive 89/336/EEC with regard to
“Electromagnetic compatibility.”
SAFETY CAUTION
Use a power cable that is properly grounded. Always use the AC cords as follows – USA (UL);
Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric
Appliance Control Act); or an AC cord that meets the local safety standards.
VIZIO L32HDTV10A Service Manual
Chapter 1 Features
1. Built in TV channel selector for TV viewing
2. Simulatnueous display of PC and TV images
3. Connectable to PC’s analog RGB port
4. Built in s-video, HDTV, composite video, HDMI ,TV and DTV out
5. Built in auto adjust function for automatic adjument of screen display
6. Smoothing function enables display of smooth texts and graphics even if image
withresolution lower than 1366x768 is magnified
7. Picture In Picture (PIP) funtion to show TV or VCR images
8. Power saving to reduce consumption power too less than 3W
9. On Screen Display: user can define display mode (i.e. color, brightness, contrast,
sharpness), sound setting, PIP, TV channel program, aspect and gamma or
reset all setting.
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Chapter 2 Specification
1. LCD CHARACTERISTICS
Type: WXGA TFT LCD
Size: 37 inch
Display Size: 37.02 inches (940.3mm) diagonal
Outline Dimension: 877.0/878.0 mm (H) x 516.8 mm (V) x 55.5 (D) mm (Typ.)
9. 3D surround processing include virtual surround.
10. Audio and video lip synchronization.
11. Support reverberation.
12. SPDIF out.
13. I2S I/F.
O . Peripherals :
1. Three UARTs with Tx and Rx FIFO , two of them have hardware flow control.
2. Two serial interfaces , one is master only the other can be set to master mode or slave
mode.
3. Two PWMs.
4. IR blaster and receiver.
5. IEEE1394 link controller.
6. IDE bus : ATA/ATAPI7 UDMA mode 5 , 100MB/s.
7. Real-time clock and watchdog controller.
8. Memory card I/F : MS/MS-pro ,SD ,CF ,and MMC
9. PCMCIA/POD/CI interface
P . IC Outline :
1. 471 Pin BGA Package.
2. 3.3V/1.2V dual Voltage.
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MX29LV320BTTC (Flash) Application :
The MX29LV320AT/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and
2M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable
read/write non-volatile random access memory.
The MX29LV320AT/B is packaged in 48-pin TSOP and 48-ball CSP. It is designed to be
reprogrammed and erased in system or in standard EPROM programmers. The standard
MX29LV320AT/B offers access time as fast as 70ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention, the MX29LV320AT/B has
separate chip enable (CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and
programming. The MX29LV320AT/B uses a command register to manage this functionality.
MXIC Flash technology reliably stores memory contents even after 100,000 erase and
program cycles. The MXIC cell is designed to optimize the erase and program mechanisms.
In addition, the combination of advanced tunnel oxide processing and low internal electric
fields for erase and programming operations produces reliable cycling.
The MX29LV320AT/B uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase
and auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi
process. Latch-up protection is proved for stresses up to 100 milliamperes on address and
data pin from -1V to VCC + 1V.
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BLOCK DIAGRAM
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BUS OPERATION--1
Legend:
L=Logic LOW=VIL, H=Logic High=VIH, VID=12.00.5V, V HH=11.5-12.5V, X=Don't Care,
AIN=Address IN, DIN=Data IN,DOUT=Data OUT
Notes:
1. When the WP/ACC pin is at VHH, the device enters the accelerated program mode. See
"Accelerated Program Operations" for more information.
2.The sector group protect and chip unprotect functions may also be implemented via
programming equipment. See the "Sector Group Protection and Chip Unprotection"
section.
3.If WP/ACC=VIL, the two outermost boot sectors remain protected. If WP/ACC=VIH, the two
outermost boot sector protection depends on whether they were last protected or
unprotected using the method described in "Sector/Sector Block Protection and
Unprotection". If WP/ACC=VHH, all sectors will be unprotected.
4.DIN or Dout as required by command sequence, data polling, or sector protection
algorithm.
5.Address are A20:A0 in word mode (BYTE=VIH), A20:A-1 in byte mode (BYTE=VIL).
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BUS OPERATION--2
Notes:
1.Code=00h means unprotected, or code=01h protected.
2.Code=99 means factory locked, or code=19h not factory locked.
WRITE COMMANDS/COMMAND SEQUENCES
To program data to the device or erase sectors of memory , the system must drive WE and
CE to VIL, and OE to VIH.
An erase operation can erase one sector, multiple sectors , or the entire device. A "sector
address" consists of the address bits required to uniquely select a sector. Writing specific
address and data commands or sequences into the command register initiates device
operations. Table A defines the valid register command sequences. Writing incorrect address
and data values or writing them in the improper sequence resets the device to reading array
data. Section has details on erasing a sector or the entire chip, or suspending/resuming the
erase operation.
After the system writes the Automatic Select command sequence, the device enters the
Automatic Select mode. The system can then read Automatic Select codes from the internal
register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings
apply in this mode. Refer to the Automatic Select Mode and Automatic Select Command
Sequence section for more information.
ICC2 in the DC Characteristics table represents the active current specification for the write
mode. The "AC Characteristics" section contains timing specification table and timing
diagrams for write operations.
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TABLE A. MX29LV320AT/B COMMAND DEFINITIONS
Legend:
X=Don't care
RA=Address of the memory location to be read.
RD=Data read from location RA during read operation.
PA=Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE or CE pulse.
PD=Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse.
SA=Address of the sector to be erased or verified. Address bits A20-A12 uniquely select any sector.
ID=22A7h(Top), 22A8h(Bottom)
Notes:
1.All values are in hexadecimal.
2.Except when reading array or Automatic Select data, all bus cycles are write operation.
3.The Reset command is required to return to the read mode when the device is in the Automatic
Select mode or if Q5 goes high.
4.The fourth cycle of the Automatic Select command sequence is a read cycle.
5.The data is 99h for factory locked and 19h for not factory locked.
6.The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. In
the third cycle of the command sequence, address bit A20=0 to verify sectors 0~31, A20=1 to verify
sectors 32~70 for Top Boot device.
7.Command is valid when device is ready to read array data or when device is in Automatic Select
mode.
8.The system may read and program functions in non-erasing sectors, or enter the Automatic Select
mode, when in the erase Suspend mode. The Erase Suspend command is valid only during a sector
erase operation.
9.The Erase Resume command is valid only during the Erase Suspend mode.
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STANDBY MODE
MX29LV320AT/B can be set into Standby mode with two different approaches. One is using both CE
and RESET pins and the other one is using RESET pin only.
When using both pins of CE and RESET, a CMOS Standby mode is achieved with both pins held at
Vcc ±0.3V. Under this condition, the current consumed is less than 0.2uA (typ.). If both of the CE and
RESET are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby
mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (ICC2)
is required even CE = "H" until the operation is completed. The device can be read with standard
access time (tCE) from either of these standby modes.
When using only RESET, a CMOS standby mode is achieved with RESET input held at Vss ± 0.3V,
Under this condition the current is consumed less than 1uA (typ.). Once the RESET pin is taken high,
the device is back to active without recovery delay.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
MX29LV320AT/B is capable to provide the Automatic Standby Mode to restrain power consumption
during readout of data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.
To active this mode, MX29LV320AT/B automatically switch themselves to low power mode when
MX29LV320AT/B addresses remain stable during access time of tACC+30ns. It is not necessary to
control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 0.2uA
(CMOS level).
RESET OPERATION
01The RESET pin provides a hardware method of resetting the device to reading array data. When the
RESET pin is driven low for at least a period of tRP, the device immediately terminates any operation
in progress, tristates all output pins, and ignores all read/write commands for the duration of the
RESET pulse. The device also resets the internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is ready to accept another command
sequence, to ensure data integrity.
Current is reduced for the duration of the RESET pulse. When RESET is held at VSS±0.3V, the device
draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS±0.3V, the standby
current will be greater.
The RESET pin may be tied to system reset circuitry. A system reset would that also reset the Flash
memory, enabling the system to read the boot-up firm-ware from the Flash memory.
If RESET is asserted during a program or erase operation, the RY/BY pin remains a "0" (busy) until the
internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms).
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The system can thus monitor RY/BY to determine whether the reset operation is complete. If RESET
is asserted when a program or erase operation is not executing (RY/BY pin is "1"), the reset operation
is completed within a time of tREADY (not during Embedded Algorithms). The system can read data
tRH after the RESET pin returns to VIH. Refer to the AC Characteristics tables for RESET parameters
and to Figure 14 for the timing diagram.
WRITE PROTECT (WP)
The write protect function provides a hardware method to protect boot sectors without using V
ID.
If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the
two "outermost" 8 Kbyte boot sectors independently of whether those sectors were protected or
unprotected using the method described in Sector/Sector Group Protection and Chip Unprotection".
The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a
bottom-boot-configured device, or the two sectors containing the highest addresses in a
top-boot-configured device.
If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8K Byte
boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for
these two sectors depends on whether they were last protected or unprotected using the method
described in "Sector/Sector Group Protection and Chip Unprotection".
Note that the WP/ACC pin must not be left floating or unconnected; inconsistent behavior of the device
may result.
SOFTWARE COMMAND DEFINITIONS :
Device operations are selected by writing specific address and data sequences into the command
register. Writing incorrect address and data values or writing them in the improper sequence will reset
the device to the read mode. Table 3 defines the valid register command sequences. Note that the
Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase
operation is in progress. Either of the two reset command sequences will reset the device
(whenapplicable).
All addresses are latched on the falling edge of WE or CE, whichever happens later. All data are
latched on rising edge of WE or CE, whichever happens first.
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: Q2, Q3, Q5, Q6, Q7, and
RY/BY.Table B and the following subsections describe the functions of these bits. Q7, RY/BY, and Q6
each offer a method for determining whether a program or erase operation is complete or in progress.
These three bits are discussed first.
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Table B. Write Operation Status
Notes:
1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.
2.Performing successive read operations from any address will cause Q6 to toggle.
3.Reading the byte/word address being programmed while in the erase-suspend program mode will
indicate logic "1" at the Q2 bit.
However, successive reads from the erase-suspended sector will cause Q2 to toggle.
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to
zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set
command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired
values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode
Register Set command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes
and reserved states should not be used as unknown operation or incompatibility with future versions
may result.
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Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these
additional functions include DLL enable/disable, bit A0; output drive strength selection, bit A1; and
QFC output enable/disable, bit A2 (NTC optional). These functions are controlled via the bit settings
shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the
Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is
programmed again or the device loses power. The Extended Mode Register must be loaded when all
banks are idle, and the controller must wait the specified time before initiating any subsequent
operation. Violating either of these requirements result in unspecified operation.
Extended Mode Register Definition
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Truth Table a: Commands
1. CKE is high for all commands shown except Self Refresh.
2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode
Register; BA0 = 1, BA1 = 0 selects ,Extended Mode Register; other combinations of BA0-BA1 are
reserved; A0-A12 provide the op-code to be written to the selected Mode Register.)
3. BA0-BA1 provide bank address and A0-A12 provide row address.
4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4);
A10 high enables the Auto Precharge feature (non-persistent), A10 low disables the Auto Precharge
feature.
5. A10 LOW: BA0, BA1 determine which bank is precharged.A10 HIGH: all banks are precharged and
BA0, BA1 are “Don’t Care.”
6. This command is auto refresh if CKE is high; Self Refresh if CKE is low.
7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care”
except for CKE.
8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should
not be used) for read bursts with Auto Precharge enabled or for write bursts
9. Deselect and NOP are functionally interchangeable.
Active
The Active command is used to open (or activate) a row in a particular bank for a subsequent access.
The value on the BA0,BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects
the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto
Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must
be issued and completed before opening a different row in the same bank.
Read
The Read command is used to initiate a burst read access to an active (open) row. The value on the
BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t
care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10
determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being
accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row
remains open for subsequent accesses.
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Write
The Write command is used to initiate a burst write access to an active (open) row. The value on the
BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t
care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10
determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being
accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row
remains open for subsequent accesses. Input data appearing on the DQs is written to the memory
array subject to the DM input logic level appearing coincident with the data. If a given DM signal is
registered low, the corresponding data is written to memory; if the DM signal is registered high, the
corresponding data inputs are ignored, and a Write is not executed to that byte/column location.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before
RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued
each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address bits
“Don’t Care” during an Auto Refresh command. The 256Mb DDR SDRAM requires Auto Refresh
cycles at an average periodic interval of 7.8μs (maximum).
Self Refresh
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the
system is powered down.When in the self refresh mode, the DDR SDRAM retains data without
external clocking. The Self Refresh command is initiated as an Auto Refresh command coincident with
CKE transitioning low. The DLL is automatically disabled upon entering Self Refresh, and is
automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read
command can be issued). Input signals except CKE (low) are “Don’t Care” during Self Refresh
operation.
The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable
prior to CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for
tXSNR because time is required for the completion of any internal refresh in progress. A simple
algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before
applying any other command.
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Operations :
Reads
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read
bursts are initiated with a Read command.
The starting column and bank addresses are provided with the Read command and Auto Precharge is
either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed
starts precharge at the completion of the burst, provided tRAS has been satisfied. For the generic
Read commands used in the following illustrations, Auto Precharge is disabled.
During Read bursts, the valid data-out element from the starting column address is available following
the CAS latency after the Read command. Each subsequent data-out element is valid nominally at the
next positive or negative clock edge (i.e. at the next crossing of CK and CK). The following timing
figure entitled “Read Burst: CAS Latencies (Burst Length=4)” illustrates the general timing for each
supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial
low state on DQS is known as the read preamble; the low state coincident with the last data-out
element is known as the read postamble . Upon completion of a burst, assuming no other commands
have been initiated, the DQs and DQS goes High-Z. Data from any Read burst may be concatenated
with or truncated with data from a subsequent Read command. In either case, a continuous flow of
data can be maintained. The first data element from the new burst follows either the last element of a
completed burst or the last desired data element of a longer burst which is being truncated. The new
Read command should be issued x cycles after the first Read command, where x equals the number
of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in
timing figure entitled “Consecutive Read Bursts: CAS Latencies (Burst Length =4 or 8)”.A Read
command can be initiated on any positive clock cycle following a previous Read command.
Nonconsecutive Read data is shown in timing figure entitled “Non-Consecutive Read Bursts: CAS
Latencies (Burst Length = 4)”. Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2,
4 or 8) within a page (or pages) can be performed as shown on following:
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Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
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Read Command
Writes
Write bursts are initiated with a Write command, as shown in timing figure Write Command on
following: The starting column and bank addresses are provided with the Write command, and Auto
Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being
accessed is precharged at the completion of the burst. For the generic Write commands used in the
following illustrations, Auto Precharge is disabled.
During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following
the write command, and subsequent data elements are registered on successive edges of DQS. The
Low state on DQS between the Write command and the first rising edge is known as the write
preamble; the Low state on DQS following the last data-in element is known as the write postamble.
The time between the Write command and the first corresponding rising edge of DQS (tDQSS) is
specified with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write
diagrams that follow are drawn for the two extreme cases (i.e. tDQSS(min) and tDQSS(max)). Timing
figure Write Burst (Burst Length = 4) on page 33 shows the two extremes of tDQSS for a burst of four.
Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS
enters High-Z and any additional input data is ignored.
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Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In
either case, a continuous flow of input data can be maintained. The new Write command can be
issued on any positive edge of clock following the previous Write command. The first data element
from the new burst is applied after either the last element of a completed burst or the last desired data
element of a longer burst which is being truncated. The new Write command should be issued x cycles
after the first Write command, where x equals the number of desired data element pairs (pairs are
required by the 2n prefetch architecture).
Write Command
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Data Input (Write)
Data Output (Read)
WM8776 Application
The WM8776 is a high performance, stereo audio codec with five channel input selector. The
WM8776 is ideal for surround sound processing applications for home hi-fi, DVD-RW and
other audiovisual equipment. Etch ADC channel has programmable gain control with
automatic level control. Digital audio output word lengths from 16-32 bits and sampling rates
from 32kHZ to 96KHZ are supported. The DAC has an input mixer allowing an external
analogue signal to be mixed with the DAC signal. There are also Headphone and line outputs,
with control for the headphone
The WM8776 supports fully independent sample rates for the ADC and DAC. The audio data
interface supports I2S, left justified, right justified and DSP formats.
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BLOCK DIAGRAM
1. Audio sample rate
The master clock forWM8776 supports DAC and ADC audio sampling rates 256fs to 768fs,
where fs is the audio sample frequency (DACLRC or ADCLRC) typically 32KHZ, 44.1KHZ,
48KHZ or 96KHZ (the DAC also supports operation at 128fs and 192fs and 192KHZ
sample rate). The master clock is used to operate the digital filters and the noise shaping
circuits.
In slave mode the WM8776 has a master detection circuit that automatically determines
the relationship between the master clock frequency and the sampling rate (to within +/- 32
system clocks) If there is a greater than 32 clocks error the interface is disabled and
ADCLRC/DACLRC for optical performance, although the WM8776 is tolerant of phase
variations or jitter on this clock.
Table shows the typical master clock frequency inputs for the WM8776.
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2. DIGITAL AUDIO INTERFACE
a. Slave mode
The audio interfaces operations in either slave mode selectable using the MS control bit. In
slave mode DIN is always an input to the WM8776 and DOUT is always an output. The
default is Slave mode. In slave mode (ms=0) ADCLRC, DACLRC, ADCBCLK, DACBCLK
are input to the WM8776 .
DIN and DACLRC are sampled by the WM8776 on the rising edge of DACBCLK; ADCLRC
is sampled on the rising edge of ADCBCLK. ADC data is output on DOUT and changes on
the falling edge of ADCBCLK. By setting control bit BCLKINV the polarity of ADCBCLK and
DACBCLK may be reversed so that DIN and DACLRC are sample on the falling edge of
DACBCLK, ADCLRC is sampled on the falling edge of ADCBCLK and DOUT changes on
the rising of ADCBCLK Slave mode as shown in the following figure.
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b. 2 Wire serial control mode
The wm8776 supports software control via a 2-wire serial bus. Many devices can be
controlled by the same bus, and each device has a uni ue 7-bit address (this is not the
same as the 7-bit address of each register in the wm8776). The wm8776 operates as a
slave device only.
2-wire serial interface as shown in the following figure.
The wm8776 has two possible device addresses, which can be selected using the CE pin
In the L37 LCD TV CE pin is LOW (device address is 34h).
In the L37 wm8776 has 2-wire interface
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Sil9011 Application
The sil9011 provides a complete solution for receiving HDMI compliant digital audio and
video. Specialized audio and video processing is available within the sil9011 to easily and
cost effectively adds HDMI capability to consumer electronics devices such as digital TVs,
plasma displays, LCD TVs and projectors.
BLOCK DIAGRAM
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1. TMDS Digital Core
The core performs 10-to-8-bit TMDS decoding on the audio and video received from the
three TMDS differential data lines along with a TMDS differential clock. The TMDS core
supports link clock rates to 165MHZ, including CE modes to 720P/1080I/1080P.
2. Active port detection
The Pane Link core detects an active TMDS clock and actively toggling DE signal. These
states are accessible in register bits, useful for monitoring the status of the HDMI input or
for automatically powering down the receiver. The 5V supply from the HDMI connector is
used as a cable detect indicator. The sil9011 can monitor the presence of this+5V supply
and, if and when necessary, provide a fast audio mute without pops when it senses the
HDMI cable pulled. The microcontroller can also poll registers in the sil9011 to check
whether an HDMI cable is connected.
3. HDCP Decryption engine
The HDCP decryption engine contains all necessary logic to decrypt the incoming audio
and video data. The decryption process is entirely controlled by the host microprocessor
through a set sequence of register reads and wires through the DDC channel.
Pre-programmed HDCP keys and key Selection Vector are used in the decryption process.
A resulting calculated to an XOR mask during each clock cycle to decrypt the audio/video
data in sync with the host.
4. Video Data Conversion and Video Output
The Sil9011 can output video in many different formats
as shown in the following figure.
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The receiver can also process the video data before it is output as show below figure
5. I2c Interface to Display Controller
2
The Controller I
running up to 400KHZ. This bus is used to configure the SIL9011 by reading/writing to the
appropriate registers. The SIL9011 is accessible on the local I
The logic state of the CI2CA pin is latched on the rising edge of REST# providing a choice
of two pairs of device address.
Control of local I
c interface (CSDA, CSCL) on the sil9011 is a slave interface capable of
2
c bits at two-device address.
2
c address with CI2CA pin
MM1942 Application
The MM1942 IC is a 5-input 2-output AV switch controlled by the I2C BUS developed for use in
television.
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BLOCK DIAGRAM
1. I2c Bus
I2C BUS is interring bus system controlled by 2 lines (SDA, SCL). Data are transmitted and received
in the units of byte and Acknowledge. It is transmitted by MSB first from the Start conditions.
The data format is set as shown in the following figure.
In the L32 TV MM1492 slave address, ADR terminal is L, and 90H is selected.
The following figure indicates the control contents of control registers and switches.
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Page 8-56
2. Switch control table
a. Video output 1
b. Audio output 1
c. Audio gain
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TDA8946 Application
In L32 TV the TDA8946AJ is a dual-channel audio power amplifier with DC gain control. It has an
output power of 2 × 10 W at an 8 Ω load and a 12 V supply.
Block diagram
1. Input configuration
The TDA8946AJ inputs can be driven symmetrical (floating) as well as asymmetrical. In the
asymmetrical mode one input pin is connected via a capacitor to the signal source and the other
input is connected to the signal ground. The signal ground should be as close as possible to the
SVR (electrolytic) capacitor ground. Note that the DC level of the input pins is half of the supply
voltage VCC, so coupling capacitors for both pins are necessary.
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2. Output power measurement
The output power as a function of the supply voltage is measured on the output pins at THD =
10%,in the L32 LCD TV Vcc=12V so we can see as shown in the following figure output about 7W.
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3. Mode selection
In the L32 LCD TV TDA8946AJ has two functional modes, which can be selected by applying the
proper DC voltage to pin MODE.
a. Mute — In this mode the amplifier is DC-biased but not operational (no audio output).
This allows the input coupling capacitors to be charged to avoid pop-noise. The device is in mute
mode when 3.5 V < V
b. Operating — In this mode the amplifier is operating normally. The operating mode is activated at
V
MODE<1.0V.
MODE < (VCC − 1.5 V).
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Chapter 9 Waveforms
1. PC MODE(1366X768 60HZ)
CH1 H-sync (FB46); CH2 V-sync (FB45)
GREEN (R194)
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CH1 VGAHSYNC# (FB46); CH2 VGAVSYNC# (FB45)
CH1 VGAVSYNC# (FB45); CH2 GREEN (R194)
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CH1 VGAL (CE81); CH2 AVOL (R252)
CH1 AUSPL (RA12) ; CH2 L+ (UA1 PIN17)
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CH1 XTALI (U9 PIN A15);CH2 XTALO (U9 PIN B15)
2. AV&TV MODE (AV1/AV2/AV3/TV) VIDEO
CH1 (R88); CH2 (Q4 PIN1)
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