Vizio L32 Service Manual

Service Manual

Model #: VIZIO L32

V, Inc

320A Kalmus Drive Costa Mesa, CA 92626

TEL : [phone] FAX :[phone]

Top Confidential

Table of Contents

CONTENTS PAGE

Sections

1. Features 1-1

2. Specifications 2-1

3. On Screen Display 3-1

4. Factory Preset Timings

5. Pin Assignment

4-1

5-1

6. Main Board I/O Connections 6-1

7. Theory of Circuit Operation 7-1

8. Waveforms 8-1

9. Trouble Shooting 9-1

10. BLOCK DI AGRAM 10-1

11.Spare Parts List 11-1

12. Complete Parts List (AUO PANEL) 12-1

13. Complete Parts List (SHARP PANEL) 13-1

Appendix

1. Main Board Circuit Diagram

2. Main Board PCB Layout

3. Assembly Explosion Drawing

Block Diagram

VIZIO L32 Service Manual

VINC Service Manual

VIZIO L32

COPYRIGHT © 2000 V, INC. ALL RIGHTS RESERVED.

IBM and IBM products are registered trademarks of International Business Machines
Corporation.

Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc.

VINC and VINC products are registered trademarks of V, Inc.

VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards
Association (VESA).

Energy Star is a registered trademark of the US Environmental Protection Agency (EPA).

No part of this document may be copied, reproduced or transmitted by any means for any
purpose without prior written permission from VINC.

FCC INFORMATION
This equipment has been tested and found to comply with the limits of a Class B digital device,
pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses and can radiate radio frequency energy, and if not installed and used in accordance with
the instructions, may cause harmful interference to radio communications. However, there is
no guarantee that the interference will not occur in a particular installation. If this equipment
does cause unacceptable interference to radio or television reception, which can be
determined by turning the equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures -- reorient or relocate the receiving
antenna; increase the separation between equipment and receiver; or connect the into an
outlet on a circuit different from that to which the receiver is connected.

FCC WARNING
To assure continued FCC compliance, the user must use a grounded power supply cord and
the provided shielded video interface cable with bonded ferrite cores. Also, any unauthorized
changes or modifications to Amtrak products will void the user’s authority to operate this
device. Thus VINC Will not be held responsible for the product and its safety.

CE CERTIFICATION
This device complies with the requirements of the EEC directive 89/336/EEC with regard to
“Electromagnetic compatibility.”

SAFETY CAUTION
Use a power cable that is properly grounded. Always use the AC cords as follows – USA (UL);
Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric
Appliance Control Act); or an AC cord that meets the local safety standards.

VIZIO L32 Service Manual

Chapter 1 Features

1. Built in TV channel selector for TV viewing

2. Simulatnueous display of PC and TV images

3. Connectable to PC’s analog RGB port

4. Built in s-video, HDTV, composite video, HDMI and TV out

5. Built in auto adjust function for automatic adjument of screen display

6. Smoothing function enables display of smooth texts and graphics even if image

withresolution lower than 1366x768 is magnified

7. Picture In Picture (PIP) funtion to show TV or VCR images

8. Power saving to reduce consumption power too less than 3W

9. On Screen Display: user can define display mode (i.e. color, brightness, contrast,

sharpness), sound setting, PIP, TV channel program, aspect and gamma or reset

all setting.

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Chapter 2 Specification

1. LCD CHARACTERISTICS

Type: WXGA TFT LCD
Size: 31.5 inch
Display Size: 31.5 inches (80.039mm) diagonal
Outline Dimension: 780.0(H) x 450.0(V) x 51.0-(D) mm (Typ.)
Pixel Pitch: 0.51075mm x 0.51075mm
Pixel Format: 1366 horiz. By 768 vert. Pixels RGB strip arrangement
Contrast ratio: 800(Typ)
Luminance, White: 500 cd/m
Display Operating Mode: normally Black
Surface Treatment: Anti glare, low reflection coating; hard coating: 2H;
Haze: 23+/-5%

2 (Typ)

2. OPTICAL CHARACTERISTICS

Viewing Angle by Contrast Ratio °Ÿ 10
Left: 85°typ.
Right: 85°typ.
Top: 85°typ.
Bottom: 85°typ.

3. SIGNAL (Refer to the Timing Chart)

Sync Signal

1) Type: TMDS

2) Input Voltage Level: 90~240 Vac, 50/ 60 Hz

3) Input Impedance: 50£[/ Signal line
RJ11, D-SUB15PIN (MINI, 3rows), Headphone, HDMI, CONNECT, RCAX3 (component),

4. Input Connectors

RCAX2 (AUDIO in), RCAX3 (composite), RCAX2 (AUDIO in)

5. POWER SUPPLY

Power Consumption: 180W MAXPower OFF: to less than 3W MAX

6.Speaker

Output 8Ω/10W (max) X2

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7. ENVIRONMENT

1. Operating Temperature: 5c~35c (Ambient)

2. Relative Humidity: Ta= 35 °C, 90%RH (Non-condensing)

3. Altitude: 0 - 14,000 feet (4267.2m)(Non-Operating)

8. DIMENSIONS (Physical

dimension)

Width: 818.3mm.
Depth: 280.5mm
Height: 643.8mm

9. WEIGHT (Physical weight)

a. Net: 19.5kgs
b. Gross: 23.5kgs

Precaution

Please pay attention to the followings when you use this TFT LCD module.

9-1. MOUNTING PRECAUTIONS

(1) You must mount a module using holes arranged in four corners or four sides.
(2) You should consider the mounting structure so that uneven force (ex. Twisted stress) is not

applied to the module. And the case on which a module is mounted should have sufficient
strength so that external force is not transmitted directly to the module.

(3) Please attach the surface transparent protective plate to the surface in order to protect the

polarizer.Transparent protective plate should have sufficient strength in order to the resist

external force.
(4) You should adopt radiation structure to satisfy the temperature specification.
(5) Acetic acid type and chlorine type materials for the cover case are not desirable because

the former generates corrosive gas of attacking the polarizer at high temperature and the

latter causes circuit break by electro-chemical reaction.
(6) Do not touch, push or rub the exposed polarizes with glass, tweezers or anything harder

than HB pencil lead. And please do not rub with dust clothes with chemical treatment.

Do not touch the surface of polarizer for bare hand or greasy cloth.(Some cosmetics are

detrimental to the polarizer.)

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(7) When the surface becomes dusty, please wipe gently with absorbent cotton or other soft

materials like chamois soaks with petroleum benzene. Normal-hexane is recommended

for cleaning the adhesives used to attach front / rear polarizers. Do not use acetone,

toluene and alcohol because they cause chemical damage to the polarizer.
(8) Wipe off saliva or water drops as soon as possible. Their long time contact with polarizer

causes deformations and color fading.
(9) Do not open the case because inside circuits do not have sufficient strength.

9-2. OPERATING PRECAUTIONS

(1) The spike noise causes the mis-operation of circuits. It should be lower than following

voltage :V=±200mV(Over and under shoot voltage)
(2) Response time depends on the temperature.(In lower temperature, it becomes longer.)
(3) Brightness depends on the temperature. (In lower temperature, it becomes lower.)

And in lower temperature, response time(required time that brightness is stable after

turned on) becomes longer.
(4) Be careful for condensation at sudden temperature change. Condensation makes damage

to polarizer or electrical contacted parts. And after fading condensation, smear or spot will

occur.
(5) When fixed patterns are displayed for a long time, remnant image is likely to occur.
(6) Module has high frequency circuits. Sufficient suppression to the electromagnetic

interference shall be done by system manufacturers. Grounding and shielding methods

may be important to minimized the interference.

9-3. HANDLING PRECAUTIONS FOR PROTECTION

(1) The protection film is attached to the bezel with a small masking tape. When the protection

film is peeled off, static electricity is generated between the film and polarizer. This should

be peeled off slowly and carefully by people who are electrically grounded and with well

ion-blown equipment or in such a condition, etc.
(2) When the module with protection film attached is stored for a long time, sometimes there

remains a very small amount of glue still on the bezel after the protection film is peeled off.
(3) You can remove the glue easily. When the glue remains on the bezel surface or its vestige

is recognized, please wipe them off with absorbent cotton waste or other soft material like

chamois soaked with normal-hexane.

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Chapter 3 On Screen Display

Main unit button

Power

Input

MENU

CH ▲

CH ▼

VOL +

VOL -

MENU / EXIT

TV Source

A. PICTURE ADJUST：

a. PICTURE MODE (USER/ VIVID1 /VIVID2 / VIVID3)

b. Adjust the BACKLIGHT (0~100)

c. Adjust the BRIGHTNESS (0~100)

d. Adjust the CONTRAST (0~100)

e. Adjust the COLOR (saturation)(0~100)

f. Adjust the TINT (hue) (0~100)

g. Adjust the SHARPNESS (0~100)

h. CLOSED CAPTION (OFF/CC1/CC2/CC3/CC4/TT1/TT2/TT3/TT4)

B. AUDIO ADJUST：

a. VOLUME (0~100)

b. BASS (0~100)

c. TREBLE (0~100)

d. BALANCE (0~100)

e. SURROUND (ON/OFF)

f. REVERB (OFF, CONCERT, LIVINGROOM, HALL, ARENA)

g. MUTE (ON/OFF)

h. SPEAKERS (ON/OFF)

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C. TV TUNER SETUP：

a. SOUND (SAP/MONO/STEREO)

b. TV/CABLE (TV/CABLE)

c. CHANNEL SEARCH (RUN)

d. SET CHANNEL

e. SKIP CHANNEL (YES/NO)

D. PARENTAL CONTROL：

a. PARENT LOCK ENABLE (ON/OFF)

b. TV RATING

c. MOVIE RATING

d. ACCESS CODE EDIT

E. PIP SETUP：

a. STYLE (OFF/PIP/POP)

b. Source (AV1、AV2、AV3、ANALOGHD1、ANALOG HD2、DIGITAL HD RGB)

c. SIZE (SMALL (20%)/MEDIUM (30%)/LARGE (40%))

d. POSITION (TOP LEFT/TOP CENTER/TOP RIGHT/MIDDLE LEFT/MIDDLE

RIGHT/BOTTOM LEFT/BOTTOM CENTER/BOTTOM RIGHT)

F. SPECIAL FEATURES：

a. LANGUAGE (ENGLISH/FRANCE/SPANISH)

b. SLEEP TIMER (OFF/30/60/90/120)

c. WIDE FORMAT (NORMAL/WIDE/ZOOM、PANORAMIC)

d. RESET ALL SETTING

PC Analog Mode

A. PICTURE ADJUST：

a. AUTO PICTURE (Run)

b. Adjust the BACKLIGHT (0~100)

c. Adjust the BRIGHTNESS (0~100)

d. Adjust the CONTRAST (0~100)

e. Adjust the V-POSITION (0~100)

f. Adjust the H-SIZE (0~100)

g. Adjust the H-POSITION (0~100)

h. Adjust the FINETUNE (0~100)

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B. COLOR TEMP：

a. COLOR TEMP. (User, 5000K, 6500K,

9300K)

b. RED (0~255)

c. GREEN (0~255)

d. BLUE (0~255)

C. AUDIO ADJUST：

a. VOLUME (0~100)

b. BASS (0~100)

c. TREBLE (0~100)

d. BALANCE (0~100)

e. SURROUND (ON/OFF)

f. REVERB (OFF, CONCERT, LIVING ROOM, HALL, ARENA)

g. MUTE (ON/OFF)

h. SPEAKERS (ON/OFF)

D. PIP SETUP：

a. STYLE (OFF/PIP/POP)

b. SOURCE (AV1、AV2、AV3、TV)

c. SIZE (SMALL (20%)/MEDIUM (30%)/LARGE (40%))

d. POSITION (TOP LEFT/TOP CENTER/TOP RIGHT/MIDDLE LEFT/MIDDLE

RIGHT/BOTTOM LEFT/BOTTOM CENTER/BOTTOM RIGHT)

E. SPECIAL FEATURES：

a. LANGUAGE (ENGLISH/FRANCE/SPANISH)

b. SLEEP TIMER (OFF/30/60/90/120)

c. WIDE FORMAT (WIDE)

d. RESET ALL SETTING

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DIGITAL HD MODE

A. PICTURE：

a. PICTURE MODE (USER/ VIVID1 /VIVID2 / VIVID3)

b. Adjust the BACKLIGHT (0~100)

c. Adjust the BRIGHTNESS (0~100)

d. Adjust the CONTRAST (0~100)

e. Adjust the COLOR (saturation)(0~100)

f. Adjust the TINT (hue) (0~100)

g. Adjust the SHARPNESS (0~100)

B. AUDIO ADJUST：

a. VOLUME (0~100)

b. BASS (0~100)

c. TREBLE (0~100)

d. BALANCE (0~100)

e. SURROUND (ON/OFF)

f. REVERB (OFF, CONCERT, LIVING ROOM, HALL, ARENA)

g. MUTE (ON/OFF)

h. SPEAKERS (ON/OFF)

C. PARENTAL CONTROL：

a. PARENT LOCK ENABLE (ON/OFF)

b. TV RATING

c. MOVIE RATING

d. ACCESS CODE EDIT

D. PIP SETUP：

a. STYLE (OFF/PIP/POP)

b. SOURCE (AV1、AV2、AV3、TV)

c. SIZE (SMALL (20%)/MEDIUM (30%)/LARGE (40%))

d. POSITION (TOP LEFT/TOPCENTER/TOP RIGHT/MIDDLELEFT/MIDDLE

RIGHT/BOTTOMLEFT/BOTTOM CENTER/BOTTOMRIGHT)

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E. SPECIAL FEATURES：

a. LANGUAGE (ENGLISH/FRANCE/SPANISH)

b. SLEEP TIMER (OFF/30/60/90/120)

c. WIDE FORMAT (NORMAL/WIDE/ZOOM、PANORAMIC)

d. RESET ALL SETTING

Video Sources：

AV1、AV2、AV3、ANALOG HD1、ANALOG HD2

A. PICTURE：

a. PICTURE MODE (USER/ VIVID1 /VIVID2 / VIVID3)

b. Adjust the BACKLIGHT (0~100)

c. Adjust the BRIGHTNESS (0~100)

d. Adjust the CONTRAST (0~100)

e. Adjust the COLOR (saturation)(0~100)

f. Adjust the TINT (hue) (0~100)

g. Adjust the SHARPNESS (0~100)

h. CLOSED CAPTION (OFF/CC1/CC2/CC3/CC4/TT1/TT2/TT3/TT4)

B. AUDIO ADJUST：

a. VOLUME (0~100)

b. BASS (0~100)

c. TREBLE (0~100)

d. BALANCE (0~100)

e. SURROUND (ON/OFF)

f. REVERB (OFF, CONCERT, LIVING

ROOM, HALL, ARENA)

g. MUTE (ON/OFF)

h. SPEAKERS (ON/OFF)

C. PARENTAL CONTROL：

a. PARENT LOCK ENABLE (ON/OFF)

b. TV RATING

c. MOVIE RATING

d. ACCESS CODE EDIT

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D. PIP SETUP：

a. STYLE (OFF/PIP/POP)

b. SOURCE (AV2、AV3、ANALOGHD1、ANALOG HD2、DIGITAL HD、

RGB、TV)

c. SIZE (SMALL (20%)/MEDIUM (30%)/LARGE (40%))

d. POSITION (TOP LEFT/TOPCENTER/TOP RIGHT/MIDDLE

LEFT/MIDDLE RIGHT/BOTTOMLEFT/BOTTOM ENTER/BOTTOM RIGHT)

E. SPECIAL FEATURES：

a. LANGUAGE (ENGLISH/FRANCE/SPANISH)

b. SLEEP TIMER (OFF/30/60/90/120)

c. WIDE FORMAT (NORMAL/WIDE/ZOOM、PANORAMIC)

d. RESET ALL SETTING

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Chapter4 Factory preset timings

This timing chart is already preset for the TFT LCD analog & digital display monitors.

Resolution

Refresh

rate

640x480 60Hz 31.5kHz 59.94Hz N N 25.175

640x480 75Hz 37.5kHz 75.00Hz N N 31.500

800X600 60Hz 37.9kHz 60.317Hz P P 40.000

800x600 75Hz 46.9kHz 75.00Hz P P 49.500

800X600 85Hz 53.7kHz 85.06Hz P P 56.250

1024x768 60Hz 48.4kHz 60.01Hz N N 65.000

1024X768 75Hz 60.0kHz 75.03Hz P P 78.750

720x400 70Hz 31.46kHz 70.08Hz N P 28.320

1366X768 60 47.7KHZ 60.00HZ P N 85.500

Remark: P: positive N: negative

Horizontal

Frequency

Vertical

Frequency

Horizontal

Polarity

Vertical

Polarity

Pixel

Rate

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Chapter 5 Pin Assignment

The TFT LCD analog display monitors use a 15 Pin Mini D-Sub connector as video

input source.

Pin Description

1 Red

2 Green

3 Blue

4 Ground

5 Ground

6 R-Ground

7 G-Ground

8 B-Ground

9 +5V for DDC

10 Ground

11 No Connection

12 (SDA)

13 H-Sync (Composite

Sync)

14 V-Sync

15 (SCL)

1

5

106

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11

15

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HDMI CONNECT PIN ASSIGNMENT

PIN SIGNAL ASSIGNMENT

1 TMDS Data2+

2 TMDS Data2 Shield

3 TMDS Data2-

4 TMDS Data1+

5 TMDS Data1 Shield

6 TMDS Data1-

7 TMDS Data0+

8 TMDS Data0 Shield

9 TMDS Data0-

10 TMDS Clock+

11 TMDS Clock Shield

12 TMDS Clock-

13 CEC

14 Reserved (N.C on device)

15 SCL

16 SDA

17 DDC/CEC Ground

18 +5V Power

19 Hot Plug Detect

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Four-Pin mini DIN S-Video Connector

a. Pin Assignment

b.Signal Level Video (Y): Analog 0.1Vp-p/75Ω

Video (C): Analog 0.286p-p/75

Sync (H+V): 0.3V below Video (Y)

c.Frequency H: 15.734KHz V: 60Hz (NTSC)

Signal Level Video (Y) : Analog 0.1Vp-p/75Ω

Video (C) : Analog 0.286p-p/75Ω

Sync (H+V): 0.3V below Video (Y)

Frequency H: 15.734Khz V: 60HZ (NTSC)

F-Type TV RF connector

a. Signal Level 60dBµV typical

b. System NTSC

c. Frequency 55~801MHz (NTSC)

PC connector 15 pin male D-sub connector

a. Pin Assignment Refer to Section 2.3.10

b. Signal Level Video (R, G, B): Analog 0.7Vp-p/75Ω Sync (H, V): TTL level

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RGB Signal:

a. Sync Type TTL (Separate / Composite) or Sync. On Green

b. Sync polarity Positive or Negative

c. Video Amplitude RGB: 0.7Vp-p

d. Frequency H: support to 30K~70KHz

V: support to 50~85Hz

Pixel Clock: support to 110MHz

HDMI Signal (Digital HD):

a. Pin Assignment Refer to HDNI Pin Assignment

b. Type A

c. Polarity Positive or Negative

d. Frequency

H: 15.734KHz V: 60Hz (NTSC-480i)

H: 31KHz V: 60Hz (NTSC-480p)

H: 45KHz V: 60Hz (NTSC-720p)

H: 33KHz V: 60Hz (NTSC-1080i)

Component signal (Analog HD1 and Analog HD2)

Analog HD1

a. Frequency H: 15.734KHz V: 60Hz (NTSC-480i)

H: 31KHz V: 60Hz (NTSC-480p)

H: 45KHz V: 60Hz (NTSC-720p)

H: 33KHz V: 60Hz (NTSC-1080i)

b. Signal level Y: 1Vp-p Pb: ±0.350Vp-p Pr: ±0.350Vp-p

c. Impedance 75Ω

Analog HD2

a. Frequency H: 15.734KHz V: 60Hz (NTSC-480i)

H: 31KHz V: 60Hz (NTSC-480p)

H: 45KHz V: 60Hz (NTSC-720p)

H: 33KHz V: 60Hz (NTSC-1080i)

b. Signal level Y: 1Vp-p Pb: ±0.350Vp-p Pr: ±0.350Vp-p

c. Impedance 75Ω

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Chapter6 Main Board I/o Connections

J7 CONNECTION (TOP→BOTTOM)

Pin Description

1 “Auto”

2 “Left”

3 “Right”

4 “Down”

5 “Gnd”

6 “Up”

7 “Menu”

8 “Source”

9 “Power”

10 “LED”

11 “IR”

12 “+5V”

J1 CONNECTION (TOP→BOTTOM)

Pin Description

1 “POWRSW”

2 “+12V”

3 “+12V”

4 “+12V”

5 “+12V”

6 “GND”

7 “GND”

8 “GND”

9 “+5V”

10 “+5V”

11 “+5V”

12 “PWM”

13 “BL ON/OFF”

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J3 CONNECTION (TOP→BOTTOM)

Pin Description Pin Description

1 “+3.3V” 16 “HPDET”

2 “ORO2” 17 “GND”

3 “ORO1” 18 “NC”

4 “ORO0” 19 “NC”

5 “FDAT” 20 “AV3 IN”

6 “FCMO” 21 “AV3 GND”

7 “GND” 22 “AV3L”

8 “GND” 23 “GND”

9 “FCLK” 24 “AV3R”

10 “GND” 25 “GND”

11 “NC” 26 “S1Y IN”

12 “NC” 27 “S1Y GND”

13 “GND” 28 “S1C IN”

14 “HPR” 29 “S1C GND”

15 “HPL” 30 “SVDET2#”

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Chapter 7 Theory of Circuit Operation

The operation of D-SUB 15pin route

The D-SUB 15pin is input analog signal to the MTK8205 transfer A/D converter then

generates the vertical and horizontal timing signals for display device.

The operation of HDMII CON route

The HDMI CON is input digital signal the signal is process to the sil9011. Then transfer to the

MTK8205, the MTK8205 generates the vertical and horizontal timing signals for display

device.

The operation of HDTV & Component route

HDTV & Component signal is input to switch IDTQS3VH257 (Select Component1 or 2). Then

transfer to the MTK8205 the MTK8205 generates the vertical and horizontal timing signals for

display device.

The operation of Video 1,2,3 & S-Video route

The Video 1,2,3 and S-Video signal is transmission signal to main board MM1492 (Switch)

and output to MTK8205 the MTK8205 generates the vertical and horizontal timing signals for

display device.

The operation of TV route

TV signal is processes to the tuner and output to MM1492 (switch) then transfer to MTK8205

the MTK8205 generates the vertical and horizontal timing signals for display device. Audio is

processes to the tuner output to SIF circuit and output to MTK8205.Then MTK8205 process to

wm8776 and output to TDA8946J transfer to speaker

The operation of keypad

There are 8 keys to control and select the function of L32 and also has one LED to indicate

the status of operation. They are “Power, Mute/Exit, OSD, ▼▲, + -, Input”.

1. The power key through POW and GND to control MTK8205, MTK8205 will receive a

low signal to turn on or off system while press the power key.

2. The other key the same as power key

3. The LED is constructed with two separate LED which color is blue and orange. The

MTK8205 direct control the LED’s when MTK8205 (OGO5) is low the LED is orange

(Close power) when MTK8205 (OGO5) is high the LED is blue (Open power).

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MT8205 Application

MT8205 is a highly integrated single chip for LCD TV supporting video input and output format

up to HDTV. It includes 3D comb filter TV Decoder to retrieve the best image from popular

composite signals. On-chip advanced motion adaptive de-interlacer converts accordingly the

interlace video into progressive one with overlay of a 2D Graphic processor. Optional 2nd

HDTV or SDTV inputs allows user to see multi-programs on same screen. Flexible scalar

provides wide adoption to various LCD panel for different video sources. Its on-chip audio

processor decodes analog signals from Tuner with lip sync control, delivering high quality

post-processed sound effect to customers. On-chip microprocessor reduces the system BOM

and shortens the schedule of UI design by high level C program. MT8205 is a cost-effective

and high performance HDTV-ready solution to TV manufactures.

BOLOCK DIAGRAM

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1. Video input

a. Input Multiplexing

1.component X2

2.composite X3

3.s-videoX1

4.HDMI X1

5.VGA X1

6.RF X1

b. Input formats:

1.support HDTV 480i/480p/720p/1080p

2.support Y/C signal 1VP-P/75Ω

3.support Y/C signal 1VP-P/75Ω

4.support 480i/408p/720p/1080i/1080p

5.support VGA input up to 1366x168@60HZ

6.support NTSC system Frequency 55~801MHZ

2. TV Decoder

For pip/pop:

Dual identical TVD on chip

3D-comb for both path

Dual VBI decoders for the application of V-chip

3. Support Formats:

Support NTSC, NTSC-4.43

Automatic Luma / Chroma gain control

Automatic TV standard detection

NTSC Motion Adaptive 3D comb filter

Motion adaptive 3D Noise Reduction

VBI decoder for closed-caption/XDS/Teletext/WSS/VPS

Macro vision detection

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BOLOCK DIAGRAM

4. 2D-Graphic/OSD processor

Two OSD planes.

Support alpha blending among these two planes and video

Support text/bitmap decoder

Support line/rectangle/gradient fill

Support bitblt

Support color key function

Support clip mask

65535/256/16/4/2-color bitmap format OSD

Automatic vertical scrolling of OSD image

Support OSD mirror and upside down

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5. Microprocessor interface

When power is supplied and power key is pressed then the rest circuit lets Reset to low

state that will reset the MTK8205 to initial state. After that the Reset will transits to high state

and the MTK8205 start to work that microprocessor executes the programs and configures

the internal registers. The execution speed of CPU is 133 MHz.

a. The I/O ports are configured as follows：

Pin name Function Type Description

AF26 VGASCL Input / Output

AE26 VGASDA Input / Output

AB23 HDDCSCL Input / Output

AB24 HDDCSDA Input / Output

AD22 SCL Input / Output

AV22 SDA Input / Output

OBO0 SOURCE Input Key detection

OBO1 MENU Input Key detection

OBO2 UP Input Key detection

OBO3 DOWN Input Key detection

OBO4 RIGHT Input Key detection

OBO5 LEFT Input Key detection

OBO6 AUTO Input Key detection

OBO7 POWER Input Key detection

OGO5 LED Output

AF24 IR Input / Output

AE23 GPIO Output Power on of TV board and panel

AD23 PWM0 Output Backlight Adjustmance

AC23 PWM1 Output Select mute

AD20 UP1_5 Output RCA out mute

AE20 UP1_4 Input S-video Detect

AF20 UP1_3 Output HDMI SCDT

AE19` UP1_2 Output YCBCRSEL

AE21 UP3_0 Output Backlight ON/OFF

AD21 UP3_1 Output HDMI CAB

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b. PIP/POP HARDWARE LIMITION:

6. Video processor

a. Color management

Flesh tone and multiple-color enhancement

Gamma/anti-Gamma correction

Color Transient Improvement (CTI)

Saturation/hue adjustment

Contrast/Brightness/Sharpness Management

Sharpness and DLTI/DCTI

Brightness and contrast adjustment

Black level extender

White peak level limiter

Adaptive Luma/Chroma Management

b. De-interlacing

Automatic detect film or video source

3:2/2:2 pull down source detection

Advanced Motion adaptive de-interlacing

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c. Scaling

Arbitrary ratio vertical/horizontal scaling of video, from1/32X to 32X

Advanced linear and non-linear Panorama scaling

Programmable Zoom viewer

Picture in picture (PIP)

Picture in picture

d. Display

12/10 10/8 8/6 Dithering processing for LCD display

10bit gamma correction

Support Alpha blending for Video and two OSD panel

Frame rate conversion

7. DRAM Usage

8205,2pcs of 8X16 DDR166 is necessary

Here is a comparison chart between (2XDDR)and(1XDDR)

MTK8205 8MX16 DDRAM test report

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8. Flash Usage

Flash is used to store FW code, fonts, bitmaps, and big tables for VGA, Video, and Gamma

2Mbyte is recommended to build a general TV model

MTK8205 Flash ROM support test report

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DDR SDRAM (M13S128168A-6T) Application

Pin description

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Command Truth Table

1. Power-Up and Initialization Sequence

The following sequence is required for POWER UP and Initialization.

1. Apply power and attempt to maintain CKE at a low state

(all other inputs may be undefined.)

- Apply VDD before or at the same time as VDDQ.

- Apply VDDQ before or at the same time as VTT & VREF).

2. Start clock and maintain stable condition for a minimum of 200us.

3. The minimum of 200us after stable power and clock (CLK, CLK),

apply NOP & take CKE high.

4. Issue precharge commands for all banks of the device.

5. Issue EMRS to enable DLL. (To issue “DLL Enable” command, provide “Low” to A0,

“High” to BA0 and “Low” to all of the rest address pins, A1~A11 and BA1)

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6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock

input is required to lock the DLL.(To issue DLL reset command, provide “High” to A8 and

“Low” to BA0)

7. Issue precharge commands for all banks of the device.

8. Issue 2 or more auto-refresh commands.

9. Issue a mode register set command with low to A8 to initialize device operation.

2. Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR

SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset

and various vendor specific options to make DDR SDRAM useful for variety of different

applications. The default value of the register is not defined, therefore the mode register

must be written after EMRS setting for proper DDR SDRAM operation. The mode register is

written by asserting low on CS , RAS , CAS , WE and BA0 (The DDR SDRAM should be in

all bank recharge with CKE already high prior to writing into the mode register).

The state of address pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0

going low is written in the mode register. Two clock cycles are requested to complete the

write operation in the mode register. The mode register contents can be changed using the

same command and clock cycle requirements during operation as long as all banks are in

the idle state. The mode register is divided into various fields depending on functionality.

The burst length uses A0~A2, addressing mode uses A3, CAS latency (read latency from

column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must

be set to low for normal MRS operation. Refer to the table for specific codes for various

burst length, addressing modes and CAS latencies.

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3. Precharge

The precharge command is used to precharge or close a bank that has activated. The

precharge command is issued when CS, RAS and WE are low and CAS is high at the rising

edge of the clock. The precharge command can be used to precharge each bank

respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used

to define which bank is precharged when the command is initiated. For write cycle,

tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the

precharge, an active command to the same bank can be initiated.

Burst Selection for Precharge by Bank address bits

A10/AP BA1 BA0 Precharge

0 0 0

0 0 1 Bank B Only
0 1 0 Bank C Only
0 1 1 Bank D Only
1 X X All Banks

Bank A Only

4. Row Active

The Bank Activation command is issued by holding CAS and WE high with CS and RAS

low at the rising edge of the clock (CLK).

The DDR SDRAM has four independent banks; so two Bank Select addresses (BA0, BA1)

are required.

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The Bank Activation command to the first read or write command must meet or exceed the

minimum of RAS to CAS delay time (tRCD min). Once a bank has been activated, it must

be precharged before another Bank Activation command can be applied to the same bank.

The minimum time interval between interleaved Bank Activation command (Bank A to Bank

B and vice versa) is the Bank-to-Bank delay time (tRRD min).

5. Read Bank

This command is used after the row activates command to initiate the burst read of data.

The read command is initiated by activating CS, CAS , and deasserting WE at the same

clock sampling (rising) edge as described in the command truth table. The length of the

burst and the CAS latency time will be determined by the values programmed during the

MRS command.

6. Write Bank

This command is used after the row activates command to initiate the burst write of data.

The write command is initiated by activating CS, CAS, and WE at the same clock sampling

(rising) edge as describe in the command truth table. The length of the burst will be

determined by the values programmed during the MRS command.

7. Burst Read Operation

Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such

that the Burst read command is issued by asserting CS and CAS low while holding RAS

and WE high at the rising edge of the clock (CLK) after tRCD from the bank activation.

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The address inputs determine the starting address for the Burst, The Mode Register sets

type of burst (Sequential or interleave) and burst length (2, 4, 8).

The first output data is available after the CAS Latency from the READ command, and the

consecutive data are presented on the falling and rising edge of Data Strobe (DQS)

adopted by DDR SDRAM until the burst length is completed.

8. Burst Write Operation

The Burst Write command is issued by having CS , CAS and WE low while holding RAS

high at the rising edge of the clock (CLK). The address inputs determine the starting column

address. There is no write latency relative to DQS required for burst write cycle.

The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time)

prior to data strobe edge enabled after tDQSS from the rising edge of the clock (CLK) that

the write command is issued.

The remaining data inputs must be supplied on each subsequent falling and rising edge of

Data Strobe until the burst length is completed. When the burst has been finished, any

additional data supplied to the DQ pins will be ignored.

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MX29LV160BTTC (Flash) Application

The MX29LV800T/B & MX29LV800AT/AB is a 8-mega bit Flash memory organized as 1M

bytes of 8 bits or 512K words of 16 bits. MXIC's Flash memories offer the most cost-effective

and reliable read/write non-volatile random access memory. The MX29LV800T/B &

MX29LV800AT/AB is packaged in 44-pin SOP, 48-pin TSOP, and 48-ball CSP. It is designed

to be reprogrammed and erased in system or in standard EPROM programmers.

BLOCK DIAGRAM

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1. COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the

command register. Writing incorrect address and data values or writing them in the

improper sequence will reset the device to the read mode. Table 5 defines the valid register

command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H)

commands are valid only while the Sector Erase operation is in progress.

2. WRITE COMMANDS/COMMAND SEQUENCES

To program data to the device or erase sectors of memory, the system must drive WE and

CE to VIL, and OE to VIH. The device features an Unlock Bypass mode to facilitate faster

programming. Once the device enters the Unlock Bypass mode, only two write cycles are

required to program a byte, instead of four. The "byte Program Command Sequence"

section has details on programming data to the device using both standard and Unlock

Bypass command sequences. An erase operation can erase one sector, multiple sectors,

or the entire device. Table indicates the address space that each sector occupies. A "sector

address" consists of the address bits required to uniquely select a sector.

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The "Writing specific address and data commands or sequences into the command register

initiates device operations. Figure 1 defines the valid register command sequences. Writing

incorrect address and data values or writing them in the improper sequence resets the

device to reading array data. Section has details on erasing a sector or the entire chip, or

suspending/resuming the erase operation.

After the system writes the auto select command sequence, the device enters the auto

select mode. The system can then read auto select codes from the internal register (which

is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this

mode. Refer to the Auto select Mode and Auto select Command Sequence section for more

information. ICC2 in the DC Characteristics table represents the active current specification

for the write mode. The "AC Characteristics" section contains timing specification table and

timing diagrams for write operations.

Figure 1

3. READ/RESET COMMAND

The read or reset operation is initiated by writing the read/reset command sequence into

the command register. Microprocessor read cycles retrieve array data. The device remains

enabled for reads until the command register contents are altered. If program-fail or

erase-fail happen, the write of F0H will reset the device to abort the operation. A valid

command must then be written to place the device in the desired state.

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4. READING ARRAY DATA

The device is automatically set to reading array data after device power-up. No commands

are required to retrieve data. The device is also ready to read array data after completing an

Automatic Program or Automatic Erase algorithm. After the device accepts an Erase

Suspend command, the device enters the Erase Suspend mode. The system can read

array data using the standard read timings, except that if it reads at an address within erase

suspended sectors, the device outputs status data. After completing a programming

operation in the Erase Suspend mode, the system may once again read array data with the

same exception. See Erase Suspend/Erase Resume Commands” for more information on

this mode. The system must issue the reset command to re-enable the device for reading

array data if Q5 goes high, or while in the auto select mode. See the "Reset Command"

section, next.

5. RESET COMMAND

Writing the reset command to the device resets the device to reading array data. Addresses

bits are don't care for this command. The reset command may be written between the

sequence cycles in an erase command sequence before erasing begins. This resets the

device to reading array data. Once erasure begins, however, the device ignores reset

commands until the operation is complete. The reset command may be written between the

sequence cycles in a program command sequence before programming begins. This resets

the device to reading array data (also applies to programming in Erase Suspend mode).

Once programming begins, however, the device ignores reset commands until the

operation is complete. The reset command may be written between the sequence cycles in

an SILICON ID READ command sequence. Once in the SILICON ID READ mode, the reset

command must be written to return to reading array data (also applies to SILICON ID READ

during Erase Suspend). If Q5 goes high during a program or erase operation, writing the

reset command returns the device to reading array data (also applies during Erase

Suspend).

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WM8776 Application

The WM8776 is a high performance, stereo audio codec with five channel input selector. The

WM8776 is ideal for surround sound processing applications for home hi-fi, DVD-RW and

other audiovisual equipment. Etch ADC channel has programmable gain control with

automatic level control. Digital audio output word lengths from 16-32 bits and sampling rates

from 32kHZ to 96KHZ are supported. The DAC has an input mixer allowing an external

analogue signal to be mixed with the DAC signal. There are also Headphone and line outputs,

with control for the headphone.

The WM8776 supports fully independent sample rates for the ADC and DAC. The audio data

interface supports I2S, left justified, right justified and DSP formats.

BLOCK DIAGRAM

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1. Audio sample rate

The master clock forWM8776 supports DAC and ADC audio sampling rates 256fs to 768fs,

where fs is the audio sample frequency (DACLRC or ADCLRC) typically 32KHZ, 44.1KHZ,

48KHZ or 96KHZ (the DAC also supports operation at 128fs and 192fs and 192KHZ sample

rate). The master clock is used to operate the digital filters and the noise shaping circuits.

In slave mode the WM8776 has a master detection circuit that automatically determines the

relationship between the master clock frequency and the sampling rate (to within +/- 32

system clocks) If there is a greater than 32 clocks error the interface is disabled and

ADCLRC/DACLRC for optical performance, although the WM8776 is tolerant of phase

variations or jitter on this clock.

Table shows the typical master clock frequency inputs for the WM8776

2. DIGITAL AUDIO INTERFACE

a. Slave mode

The audio interfaces operations in either slave mode selectable using the MS control bit. In

slave mode DIN is always an input to the WM8776 and DOUT is always an output. The

default is Slave mode. In slave mode (ms=0) ADCLRC, DACLRC, ADCBCLK, DACBCLK are

input to the WM8776

DIN and DACLRC are sampled by the WM8776 on the rising edge of DACBCLK; ADCLRC is

sampled on the rising edge of ADCBCLK. ADC data is output on DOUT and changes on the

falling edge of ADCBCLK. By setting control bit BCLKINV the polarity of ADCBCLK and

DACBCLK may be reversed so that DIN and DACLRC are sample on the falling edge of

DACBCLK, ADCLRC is sampled on the falling edge of ADCBCLK and DOUT changes on the

rising of ADCBCLK Slave mode as shown in the following figure.

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b. 2 Wire serial control mode

The wm8776 supports software control via a 2-wire serial bus. Many devices can be

controlled by the same bus, and each device has a unique 7-bit address (this is not the

same as the 7-bit address of each register in the wm8776). The wm8776 operates as a

slave device only.

2-wire serial interface as shown in the following figure.

The wm8776 has two possible device addresses, which can be selected using the CE pin

In the L32 LCD TV CE pin is LOW (device address is 34h)

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In the L32 wm8776 has 2-wire interface

Sil9011 Application

The sil9011 provides a complete solution for receiving HDMI compliant digital audio and

video. Specialized audio and video processing is available within the sil9011 to easily and

cost effectively adds HDMI capability to consumer electronics devices such as digital TVs,

plasma displays, LCD TVs and projectors.

BLOCK DIAGRAM

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1. TMDS Digital Core

The core performs 10-to-8-bit TMDS decoding on the audio and video received from the

three TMDS differential data lines along with a TMDS differential clock. The TMDS core

supports link clock rates to 165MHZ, including CE modes to 720P/1080I/1080P.

2. Active port detection

The Pane Link core detects an active TMDS clock and actively toggling DE signal. These

states are accessible in register bits, useful for monitoring the status of the HDMI input or

for automatically powering down the receiver. The 5V supply from the HDMI connector is

used as a cable detect indicator. The sil9011 can monitor the presence of this+5V supply

and, if and when necessary, provide a fast audio mute without pops when it senses the

HDMI cable pulled. The microcontroller can also poll registers in the sil9011 to check

whether an HDMI cable is connected.

3. HDCP Decryption engine

The HDCP decryption engine contains all necessary logic to decrypt the incoming audio

and video data. The decryption process is entirely controlled by the host microprocessor

through a set sequence of register reads and wires through the DDC channel.

Pre-programmed HDCP keys and key Selection Vector are used in the decryption process.

A resulting calculated to an XOR mask during each clock cycle to decrypt the audio/video

data in sync with the host.

4. Video Data Conversion and Video Output

The Sil9011 can output video in many different formats as shown in the following figure.

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The receiver can also process the video data before it is output as show below figure

5. I2c Interface to Display Controller

The Controller I2c interface (CSDA, CSCL) on the sil9011 is a slave interface capable of

running up to 400KHZ. This bus is used to configure the SIL9011 by reading/writing to the

appropriate registers. The SIL9011 is accessible on the local I

The logic state of the CI2CA pin is latched on the rising edge of REST# providing a choice

of two pairs of device address.

Control of local I

2

c address with CI2CA pin

2

c bits at two-device address.

MM1942 Application

The MM1942 IC is a 5-input 2-output AV switch controlled by the I2C BUS developed for use in

television.

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BLOCK DIAGRAM

1. I2c Bus

I2C BUS is interring bus system controlled by 2 lines (SDA, SCL). Data are transmitted and

received in the units of byte and Acknowledge. It is transmitted by MSB first from the Start

conditions.

The data format is set as shown in the following figure.

In the L32 TV MM1492 slave address, ADR terminal is L, and 90H is selected.

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The following figure indicates the control contents of control registers and switches.

2. Switch control table

a. Video output 1

b. Audio output 1

c. Audio gain

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TDA8946 Application

In L32 TV the TDA8946AJ is a dual-channel audio power amplifier with DC gain control. It has an

output power of 2 × 10 W at an 8 Ω load and a 12 V supply.

Block diagram

1. Input configuration

The TDA8946AJ inputs can be driven symmetrical (floating) as well as asymmetrical. In the

asymmetrical mode one input pin is connected via a capacitor to the signal source and the

other input is connected to the signal ground. The signal ground should be as close as

possible to the SVR (electrolytic) capacitor ground. Note that the DC level of the input pins

is half of the supply voltage VCC, so coupling capacitors for both pins are necessary

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2. Output power measurement

The output power as a function of the supply voltage is measured on the output pins at THD

= 10%,in the L32 LCD TV Vcc=12V so we can see as shown in the following figure output

about 7W.

3. Mode selection

In the L32 LCD TV TDA8946AJ has two functional modes, which can be selected by applying the

proper DC voltage to pin MODE.

a. Mute — In this mode the amplifier is DC-biased but not operational (no audio output).

This allows the input coupling capacitors to be charged to avoid pop-noise. The device is in mute

mode when 3.5 V < V

b. Operating — In this mode the amplifier is operating normally. The operating mode is activated at

V

MODE<1.0V.

MODE < (VCC − 1.5 V).

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Chapter8 Waveforms

PC MODE(1366X768 60HZ)

CH1 H-sync (FB46); CH2 V-sync (FB45)

GREEN (R194)

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CH1 VGAHSYNC# (FB46); CH2 VGAVSYNC# (FB45)

CH1 VGAVSYNC# (FB45); CH2 GREEN (R194)

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CH1 VGAL (CE81); CH2 AVOL (R252)

CH1 AUSPL (RA12) ; CH2 L+ (UA1 PIN17)

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CH1 XTALI (U9 PIN A15);CH2 XTALO (U9 PIN B15)

AV&TV MODE (AV1/AV2/AV3/TV) VIDEO

CH1 (R88); CH2 (Q4 PIN1)

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CH1 CVBS1+ (U9 PINA2); CH2 CVBS1 (R136)

CH1 AV1L (U20 PIN1); CH2 AUO1L_SWO (U20 PIN36)

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CH1 AUSPL (RA12) ; CH2 L+ (UA1 PIN17)

CH1 D_CLK# (U11 PIN46);CH2 D_DQ15(U11 PIN65)

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CH1 DACMCLK (U22 PIN11);CH2 DOUT (U22 PIN12)

CH1 SCL34H(U22 PIN19);CH2 SDA34H (U22 PIN18)

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ANALOG HD MODE (ANALOG HD1/HD2)

CH1Y1_IN (R105); CH2 Y (U21 PIN7)

CH1Y (R280); CH2 Y+ (C120)

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CH1 TUL (U20 PIN44); CH2 AUO1L_SWO (U20 PIN 36)

CH1 AUSPL (RA12) ; CH2 L+ (UA1 PIN17)

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DIGITAL HD

CH1 DATA2+ (P1 PIN 1); CH2 DATA2- (P1 PIN3)

CH1 HDMI0 (U16 PIN 124) ;CH2 HDMI15 (U16 PIN 102)

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CH1 XTLI (U16 PIN85) ;CH2 XTLO (U16 PIN86)

CH1 HDMISDA (U16 PIN39);CH2 HDMISCL (U16 PIN40)

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POWER ON/OFF

CH1 DV120B (F1); CH2 GPIO (R3); POWER ON

CH1 DV120B (F1); CH2 GPIO (R3); POWER OFF

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CH1 DV120B (F1); CH2 GPIO (R3); AC POWER ON

CH1 DV120B (F1); CH2 GPIO (R3); AC POWER OFF

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CH1 DV50B (U7 PIN8); CH2 GPIO (R3); POWER ON

CH1 DV50B (U7 PIN8); CH2 GPIO (R3); POWER OFF

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CH1 DV50B (U7 PIN8); CH2 GPIO (R3); POWER AC ON

CH1 DV50B (U7 PIN8); CH2 GPIO (R3); POWER AC OFF

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CH1 DV120B (U6 PIN1); CH2 AV_V90 (U6 PIN3) POWER ON

CH1 DV120B (U6 PIN1); CH2 AV_V90 (U6 PIN3) POWER OFF

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CH1 DV120B (U6 PIN1); CH2 AV_V90 (U6 PIN3) AC POWER ON

CH1 DV120B (U6 PIN1); CH2 AV_V90 (U6 PIN3) AC POWER OFF

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CH1 DV50A (U4 PIN1); CH2 DV33A (F3) AC POWER ON

CH1 DV50A (U4 PIN1); CH2 DV33A (F3) AC POWER OFF

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CH1 DV33A (U5 PIN 1); CH2 DV18A (U5 PIN2) AC POWER ON

CH1 DV33A (U5 PIN 1); CH2 DV18A (U5 PIN2) AC POWER OFF

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CH1 DV25 (U13 PIN7); CH2 D1V25 (U13 PIN3) POWER ON

CH1 DV25 (U13 PIN7); CH2 D1V25 (U13 PIN3) POWER OFF

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CH1 DV25 (U13 PIN7); CH2 D1V25 (U13 PIN3) AC POWER ON

CH1 DV25 (U13 PIN7); CH2 D1V25 (U13 PIN3) AC POWER OFF

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Chapter 9 Trouble shooting

MONITOR DISPLAY NOTHING (PC MODE)

Start

LED is lighted

N0

1. Is Power board output
+5V?

2. Is J1 connector good?

3. Is DC-DC OK?

4. Is U4 (3.3V) working ok?

LED is lighting?

Is backlight on?

Yes

Yes

N0

N0

N0

It is in power saving

1. Check video cable

2. Is the timing supported?

3. Check sync input

4. Check VGASOG rout if analog

(SOG)

1.Check J1 PIN 1

2.Is inverter ok?

Yes
Yes

N0

U9 no data out?

It means data to LVDS

1.Is J6 connecting well?

2.Check J1 +5V&+12V

3.Is panel ok?

Yes

U9 no data in?

N0

1.Is U9 working good?

2.Is U11&U12 working good?

3.IS U10 working good?

1. Check P3 D-sub Input correct

2. Check analog input route

END

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(TV, COMPOSITE VIDEO1, 2, 3, S-VIDEO) IS NOT DISPLAY CORRECTLY

Star t

N0

Input signal good?

1.Check video

2.Check DVD player

Yes

U20 input correct?

Yes

U20 output correct?

Yes

LVDS output correct?

Yes

1.Chcak J6 Connect is good?

2.Is panel working ok?

END

N0

N0

N0

1.Check P2 signal

2.Check signal between P2 and

U20 (IF AV1/AV2 mode)

3.Check Tuner &U20 (IF TV mode)

4.Check J4&J6 (IF AV3&S-Video)

5.Check U20 POWER +9V

6.Check U22 data input/output

1.Check signal between U20 and

U9

1.Check signal between U20 and

U9

2.Check U9 clock (27MHz)

3.Check U9 power

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(COMPONENT1, 2) IS NOT DISPLAY CORRECTLY

Star t

N0

Input signal good?

1.Check video

2.Check host’s setting

Yes

U21 input correct?

Yes

U9 input correct?

Yes

LVDS output correct ?

Yes

1.Is J6 connected good?

2.Is panel working ok?

END

N0

N0

N0

1.Check signal between P8&U21

2.Check U21 power 3.3V

1.Check signal between U21&U9

2.Check U9 Clock (27MHZ)

1.Check U9

2.Check U9 power 3.3V 1.8V

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U16

(HDMI) IS NOT DISPLAY CORRECTLY

Star t

N0

Input signal good?

1.Check video

2.Check host’s setting

Yes

N0

U16 input correct?

1.Check p1 connect

2.Check signal between P1 and

Yes

U16 no data out ?

1.Is J6 connected good?

2.Is panel working ok?

Yes

N0

1.Check U16 power

2.Check between signal U16 and
U9

3.Check clock 28.224MHZ

Yes

END

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TROUBLE OF DC-DC CONVERTER

Star t

J1 PIN 9,10,11

N0

The voltage is about + 5V

1.Check power board

2.Check power cable connection
J1

J1 PIN 2,3,4,5

U7 pin 5 6 7 8

U4 pin2

U6 pin 3

U14 pin2

Yes

Yes

Yes

Yes

Yes

N0

N0

N0

N0

N0

The voltage is about + 12V while
power switch on

1.J1 connection good

2.Check U9 GPIO Pin

3.Check power board

The voltage is about +5V while
power switch on

1.J1 connection good

2. Check U9 GPIO Pin

The voltage is about +3.3V

1.J1 to connection good?

2.Check U4

The voltage is about +9V

1.Check U9 GPIO Pin

2.Check U6

The voltage is about +2.5V while
power switch on

1.Check U9 GPIO Pin

2.Check U14

U5 pin2

U13 pin2

END

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Yes

N0

The voltage is about +1.8V

1.Check J1 Connect

2.Check U5&L5

The voltage is about +1.25V
while power switch on

1.Check J1 Connect

2.Check U13

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TROUBLE OF DDC READING

Star t

N0

Analog DDC OK?

Yes

N0

HDMIDDC OK?

Support DDC1/2B

1.Analog cable ok?

2.Check signal (U18 to P3)

3.Check U18 Voltage

4.Is compliant protocol?

Support DDC1/2B

1.Analog cable ok?

2.Check signal (U17 to P1)

3.Check U17 Voltage

4.Is compliant protocol?

Yes

END

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Chapter 10 Block Diagram

System Block Diagram

32” WXGA panel

Digital

Video bus AC IN

Power Board

Speakers

□□□□□

J7 j6 J1 J5

Main Board

P11 P1 P3 P5 P8 P10 P2 P9 TU1

Keypad/IR

Board RJ11 HDMI Analog Audio in Component Audio Composite Audio RF

The TV system block diagram is powered by power board that transforms AC source

of 100V~240V AC +/- 10% @ 50/60 HZ into DC 5V & 12V& 24Vsource. The main

board receives different types of video signal into the MTK8205 Ic. Afterward, the

MTK8205 Ic process the signals control the various functions of the monitor and

outputs control signal, video signal and power to the 30” WXGA panel to be

displayed.

The power send to the panel is first processed by the inverter. The function of the

inverter is to step up the voltagesupplied by the main board to the power that is

needed to light up the lamps in the panel. Simultaneously, the digital video signals are

processed in the panel and the outcome determines the brightness, pixel on/off and

the color displayed on the panel.The analog video signals of S-video, YpbPr, TV, PC

and A/V all video signals are translated from analog signals into MTK8205 generates

the vertical and horizontal timing signals for display device.

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The analog audio of s-video, YpbPr, TV, PC and A/V is transmitting to the WM877

processed.

The purpose is process the input audio signal to control volume, bass, treble,

surround, and balance. The HDMI video and audio is must transmitting to sil9011

processed then TMDS signal to the MTK8205 generates the vertical and horizontal

timing signals for display device. All functions are controllable by the main board.

Plus, all functions in the IC boards are programmable using I2C Bus.

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Main Board Block Diagram

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